2.7 V to 5.5 V, Serial-Input, Voltage Output, Unbuffered 16-Bit DAC Data Sheet AD5541A FEATURES FUNCTIONAL BLOCK DIAGRAMS 16-bit resolution VDD 11.8 nV/√Hz noise spectral density AD5541A 1 µs settling time REF 16-BIT DAC VOUT 1.1 nV-sec glitch energy 0.05 ppm/°C temperature drift AGND 5 kV HBM ESD classification VLOGIC 16-BIT DAC LATCH 0.375 mW power consumption at 3 V CS 2.7 V to 5.5 V single-supply operation CONTROL Hardware CS and LDAC functions DIN LOGIC 50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface SCLK SERIAL INPUT REGISTER Power-on reset clears DAC output to zero scale LDAC AvMaiSlaObPle in 3 mm × 3 mm, 8-/10-lead LFCSP and 10-lead DGND 08516-001 Figure 1. AD5541A APPLICATIONS VDD Automatic test equipment Precision source-measure instruments AD5541A-1 Data acquisition systems REF 16-BIT DAC VOUT Medical instrumentation Aerospace instrumentation CS 16-BIT DAC LATCH Communications infrastructure equipment Industrial control DIN CONTROL LOGIC SCLK SERIAL INPUT REGISITER CLR GND 08516-002 Figure 2. AD5541A-1 GENERAL DESCRIPTION The AD5541A uses a versatile 3-wire interface that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and DSP interface The AD5541A is a single, 16-bit, serial input, unbuffered voltage standards. output digital-to-analog converter (DAC) that operates from a single 2.7 V to 5.5 V supply. Table 1. Related Devices The DAC output range extends from 0 V to V and is guaranteed Part No. Description REF monotonic, providing ±1 LSB INL accuracy at 16 bits without AD5040/AD5060 2.7 V to 5.5 V 14-/16-bit buffed output DACs AD5541/AD5542 2.7 V to 5.5 V 16-bit voltage output DACs adjustment over the full specified temperature range of −40°C AD5781/AD5791 18-/20-bit voltage output DACs to +125°C. The AD5541A is available in a 3 mm × 3 mm, 10-lead AD5024/AD5064 4.5 V to 5.5 V, 12-/16-bit quad channel DACs LFCSP and 10-lead MSOP. The AD5541A-1 is available in a AD5061 Single, 16-bit nanoDAC, ±4 LSB INL, SOT-23 3 mm × 3 mm, 8-lead LFCSP. AD5542A 16-bit, bipolar, voltage output DAC Offering unbuffered outputs, the AD5541A achieves a 1 µs set- PRODUCT HIGHLIGHTS tling time with low power consumption and low offset errors. Providing low noise performance of 11.8 nV/√Hz and low 1. 16-bit performance without adjustment. glitch, the AD5541A is suitable for deployment across multiple 2. 2.7 V to 5.5 V single operation. end systems. 3. Low 11.8 nV/√Hz noise spectral density. 4. Low 0.05 ppm/°C temperature drift. 5. 3 mm × 3 mm LFCSP and MSOP packaging. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5541A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 14 Applications ....................................................................................... 1 Unipolar Output Operation ...................................................... 15 Functional Block Diagrams ............................................................. 1 Output Amplifier Selection ....................................................... 15 General Description ......................................................................... 1 Force Sense Amplifier Selection ............................................... 16 Product Highlights ........................................................................... 1 Reference and Ground ............................................................... 16 Revision History ............................................................................... 2 Power-On Reset .......................................................................... 16 Specifications ..................................................................................... 3 Power Supply and Reference Bypassing .................................. 16 AC Characteristics ........................................................................ 4 Applications Information .............................................................. 17 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 17 Absolute Maximum Ratings ............................................................ 6 AD5541A to ADSP-BF531 Interface ....................................... 17 ESD Caution .................................................................................. 6 AD5541A to SPORT Interface .................................................. 17 Pin Configurations and Function Descriptions ........................... 7 Layout Guidelines....................................................................... 17 Typical Performance Characteristics ............................................. 9 Galvanically Isolated Interface ................................................. 17 Terminology .................................................................................... 13 Decoding Multiple DACs .......................................................... 18 Theory of Operation ...................................................................... 14 Outline Dimensions ....................................................................... 19 Digital-to-Analog Section ......................................................... 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/2018—Rev. A to Rev. B Changes to Figure 3 ........................................................................... 5 Change to Output Noise Parameter, Table 3 ................................. 4 Changes to Table 5 ............................................................................. 6 Changes to Figure 25 ...................................................................... 12 Changes to Table 6 ............................................................................. 7 Updated Outline Dimensions ....................................................... 19 Added Figure 5 and Figure 6 ............................................................ 8 Changes to Ordering Guide .......................................................... 20 Added Table 7; Renumbered Sequentially ..................................... 8 Changes to Figure 15 ...................................................................... 10 3/2011—Rev. 0 to Rev. A Changed V to V – 1 LSB in Unipolar Output Operation REF REF Added 10-Lead LFCSP and 8-Lead LFCSP ..................... Universal Section .............................................................................................. 15 Changes to Features, General Description, and Product Updated Outline Dimensions ....................................................... 18 Highlights Sections and Table 1 ..................................................... 1 Changes to Ordering Guide .......................................................... 18 Added Figure 2; Renumbered Sequentially .................................. 1 Changes to Logic Inputs Parameter, Table 1 ................................. 3 7/2010—Revision 0: Initial Version Rev. B | Page 2 of 20

Data Sheet AD5541A SPECIFICATIONS V = 2.7 V to 5.5 V, 2.5 V ≤ V ≤ V , AGND = DGND = 0 V, −40°C < T < +125°C,1 unless otherwise noted. DD REF DD A Table 2. Parameter Min Typ Max Unit Test Condition STATIC PERFORMANCE Resolution 16 Bits Relative Accuracy (INL) ±0.5 ±1.0 LSB B grade ±0.5 ±2.0 LSB A grade Differential Nonlinearity (DNL) ±0.5 ±1.0 LSB Guaranteed monotonic Gain Error 0.5 ±2 LSB T = 25°C A ±3 LSB −40°C < T < +85°C A ±4 LSB −40°C < T < +125°C A Gain Error Temperature Coefficient ±0.1 ppm/°C Zero-Code Error 0.3 ±0.7 LSB T = 25°C A ±1.5 LSB −40°C < T < +85°C A ±3 LSB −40°C < T < +125°C A Zero-Code Temperature Coefficient ±0.05 ppm/°C DC Power Supply Rejection Ratio ±1 LSB ΔV ± 10% DD OUTPUT CHARACTERISTICS2 Output Voltage Range 0 V − 1 LSB V Unipolar operation REF DAC Output Impedance 6.25 kΩ Tolerance typically 20% DAC REFERENCE INPUT3 Reference Input Range 2.0 V V DD Reference Input Resistance 9 kΩ Unipolar operation Reference Input Capacitance 26 pF Code 0x0000 26 pF Code 0xFFFF LOGIC INPUTS Input Current ±1 μA Input Low Voltage, VINL 0.4 V VLOGIC = 1.8 V to 5.5 V 0.8 V VLOGIC = 2.7 V to 5.5 V Input High Voltage, VINH 2.4 V VLOGIC = 4.5 V to 5.5 V 1.8 V VLOGIC = 2.7 V to 3.6 V 1.3 V VLOGIC = 1.8 V to 2.7 V Input Capacitance2 10 pF Hysteresis Voltage2 0.15 V POWER REQUIREMENTS V 2.7 5.5 V All digital inputs at 0 V, V , or V DD LOGIC DD I 125 150 µA V = V or V and V = GND DD IH LOGIC DD IL V 1.8 5.5 V LOGIC I 15 24 µA All digital inputs at 0 V, V , or V LOGIC LOGIC DD Power Dissipation 0.625 0.825 mW 1 For 2.7 V ≤ VLOGIC ≤ 5.5 V: −40°C < TA < +125°C. For 1.8 V ≤ VLOGIC ≤ 2.7 V: −40°C < TA < +105°C. 2 Guaranteed by design, but not subject to production test. 3 Reference input resistance is code-dependent, minimum at 0x8555. Rev. B | Page 3 of 20

AD5541A Data Sheet AC CHARACTERISTICS V = 2.7 V to 5.5 V, 2.5 V ≤ V ≤ V , AGND = DGND = 0 V, −40°C < T < +125°C, unless otherwise noted. DD REF DD A Table 3. Parameter Min Typ Max Unit Test Condition Output Voltage Settling Time 1 μs To ½ LSB of full scale, C = 10 pF L Slew Rate 17 V/μs C = 10 pF, measured from 0% to 63% L Digital-to-Analog Glitch Impulse 1.1 nV-sec 1 LSB change around major carry Reference −3 dB Bandwidth 2.2 MHz All 1s loaded Reference Feedthrough 1 mV p-p All 0s loaded, V = 1 V p-p at 100 kHz REF Digital Feedthrough 0.2 nV-sec Signal-to-Noise Ratio 92 dB Spurious Free Dynamic Range 80 dB Digitally generated sine wave at 1 kHz Total Harmonic Distortion 74 dB DAC code = 0xFFFF, frequency 10 kHz, V = 2.5 V ± 1 V p-p REF Output Noise Spectral Density 11.8 nV/√Hz DAC code = 0x0000, frequency = 1 kHz Output Noise 1.25 μV p-p 0.1 Hz to 10 Hz Rev. B | Page 4 of 20

Data Sheet AD5541A TIMING CHARACTERISTICS V = 5 V, 2.5 V ≤ V ≤ V , V = 90% of V , V = 10% of V , AGND = DGND = 0 V, −40°C < T < +105°C, unless otherwise DD REF DD INH LOGIC INL LOGIC A noted. Table 4. Limit at Limit at Parameter1,2 1.8 ≤ V ≤ 2.7 V 2.7 V ≤ V ≤ 5.5 V Unit Description LOGIC LOGIC f 14 50 MHz max SCLK cycle frequency SCLK t 70 20 ns min SCLK cycle time 1 t 35 10 ns min SCLK high time 2 t 35 10 ns min SCLK low time 3 t4 5 5 ns min CS low to SCLK high setup t5 5 5 ns min CS high to SCLK high setup t6 5 5 ns min SCLK high to CS low hold time t7 10 5 ns min SCLK high to CS high hold time t 35 10 ns min Data setup time 8 t 5 4 ns min Data hold time (V = 90% of V , V = 10% of V ) 9 INH DD INL DD t 5 5 ns min Data hold time (V = 3 V, V = 0 V) 9 INH INL t10 20 20 ns min LDAC pulse width t11 10 10 ns min CS high to LDAC low setup t12 15 15 ns min CS high time between active periods 1 Guaranteed by design and characterization. Not production tested. 2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. t1 SCLK t6 t2 t3 t5 t4 t7 CS t12 t8 t9 DIN DB15 t11 LDAC t10 08516-003 Figure 3. Timing Diagram Rev. B | Page 5 of 20

AD5541A Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 5. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to AGND −0.3 V to +6 V DD section of this specification is not implied. Operation beyond V to DGND −0.3 V to +6 V LOGIC the maximum operating conditions for extended periods may Digital Input Voltage to DGND −0.3 V to V /V + DD LOGIC affect product reliability. 0.3 V VOUT to AGND −0.3 V to VDD + 0.3 V ESD CAUTION AGND to DGND −0.3 V to +0.3 V Input Current to Any Pin Except Supplies ±10 mA Operating Temperature Range Industrial (A, B Versions) −40°C to +125°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature (T max) 150°C J Package Power Dissipation (T max − T )/θ J A JA Thermal Impedance, θ JA LFCSP (CP-10-9) 50°C/W LFCSP (CP-8-11) 62°C/W MSOP (RM-10) 135°C/W Lead Temperature, Soldering Peak Temperature1 260°C ESD2 5 kV 1 As per JEDEC Standard 20. 2 Human body model (HBM) classification. Rev. B | Page 6 of 20

Data Sheet AD5541A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 10 VLOGIC VOUT 2 AD5541A 9 DGND AGND 3 TOP VIEW 8 LDAC RCESF 45 (Not to Scale) 76 DSCINLK 08516-031 Figure 4. AD5541A 10-Lead MSOP Pin Configuration Table 6. AD5541A Pin Function Descriptions Pin No. Mnemonic Description 1 V Analog Supply Voltage. DD 2 V Analog Output Voltage from the DAC. OUT 3 AGND Ground Reference Point for Analog Circuitry. 4 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The reference can range from 2 V to V . DD 5 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 6 SCLK Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. The duty cycle must be between 40% and 60%. 7 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input register on the rising edge of SCLK. 8 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the serial register data. 9 DGND Digital Ground. Ground reference for digital circuitry. 10 V Logic Power Supply. LOGIC Rev. B | Page 7 of 20

AD5541A Data Sheet REF 1 8 GND VDD 1 10 VLOGIC VOUT 2 AD5541A 9 DGND CS 2 AD5541A-1 7 VDD AGND 3 TOP VIEW 8 LDAC TOP VIEW (Not to Scale) SCLK 3 (Not to Scale) 6 VOUT REF 4 7 DIN DIN 4 5 CLR CS 5 6 SCLK NOTES NOTES 1. FOR INCREASED RELIABILITY OF THE SOLDER 1. FOR INCREASED RELIABILITY OF THE SOLDER TJITOO I ISNT HTRESE ACSNOUDBM SMMTEARNXADITMEEUD, M GT NTHADHT.E RTMHEALP ACDA PBAEB SILOITLYD,ERED 08516-004 TJITOO I ISTN HTRESE ACSNOUDBM SMMTEARNXADITMEEUD, M GT NHTADHT.E RTMHEALP ACDA PBAEB SILOITLYD,ERED 08516-005 Figure 5. AD5541A-1 8-Lead LFCSP Pin Configuration Figure 6. AD5541A 10-Lead LFCSP Pin Configuration Table 7. AD5541A-1 and AD5541A Pin Function Descriptions Pin No. 8-Lead LFCSP 10-Lead LFCSP Mnemonic Description 1 4 REF Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. The reference can range from 2 V to V . DD 2 5 CS Logic Input Signal. The chip select signal is used to frame the serial data input. 3 6 SCLK Clock Input. Data is clocked into the serial input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. 4 7 DIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the serial input register on the rising edge of SCLK. 5 N/A1 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the serial input register and the DAC register are cleared to zero scale. 6 2 V Analog Output Voltage from the DAC. OUT N/A1 9 DGND Digital Ground. Ground reference for digital circuitry. 7 1 V Analog Supply Voltage. DD 8 N/A1 GND Ground Reference Point for Both Analog and Digital Circuitry. N/A1 3 AGND Ground Reference Point for Analog Circuitry. N/A1 10 V Logic Power Supply. LOGIC N/A1 8 LDAC LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the serial input register. EPAD Exposed Pad. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, GND. 1 N/A means not applicable. Rev. B | Page 8 of 20

Data Sheet AD5541A TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0.50 VDD = 5V VDD = 5V VREF = 2.5V B) VREF = 2.5V TY (LSB) 0.25 RITY (LS 0.25 NEARI 0 LINEA AL NONLI–0.25 TIAL NON 0 R N INTEG–0.50 DIFFERE–0.25 –0.750 8192 16,384 24,576 3C2O,7D6E8 40,960 49,152 57,344 65,536 08516-006 –0.500 8192 16,384 24,576 3C2O,7D6E8 40,960 49,152 57,344 65,536 08516-009 Figure 7. Integral Nonlinearity vs. Code Figure 10. Differential Nonlinearity vs. Code 0.25 0.75 VDD = 5V VDD = 5V VREF = 2.5V B) VREF = 2.5V TY (LSB) 0 RITY (LS 0.50 NEARI–0.25 LINEA 0.25 AL NONLI–0.50 TIAL NON 0 R N INTEG–0.75 DIFFERE–0.25 –1.00–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 08516-007 –0.50–60 –40 –20 0 TEM20PERA4T0URE6 (0°C) 80 100 120 140 08516-010 Figure 8. Integral Nonlinearity vs. Temperature Figure 11. Differential Nonlinearity vs. Temperature 0.50 0.75 VREF = 2.5V VDD = 5V TA = 25°C TA = 25°C 0.25 0.50 B) DNL B) DNL S S L L OR ( 0 OR ( 0.25 R R R R E E Y Y T T RI–0.25 RI 0 A A NE NE INL LI LI –0.50 –0.25 INL –0.752 3 SUPP4LY VOLTAG5E (V) 6 708516-008 –0.500 1 RE2FERENCE 3VOLTAGE4 (V) 5 6 08516-011 Figure 9. Linearity Error vs. Supply Voltage Figure 12. Linearity Error vs. Reference Voltage Rev. B | Page 9 of 20

AD5541A Data Sheet 3 1.5 2 VVTADR DE=F = 2= 55 °2VC.5V 1.0 VTVADR DE=F = 2= 55 °2VC.5V B) S SB) 1 R (L 0.5 RROR (L 0 E ERRO 0 E D GAIN –1 RO-CO–0.5 E Z –2 –1.0 ––3100 –50 TEM0PERATURE5 0(°C) 100 150 08516-012 –1.5–55 –5 TEMPERATU4R5E (°C) 95 08516-015 Figure 13. Gain Error vs. Temperature Figure 16. Zero-Code Error vs. Temperature 160 200 VDD = 5V TA = 25°C 140 VTAR E=F 2=5 °2C.5V SUPPLY CURRENT (µA) 110246800000 SUPPLY CURRENT (µA) 11055000 RVDEDF E=R 5EVNCE VOLTASVGUREEPFP =L Y2 .V5VOLTAGE 20 0–55 –5 TEMPERATU4R5E (°C) 95 08516-013 00 1 2 VOLTA3GE (V) 4 5 6 08516-016 Figure 14. Supply Current vs. Temperature Figure 17. Supply Current vs. Reference Voltage or Supply Voltage 200 200 VDD = 5V 180 VREF = 2.5V TA = 25°C 160 A)150 CURRENT (µA)111024000 E CURRENT (µ100 PPLY 80 RENC SU 60 EFE 50 R 40 20 0 1.0 1.1 1.2 DI1G.3ITA1L. 4INPU1.T5 VO1L.T6AG1E. 7(V)1.8 1.9 2.0 08516-014 00 10,000 20,000 C3O0,D00E0 (De4c0i,m00a0l) 50,000 60,000 70,000 08516-017 Figure 15. Supply Current vs. Digital Input Voltage Figure 18. Reference Current vs. Code Rev. B | Page 10 of 20

Data Sheet AD5541A VREF = 2.5V VREF = 2.5V VDD = 5V VDD = 5V TA = 25°C TA = 25°C 100 DIN (5V/DIV) 100•••• •••• •••• •••• •••• •••• •••• •••• •••• •••• VOUT (1V/DIV) 90 90 VOUT (50mV/DIV) VOUT (50mV/DIV) GAIN = –216 10 10 1LSB = 8.2mV 0% 0%•••• •••• •••• •••• •••• •••• •••• •••• •••• •••• 2µs/DIV 08516-018 0.5µs/DIV 08516-021 Figure 19. Digital Feedthrough Figure 22. Small Signal Settling Time 1.236 5 5 +125°C CS +25°C 0 –55°C 1.234 4 –5 1.232 E (V) –10 S 3 TAG1.230 HIT VOL –15 2 1.228 VOUT –20 1 1.226 –25 1.22–40.5 0 0.5TIME (ns)1.0 1.5 2.0–30 08516-032 0 90 100IDD SUPPLY1 (1µ0A) 120 08516-038 Figure 20. Digital-to-Analog Glitch Impulse Figure 23. Analog Supply Current Histogram 6 +125°C +25°C 2µs/DIV VVRDEDF = = 5 2V.5V 5 –55°C TA = 25°C CS (5V/DIV) 100•••• •••• •••• •••• •••• •••• •••• •••• •••• •••• 90 4 10pF S 50pF HIT3 100pF 2 200pF 10 1 0%•••• •••• •••• •••• •••• •••• •••• •••• •••• •••• VOUT (0.5V/DIV) 08516-020 0 15 16 ILOGIC1 A7T RAILS (µ1A8) 19 08516-039 Figure 21. Large Signal Settling Time Figure 24. Digital Supply Current Histogram Rev. B | Page 11 of 20

AD5541A Data Sheet 1.5 40 1.0 20 ms) 0 V r 0.5 E (µ Bm) –20 NOIS 0 (dUT UT VO–40 TP –0.5 OU –60 –1.0 –80 –1.50 20 40TIME (Se6c0onds) 80 100 08516-033 –1000 10,000 20,000 F3R0E,0Q0U0EN4C0Y,0 (0H0z) 50,000 60,000 70,000 08516-036 Figure 25. 0.1 Hz to 10 Hz Output Noise Figure 28. Total Harmonic Distortion 40 10 Hz)35 0 s/ m V r30 –10 n TY (25 Bm) DENSI20 (dREF–20 CTRAL 15 V/VOUT–30 PE –40 S10 E S NOI 5 –50 0600 700 800 9F0R0EQU1E0N00CY (H11z0)0 1200 1300 1400 08516-034 –601k 10k F1R00EkQUENCY (1HMz) 10M 100M 08516-037 Figure 26. Noise Spectral Density vs. Frequency,1 kHz Figure 29. Multiplying Bandwidth 14 Hz)12 s/ m V r10 n Y ( T SI 8 N E D AL 6 R T C E P 4 S E S OI 2 N 90600 9700 9800 99F0R0EQ1U0E,0N0C0Y 1(H0,z1)00 10,200 10,300 10,400 08516-035 Figure 27. Noise Spectral Density vs. Frequency, 10 kHz Rev. B | Page 12 of 20

Data Sheet AD5541A TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy or Integral Nonlinearity (INL) Digital-to-analog glitch impulse is the impulse injected into the For the DAC, relative accuracy or INL is a measure of the analog output when the input code in the DAC register changes maximum deviation, in LSBs, from a straight line passing state. It is normally specified as the area of the glitch in nV-sec through the endpoints of the DAC transfer function. A typical and is measured when the digital input code is changed by INL vs. code plot is shown in Figure 7. 1 LSB at the major carry transition. A digital-to-analog glitch Differential Nonlinearity (DNL) impulse plot is shown in Figure 20. DNL is the difference between the measured change and the Digital Feedthrough ideal 1 LSB change between any two adjacent codes. A specified Digital feedthrough is a measure of the impulse injected into differential nonlinearity of ±1 LSB maximum ensures mono- the analog output of the DAC from the digital inputs of the tonicity. A typical DNL vs. code plot is shown in Figure 10. DAC, but it is measured when the DAC output is not updated. Gain Error CS is held high while the SCLK and DIN signals are toggled. It Gain error is the difference between the actual and ideal analog is specified in nV-sec and is measured with a full-scale code output range, expressed as a percent of the full-scale range. change on the data bus, that is, from all 0s to all 1s and vice It is the deviation in slope of the DAC transfer characteristic versa. A typical digital feedthrough plot is shown in Figure 19. from ideal. Power Supply Rejection Ratio (PSRR) Gain Error Temperature Coefficient PSRR indicates how the output of the DAC is affected by changes Gain error temperature coefficient is a measure of the change in the power supply voltage. The power supply rejection ratio is in gain error with changes in temperature. It is expressed in expressed in terms of percent change in output per percent ppm/°C. change in V for full-scale output of the DAC. V is varied by DD DD Zero-Code Error ±10%. Zero-code error is a measure of the output error when zero Reference Feedthrough code is loaded to the DAC register. Reference feedthrough is a measure of the feedthrough from the Zero-Code Temperature Coefficient V input to the DAC output when the DAC is loaded with all REF This is a measure of the change in zero-code error with a 0s. A 100 kHz, 1 V p-p is applied to V . Reference feedthrough REF change in temperature. It is expressed in mV/°C. is expressed in mV p-p. Rev. B | Page 13 of 20

AD5541A Data Sheet THEORY OF OPERATION The AD5541A is a single, 16-bit, serial input, voltage output SERIAL INTERFACE DAC. It operates from a single supply ranging from 2.7 V to 5 V The AD5541A is controlled by a versatile 3- or 4-wire serial and consumes typically 125 µA with a supply of 5 V. Data is written interface that operates at clock rates of up to 50 MHz and is to these devices in a 16-bit word format, via a 3- or 4-wire serial compatible with SPI, QSPI, MICROWIRE, and DSP interface interface. To ensure a known power-up state, this part is designed standards. The timing diagram is shown in Figure 3. The with a power-on reset function. The output is reset to 0 V. AD5541A has a separate serial input register from the 16-bit DIGITAL-TO-ANALOG SECTION DAC register that allows preloading of a new data value into the serial input register without disturbing the present DAC output The DAC architecture consists of two matched DAC sections. voltage. A simplified circuit diagram is shown in Figure 30. The DAC architecture of the AD5541A is segmented. The four MSBs of Input data is framed by the chip select input, CS. After a high- the 16-bit data-word are decoded to drive 15 switches, E1 to to-low transition on CS, data is shifted synchronously and E15. Each switch connects one of 15 matched resistors to either latched into the serial input register on the rising edge of the AGND or VREF. The remaining 12 bits of the data-word drive serial clock, SCLK. After 16 data bits have been loaded into the the S0 to S11 switches of a 12-bit voltage mode R-2R ladder serial input register, a low-to-high transition on CS transfers the network. contents of the shift register to the DAC register if LDAC is held R R VOUT low. If LDAC is high at this point, a low-to-high transition on CS transfers the contents into the serial input register only. 2R 2R 2R . . . . . 2R 2R 2R . . . . . 2R After a new value is fully loaded in the serial input register, it S0 S1 . . . . . S11 E1 E2 . . . . . E15 can be asynchronously transferred to the DAC register by VREF strobing the LDAC pin. Data is loaded MSB first in 16-bit words. Data can be loaded to the part only while CS is low. 12-BIT R-2R LADDER INTFOO U15R EMQSUBAsL D SEECGOMDEENDTS 08516-022 Figure 30. DAC Architecture With this type of DAC configuration, the output impedance is independent of code, whereas the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage, as shown in the following equation: V ×D V = REF OUT 2N where: D is the decimal data-word loaded to the DAC register. N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following: 2.5×D V = OUT 65,536 This gives a V of 1.25 V with midscale loaded and 2.5 V with OUT full scale loaded to the DAC. The LSB size is V /65,536. REF Rev. B | Page 14 of 20

Data Sheet AD5541A UNIPOLAR OUTPUT OPERATION OUTPUT AMPLIFIER SELECTION This DAC is capable of driving unbuffered loads of 60 kΩ. For bipolar mode, a precision amplifier should be used and Unbuffered operation results in low supply current, typically supplied from a dual power supply. This provides the ±V REF 300 μA, and a low offset error. The AD5541A provides a output. In a single-supply application, selection of a suitable unipolar output swing ranging from 0 V to V − 1 LSB. op amp may be more difficult because the output swing of the REF Figure 31 shows a typical unipolar output voltage circuit. The amplifier does not usually include the negative rail, in this case, code table for this mode of operation is shown in Table 8. The AGND. This can result in some degradation of the specified example includes the ADR421 2.5 V reference and the AD8628 performance unless the application does not use codes near zero. low offset and zero-drift reference buffer. The selected op amp must have a very low offset voltage (the Table 8. Unipolar Code Table DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need DAC Latch Contents for output offset trims. Input bias current should also be very MSB LSB Analog Output low because the bias current, multiplied by the DAC output 1111 1111 1111 1111 V × (65,535/65,536) impedance (approximately 6 kΩ), adds to the zero-code error. REF 1000 0000 0000 0000 V × (32,768/65,536) = ½ V Rail-to-rail input and output performance is required. For fast REF REF 0000 0000 0000 0001 V × (1/65,536) settling, the slew rate of the op amp should not impede the REF 0000 0000 0000 0000 0 V settling time of the DAC. Output impedance of the DAC is constant and code independent, but to minimize gain errors, Assuming a perfect reference, the unipolar worst-case output the input impedance of the output amplifier should be as high voltage can be calculated from the following equation: as possible. The amplifier should also have a 3 dB bandwidth of V = D ×(V +V )+V +INL 1 MHz or greater. The amplifier adds another time constant to OUT−UNI 216 REF GE ZSE the system, thus increasing the settling time of the output. A where: higher 3 dB amplifier bandwidth results in a shorter effective V is the unipolar mode worst-case output. settling time of the combined DAC and amplifier. OUT−UNI D is the code loaded to DAC. V is the reference voltage applied to the part. REF V is the gain error in volts. GE V is the zero-scale error in volts. ZSE INL is the integral nonlinearity in volts. 5V 1µF 0.1µF 2 AD8628 VIN VOUT 6 1+0µF 5V ADR421 0.1µF 0.1µF 4 SERIAL INTERFACE VDD REF CS AD820/ OP196 UNIPOLAR DIN AD5541A VOUT OUTPUT SCLK EXTERNAL DGND AGND OPAMP 08516-023 Figure 31. Unipolar Output Rev. B | Page 15 of 20

AD5541A Data Sheet FORCE SENSE AMPLIFIER SELECTION POWER-ON RESET Use single-supply, low noise amplifiers. A low output impedance at The AD5541A has a power-on reset function to ensure that the high frequencies is preferred because the amplifiers must be output is at a known state on power-up. On power-up, the DAC able to handle dynamic currents of up to ±20 mA. register contains all 0s until the data is loaded from the serial REFERENCE AND GROUND register. However, the serial register is not cleared on power-up; therefore, its contents are undefined. When loading data initially Because the input impedance is code dependent, drive the refer- to the DAC, 16 bits or more should be loaded to prevent erroneous ence pin from a low impedance source. The AD5541A operates data appearing on the output. If more than 16 bits are loaded, with a voltage reference ranging from 2 V to V . References DD the last 16 are kept, and if less than 16 bits are loaded, bits remain below 2 V result in reduced accuracy. The full-scale output from the previous word. If the AD5541A must be interfaced voltage of the DAC is determined by the reference. Table 8 with data shorter than 16 bits, pad the data with 0s at the LSBs. outlines the analog output voltage or particular digital codes. POWER SUPPLY AND REFERENCE BYPASSING If the application does not require separate force and sense For accurate high resolution performance, it is recommended lines, tie the lines close to the package to minimize voltage that the reference and supply pins be bypassed with a 10 μF drops between the package leads and the internal die. tantalum capacitor in parallel with a 0.1 μF ceramic capacitor. Rev. B | Page 16 of 20

Data Sheet AD5541A APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING LAYOUT GUIDELINES Microprocessor interfacing to the AD5541A is via a serial bus In any circuit where accuracy is important, careful consider- that uses standard protocol that is compatible with DSP proces- ation of the power supply and ground return layout helps to sors and microcontrollers. The communications channel requires ensure the rated performance. Design the printed circuit board a 3- or 4-wire interface consisting of a clock signal, a data signal, (PCB) on which the AD5541A is mounted so that the analog and a synchronization signal. The AD5541A requires a 16-bit and digital sections are separated and confined to certain areas data-word with data valid on the rising edge of SCLK. of the board. If the AD5541A is in a system where multiple devices require an analog ground-to-digital ground connection, AD5541A TO ADSP-BF531 INTERFACE make the connection at one point only. Establish the star The SPI interface of the AD5541A is designed to be easily ground point as close as possible to the device. connected to industry-standard DSPs and microcontrollers. The AD5541A should have ample supply bypassing of 10 μF Figure 32 shows how the AD5541A can be connected to the in parallel with 0.1 μF on each supply located as close to the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an package as possible, ideally right up against the device. The integrated SPI port that can be connected directly to the SPI 10 μF capacitors are the tantalum bead type. The 0.1 μF capaci- pins of the AD5541A. tor should have low effective series resistance (ESR) and low AD5541A effective series inductance (ESI), such as the common ceramic SPISELx CS types, which provide a low impedance path to ground at high SCK SCLK frequencies to handle transient currents due to internal logic MOSI DIN switching. ADSP-BF531 GALVANICALLY ISOLATED INTERFACE PF9 LDAC 08516-040 Iann misoanlayt iporno bceasrsr iceor nbtertowl eaepnp ltihcaet cioonnst,r oitl liesr n aencde stshaer yu ntoit p breoivnigd e Figure 32. AD5541A to ADSP-BF531 Interface controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. iCoupler® AD5541A TO SPORT INTERFACE products from Analog Devices provide voltage isolation in excess The Analog Devices ADSP-BF527 has one SPORT serial port. of 2.5 kV. The serial loading structure of the AD5541A makes Figure 33 shows how one SPORT interface can be used to the part ideal for isolated interfaces because the number of control the AD5541A. interface lines is kept to a minimum. Figure 34 shows a 4-channel isolated interface to the AD5541A using an ADuM1400. For AD5541A SPORT_TFS CS further information, visit http://www.analog.com/icouplers. SPORT_TSCK SCLK CONTROLLER ADuM14001 SPORT_DTO DIN SERIAL VIA VOA TO CLOCK IN ENCODE DECODE SCLK ADSP-BF527 GPIO0 LDAC 08516-041 DASTAE ROIAUTL VIB ENCODE DECODE VOB TDOIN Figure 33. AD5541A to SPORT Interface SYNC OUT VIC ENCODE DECODE VOC TCOS LOAD DOAUCT VID ENCODE DECODE VOD TLODAC 1ADDITIONAL PINS OMITTED FOR CLARITY. 08516-042 Figure 34. Isolated Interface Rev. B | Page 17 of 20

AD5541A Data Sheet DECODING MULTIPLE DACS AD5541A SCLK The CS pin of the AD5541A can be used to select one of a CS number of DACs. All devices receive the same serial clock and DIN DIN VOUT VDD SCLK serial data, but only one device receives the CS signal at any one time. The DAC addressed is determined by the decoder. There is ENABLE EN AD5541A some digital feedthrough from the digital input lines. Using a CS burst clock minimizes the effects of digital feedthrough on the ADCDORDEESDS DECODER DIN VOUT analog signal channels. Figure 35 shows a typical circuit. SCLK DGND AD5541A CS DIN VOUT SCLK AD5541A CS DSCINLK VOUT 08516-030 Figure 35. Addressing Multiple DACs Rev. B | Page 18 of 20

Data Sheet AD5541A OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA A091709- Figure 36. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters DETAIL A (JEDEC 95) 2.48 2.38 3.10 2.23 3.00 SQ 2.90 0.50 BSC 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 0.20 MIN TOP VIEW BOTTOM VIEW PININD I1CATOR AREA OPTIONS (SEE DETAIL A) 0.80 FOR PROPER CONNECTION OF 0.75 SIDE VIEW 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. PKG-004362 SEPALTAINNGE 000...322050 0.20 REF 0.08 02-07-2017-C Figure 37. 10-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-10-9) Dimensions shown in millimeters Rev. B | Page 19 of 20

AD5541A Data Sheet DETAIL A (JEDEC 95) 2.44 3.10 2.34 3.00 SQ 2.24 2.90 0.50 BSC 5 8 PIN 1 INDEX 1.70 AREA EXPPAODSED 1.60 0.50 1.50 0.40 4 11 0.30 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR AREA OPTIONS (SEE DETAIL A) 0.80 0.75 SIDE VIEW 0.05 MAX FTOHER EPXRPOOPSEERD C POANDN, ERCETFIEORN TOOF 0.70 0.02 NOM THE PIN CONFIGURATION AND COPLANARITY FUNCTION DESCRIPTIONS SEATING 0.30 0.08 SECTION OF THIS DATA SHEET PKG-005136 PLANE CO00..M2250PLIANTTOJEDEC S0.T2A0N3 DRAERFDS MO-229-W3030D-4 02-10-2017-C Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-11) Dimensions shown in millimeters ORDERING GUIDE Power-On Package Marking Model1 INL DNL Reset to Code Temperature Range Package Description Option Code AD5541ABRMZ ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DEQ AD5541ABRMZ-REEL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DEQ AD5541AARMZ ±2 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DER AD5541AARMZ-REEL7 ±2 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead MSOP RM-10 DER AD5541AACPZ-REEL7 ±2 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead LFCSP CP-10-9 DER AD5541ABCPZ-REEL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead LFCSP CP-10-9 DEQ AD5541ABCPZ-500RL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 10-Lead LFCSP CP-10-9 DEQ AD5541ABCPZ-1-RL7 ±1 LSB ±1 LSB Zero Scale −40°C to +125°C 8-Lead LFCSP CP-8-11 DFG EVAL-AD5541ASDZ AD5541A Evaluation Board 1 Z = RoHS Compliant Part. ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08516-0-4/18(B) Rev. B | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5541ASDZ AD5541AACPZ-REEL7 AD5541ABCPZ-1-RL7 AD5541ABRMZ-REEL7 AD5541ABRMZ AD5541AARMZ-REEL7 AD5541AARMZ AD5541ABCPZ-REEL7 AD5541AR AD5541ARZ-REEL7 AD5541ARZ