a 32-Channel, 14-Bit DAC with Precision Infinite Sample-and-Hold Mode AD5532B* FEATURES GENERAL DESCRIPTION High Integration: The AD5532B is a 32-channel, voltage output, 14-bit DAC with 32-Channel DAC in 12 mm (cid:1) 12 mm CSPBGA an additional precision infinite sample-and-hold mode. The Guaranteed Monotonic to 14 Bits selected DAC register is written to via the 3-wire serial inter- Infinite Sample-and-Hold Capability to (cid:2)0.018% Accuracy face and V for this DAC is then updated to reflect the new OUT Infinite Sample-and-Hold Total Unadjusted Error (cid:2)2.5mV contents of the DAC register. DAC selection is accomplished via Adjustable Voltage Output Range address bits A0–A4. The output voltage range is determined by Readback Capability the offset voltage at the OFFS_IN pin and the gain of the DSP/Microcontroller Compatible Serial Interface output amplifier. It is restricted to a range from V + 2 V to SS Output Impedance 0.5 (cid:3) V – 2 V because of the headroom of the output amplifier. DD Output Voltage Span 10 V The device is operated with AV = +5 V ± 5%, DV = +2.7V Temperature Range –40(cid:4)C to +85(cid:4)C CC CC to +5.25 V, V = –4.75 V to –16.5 V, and V = +8 V to +16.5V SS DD APPLICATIONS and requires a stable 3 V reference on REF_IN as well as an Automatic Test Equipment offset voltage on OFFS_IN. Optical Networks Level Setting PRODUCT HIGHLIGHTS Instrumentation 1. 32-channel, 14-bit DAC in one package, guaranteed Industrial Control Systems monotonic. Data Acquisition 2. The AD5532B is available in a 74-lead CSPBGA with a body Low Cost I/O size of 12 mm (cid:1) 12 mm. 3. In infinite sample-and-hold mode, a total unadjusted error of ±2.5 mV is achieved by laser-trimming on-chip resistors. FUNCTIONAL BLOCK DIAGRAM DVCC AVCC REF IN REF OUT OFFS IN VDD VSS AD5532B VOUT 0 VIN ADC DAC TRACK/RESET 14-BIT BUSY BUS VOUT 31 DAC GND MUX DAC AGND OFFS OUT DAC DGND MODE INTERFACE SER/ PAR CONTROL LOGIC ADDRESS INPUT REGISTER WR SCLK DIN DOUT SYNC/CS A4–A0 CAL OFFSET_SEL *Protected by U.S. Patent No. 5,969,657. REV.A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD5532B–SPECIFICATIONS (V = +8 V to +16.5 V, V = –4.75 V to –16.5 V; AV = +4.75 V to +5.25 V; DD SS CC DV = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; CC OFFS_IN = OV; Output Range from V + 2 V to V – 2 V. All outputs unloaded. All specifications T to T , unless otherwise noted.) SS DD MIN MAX AD5532B-1 Parameter1 B Version2 Unit Conditions/Comments DAC DC PERFORMANCE Resolution 14 Bits Integral Nonlinearity (INL) ±0.39 % of FSR max ±0.15% typ Differential Nonlinearity (DNL) ±1 LSB max ±0.5 LSB typ Monotonic Offset 90/170/250 mV min/typ/max See Figure 6. Gain 3.52 typ Full-Scale Error –1/+0.5 % of FSR max ISHA DC PERFORMANCE V to V Nonlinearity3 ±0.006 % typ After Offset and Gain Adjustment IN OUT ±0.018 % max Total Unadjusted Error (TUE) ±2.5 mV typ See TPC 6. ±12 mV max Offset Error ±1 mV typ ±10 mV max Gain 3.51/3.52/3.53 min/typ/max ISHA ANALOG INPUT (V ) IN Input Voltage Range 0 to 3 V Nominal Input Range Input Lower Dead Band 70 mV max 50 mV typ. Referred to V . IN See Figure 7. Input Upper Dead Band 40 mV max 12 mV typ. Referred to V . IN See Figure 7. Input Current 1 µA max 100 nA typ. V acquired IN onone channel. Input Capacitance4 20 pF typ ANALOG INPUT (OFFS_IN) Input Current 1 µA max 100 nA typ Input Voltage Range 0/4 V min/max Output Range Restricted from V + 2 V to V – 2 V SS DD VOLTAGE REFERENCE REF_IN Nominal Input Voltage 3.0 V typ Input Voltage Range4 2.85/3.15 V min/max Input Current 1 µA max <1 nA typ REF_OUT Output Voltage 3 V typ Output Impedance4 280 kΩ typ Reference Temperature Coefficient4 60 ppm/°C typ ANALOG OUTPUTS (V 0–31) OUT Output Temperature Coefficient4, 5 10 ppm/°C typ DC Output Impedance4 0.5 Ω typ Output Range V + 2/V – 2 V min/max 100 µA Output Load SS DD Resistive Load4, 6 5 kΩ min Capacitive Load4, 6 100 pF max Short-Circuit Current4 7 mA typ DC Power-Supply Rejection Ratio4 –70 dB V = +15 V ± 5% DD –70 dB V =(cid:1)15 V ± 5% SS DC Crosstalk4 250 µV max Outputs Loaded ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient4, 5 10 ppm/°C typ DC Output Impedance4 1.3 kΩ typ Output Range 50 to REF_IN – 12 mV typ Output Current 10 µA max Source Current Capacitive Load 100 pF max –2– REV. A

AD5532B AD5532B-1 Parameter1 B Version2 Unit Conditions/Comments DIGITAL INPUTS7 Input Current ±10 µA max ±5 µA typ Input Low Voltage 0.8 V max DV = 5 V ± 5% CC 0.4 V max DV = 3 V ± 10% CC Input High Voltage 2.4 V min DV = 5 V ± 5% CC 2.0 V min DV = 3 V ± 10% CC Input Hysteresis (SCLK and CS Only) 200 mV typ Input Capacitance 10 pF max DIGITAL OUTPUTS (BUSY, D )7 OUT Output Low Voltage, DV = 5 V 0.4 V max Sinking 200 µA CC Output High Voltage, DV = 5 V 4.0 V min Sourcing 200 µA CC Output Low Voltage, DV = 3 V 0.4 V max Sinking 200 µA CC Output High Voltage, DV = 3 V 2.4 V min Sourcing 200 µA CC High Impedance Leakage Current ±1 µA max D Only OUT High Impedance Output Capacitance 15 pF typ D Only OUT POWER REQUIREMENTS Power Supply Voltages V 8/16.5 V min/max DD V –4.75/–16.5 V min/max SS AV 4.75/5.25 V min/max CC DV 2.7/5.25 V min/max CC Power Supply Currents8 I 15 mA max 10 mA typ. All channels full-scale. DD I 15 mA max 10 mA typ. All channels full-scale. SS AICC 33 mA max 26 mA typ DICC 1.5 mA max 1 mA typ Power Dissipation8 280 mW typ V = +10 V, V = –5 V DD SS NOTES 1See Terminology section. 2B Version: Industrial temperature range –40°C to +85°C; typical at +25°C. 3Input range 100 mV to 2.96 V. 4Guaranteed by design and characterization, not production tested. 5AD780 as reference for the AD5532B. 6Ensure that you do not exceed T (max). See Absolute Maximum Ratings section. J 7Guaranteed by design and characterization, not production tested. 8Output unloaded. Specifications subject to change without notice. REV. A –3–

AD5532B AC CHARACTERISTICS (V = +8 V to +16.5 V, V = –4.75 V to –16.5 V; AV = +4.75 V to +5.25 V; DV = +2.7 V to +5.25 V; DD SS CC CC AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications T to T , unless otherwise noted.) MIN MAX AD5532B-1 Parameter1 B Version2 Unit Conditions/Comments DAC AC CHARACTERISTICS3 Output Voltage Settling Time 22 µs max 500 pF, 5 kΩ Load Full-Scale Change OFFS_IN Settling Time 10 µs max 500 pF, 5 kΩ Load; 0 V to 3 V Step Digital-to-Analog Glitch Impulse 1 nV-styp 1 LSB Change Around Major Carry Digital Crosstalk 5 nV-styp Analog Crosstalk 1 nV-styp Digital Feedthrough 0.2 nV-styp Output Noise Spectral Density @ 1 kHz 400 nV/√Hz typ ISHA AC CHARACTERISTICS Output Voltage Settling Time3 3 µs max Outputs Unloaded Acquisition Time 16 µs max AC Crosstalk3 5 nV-styp NOTES 1See Terminology section. 2B Version: Industrial temperature range –40°C to +85°C; typical at +25°C. 3Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. TIMING CHARACTERISTICS PARALLEL INTERFACE Limit at T , T MIN MAX Parameter1, 2 (B Version) Unit Conditions/Comments t 0 ns min CS to WR Setup Time 1 t 0 ns min CS to WR Hold Time 2 t 50 ns min CS Pulsewidth Low 3 t 50 ns min WR Pulsewidth Low 4 t 20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time 5 t 7 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time 6 NOTES 1See Parallel Interface Timing Diagram. 2Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. SERIAL INTERFACE Limit at T , T MIN MAX Parameter1, 2 (B Version) Unit Conditions/Comments f 3 14 MHz max SCLK Frequency CLKIN t 28 ns min SCLK High Pulsewidth 1 t 28 ns min SCLK Low Pulsewidth 2 t 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time 3 t 50 ns min SYNC Low Time 4 t 15 ns min D Setup Time 5 IN t 5 ns min D Hold Time 6 IN t 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback 7 t 4 20 ns max SCLK Rising Edge to D Valid 8 OUT t 4 60 ns max SCLK Falling Edge to D High Impedance 9 OUT t 400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback 10 t 400 ns min 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write 11 t 5 7 ns min SCLK Falling Edge to SYNC Falling Edge for Readback 12 NOTES 1See Serial Interface Timing Diagrams. 2Guaranteed by design and characterization, not production tested. 3In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns. 4These numbers are measured with the load circuit of Figure 2. 5SYNC should be taken low while SCLK is low for readback. Specifications subject to change without notice. –4– REV. A

AD5532B PARALLEL INTERFACE TIMING DIAGRAM CS 200(cid:5)A IOL WR TO OUTPUT 1.6V PIN CL 50pF A4–A0, CAL, OFFS SEL 200(cid:5)A IOH Figure 1.Parallel Write (ISHA Mode Only) Figure 2.Load Circuit for D Timing Specifications OUT SERIAL INTERFACE TIMING DIAGRAMS t 1 SCLK 1 2 3 4 5 6 7 8 9 10 t3 t2 SYNC t4 t5 t 6 DIN MSB LSB Figure 3.10-Bit Write (ISHA Mode and Both Readback Modes) t 1 SCLK 1 2 3 4 5 21 22 23 24 1 t3 t2 SYNC t4 t5 t11 t 6 DIN MSB LSB Figure 4.24-Bit Write (DAC Mode) t7 t1 SCLK 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 t t 12 2 SYNC t10 t4 t t 8 9 DOUT MSB LSB Figure 5.14-Bit Read (Both Readback Modes) REV. A –5–

AD5532B ABSOLUTE MAXIMUM RATINGS1, 2 Max Continuous Load Current at T = 70°C, J (T = 25°C, unless otherwise noted.) per Channel Group . . . . . . . . . . . . . . . . . . . . . . . 15.5 mA4 A VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V NOTES V to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V 1Stresses above those listed under Absolute Maximum Ratings may cause perma- SS AV to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V nent damage to the device. This is a stress rating only; functional operation of the CC device at these or any other conditions above those listed in the operational DV to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V CC sections of this specification is not implied. Exposure to absolute maximum rating Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV + 0.3 V CC conditions for extended periods may affect device reliability. Digital Outputs to DGND . . . . . . . . . –0.3 V to DVCC + 0.3 V 2Transient currents of up to 100 mA will not cause SCR latch-up. REF_IN to AGND, DAC_GND . . . . –0.3 V to AV + 0.3 V 3This limit includes load power. CC V to AGND, DAC_GND . . . . . . . . –0.3 V to AV + 0.3 V 4This maximum allowed continuous load current is spread over eight channels, IN CC with channels grouped as follows: V 0–31 to AGND . . . . . . . . . . V – 0.3 V to V + 0.3 V OUT SS DD Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10 OFFS_IN to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Group 2: Channels 14, 16, 18, 20, 21, 24, 25, 26 OFFS_OUT to AGND . . . . AGND – 0.3 V to AV + 0.3 V Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29 CC AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31 Operating Temperature Range For higher junction temperatures, derate as follows: Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Max Continuous Junction Temperature (T max) . . . . . . . . . . . . . . . . . . 150°C Load Current 74-Lead CSPBGA PackagJe, θ Thermal Impedance . . 41°C/W TJ (°C) per Group (mA) JA Reflow Soldering 70 1.55 Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C 90 9.025 100 6.925 Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec 110 5.175 Max Power Dissipation . . . . . . . . . . . . (150°C – T )/θ mW3 A JA 125 3.425 135 2.55 150 1.5 ORDERING GUIDE Output Output Impedance Voltage Span Package Package Model Function (Typ) (V) Description Option AD5532BBC-1 32 DACs, 32-Channel Precision ISHA 0.5 Ω 10 74-Lead CSPBGA BC-74 AD5532ABC-1* 32 DACs, 32-Channel ISHA 0.5 Ω 10 74-Lead CSPBGA BC-74 AD5532ABC-2* 32 DACs, 32-Channel ISHA 0.5 Ω 20 74-Lead CSPBGA BC-74 AD5532ABC-3* 32 DACs, 32-Channel ISHA 500 Ω 10 74-Lead CSPBGA BC-74 AD5532ABC-5* 32 DACs, 32-Channel ISHA 1 kΩ 10 74-Lead CSPBGA BC-74 AD5533ABC-1* 32-Channel ISHA Only 0.5 Ω 10 74-Lead CSPBGA BC-74 AD5533BBC-1* 32-Channel Precision ISHA Only 0.5 Ω 10 74-Lead CSPBGA BC-74 EVAL-AD5532EB Evaluation Board *Separate Data Sheet. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5532B features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –6– REV. A

AD5532B PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E F F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 74-Lead CSPBGA Ball Configuration CSPBGA Ball CSPBGA Ball CSPBGA Ball Number Name Number Name Number Name A1 NC* C10 AVCC1 J10 VO9 A2 A4 C11 REF_OUT J11 VO11 A3 A2 D1 VO20 K1 VO17 A4 A0 D2 DAC_GND2 K2 VO15 A5 CS/SYNC D10 AVCC2 K3 VO27 A6 DVCC D11 OFFS_OUT K4 VSS3 A7 SCLK E1 VO26 K5 VSS1 A8 OFFSET_SEL E2 VO14 K6 VSS4 A9 BUSY E10 AGND1 K7 VDD2 A10 TRACK/RESET E11 OFFS_IN K8 VO2 A11 NC* F1 VO25 K9 VO10 B1 VO16 F2 VO21 K10 VO13 B2 NC* F10 AGND2 K11 VO12 B3 A3 F11 VO6 L1 NC* B4 A1 G1 VO24 L2 VO28 B5 WR G2 VO8 L3 VO29 B6 DGND G10 VO5 L4 VO30 B7 D G11 VO3 L5 VDD3 IN B8 CAL H1 VO23 L6 VDD1 B9 SER/PAR H2 VIN L7 VDD4 B10 DOUT H10 VO4 L8 VO31 B11 REF_IN H11 VO7 L9 VO0 C1 VO18 J1 VO22 L10 VO1 C2 DAC_GND1 J2 VO19 L11 NC* C6 NC* J6 VSS2 *NC = Not Connected REV. A –7–

AD5532B PIN FUNCTION DESCRIPTIONS Mnemonic Description AGND (1–2) Analog GND Pins AV (1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. CC V (1–4) V Supply Pins. Voltage range from 8 V to 16.5 V. DD DD V (1–4) V Supply Pins. Voltage range from –4.75 V to –16.5 V. SS SS DGND Digital GND Pins DV Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. CC DAC_GND (1–2) Reference GND Supply for all the DACs REF_IN Reference Voltage for Channels 0–31 REF_OUT Reference Output Voltage V (0–31) Analog Output Voltages from the 32 Channels OUT V Analog Input Voltage. Connect this to AGND if operating in DAC mode only. IN A4–A11, A02 Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. CAL1 Parallel Interface. Control input that allows all 32 channels to acquire V simultaneously. IN CS/SYNC This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for the serial interface. WR1 Parallel Interface. Write pin. Active low. This is used in conjunction with the CS pin to address the device using the parallel interface. OFFSET_SEL1 Parallel Interface. Offset select pin. Active high. This is used to select the offset channel. SCLK2 Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode). D 2 Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. IN D Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid OUT on the falling edge of SCLK. SER/PAR1 This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low, the parallel interface will be used. If it is tied high, the serial interface will be used. OFFS_IN Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the offset channel. OFFS_OUT Offset Output. This is the acquired/programmed offset voltage that can be tied to OFFS_IN to offset the span. BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. TRACK/RESET2 If this input is held high, V is acquired once the channel is addressed. While it is held low, the input to the IN gain/offset stage is switched directly to V . The addressed channel begins to acquire V on the rising edge IN IN of TRACK. See TRACK Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going pulseof between 90 ns and 200 ns to this pin. See section on RESET Function for further details. NOTES 1Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition. 2Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition. OUTPUT VOLTAGE VOUT GAIN ERROR + FULL-SCALE OFFSET ERROR ERROR RANGE IDEAL TRANSFER IDEAL GAIN (cid:1) REFIN FUNCTION IDEAL TRANSFER ACTUAL FUNCTION OFFSET TRANSFER ERROR FUNCTION OFFSET RANGE IDEAL GAIN (cid:1) 50mV 0 16k 0V 70mV 2.96 3V VIN DAC CODE LOWER UPPER DEAD BAND DEAD BAND Figure 6.DAC Transfer Function (OFFS_IN = 0) Figure 7.ISHA Transfer Function –8– REV. A

AD5532B TERMINOLOGY Output Noise Spectral Density DAC MODE This is a measure of internally generated random noise. Random Integral Nonlinearity (INL) noise is characterized as a spectral density (voltage per root Hertz). This is a measure of the maximum deviation from a straight line It is measured by loading all DACs to midscale and measuring passing through the endpoints of the DAC transfer function. It is noise at the output. It is measured in nV/√Hz. expressed as a percentage of full-scale span. Output Temperature Coefficient Differential Nonlinearity (DNL) This is a measure of the change in analog output with changes Differential nonlinearity (DNL) is the difference between the in temperature. It is expressed in ppm/°C. measured change and the ideal 1 LSB change between any two DC Power Supply Rejection Ratio adjacent codes. A specified DNL of ±1 LSB maximum ensures DC power supply rejection ratio (PSRR) is a measure of the change monotonicity. in analog output for a change in supply voltage (V and V ). DD SS Offset It is expressed in dBs. V and V are varied ±5%. DD SS Offset is a measure of the output with all zeros loaded to the DC Crosstalk DAC and OFFS_IN = 0. Since each DAC is lifted off the ground This is the change in the output level of one DAC at midscale in by approximately 50 mV, this output will typically be: response to a full-scale code change (all 0s to all 1s and vice versa) V =GAIN ×50mV and output change of all other DACs. It is expressed in µV. OUT Full-Scale Error ISHA MODE This is a measure of the output error with all 1s loaded to the Total Unadjusted Error (TUE) DAC. It is expressed as a percentage of full-scale range. It includes This is a comprehensive specification that includes relative the offset error. See Figure 6. It is calculated as: accuracy, gain and offset errors. It is measured by sampling a ( ) range of voltages on V and comparing the measured voltages Full-ScaleError =V – IdealGain×REFIN IN OUT(FullScale) on V to the ideal value. It is expressed in mV. OUT where V to V Nonlinearity IN OUT IdealGain=3.52 for AD5532B−1 This is a measure of the maximum deviation from a straight line passing through the endpoints of the V versus V transfer IN OUT Output Settling Time function. It is expressed as a percentage of the full-scale span. This is the time taken from when the last data bit is clocked into the DAC until the output has settled to within ±0.39%. Offset Error This is a measure of the output error when V = 70 mV. Ideally, IN OFFS_IN Settling Time with V = 70 mV: IN This is the time taken from a 0 V–3 V step change in input voltage ( ) [( ) ] on OFFS_IN until the output has settled to within ±0.39%. V = Gain×70 – Gain–1 ×V mV OUT OFFS_IN Digital-to-Analog Glitch Impulse Offset error is a measure of the difference between V (actual) This is the area of the glitch injected into the analog output when OUT and V (ideal). It is expressed in mV and can be positive or the code in the DAC register changes state. It is specified as the OUT negative. See Figure 7. area of the glitch in nV-secs when the digital code is changed by 1 LSB at the major carry transition (011...11 to 100...00 or Gain Error 100...00 to 011...11). This is a measure of the span error of the analog channel. It is the deviation in slope of the transfer function expressed in mV. Digital Crosstalk See Figure 7. It is calculated as: This is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice Gain Error = Actual Full-Scale Output – versa) is being written to another DAC. It is expressed in nV-secs. Ideal Full-Scale Output – Offset Error where Analog Crosstalk This the area of the glitch transferred to the output (VOUT) of Ideal Full-Scale Output = (Gain (cid:1) 2.96) – [(Gain – 1) (cid:1) VOFFS_IN] one DAC due to a full-scale change in the output (VOUT) of AC Crosstalk another DAC. The area of the glitch is expressed in nV-secs. This is the area of the glitch that occurs on the output of one Digital Feedthrough channel while another channel is acquiring. It is expressed in This is a measure of the impulse injected into the analog outputs nV-secs. from the digital control inputs when the part is not being written Output Settling Time to, i.e., CS/SYNC is high. It is specified in nV-secs and is mea- This is the time taken from when BUSY goes high to when the sured with a worst-case change on the digital input pins, e.g., from output has settled to ±0.018%. all 0s to all 1s and vice versa. Acquisition Time This is the time taken for the V input to be acquired. It is the IN length of time that BUSY stays low. REV. A –9–

AD5532B–Typical Performance Characteristics 1.0 5.370 VREFIN = 3V DAC LOADED TO MIDSCALE 0.8 VOFFS_IN = 0V VREFIN = 3V 0.6 TA = 25(cid:4)C 40 5.360 VOFFS_IN = 0V Bs 0.4 L ERROR – LS–000...022 FREQUENCY 3200 V – VOUT55..335400 DN–0.4 –0.6 10 5.330 –0.8 0 –1.00 2k 4k 6k 8k 10k 12k 14k 16k 0 0.05 0.10 0.15 5.320–40 0 40 80 DAC CODE FSR – % TEMPERATURE – (cid:4)C TPC 1.Typical DNL Plot TPC 2.INL Error Distribution TPC 3.V vs. Temperature OUT at 25°C (DAC Mode) 3.530 10.0 40 TA = 25(cid:4)C TA = 25(cid:4)C VREFIN = 3V VREFIN = 3V VIN = 1V 8.0 VOFFS_IN = 0.5V 3.525 6.0 Y C V V N – UT – UT4.0 QUE20 O O E V V R F 3.520 2.0 0.0 3.515 –2.0 0 6 4 2 0 –2 –4 –6 TIME BASE – 2(cid:5)s/DIV –4 –3 –2 –1 0 1 2 3 4 5 6 7 8 SINK/SOURCE CURRENT – mA TOTAL UNADJUSTED ERROR (cid:6) mV TPC 4.V Source and Sink TPC 5.Full-Scale Settling Time TPC 6.TUE Distribution at 25°C OUT Capability (ISHA Mode) 0.024 70k 00..002106 TVVARO EF=FF 2SIN5_ I=(cid:4)NC 3=V 0V 5V 60k 63791 TVVARIN E= =F 2 IN15 .=(cid:4)5C V3V 0.012 VOFFS_IN = 0V 100 50k % 0.008 90 BUSY V ERROR – OUT––0000....000000004480 VOUT TVAR E=F I2N5 =(cid:4)C 3V FREQUENCY3400kk –0.012 10 VIN = 0 1.5V 20k 0% –0.016 10k –0.020 1V 2(cid:5)s 200 1545 –0.024 0 0.1 2.96 5.2670 5.2676 5.2682 VIN – V VOUT – V TPC 7.V to V Accuracy After TPC 8.Acquisition Time and Output TPC 9.ISHA Mode Repeatability IN OUT Offset and Gain Adjustment (ISHA Settling Time (ISHA Mode) (64 K Acquisitions) Mode) –10– REV. A

AD5532B FUNCTIONAL DESCRIPTION ISHA Mode The AD5532B can be thought of as consisting of 32 DACs and In ISHA mode the input voltage V is sampled and converted IN an ADC (for ISHA mode) in a single package. In DAC mode, into a digital word. The noninverting input to the output buffer a14-bit digital word is loaded into one of the 32 DAC registers (gain and offset stage) is tied to V during the acquisition period IN via the serial interface. This is then converted (with gain and to avoid spurious outputs while the DAC acquires the correct offset) into an analog output voltage (V 0–V 31). code. This is completed in 16 µs max. At this time, the updated OUT OUT DAC output assumes control of the output voltage. The output To update a DAC’s output voltage, the required DAC is addressed voltage of the DAC is connected to the noninverting input of via the serial port. When the DAC address and code have been the output buffer. Since the channel output voltage is effectively loaded, the selected DAC converts the code. the output of a DAC, there is no droop associated with it. As On power-on, all the DACs, including the offset channel, are long as power is maintained to the device, the output voltage loaded with zeros. Each of the 33 DACs is offset internally by will remain constant until this channel is addressed again. Since 50 mV (typ) from GND so the outputs V 0 to V 31 are OUT OUT the internal DACs are offset by 70 mV (max) from GND, the 50 mV (typ) on power-on if the OFFS_IN pin is driven directly by minimum V in ISHA mode is 70 mV. The maximum V is IN IN the on-board offset channel (OFFS_OUT), i.e., if OFFS_IN = 2.96 V due to the upper dead band of 40 mV (max). OFFS_OUT = 50 mV = > V = (Gain × V )– (Gain –1) × OUT DAC Analog Input (ISHA Mode) V = 50 mV. OFFS_IN The equivalent analog input circuit is shown in Figure 8. The Output Buffer Stage—Gain and Offset capacitor C1 is typically 20 pF and can be attributed to pin The function of the output buffer stage is to translate the 50 mV–3V capacitance and 32 off-channels. When a channel is selected, an typical output of the DAC to a wider range. This is done by extra 7.5 pF (typ) is switched in. This capacitor C2 is charged gaining up the DAC output by 3.52 and offsetting the voltage to the previously acquired voltage on that particular channel by the voltage on OFFS_IN pin. so it must charge/discharge to the new level. It is essential that the V =3.52×V –2.52×V external source can charge/discharge this additional capacitance OUT DAC OFFS_IN within 1 µs to 2 µs of channel selection so that V can be IN V is the output of the DAC. acquired accurately. For this reason a low impedance source DAC V is the voltage at the OFFS_IN pin. is recommended. OFFS_IN Table I shows how the output range on V relates to the offset OUT ADDRESSED voltage supplied by the user: CHANNEL Table I. Sample Output Voltage Ranges VIN C1 C2 20pF 7.5pF V V (Typ) V (Typ) OFFS_IN DAC OUT (V) (V) (V) 0 0.05 to 3 0.176 to 10.56 1 0.05 to 3 –2.34 to +8.04 2.130 0.05 to 3 –5.192 to +5.192 Figure 8.Analog Input Circuit Large source impedances will significantly affect the performance V is limited only by the headroom of the output amplifiers. OUT of the ADC. This may necessitate the use of an input buffer V must be within maximum ratings. OUT amplifier. Offset Voltage Channel TRACK Function (ISHA Mode) The offset voltage can be externally supplied by the user at Normally in ISHA mode of operation, TRACK is held high and OFFS_IN or it can be supplied by an additional offset voltage the channel begins to acquire when it is addressed. However, if channel on the device itself. The offset can be set up in two ways. TRACK is low when the channel is addressed, V is switched to IN In ISHA mode the required offset voltage is set up on V IN the output buffer and an acquisition on the channel will not and acquired by the offset channel. In DAC mode, the code occur until a rising edge of TRACK. At this stage the BUSY pin corresponding to the offset value is loaded directly into the will go low until the acquisition is complete, at which point the offset DAC. This offset channel’s DAC output is directly DAC assumes control of the voltage to the output buffer and connected to the OFFS_OUT pin. By connecting OFFS_OUT to V is free to change again without affecting this output value. IN OFFS_IN this offset voltage can be used as the offset voltage This is useful in an application where the user wants to ramp up for the 32 output amplifiers. The offset must be chosen so V until V reaches a particular level (Figure 9). V does that V is within maximum ratings. IN OUT IN OUT not need to be acquired continuously while it is ramping up. Reset Function TRACK can be kept low and only when V has reached its OUT The reset function on the AD5532B can be used to reset all nodes desired voltage is TRACK brought high. At this stage, the on this device to their power-on-reset condition. This is imple- acquisition of V begins. IN mented by applying a low going pulse of between 90 ns and 200 ns In the example shown, a desired voltage is required on the output to the TRACK/RESET pin on the device. If the applied pulse is of the pin driver. This voltage is represented by one input to a less than 90 ns, it is assumed to be a glitch and no operation comparator. The microcontroller/microprocessor ramps up the takes place. If the applied pulse is wider than 200 ns, this pin input voltage on V through a DAC. TRACK is kept low adopts its track function on the selected channel, V is switched IN IN while the voltage on V ramps up so that V is not continu- to the output buffer, and an acquisition on the channel will not IN IN ally acquired. When the desired voltage is reached on the output occur until a rising edge of TRACK. REV. A –11–

AD5532B PIN DRIVER OUTPUT VOUT1 DEVICE VIN ACQUISITION STAGE UNDER CONTROLLER DAC CIRCUIT TEST BUSY AD5532B TRACK THRESHOLD VOLTAGE ONLY ONE CHANNEL SHOWN FOR SIMPLICITY Figure 9.Typical ATE Circuit Using TRACK Input of the pin driver, the comparator output switches. The µC/µP Table II. Modes of Operation then knows what code is required to be input in order to obtain Mode Bit 1 Mode Bit 2 Operating Mode the desired voltage at the DUT. The TRACK input is now brought high and the part begins to acquire VIN. At this stage, 0 0 ISHA Mode BUSY goes low until VIN has been acquired. The output buffer 0 1 DAC Mode is then switched from VIN to the output of the DAC. 1 0 Acquire and Readback 1 1 Readback MODES OF OPERATION The AD5532B can be used in four different modes of oper- 1. ISHA Mode ation. These modes are set by two mode bits, the first two bits in In this mode, a channel is addressed and that channel the serial word. acquires the voltage on V . This mode requires a 10-bit IN write (see Figure3) to address the relevant channel (V 0– OUT V 31, offset channel or all channels). MSB is written first. OUT MSB LSB 0 0 CAL OFFSET SEL 0 A4–A0 MODE BIT 1 MODE BIT 2 TEST BIT MODE BITS a.10-Bit Input Serial Write Word (ISHA Mode) MSB LSB 0 1 CAL OFFSET SEL 0 A4–A0 DB13–DB0 TEST BIT MODE BITS b.24-Bit Input Serial Write Word (DAC Mode) MSB LSB MSB LSB 1 0 CAL OFFSET SEL 0 A4–A0 DB13–DB0 TEST BIT MODE BITS 10-BIT 14-BIT DATA SERIAL WORD READ FROM PART AFTER WRITTEN TO PART NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) c.Input Serial Interface (Acquire and Readback Mode) MSB LSB MSB LSB 1 1 CAL OFFSET SEL 0 A4–A0 DB13–DB0 TEST BIT MODE BITS 10-BIT 14-BIT DATA SERIAL WORD READ FROM PART AFTER WRITTEN TO PART NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) d.Input Serial Interface (Readback Mode) Figure 10.Serial Interface Formats –12– REV. A

AD5532B 2. DAC Mode Test Bit In this standard mode, a selected DAC register is loaded serially. This must be set low for correct operation of the part. This requires a 24-bit write (10 bits to address the relevant A4–A0 Bits DAC plus an extra 14 bits of DAC data). (See Figure4.) MSB Used to address any one of the 32 channels (A4 = MSB of is written first. The user must allow 400 ns (min) between address, A0 = LSB). successive writes in DAC mode. DB13–DB0 Bits 3. Acquire and Readback Mode These are used to write a 14-bit word into the addressed DAC This mode allows the user to acquire V and read back the IN register. Clearly, this is only valid when in DAC mode. data in a particular DAC register. The relevant channel is addressed (10-bit write, MSB first) and V is acquired in The serial interface is designed to allow easy interfacing to most IN 16 µs (max). Following the acquisition, after the next falling microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI™, SPI™, DSP56000, TMS320, and ADSP-21xx, without the need for any edge of SYNC, the data in the relevant DAC register is clocked out onto the D line in a 14-bit serial format. glue logic. When interfacing to the 8051, the SCLK must be inverted. OUT (See Figure5.) The full acquisition time must elapse before The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. the DAC register data can be clocked out. Figures 3, 4, and 5 show the timing diagram for a serial read and 4. Readback Mode Again, this is a readback mode but no acquisition is performed. write to the AD5532B. The serial interface works with both a con- The relevant channel is addressed (10-bit write, MSB first) tinuous and a noncontinuous serial clock. The first falling edge of and on the next falling edge of SYNC, the data in the relevant SYNC resets a counter that counts the number of serial clocks DAC register is clocked out onto the D line in a 14-bit to ensure the correct number of bits are shifted in and out of the OUT serial format. (See Figure5.) The user must allow 400 ns (min) serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once the correct between the last SCLK falling edge in the 10-bit write and number of bits for the selected mode have been shifted in or out, the falling edge of SYNC in the 14-bit readback. The serial the SCLK is ignored. In order for another serial transfer to take write and read words can be seen in Figure 10. place, the counter must be reset by the falling edge of SYNC. This feature allows the user to read back the DAC register code of any of the channels. In DAC mode, this is useful in In readback, the first rising SCLK edge after the falling edge of verification of write cycles. In ISHA mode, readback is useful SYNC causes DOUT to leave its high impedance state and data if the system has been calibrated and the user wants to know is clocked out onto the DOUT line and also on subsequent SCLK what code in the DAC corresponds to a desired voltage on rising edges. The DOUT pin goes back into a high impedance V . If the user requires this voltage again, the user can input state on the falling edge of the fourteenth SCLK. Data on the OUT the code directly to the DAC register without going through DIN line is latched in on the first SCLK falling edge after the the acquisition sequence. falling edge of the SYNC signal and on subsequent SCLK falling edges. During readback D is ignored. The serial interface will IN not shift data in or out until it receives the falling edge of the INTERFACES SYNC signal. SERIAL INTERFACE The SER/PAR pin is tied high to enable the serial interface and PARALLEL INTERFACE (ISHA Mode Only) to disable the parallel interface. The serial interface is controlled The SER/PAR bit must be tied low to enable the parallel interface by four pins as follows: and disable the serial interface. The parallel interface is controlled by nine pins. SYNC, D , SCLK IN Standard 3-wire interface pins. The SYNC pin is shared CS with the CS function of the parallel interface. Active low package select pin. This pin is shared with the SYNC function for the serial interface. D OUT Data out pin for reading back the contents of the DAC WR registers. The data is clocked out on the rising edge of SCLK Active low write pin. The values on the address pins are and is valid on the falling edge of SCLK. latched on a rising edge of WR. Mode Bits A4–A0 There are four different modes of operation as described above. Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32). Cal Bit In DAC mode, this is a test bit. When it is high it is used to load Offset_Sel all zeros or all ones to the 32DACs simultaneously. In ISHA mode, Offset select pin. This has the same function as the Offset_Sel all 32 channels acquire V simultaneously when this bit is high. bit in the serial interface. When it is high, the offset channel IN In ISHA mode, the acquisition time is then 45 µs (typ) and is addressed. The address on A4–A0 is ignored in this case. accuracy may be reduced. This bit is set low for normal operation. Cal Offset_Sel Bit When this pin is high, all 32 channels acquire V simulta- IN If this is set high, the offset channel is selected and Bits A4–A0 neously. The acquisition time is then 45 µs (typ) and accuracy are ignored. may be reduced. *SPI and QSPI are trademarks of Motorola, Inc. REV. A –13–

AD5532B MICROPROCESSOR INTERFACING When data is being transmitted to the AD5532B, the SYNC line AD5532B to ADSP-21xx Interface is taken low (PC7). Data appearing on the MOSI output is valid The ADSP-21xx family of DSPs is easily interfaced to the on the falling edge of SCK. Serial data from the 68HC11 is AD5532B without the need for extra logic. transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In A data transfer is initiated by writing a word to the TX register order to transmit 10 data bits in ISHA mode, it is important to after the SPORT has been enabled. In a write sequence, data is left-justify the data in the SPDR register. PC7 must be pulled clocked out on each rising edge of the DSP’s serial clock and low to start a transfer. It is taken high and pulled low again before clocked into the AD5532B on the falling edge of its SCLK. any further read/write cycles can take place. In readback, 16 bits of data are clocked out of the AD5532B on each rising edge of SCLK and clocked into the DSP on the AD5532B to PIC16C6x/7x rising edge of SCLK. D is ignored. The valid 14 bits of data The PIC16C6x/7x synchronous serial port (SSP) is configured as IN will be centered in the 16-bit RX register when using this configu- an SPI master with the clock polarity bit = 0. This is done by ration. The SPORT control register should be set up as follows: writing to the synchronous serial port control register (SSPCON). See PIC16/17 Microcontroller User Manual. In this example, TFSW = RFSW = 1, Alternate Framing I/Oport RA1 is being used to pulse SYNC and enable the serial INVRFS = INVTFS = 1, Active Low Frame Signal port of the AD5532B. This microcontroller transfers only eight DTYPE = 00, Right Justify Data bits of data during each serial transfer operation; therefore, two or ISCLK = 1, Internal Serial Clock three consecutive read/write operations are needed depending TFSR = RFSR = 1, Frame Every Word on the mode. Figure 13 shows the connection diagram. IRFS = 0, External Framing Signal ITFS = 1, Internal Framing Signal SLEN = 1001, 10-Bit Data-Words (ISHA Mode Write) AD5532B* PIC16C6x/7x* SLEN = 0111, 3 8-Bit Data-Words (DAC Mode Write) SCLK SCK/RC3 SLEN = 1111, 16-Bit Data-Words (Readback Mode) DOUT SDO/RC5 Figure 11 shows the connection diagram. DIN SDI/RC4 SYNC RA1 AD5532B* ADSP-2101/ *ADDITIONAL PINS OMITTED FOR CLARITY DOUT DR ADSP-2103* Figure 13.AD5532B to PIC16C6x/7x Interface SYNC TFS RFS AD5532B to 8051 DIN DT The AD5532B requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode0. In this SCLK SCLK mode, serial data enters and exits through RxD and a shift clock *ADDITIONAL PINS OMITTED FOR CLARITY is output on TxD. Figure 14 shows how the 8051 is connected to the AD5532B. Because the AD5532B shifts data out on the Figure 11.AD5532B to ADSP-2101/ADSP-2103 Interface rising edge of the shift clock and latches data in on the falling AD5532B to MC68HC11 edge, the shift clock must be inverted. The AD5532B requires its The serial peripheral interface (SPI) on the MC68HC11 is confi- data with the MSB first. Since the 8051 outputs the LSB first, gured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, the transmit routine must take this into account. and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see 68HC11 User AD5532B* 8051* Manual. SCK of the 68HC11 drives the SCLK of the AD5532B, the MOSI output drives the serial data line (D ) of the AD5532B, SCLK TxD IN and the MISO input is driven from D . The SYNC signal is DOUT RxD OUT derived from a port line (PC7). A connection diagram is shown DIN in Figure 12. SYNC P1.1 *ADDITIONAL PINS OMITTED FOR CLARITY AD5532B* MC68HC11* Figure 14.AD5532B to 8051 Interface DOUT MISO SYNC PC7 SCLK SCK DIN MOSI *ADDITIONAL PINS OMITTED FOR CLARITY Figure 12.AD5532B to MC68HC11 Interface –14– REV. A

AD5532B APPLICATION CIRCUITS Typical Application Circuit (ISHA Mode) AD5532B in a Typical ATE System The AD5532B can be used to set up voltage levels on 32 channels The AD5532B is ideally suited for use in automatic test as shown in the circuit below. An AD780 provides the 3 V refer- equipment. Several DACs are required to control pin drivers, ence for the AD5532B, and for the AD5541 16-bit DAC. A simple comparators, active loads, and signal timing. Traditionally, 3-wire serial interface is used to write to the AD5541. Because sample-and-hold devices were used in these applications. the AD5541 has an output resistance of 6.25 kW (typ), the time taken to charge/discharge the capacitance at the V pin is signifi- The AD5532B has several advantages: no refreshing is required, IN cant. Thus an AD820 is used to buffer the DAC output. Note there is no droop, pedestal error is eliminated, and there is no that it is important to minimize noise on V and REFIN when need for extra filtering to remove glitches. Overall a higher level IN laying out this circuit. of integration is achieved in a smaller area (see Figure 15). AVCC AVCC DVCC VSS PARAMETRIC MEASUREMENT SYSTEM BUS UNIT DAC VDD DAC ACTIVE LOAD AD820 VIN DAC CS AD5541* AD5532B* VOUT 0–31 DIN SCLK OFFS_IN STORED REF DATA DRIVER OFFS_OUT AND INHIBIT DAC PATTERN REFIN FORMATTER DAC DUT AD780* PERIOD GENERATION VOUT AND SCLK DIN SYNC DELAY DAC TIMING COMPARE REGISTER *ADDITIONAL PINS OMITTED FOR CLARITY DAC Figure 17.Typical Application Circuit (ISHA Mode) COMPARATOR DACs SYSTEM BUS POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration Figure 15.AD5532B in an ATE System of the power supply and ground return layout helps to ensure the Typical Application Circuit (DAC Mode) rated performance. The printed circuit board on which the The AD5532B can be used in many optical networking applications AD5532B is mounted should be designed so that the analog and that require a large number of DACs to perform control and digital sections are separated, and confined to certain areas of the measurement functions. In the example shown in Figure 16, the board. If the AD5532B is in a system where multiple devices require outputs of the AD5532B are amplified and used to control actuators an AGND-to-DGND connection, the connection should be made that determine the position of MEMS mirrors in an optical switch. at one point only. The star ground point should be established The exact position of each mirror is measured using sensors. The as close as possible to the device. For supplies with multiple pins sensor readings are muxed using four dual 4-channel matrix switches (V , V , AV ), it is recommended to tie those pins together. SS DD CC (ADG739) and fed back to an 8-channel 14-bit ADC (AD7856). The AD5532B should have ample supply bypassing of 10µF in parallel with 0.1 µF on each supply located as close to the package The control loop is driven by an ADSP-2191M, a 16-bit fixed- as possible, ideally right up against the device. The 10µF capacitors point DSP with three SPORT interfaces and two SPI ports. The are the tantalum bead type. The 0.1µF capacitor should have DSP uses some of these serial ports to write data to the DAC, low effective series resistance (ESR) and effective series induc- control the multiplexer, and read back data from the ADC. tance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. S 1 1 E 1 MEMS N ADG739 AD5532B MAIRRRRAOYR S (cid:1) 4 AD7856 32 32 O 8 R AD8544 (cid:1) 2 ADSP-2191M Figure 16.Typical Optical Control and Measurement Application Circuit REV. A –15–

09/19/02 2:30 PM_GS AD5532B The power supply lines of the AD5532B should use as large a trace line. If this capacitor is necessary, then for optimum throughput as possible to provide low impedance paths and reduce the effects of it may be necessary to buffer the source that is driving V . IN glitches on the power supply line. Fast switching signals such as Avoid crossover of digital and analog signals. Traces on opposite clocks should be shielded with digital ground to avoid radiating sides of the board should run at right angles to each other. This noise to other parts of the board, and should never be run near reduces the effects of feedthrough through the board. A microstrip the reference inputs. A ground line routed between the D and IN technique is by far the best, but not always possible with a double- SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, sisi ddeedd ibcoaaterdd .t oIn g trhoiusn tde cphlnaniqeu we,h tilhee s cigonmalp tornaceenst asride ep olafc tehde obno tahrde 2(A) but separating the lines will help). solder side. 9/0 – 0 Note that it is essential to minimize noise on V and REFIN – IN As is the case for all thin packages, care must be taken to avoid 9 lines. Particularly for optimum ISHA performance, the VIN line flexing the package and to avoid a point load on the surface of 270 must be kept noise-free. Depending on the noise performance of the package during the assembly process. C0 the board, a noise filtering capacitor may be required on the V IN OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74) Dimensions shown in millimeters A1 CORNER INDEX AREA 12.00 BSC SQ 11 10 9 8 7 6 5 4 3 2 1 A A1 B C D E TOP VIEW 1.00 BOTTOM F 10.00 BSC BSC VIEW SQ G H J K L 1.00 BSC 1.70 DETAIL A MAX DETAIL A 0.30 MIN 0.20 MAX COPLANARITY 0.70 0.60 SEATING 0.50 PLANE BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1 A. S. U. Revision History N D I E Location Page NT RI 9/02—Data Sheet changed from REV. 0 to REV. A. P Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Changes to SERIAL INTERFACE table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Replaced Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Updated BC-74 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 –16– REV. A