32-Channel, 14-Bit Voltage-Output DAC AD5532 FEATURES GENERAL DESCRIPTION High integration: The AD55321 is a 32-channel, 14-bit voltage-output DAC with 32-channel DAC in 12 mm × 12 mm CSPBGA an additional infinite sample-and-hold mode. The selected Adjustable voltage output range DAC register is written to via the 3-wire serial interface; V OUT Guaranteed monotonic for this DAC is then updated to reflect the new contents of the Readback capability DAC register. DAC selection is accomplished via Address Bits DSP/microcontroller compatible serial interface A0–A4. The output voltage range is determined by the offset Output impedance: voltage at the OFFS_IN pin and the gain of the output amplifier. 0.5 Ω (AD5532-1, AD5532-2) It is restricted to a range from V + 2 V to V – 2 V because of SS DD 500 Ω (AD5532-3) the headroom of the output amplifier. 1 kΩ (AD5532-5) Output voltage span: The device is operated with AV = 5 V ± 5%; DV = 2.7 V to CC CC 10 V (AD5532-1, AD5532-3, AD5532-5) 5.25 V; V = −4.75 V to −16.5 V; and V = 8 V to 16.5 V. The SS DD 20 V (AD5532-2) AD5532 requires a stable 3 V reference on REF_IN as well as an Infinite sample-and-hold capability to ±0.018% accuracy offset voltage on OFFS_IN. Temperature range −40°C to +85°C PRODUCT HIGHLIGHTS APPLICATIONS 1. 32-channel, 14-bit DAC in one package, guaranteed Automatic test equipment monotonic. Optical networks 2. Available in a 74-lead CSPBGA package with a body size of Level setting 12 mm ×12 mm. Instrumentation 3. Droopless/infinite sample-and-hold mode. Industrial control systems Data acquisition Low cost I/O DVCC AVCC REF_IN REF_OUT OFFS_IN VDD VSS AD5532 VOUT0 VIN ADC DAC S TRACK/RESET BU T BI BUSY 14- VOUT31 DAC_GND MUX DAC AGND E OFFS_OUT D O DAC DGND M INTERFACE SER/PAR CONTROL LOGIC ADDRESS INPUT REGISTER WR SCLK DIN DOUT SYNC/CS A4–A0 CAL OFFSET_SEL 00939-C-001 Figure 1. Functional Block Diagram Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2010 Analog Devices, Inc. All rights reserved.

AD5532 TABLE OF CONTENTS Specifications ..................................................................................... 3 Output Buffer Stage—Gain and Offset.................................... 14 ISHA Mode .................................................................................... 5 Offset Voltage Channel .............................................................. 14 Timing Characteristics ..................................................................... 6 Reset Function ............................................................................ 14 Parallel Interface ........................................................................... 6 ISHA Mode ................................................................................. 14 Parallel Interface Timing Diagrams ........................................... 6 Analog Input (ISHA Mode) ...................................................... 14 Serial Interface .............................................................................. 7 TRACK Function (ISHA Mode) .............................................. 15 Absolute Maximum Ratings ............................................................ 8 Modes of Operation ................................................................... 15 ESD Caution .................................................................................. 8 Serial Interface ............................................................................ 16 Pin Configuration and Function Descriptions ............................. 9 Parallel Interface (ISHA Mode Only) ...................................... 17 Terminology .................................................................................... 11 Microprocessor Interfacing ....................................................... 17 Dac Mode .................................................................................... 11 Application Circuits ................................................................... 18 ISHA Mode .................................................................................. 11 Power Supply Decoupling ......................................................... 19 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 20 Functional Description .................................................................. 14 Ordering Guide .......................................................................... 20 REVISION HISTORY 6/10—Data Sheet Changed from Rev. C to Rev. D Changes to Table 5 ...................................................................... 8 Changes to Ordering Guide .................................................... 20 6/04—Data Sheet Changed from Rev. B to Rev. C Updated Format ........................................................... Universal Changed LFBGA to CSPBGA .................................... Universal Changes to Outline Dimensions ............................................. 24 Changes to Ordering Guide .................................................... 24 6/02—Data Sheet Changed from Rev. A to Rev. B Term SHA changed to ISHA ........................................... Global Changes to Absolute Maximum Ratings ................................. 6 Changes to Ordering Guide ...................................................... 6 Changes to Functional Description ....................................... 11 Changes to Table 8 .................................................................... 11 Changes to ISHA Mode ........................................................... 11 Added Figure 27 and accompanying text .............................. 15 Changes to Power Supply Decoupling Section ..................... 15 Rev. D | Page 2 of 20

AD5532 SPECIFICATIONS V = 8 V to 16.5 V, V = –4.75 V to –16.5 V; AV = 4.75 V to 5.25 V; DV = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; DD SS CC CC REF_IN = 3 V; output range from V + 2 V to V − 2 V. All outputs unloaded. All specifications T to T , unless otherwise noted. SS DD MIN MAX Table 1. A Version1 Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments DAC DC PERFORMANCE Resolution 14 14 Bits Integral Nonlinearity (INL) ±0.39 ±0.39 % of FSR max ±0.15% typ Differential Nonlinearity (DNL) ±1 ±1 LSB max ±0.5 LSB typ, monotonic Offset 90/170/250 180/350/500 mV min/typ/max See Figure 8 Gain 3.52 7 typ Full Scale Error ±2 ±2 % of FSR max VOLTAGE REFERENCE REF_IN Nominal Input Voltage 3.0 3.0 V typ Input Voltage Range3 2.85/3.15 2.85/3.15 V min/max Input Current 1 1 μA max < 1 nA typ REF_OUT Output Voltage 3 3 V typ Output Impedance3 280 280 kΩ typ Reference Temperature Coefficient3 60 60 ppm/°C typ ANALOG OUTPUTS (V 0–31) OUT Output Temperature Coefficient3, 4 10 10 ppm/°C typ DC Output Impedance3 AD5532-1 0.5 0.5 Ω typ AD5532-3 500 Ω typ AD5532-5 1 kΩ typ Output Range V + 2/V − 2 V + 2 /V − 2 V min/max SS DD SS DD Resistive Load3, 5 5 5 kΩ min Capacitive Load3, 5 AD5532-1 500 500 pF max AD5532-3 15 nF max AD5532-5 40 nF max Short-Circuit Current3 7 7 mA typ DC Power-Supply Rejection Ratio3 −70 −70 dB typ VDD = +15 V ±5% −70 −70 dB typ V = −15 V ±5% SS DC Crosstalk3 250 1800 μV max ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient3, 4 10 10 ppm/°C typ DC Output Impedance3 1.3 1.3 kΩ typ Output Range 50 to REF_IN−12 50 to REF_IN−12 mV typ Output Current 10 10 μA max Source current Capacitive Load 100 100 pF max DIGITAL INPUTS3 Input Current ±10 ±10 μA max ±5 μA typ Input Low Voltage 0.8 0.8 V max DV = 5 V ±5% CC 0.4 0.4 V max DV = 3 V ±10% CC Input High Voltage 2.4 2.4 V min DV = 5 V ±5% CC 2.0 2.0 V min DV = 3 V ±10% CC Input Hysteresis (SCLK and CS Only) 200 200 mV typ Rev. D | Page 3 of 20

AD5532 A Version1 Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments Input Capacitance 10 10 pF max DIGITAL OUTPUTS (BUSY, D )3 OUT Output Low Voltage, DV = 5 V 0.4 0.4 V max Sinking 200 μA. CC Output High Voltage, DV = 5 V 4.0 4.0 V min Sourcing 200 μA. CC Output Low Voltage, DV = 3 V 0.4 0.4 V max Sinking 200 μA. CC Output High Voltage, DV = 3 V 2.4 2.4 V min Sourcing 200 μA. CC High Impedance Leakage Current ±1 ±1 μA max D only. OUT High Impedance Output Capacitance 15 15 pF typ D only. OUT POWER REQUIREMENTS Power-Supply Voltages V 8/16.5 8/16.5 V min/max DD VSS −4.75/−16.5 −4.75/−16.5 V min/max AV 4.75/5.25 4.75/5.25 V min/max CC DV 2.7/5.25 2.7/5.25 V min/max CC Power-Supply Currents6 I 15 15 mA max 10 mA typ. All channels DD full scale. I 15 15 mA max 10 mA typ. All channels SS full scale. AICC 33 33 mA max 26 mA typ. DICC 1.5 1.5 mA max 1 mA typ. Power Dissipation6 280 280 mW typ V = 10 V, V = −5 V. DD SS AC CHARACTERISTICS3 500 pF, 5 kΩ load. Full-scale Output Voltage Settling Time 22 30 μs max change. OFFS_IN Settling Time 10 25 500 pF, 5 kΩ load; 0 V to 3 V μs max step. Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB change around. Major carry. Digital Crosstalk 5 5 nV-s typ Analog Crosstalk 1 1 nV-s typ Digital Feedthrough 0.2 0.2 nV-s typ Output Noise Spectral Density @ 1 kHz 400 400 nV/(√Hz) typ 1 A version: Industrial temperature range -40°C to +85°C; typical at +25°C. 2 See Terminology section. 3 Guaranteed by design and characterization, not production tested. 4 AD780 as reference for the AD5532. 5 Ensure that you do not exceed TJ (max). See Absolute Maximum Ratings section. 6 Output unloaded. Rev. D | Page 4 of 20

AD5532 ISHA MODE Table 2. A Version1 Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments ANALOG CHANNEL V to V Nonlinearity3 ±0.018 ±0.018 % max ±0.006% typ after offset and gain adjustment. IN OUT Offset Error ±50 ±75 mV max ±10 mV typ. See Figure 9. Gain 3.46/3.52/3.6 6.96/7/7.02 min/typ/max See Figure 9 ANALOG INPUT (V ) IN Input Voltage Range 0 to 3 0 to 3 V Nominal input range. Input Lower Dead Band 70 70 mV max 50 mV typ. Referred to V . See Figure 9. IN Input Upper Dead Band 40 40 mV max 12 mV typ. Referred to V . See Figure 9. IN Input Current 1 1 μA max 100 nA typ. V acquired on 1 channel. IN Input Capacitance4 20 20 pF typ ANALOG INPUT (OFFS_IN) Input Current 1 1 μA max 100 nA typ. Input Voltage Range 0/4 0/4 Vmin/max Output range restricted from V + 2 V to V − 2 V. SS DD AC CHARACTERISTICS Output Settling Time4 3 3 μs max Output unloaded. Acquisition Time 16 16 μs max AC Crosstalk4 5 5 nV-s typ 1 A version: Industrial temperature range -40°C to +85°C; typical at +25°C. 2 See Terminology section. 3 Input range 100 mV to 2.96 V. 4 Guaranteed by design and characterization, not production tested. Rev. D | Page 5 of 20

AD5532 TIMING CHARACTERISTICS PARALLEL INTERFACE Table 3. Parameter1, 2 Limit at T , T (A Version) Unit Conditions/Comments MIN MAX t 0 ns min CS to WR setup time 1 t 0 ns min CS to WR hold time 2 t 50 ns min CS pulse width low 3 t 50 ns min WR pulse width low 4 t 20 ns min A4–A0, CAL, OFFS_SEL to WR setup time 5 t 7 ns min A4–A0, CAL, OFFS_SEL to WR hold time 6 1 See Figure 2 and Figure 3, the parallel interface timing diagrams. 2 Guaranteed by design and characterization, not production tested. PARALLEL INTERFACE TIMING DIAGRAMS t1 t2 CS t3 200μA IOL t 4 WR TO OUTPUT 1.6V t5 t6 PIN CL A4O–FAF0S, _CSAELL, 00939-C-002 50pF 200μA IOH 00939-C-003 Figure 2. Parallel Write (ISHA Mode Only) Figure 3. Load Circuit for DOUT Timing Specifications Rev. D | Page 6 of 20

AD5532 SERIAL INTERFACE Table 4. Parameter1, 2 Limit at T , T (A Version) Unit Conditions/Comments MIN MAX f 3 14 MHz max SCLK frequency CLKIN t 28 ns min SCLK high pulse width 1 t 28 ns min SCLK low pulse width 2 t 15 ns min SYNC falling edge to SCLK falling edge setup time 3 t 50 ns min SYNC low time 4 t 10 ns min D setup time 5 IN t 5 ns min D hold time 6 IN t 5 ns min SYNC falling edge to SCLK rising edge setup time for read back 7 t 4 20 ns max SCLK rising edge to D valid 8 OUT t94 60 ns max SCLK falling edge to DOUT high impedance t 400 ns min 10th SCLK falling edge to SYNC falling edge for read back 10 t 400 ns min 24th SCLK falling edge to SYNC falling edge for DAC mode write 11 t 5 7 ns min SCLK falling edge to SYNC falling edge setup time for read back 12 t 1 SCLK 1 2 3 4 5 6 7 8 9 10 t t 3 2 SYNC t4 t5 t 6 DIN 00939-C-004 MSB LSB Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes) t 1 SCLK 1 2 3 4 5 21 22 23 24 1 t t 3 2 SYNC t t t 4 5 11 t 6 DIN 00939-C-005 MSB LSB Figure 5. 24-Bit Write (DAC Mode) t t 7 1 SCLK 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 t12 t2 SYNC t10 t4 DOUT t8 t9 00939-C-006 MSB LSB Figure 6. 14-Bit Read (Both Readback Modes) 1 See Figure 4, Figure 5, and Figure 6. 2 Guaranteed by design and characterization, not production tested. 3 In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns. 4 These numbers are measured with the load circuit of Figure 3. 5 SYNC should be taken low while SCLK is low for read back. Rev. D | Page 7 of 20

AD5532 ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter1 Rating other conditions above those indicated in the operational VDD to AGND −0.3 V to +17 V section of this specification is not implied. Exposure to absolute VSS to AGND +0.3 V to −17 V maximum rating conditions for extended periods may affect AVCC to AGND, DAC_GND −0.3 V to +7 V device reliability. DVCC to DGND −0.3 V to +7 V For higher junction temperatures derate as follows: Digital Inputs to DGND −0.3 V to DV + 0.3 V CC Digital Outputs to DGND −0.3 V to DV + 0.3 V TJ (°C) Max Continuous Load Current per Group (mA) CC REF_IN to AGND, DAC_ GND −0.3 V to AV + 0.3 V 70 15.5 CC VIN to AGND, DAC_GND −0.3 V to AVCC + 0.3 V 90 9.025 VOUT 0–31 to AGND VSS − 0.3 V to VDD + 0.3 V 100 6.925 OFFS_IN to AGND V − 0.3 V to V + 0.3 V 110 5.175 SS DD OFFS_OUT to AGND AGND - 0.3 V to AV + 0.3 V 125 3.425 CC AGND to DGND −0.3 V to +0.3 V 135 2.55 150 1.5 Operating Temperature Range Industrial −40°C to +85°C Storage Temperature Range −65°C to +150°C ESD CAUTION Junction Temperature (T max) 150°C J 74-Lead CSPBGA Package, 41°C/W θ Thermal Impedance JA Reflow Soldering Peak Temperature AD5532ABC-x 220°C AD5532ABCZ-x 260°C Time at Peak Temperature 10 sec to 40 sec Max Power Dissipation (150°C − T )/θ mW2 A JA Max Continuous Load Current at 15 mA3 T = 70°C, per Channel Group J 1 Transient currents of up to 100 mA do not cause SCR latch-up. 2 This limit includes load power. 3 This maximum allowed continuous load current is spread over 8 channels and channels are grouped as follows: Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10 Group 2: Channels 14, 16, 18, 20. 21, 24, 25, 26 Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29 Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31 Rev. D | Page 8 of 20

AD5532 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E F TOP VIEW F G G H H J J K K L L 1 2 3 4 5 6 7 8 9 10 11 00939-C-028 Figure 7. 74-Lead CSPBGA Ball Configuration Table 6. 74-Lead CSPBGA Ball Configuration CSPBGA Number Ball Name CSPBGA Number Ball Name CSPBGA Number Ball Name A1 Not connected C10 AV 1 J10 VO9 CC A2 A4 C11 REF_OUT J11 VO11 A3 A2 D1 VO20 K1 VO17 A4 A0 D2 DAC_GND2 K2 VO15 A5 CS/SYNC D10 AV 2 K3 VO27 CC A6 DV D11 OFFS_OUT K4 V 3 CC SS A7 SCLK E1 VO26 K5 V 1 SS A8 OFFSET_SEL E2 VO14 K6 V 4 SS A9 BUSY E10 AGND1 K7 V 2 DD A10 TRACK/RESET E11 OFFS_IN K8 VO2 A11 Not connected F1 VO25 K9 VO10 B1 VO16 F2 VO21 K10 VO13 B2 Not connected F10 AGND2 K11 VO12 B3 A3 F11 VO6 L1 Not connected B4 A1 G1 VO24 L2 VO28 B5 WR G2 VO8 L3 VO29 B6 DGND G10 VO5 L4 VO30 B7 D G11 VO3 L5 V 3 IN DD B8 CAL H1 VO23 L6 V 1 DD B9 SER/PAR H2 VIN L7 V 4 DD B10 DOUT H10 VO4 L8 VO31 B11 REF_IN H11 VO7 L9 VO0 C1 VO18 J1 VO22 L10 VO1 C2 DAC_GND1 J2 VO19 L11 Not connected C6 Not connected J6 V 2 SS Rev. D | Page 9 of 20

AD5532 Table 7. Pin Function Descriptions Pin Function AGND (1–2) Analog GND pins. AV (1–2) Analog Supply pins. Voltage range from 4.75 V to 5.25 V. CC V (1–4) V Supply pins. Voltage range from 8 V to 16.5 V. DD DD V (1–4) V Supply pins. Voltage range from –4.75 V to –16.5 V. SS SS DGND Digital GND pins. DV Digital Supply pins. Voltage range from 2.7 V to 5.25 V. CC DAC_GND (1–2) Reference GND supply for all DACs. REF_IN Reference voltage for Channels 0–31. REF_OUT Reference Output Voltage. V (0–31) Analog Output Voltages from the 32 channels. OUT V Analog Input Voltage. Connect this to AGND if operating in DAC mode only. IN A4–A1, A0 Parallel Interface: 5 address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Internal pull-up devices on these logic inputs. Therefore, they can be left floating and default to a logic high condition. CAL Parallel Interface: Control input that allows all 32 channels to acquire V simultaneously. Internal pull-down devices on IN these logic inputs. Therefore, they can be left floating and default to a logic low condition CS/SYNC This is the active low Chip Select pin for the parallel interface and the Frame Synchronization pin for the serial interface. WR Parallel interface: Write pin; active low. This is used in conjunction with the CS pin to address the device using the parallel interface. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low condition. OFFSET_SEL Parallel interface: Offset Select pin; active high. This is used to select the offset channel. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low condition SCLK Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode). D Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Internal pull-up devices on these logic IN inputs. Therefore, they can be left floating and default to a logic high condition. D Output from the DAC registers for read back. Data is clocked out on the rising edge of SCLK and is valid on the falling OUT edge of SCLK. SER/PAR This pin allows the user to select whether the serial or parallel interface is used. If the pin is tied low, the parallel interface is used. If it is tied high, the serial interface is used. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low condition. OFFS_IN Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the user wants to drive this pin with the offset channel. OFFS_OUT Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the span. BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when the acquisition operation is complete. TRACK/RESET If this input is held high, V is acquired once the channel is addressed. While it is held low, the input to the gain/offset IN stage is switched directly to V . The addressed channel begins to acquire V on the rising edge of TRACK. See TRACK IN IN Input section for further information. This input can also be used as a means of resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going pulse of between 90 ns and 200 ns to this pin. See section on RESET Function for further details. Internal pull-up devices on these logic inputs. Therefore, they can be left floating and default to a logic high condition. VOUT OUTPUT VOLTAGE GAIN ERROR + OFFSET ERROR FULL-SCALE IDEAL ERROR RANGE TRANSFER FUNCTION IDEAL GAIN× REFIN ACTUAL IDEAL TRANSFER OFFSET TRANSFER FUNCTION ERROR FUNCTION OFFSET RANGE IDEAL GAIN× 50mV Figure 80. DAC Transfer DFAuCn cCtiOoDnE (OFFS_1IN6k=0) 00939-C-007 0DVELAODW BEAR7N0DmV DE2U.A9PD6P BE3AVRND VIN 00939-C-008 Figure 9. ISHA Transfer Function Rev. D | Page 10 of 20

AD5532 TERMINOLOGY Output Noise Spectral Density DAC MODE This is a measure of internally generated random noise. Integral Nonlinearity (INL) Random noise is characterized as a spectral density (voltage per This is a measure of the maximum deviation from a straight root Hertz). It is measured by loading all DACs to midscale and line passing through the endpoints of the DAC transfer measuring noise at the output. It is measured in nV/(√Hz). function. It is expressed as a percentage of full-scale span. Differential Nonlinearity (DNL) Output Temperature Coefficient This is the difference between the measured change and the This is a measure of the change in analog output with changes ideal 1 LSB change between any two adjacent codes. A specified in temperature. It is expressed in ppm/°C. DNL of ±1 LSB maximum ensures monotonicity. DC Power-Supply Rejection Ratio (PSRR) Offset DC power-supply rejection ratio is a measure of the change in Offset is a measure of the output with all zeros loaded to the analog output for a change in supply voltage (VDD and VSS). It is DAC and OFFS_IN = 0. Because the DAC is lifted off the expressed in dBs. VDD and VSS are varied ±5%. ground by approximately 50 mV, this output is typically DC Crosstalk V =Gain×50mV This is the DC change in the output level of one DAC at OUT midscale in response to a full-scale code change (all 0s to all 1s Full-Scale Error and vice versa) and an output change of all other DACs. It is This is a measure of the output error with all 1s loaded to the expressed in μV. DAC. It is expressed as a percentage of full-scale range. See Figure 8. It is calculated as ISHA MODE Full−ScaleError=VOUT(Full−Scale)−(IdealGain×REFIN) VIN to VOUT Nonlinearity The measure of the maximum deviation from a straight line where passing through the endpoints of the V versus V transfer IdealGain=3.52forAD5532−1/−3/−5 IN OUT function. It is expressed as a percentage of the full-scale span. IdealGain=7forAD5532−2 Offset Error Output Settling Time This is a measure of the output error when VIN = 70 mV. Ideally, This is the time taken from when the last data bit is clocked into with VIN = 70 mV: ( ) the DAC until the output has settled to within ±0.39%. V =(Gain×70)− (Gain−1)×V mV OUT OFFS_IN OFFS_IN Settling Time Offset error is a measure of the difference between V (actual) OUT The time taken from a 0 V to 3 V step change in input voltage and V (ideal). It is expressed in mV and can be positive or OUT on OFFS_IN until the output has settled to within ±0.39%. negative. See Figure 9. Digital-to-Analog Glitch Impulse Gain Error This is the area of the glitch injected into the analog output This is a measure of the span error of the analog channel. It is when the code in the DAC register changes state. It is specified the deviation in slope of the transfer function expressed in mV. as the area of the glitch in nV-secs when the digital code is See Figure 9. It is calculated as changed by 1 LSB at the major carry transition (011 . . . 11 to Gain Error = 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Actual Full-Scale Output − Ideal Full-Scale Output − Offset Error Digital Crosstalk where: This is the glitch impulse transferred to the output of one DAC ( ) IdealFull−ScaleOutput=Gain×2.96− (Gain−1)×V at midscale while a full-scale code change (all 1s to all 0s and OFFS_IN vice versa) is written to another DAC. It is expressed in nV-secs. AC Crosstalk Analog Crosstalk This is the area of the glitch that occurs on the output of one This is the area of the glitch transferred to the output (V ) of channel while another channel is acquiring. It is expressed in OUT one DAC due to a full-scale change in the output (V ) of nV-secs. OUT another DAC. The area of the glitch is expressed in nV-secs. Output Settling Time Digital Feedthrough This is the time taken from when BUSY goes high to when the This is a measure of the impulse injected into the analog output has settled to ±0.018%. outputs from the digital control inputs when the part is not Acquisition Time being written to, i.e., CS/SYNC is high. It is specified in nV-secs This is the time taken for the V input to be acquired. It is the IN and is measured with a worst-case change on the digital input length of time that BUSY stays low. pins, for example, from all 0s to all 1s and vice versa. Rev. D | Page 11 of 20

AD5532 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 3.535 VREFIN = 3V TA = 25°C 0.8 VOFFS_IN = 0V VREFIN = 3V TA = 25°C 0.6 0.4 B) 3.530 LS 0.2 ROR ( 0 (V)UT R O L E–0.2 V DN–0.4 3.525 –0.6 ––10..08 00939-C-009 3.520 00939-C-012 0 2k 4k 6k 8k 10k 12k 14k 16k 6 4 2 0 –2 –4 –6 DAC CODE SINK/SOURCE CURRENT (mA) Figure 10. Typical DNL Plot Figure 13. VOUT Source and Sink Capability 10 1.0 0.2 TA = 25°C VREFIN = 3V 8 VOFFS_IN = 0.5V 0.5 DNL MAX 0.1 OR (LSB) 0 INL MAX 0 R (% FSR) (V)UT 46 R O O R R V E INL MIN R NL L E 2 D N I –0.5 DNL MIN –0.1 0 –1.0 –0.2 00939-C-010 –2 00939-C-013 –40 0 40 80 TEMPERATURE (°C) TIME BASE (2μs/DIV) Figure 14. Full-Scale Settling Time Figure 11. INL Error an DNL Error vs. Temperature 5.325 5.309 DAC LOADED TO MIDSCALE VREFIN = 3V 5.308 VOFFS_IN = 0V 5.315 5.307 5.306 5.305 V (V)OUT5.295 V (V)OUT55..330054 5.303 5.285 TA = 25°C 5.275 00939-C-011 55..330021 VVROEFFFISN_ I=N 3=V 0V 00939-C-014 –40 0 40 80 TEMPERATURE (°C) TIME BASE (50ns/DIV) Figure 12. VOUT vs. Temperature Figure 15. Major Code Transition Glitch Impulse Rev. D | Page 12 of 20

AD5532 0.024 70k TA = 25°C 63791 TA = 25°C 0.020 VREFIN = 3V VREFIN = 3V 0.016 VOFFS_IN = 0V 60k VIN = 1.5V VOFFS_IN = 0V 0.012 50k 0.008 %) ERROR (OUT–00..0000044 FREQUENCY 3400kk V –0.008 20k –0.012 –0.016 ––00..002240 00939-C-015 100k 200 1545 00939-C-017 0.10 2.96 5.2670 5.2676 5.2682 VIN (V) VOUT (V) Figure 16. VIN to VOUT Accuracy after Offset and Gain Adjustment (ISHA Figure 18. ISHA-Mode Repeatability (64 k Acquisitions) Mode) 5V 100 90 BUSY VOUT TA = 25°C VREFIN = 3V VIN = 0→1.5V 10 0% 1V 2μs 00939-C-016 Figure 17. Acquisition Time and Output Settling Time (ISHA Mode) Rev. D | Page 13 of 20

AD5532 FUNCTIONAL DESCRIPTION The AD5532 consists of 32 DACs and an ADC (for ISHA OFFS_IN this offset voltage can be used as the offset voltage for mode) in a single package. In DAC mode, a 14-bit digital word the 32 output amplifiers. It is important to choose the offset so is loaded into one of the 32 DAC Registers via the serial that V is within maximum ratings. OUT interface. This is then converted (with gain and offset) into an RESET FUNCTION analog output voltage (V 0–V 31). OUT OUT The reset function on the AD5532 can be used to reset all To update a DAC’s output voltage, the required DAC is nodes on this device to their power-on reset condition. This is addressed via the serial port. When the DAC address and code implemented by applying a low-going pulse of between 90 ns have been loaded, the selected DAC converts the code. and 200 ns to the TRACK/RESETpin on the device. If the applied pulse is less than 90 ns, it is assumed to be a glitch At power-on, all the DACs, including the offset channel, are and no operation takes place. If the applied pulse is wider loaded with zeros. Each of the 33 DACs is offset internally by than 200 ns, this pin adopts its track function on the selected 50 mV (typ) from GND, so the outputs V 0 to V 31 are OUT OUT channel, V is switched to the output buffer, and an acquisition 50 mV (typ) at power-on if the OFFS_IN pin is driven directly IN by the on-board offset channel (OFFS_OUT), i.e. if OFFS_IN is on the channel does not occur until a rising edge of TRACK. 50 mV, V = (Gain × V ) – (Gain – 1) ×V = 50 mV. OUT DAC OFFS_IN ISHA MODE OUTPUT BUFFER STAGE—GAIN AND OFFSET In ISHA mode, the input voltage V is sampled and converted IN The function of the output buffer stage is to translate the 50 into a digital word. The noninverting input to the output buffer mV–3 V output of the DAC to a wider range. This is done by (gain and offset stage) is tied to VIN during the acquisition gaining up the DAC output by 3.52/7 and offsetting the voltage period to avoid spurious outputs, while the DAC acquires the by the voltage on OFFS_IN pin. correct code. This is completed in 16 μs max. The updated DAC output then assumes control of the output voltage. The output AD5532-1/AD5532-3/AD5532-5: voltage of the DAC is connected to the noninverting input of V =3.52 × V − 2.52 × V the output buffer. Because the channel output voltage is OUT DAC OFFS_IN effectively the output of a DAC, there is no droop associated AD5532-2: with it. As long as power is maintained to the device, the output V =7 × V − 6 × V voltage is constant until this channel is addressed again. OUT DAC OFFS_IN Because the internal DACs are offset by 70 mV (max) from V is the output of the DAC. DAC GND, the minimum V in ISHA mode is 70 mV. The V is the voltage at the OFFS_IN pin. IN OFFS_IN maximum V is 2.96 V due to the upper dead band of 40 mV IN The following table shows how the output range on V relates OUT (max). to the offset voltage supplied by the user. ANALOG INPUT (ISHA MODE) Table 8. Sample Output Voltage Ranges Figure 19 shows the equivalent analog input circuit. The V V V V OFFS_IN DAC OUT OUT Capacitor C1 is typically 20 pF and can be attributed to pin (V) (V) (AD5532-1/-3/-5) (AD5532-2) capacitance and 32 off-channels. When a channel is selected, an 0.5 0.05 to 3 −1.26 to +9.3 Headroom limited extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged 1 0.05 to 3 −2.52 to +8.04 −6 to +15 to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. The external source V is limited only by the headroom of the output amplifiers. OUT must be able to charge/discharge this additional capacitance V must be within maximum ratings. OUT within 1 μs–2 μs of channel selection so that V can be IN OFFSET VOLTAGE CHANNEL acquired accurately. Thus, a low impedance source is suggested. The offset voltage can be externally supplied by the user at ADDRESSED CHANNEL OFFS_IN or it can be supplied by an additional offset voltage VIN C1 C2 channel on the device itself. The offset can be set up in two 20pF 7.5pF ways. In ISHA mode, the required offset voltage is set up on V IN aconrdr eascpqounirdeidn gb yto t hthe eo offfsfeste tc hvaalnunee ils. Ilona DdAedC d mireocdtely, tihneto c othdee 00939-C-018 offset DAC. This offset channel’s DAC output is directly Figure 19. Analog Input Circuit connected to OFFS_OUT. By connecting OFFS_OUT to Large source impedances significantly affect the performance of the ADC. An input buffer amplifier may be required. Rev. D | Page 14 of 20

AD5532 1. ISHA Mode TRACK FUNCTION (ISHA MODE) In this mode, a channel is addressed and that channel acquires Typically in ISHA mode of operation TRACK is held high and the voltage on V . This mode requires a 10-bit write (see Figure IN the channel begins to acquire when it is addressed. However, if 21a) to address the relevant channel (V 0–V 31, offset OUT OUT TRACK is low when the channel is addressed, V is switched to IN channel or all channels). MSB is written first. the output buffer and an acquisition on the channel does not 2. DAC Mode occur until a rising edge of TRACK. At this stage, the BUSY pin goes low until the acquisition is complete, at which point the In this standard mode, a selected DAC register is loaded serially. DAC assumes control of the voltage to the output buffer and V This requires a 24-bit write (10 bits to address the relevant DAC IN is free to change again without affecting this output value. plus an extra 14 bits of DAC data). MSB is written first. The user must allow 400 ns (min) between successive writes in DAC This is useful in an application where the user wants to ramp up mode. V until V reaches a particular level (see Figure 20). V IN OUT IN 3. Acquire and Readback Mode does not need to be acquired continuously while it is ramping This mode allows the user to acquire V and read back the data up. TRACK can be kept low and only when V has reached its IN OUT in a particular DAC register. The relevant channel is addressed desired voltage is TRACK brought high. At this stage, the (10-bit write, MSB first) and V is acquired in 16 μs (max). acquisition of V begins. IN IN Following the acquisition, after the next falling edge of SYNC, In the example shown, a desired voltage is required on the the data in the relevant DAC register is clocked out onto the output of the pin driver. This voltage is represented by one input DOUT line in a 14-bit serial format. The full acquisition time to a comparator. The microcontroller/microprocessor ramps up must elapse before the DAC register data can be clocked out. the input voltage on VIN through a DAC. TRACK is kept low 4. Readback Mode while the voltage on V ramps up so that V is not continually IN IN Again, this is a Readback mode but no acquisition is performed. acquired. When the desired voltage is reached on the output of The relevant channel is addressed (10-bit write, MSB first) and the pin driver, the comparator output switches. The μC/μP then on the next falling edge of SYNC, the data in the relevant DAC knows what code is required to be input to obtain the desired register is clocked out onto the D line in a 14-bit serial voltage at the DUT. The TRACK input is now brought high and OUT format. The user must allow 400 ns (min) between the last the part begins to acquire V . At this stage BUSY goes low until IN SCLK falling edge in the 10-bit write and the falling edge of V has been acquired. The output buffer is then switched from IN SYNC in the 14-bit read back. The serial write and read words V to the output of the DAC. IN can be seen in Figure 21. MODES OF OPERATION This feature allows the user to read back the DAC register code The AD5532 can be used in four different modes of operation. of any of the channels. In DAC mode, this is useful in These modes are set by two mode bits, the first two bits in the verification of write cycles. In ISHA mode, readback is useful if serial word. the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on V . If OUT Table 9. Modes of Operation this voltage is required again, the user can input the code Mode Bit 1 Mode Bit 2 Operating Mode directly to the DAC register without going through the 0 0 ISHA mode acquisition sequence. 0 1 DAC mode 1 0 Acquire and Read Back 1 1 Read Back PIN DRIVER OUTPUT VOUT1 DEVICE CONTROLLER DAC VIN ACCQIURICSUITITION STAGE UTENSDTER BUSY AD5532 TRACK THRESHOLD ONLY ONE CHANNEL SHOWN FOR SIMPLICITY VOLTAGE 00939-C-019 Figure 20. Typical ATE Circuit Using TRACK Input Rev. D | Page 15 of 20

AD5532 SERIAL INTERFACE not shift data in or out until it receives the falling edge of the The serial interface allows easy interfacing to most micro- SYNC signal. controllers and DSPs, such as the PIC16C, PIC17C, QSPI, SPI, Table 10 DSP56000, TMS320, and ADSP-21xx, without the need for any Pin Description glue logic. When interfacing to the 8051, the SCLK must be SER/PAR This pin is tied high to enable the serial interface inverted. The Microprocessor Interfacing section explains how and to disable the parallel interface. The serial to interface to some popular DSPs and microcontrollers. Figure interface is controlled by the four pins that follow. 4, Figure 5, and Figure 6 show the timing diagram for a serial SYNC, Standard 3-wire interface pins. The SYNC pin is read and write to the AD5532. The serial interface works with D , SCLK shared with the CS function of the parallel interface. IN both a continuous and a noncontinuous serial clock. The first D Data Out pin for reading back the contents of the OUT falling edge of SYNC resets a counter that counts the number of DAC registers. The data is clocked out on the rising serial clocks to ensure the correct number of bits are shifted in edge of SCLK and is valid on the falling edge of and out of the serial shift registers. Any further edges on SYNC SCLK. Mode The four different modes of operation are described are ignored until the correct number of bits are shifted in or Bits in the Modes of Operation section. out. Once the correct number of bits for the selected mode has Cal Bit In DAC mode, this is a test bit. When high, it loads all been shifted in or out, the SCLK is ignored. In order for another 0s or all 1s to the 32 DACs simultaneously. In ISHA serial transfer to take place the counter must be reset by the mode, all 32 channels acquire V at the same time IN falling edge of SYNC. when this bit is high. In ISHA mode, the acquisition time is then 45 μs (typ) and accuracy may be In readback, the first rising SCLK edge after the falling edge of reduced. This bit is set low for normal use. SYNC causes DOUT to leave its high impedance state and data is Offset Sel If this is set high, the offset channel is selected and clocked out onto the D line and also on subsequent SCLK Bit Bits A4–A0 are ignored. OUT rising edges. The D pin goes back into a high impedance Test Bit Must be set low for correct operation of the part. OUT state on the falling edge of the 14th SCLK. Data on the D line A4–A0 Used to address any one of the 32 channels IN is latched in on the first SCLK falling edge after the falling edge (A4 = MSB of address, A0 = LSB). of the SYNC signal and on subsequent SCLK falling edges. DB13– Used to write a 14-bit word into the addressed DAC DB0 register. Only valid when in DAC mode. During read-back D is ignored. The serial interface does IN MSB LSB 0 0 CAL OFFSET_SEL 0 A4–A0 MODE BIT 1 MODE BIT 2 TEST BIT MODE BITS a. 10-BIT SERIAL WRITE WORD (ISHA MODE) MSB LSB 0 1 CAL OFFSET_SEL 0 A4–A0 DB13–DB0 TEST BIT MODE BITS b. 24-BIT INPUT SERIAL WRITE WORD (DAC MODE) MSB LSB MSB LSB 1 0 CAL OFFSET_SEL 0 A4–A0 DB13–DB0 TEST BIT MODE BITS 10-BIT 14-BIT DATA SERIAL WORD READ FROM PART AFTER WRITTEN TO PART NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) c. INPUT SERIAL INTERFACE (ACQUIRE AND READ-BACK MODE) MSB LSB MSB LSB 1 1 CAL OFFSET_SEL 0 A4–A0 DB13–DB0 TEST BIT MODE BITS 10-BIT 14-BIT DATA SERIAL WORD READ FROM PART AFTER WRITTEN TO PART NEXT FALLING EDGE OF SYNC d. INPUT SEFRigIAuLre I N21T.E SReFriAaCl IEn t(RerEfaAcDe- BFoArCmKa MtsO DE(D)B13 = MSB OF DAC WORD) 00939-C-020 Rev. D | Page 16 of 20

AD5532 PARALLEL INTERFACE (ISHA MODE ONLY) The SER/PAR bit must be tied low to enable the parallel Figure 22 shows the connection diagram. interface and disable the serial interface. The parallel interface is AD5532* ADSP-2101/ controlled by nine pins, as described in Table 11. ADSP-2103* DOUT DR Table 11. SYNC TFS Pin Description RFS CS Active low package select pin. This pin is shared WR Awcitthiv teh leo wSY wNrCit feu pnicnt.i oTnh efo vra tlhuee ss eornia tlh ine taedrfdarcees.s SCDLIKN DSCTLK 00939-C-021 pins are latched on a rising edge of WR. *ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. AD5532 to ADSP-2101/ADSP-2103 Interface A4–A0 Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the AD5532 to MC68HC11 relevant channel (out of a possible 32). The serial peripheral interface (SPI) on the MC68HC11 is OFFSET_SEL Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it configured for master mode (MSTR) = 1, clock polarity bit is high, the offset channel is addressed. The (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is address on A4–A0 is ignored in this case. configured by writing to the SPI control register (SPCR)—see CAL When this pin is high, all 32 channels acquire the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK VIN simultaneously. The acquisition time is then of the AD5532, the MOSI output drives the serial data line (D ) IN 45 μs (typ) and accuracy may be reduced. of the AD5532, and the MISO input is driven from D . The OUT SYNC signal is derived from a port line (PC7). When data is MICROPROCESSOR INTERFACING being transmitted to the AD5532, the SYNC line is taken low AD5532 to ADSP-21xx Interface (PC7). Data appearing on the MOSI output is valid on the ADSP-21xx DSPs are easily interfaced to the AD5532 without falling edge of SCK. Serial data from the 68HC11 is transmitted the need for extra logic. in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To transmit A data transfer is initiated by writing a word to the TX register 10 data bits in ISHA mode, it is important to left-justify the data after the SPORT has been enabled. In a write sequence, data is in the SPDR register. PC7 must be pulled low to start a transfer. clocked out on each rising edge of the DSP serial clock and It is taken high and pulled low again before other read/write clocked into the AD5532 on the falling edge of its SCLK. In cycles can take place. Figure 23 shows a connection diagram. readback, 16 bits of data are clocked out of the AD5532 on each AD5532* MC68HC11* rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. DIN is ignored. The valid 14 bits of data is DOUT MISO centered in the 16-bit RX register in this configuration. The SYNC PC7 SPORT Control register should be set up as in Table 12. SCLK SCK TTFaSbWle =1 2R.F SW = 1 Alternate framing DIN MOSI 00939-C-022 INVRFS = INVTFS = 1 Active low frame signal *ADDITIONAL PINS OMITTED FOR CLARITY DTYPE = 00 Right justify data Figure 23. AD5532 to MC68HC11 Interface ISCLK = 1 Internal serial clock TFSR = RFSR = 1 Frame every word IRFS = 0 External framing signal ITFS = 1 Internal framing signal SLEN = 1001 10-bit data-words (ISHA mode write) SLEN = 0111 3 × 8-bit data-words (DAC mode write) SLEN = 1111 16-bit data-words (Readback mode) Rev. D | Page 17 of 20

AD5532 AD5532 to PIC16C6x/7x The PIC16C6x/7x synchronous serial port (SSP) is configured The AD5532 has several advantages: no refreshing is required, as an SPI master with the Clock Polarity Bit = 0. This is done by there is no droop, pedestal error is eliminated, and there is no writing to the synchronous serial port control register need for extra filtering to remove glitches. Overall a higher level (SSPCON). See the PIC16/17 Microcontroller User Manual. In of integration is achieved in a smaller area (see Figure 26). this example, the I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5532. This microcontroller PARAMETRIC MEASUREMENT SYSTEM BUS transfers only eight bits of data during each serial transfer UNIT DAC operation; therefore, two or three consecutive read/write DAC ACTIVE operations are needed depending on the mode. Figure 24 LOAD shows the connection diagram. DAC AD5532* PIC16C6x/7x* STORED DATA DRIVER SCLK SCK/RC3 AND INHIBIT DAC PATTERN FORMATTER DOUT SDO/RC5 DAC DUT DIN SDI/RC4 PERIOD SYNC RA1 00939-C-023 GENTDEIAEMRNLIANADTGYION COMPARE DAC REGISTER *ADDITIONAL PINS OMITTED FOR CLARITY DAC Figure 24. AD5532 to PIC16C6x/7x Interface AD5532 to 8051 DACs SYSTEM BUS COMPARATOR 00939-C-025 The AD5532 requires a clock synchronized to the serial data. Figure 26. AD5532 in an ATE System The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD and a Typical Application Circuit (DAC Mode) shift clock is output on TxD. Figure 25 shows how the 8051 is The AD5532 can be used in many optical networking connected to the AD5532. Because the AD5532 shifts data out applications that require a large number of DACs to perform on the rising edge of the shift clock and latches data in on the control and measurement functions. In the example shown in falling edge, the shift clock must be inverted. The AD5532 Figure 27, the outputs of the AD5532 are amplified and used to requires its data with the MSB first. Because the 8051 outputs control actuators that determine the position of MEMS mirrors the LSB first, the transmit routine must take this into account. in an optical switch. The exact position of each mirror is measured using sensors. The sensor readings are muxed using AD5532* 8051* four dual, 4-channel matrix switches (ADG739) and fed back to SCLK TxD an 8-channel, 14-bit ADC (AD7856). DOUT RxD The control loop is driven by an ADSP-2191M, a 16-bit fixed- DIN point DSP with 3 SPORT interfaces and 2 SPI ports. The DSP SYNC P1.1 00939-C-024 uthsee sm suomltiep loefx tehr,e asne dse rreiaadl p boarctks tdoa twar firtoe mda ttha et oA tDheC D. AC, control *ADDITIONAL PINS OMITTED FOR CLARITY Figure 25. AD5532 to 8051 Interface S APPLICATION CIRCUITS 1 1 E 1 MEMS N ADG739 AD5532 in a Typical ATE System AD5532 32 MAIRRRRAOYR 32 OS ×4 8 AD7856 R The AD5532 is ideally suited for use in automatic test equipment. Several DACs are required to control pin drivers, AD8544 comparators, active loads, and signal timing. Traditionally, ×2 sample-and-hold devices were used in this application. ADSP-2191M 00939-C-026 Figure 27. Typical Optical Control and Measurement Application Circuit Rev. D | Page 18 of 20

AD5532 Typical Application Circuit (ISHA Mode) The AD5532 can be used to set up voltage levels on 32 channels The power supply lines of the AD5532 should use as large a as shown in the circuit that follows. An AD780 provides the 3 V trace as possible to provide low impedance paths and reduce the reference for the AD5532 and for the AD5541 16-bit DAC. A effects of glitches on the power supply line. Fast switching simple 3-wire interface is used to write to the AD5541. Because signals, such as clocks, should be shielded with digital ground the AD5541 has an output resistance of 6.25 kΩ(typ), the time to avoid radiating noise to other parts of the board and should taken to charge/discharge the capacitance at the V pin is never be run near the reference inputs. A ground line routed IN significant. Hence an AD820 is used to buffer the DAC output. between the D and SCLK lines helps reduce crosstalk between IN Note that it is important to minimize noise on V and REFIN them (not required on a multilayer board as there is a separate IN when laying out the circuit. ground plane, but separating the lines helps). AVCC AVCC DVCC VSS Note it is essential to minimize noise on V and REFIN lines. IN Particularly for optimum ISHA performance, the V line must IN VDD be kept noise free. Depending on the noise performance of the board, a noise filtering capacitor may be required on the V CS AD5541* AD820 VINAD5532* VOUT0–VOUT31 line. If this capacitor is necessary, then for optimum througINhput DIN it may be necessary to buffer the source which is driving V . SCLK OFFS_IN IN REF Avoid crossover of digital and analog signals. Traces on OFFS_OUT opposite sides of the board should run at right angles to each REFIN other. This reduces the effects of feedthrough through the board. A micro-strip technique is by far the best, but not always AD780* possible with a double-sided board. In this technique, the VOUT *ADDITIONAL PINS OMITTED FOSRC CLKLARDITINY SYNC 00939-C-027 csiogmnaplo tnraecnets s aidree pofla tcheed b oona rtdh ei ss odleddeirc astiedde .t o ground plane while Figure 28. Typical Application Circuit (ISHA Mode) As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of POWER SUPPLY DECOUPLING the package during the assembly process. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5532 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5532 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (V , V , AV ) it is recom- SS DD CC mended to tie those pins together. The AD5532 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Rev. D | Page 19 of 20

AD5532 OUTLINE DIMENSIONS 12.00 A1 CORNER BSC SQ INDEXAREA 1110 9 8 7 6 5 4 3 21 A BALLA1 B INDICATOR C 10.00 D BSC SQ BOTTOM E TOP VIEW VIEW F G 1.00 H BSC J K L DETAIL A 1.70 MAX DETAIL A 1.10 0.25 0.30 MIN 0.20 0.70 COPLANARITY 0.60 SEATING 0.50 PLANE BALL DIAMETER COMPLIANTTO JEDEC STANDARDS MO-192-ABD-1 061306-A Figure 29. 74-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-74) Dimensions shown in millimeters ORDERING GUIDE Temperature Output Output Package Package Model1 Range Function Impedance Voltage Span Description Option AD5532ABC-1 −40°C to +85°C 32 DACs, 32-Channel ISHA 0.5 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABC-1REEL −40°C to +85°C 32 DACs, 32-Channel ISHA 0.5 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABC-2 −40°C to +85°C 32 DACs, 32-Channel ISHA 0.5 Ω typ 20 V 74-Ball CSP_BGA BC-74 AD5532ABC-3 −40°C to +85°C 32 DACs, 32-Channel ISHA 500 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABC-3REEL −40°C to +85°C 32 DACs, 32-Channel ISHA 500 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABC-5 −40°C to +85°C 32 DACs, 32-Channel ISHA 1 kΩ typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABC-5REEL −40°C to +85°C 32 DACs, 32-Channel ISHA 1 kΩ typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABCZ-1 −40°C to +85°C 32 DACs, 32-Channel ISHA 0.5 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABCZ-1REEL −40°C to +85°C 32 DACs, 32-Channel ISHA 0.5 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABCZ-2 −40°C to +85°C 32 DACs, 32-Channel ISHA 0.5 Ω typ 20 V 74-Ball CSP_BGA BC-74 AD5532ABCZ-3 −40°C to +85°C 32 DACs, 32-Channel ISHA 500 Ω typ 10 V 74-Ball CSP_BGA BC-74 AD5532ABC-5 −40°C to +85°C 32 DACs, 32-Channel ISHA 1 kΩ typ 10 V 74-Ball CSP_BGA BC-74 EVAL-AD5532EBZ Evaluation Board 1 Z = RoHS Compliant Part. © 2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00939-0-6/10(D) Rev. D | Page 20 of 20