Quad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs Data Sheet AD5522 FEATURES APPLICATIONS Quad parametric measurement unit (PMU) Automated test equipment (ATE) FV, FI, FN (high-Z), MV, MI functions Per-pin parametric measurement unit 4 programmable current ranges (internal R ) Continuity and leakage testing SENSE ±5 μA, ±20 μA, ±200 μA, and ±2 mA Device power supply 1 programmable current range up to ±80 mA (external R ) Instrumentation SENSE 22.5 V FV range with asymmetrical operation Source measure unit (SMU) Integrated 16-bit DACs provide programmable levels Precision measurement Gain and offset correction on chip Low capacitance outputs suited to relayless systems On-chip comparators per channel FI voltage clamps and FV current clamps Guard drive amplifier System PMU connections Programmable temperature shutdown SPI- and LVDS-compatible interfaces Compact 80-lead TQFP with exposed pad (top or bottom) FUNCTIONAL BLOCK DIAGRAM AGND AVSS AVDD DVCC DGND CCOMP[0:3] SYS_FORCE SYS_SENSE ×4 EN EXTFOH[0:3] REFVGRNEDF 111666 CMX 1 RR REEEGGG×2 X2 ROEGFF×S2ET1 6DACCL1H6- BDIATC CLH SW3 CFF[0:3] 16 INTERNAL RANGE SELECT 16 ×6 – FIN SW1 (±5µA, ±20µA, ±200µA, ±2mA)60Ω 1kΩ 16 MX1 R REEGG X2 REG16F1IN6 -DBAITC + AGND F+ORCE FOH[0:3] C REG MEASVH AMPLIFIER ×6 (Hi-Z) – SW5RSENSE SW2 SW4 SW6 4kΩ 111666 CMX 1 RR REEEGGG×2 X2 REG×2 16CL16L- DBAITC SW10 IVC RMEANIDNTGTEOER CL+L +– 2kΩ SW7 SW8 EXTMEASIH[0:3] ER(CXSUETRNESRREENNATLS ×5 or ×10 EXTMEASIL[0:3] UPTO ±80mA) MEASOUT[0:3] SW12 MUMX×EA1A/N×S0DO. 2UGTAIN TEMP – +– 4kΩ SW9 SENSOR MEASURE AGND 111666 CMX 1 RR REEEGGG×6 X2 RE×G616CP1H6- BDIATC SW11 AGND + CINU-ARMRPENT +– SW13 SW16 MGGEUUAAASRRVDDH[I0[N0:[3:03]:]3]/ DUT 111666 CMX 1 RR REEEGGG×6 X2 RE×G616CP1L6 -DBAITC CPL– + C–PH+ ×1– MVOELATSAUGREE +– DUTGND SW14 GUSAWR1D5AMP DDUUTTGGNNDD[0:3] COMPARATOR IN-AMP 10kΩ AGND 16 1O D6FA-FBCSITET OATOUMTPAPLLUILF TI EDRASC MEMATUSOOXUT SETENMSOPR TMPALM 16 SERIAL CLAMPAND POWER-ON INTERFACE GUARD CGALM RESET ALARM RESETSDO SCLKSDI SYNC BUSY LOAD SLVPDI/S CSCPOLKL0/ CSDPOIH0/ CSYPNOCL1/ CSDPOOH1/ CCPPOOL02/ CCPPOOH12/ CCPPOOL23/ CCPPOOH33/ 06197-001 Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5522 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Calibration................................................................................... 38 Applications ....................................................................................... 1 Additional Calibration ............................................................... 39 Functional Block Diagram .............................................................. 1 System Level Calibration ........................................................... 39 Revision History ............................................................................... 3 Circuit Operation ........................................................................... 40 General Description ......................................................................... 4 Force Voltage (FV) Mode .......................................................... 40 Specifications ..................................................................................... 6 Force Current (FI) Mode ........................................................... 41 Timing Characteristics .............................................................. 11 Serial Interface ................................................................................ 42 Absolute Maximum Ratings .......................................................... 15 SPI Interface ................................................................................ 42 Thermal Resistance .................................................................... 15 LVDS Interface............................................................................ 42 ESD Caution ................................................................................ 15 Serial Interface Write Mode ...................................................... 42 Pin Configurations and Function Descriptions ......................... 16 RESET Function ......................................................................... 42 Typical Performance Characteristics ........................................... 22 BUSY and LOAD Functions ..................................................... 42 Terminology .................................................................................... 29 Register Update Rates ................................................................ 44 Theory of Operation ...................................................................... 30 Register Selection ....................................................................... 44 Force Amplifier ........................................................................... 30 Write System Control Register ................................................. 46 Comparators ................................................................................ 30 Write PMU Register ................................................................... 48 Clamps ......................................................................................... 30 Write DAC Register ................................................................... 50 Current Range Selection ............................................................ 31 Read Registers ............................................................................. 53 High Current Ranges ................................................................. 31 Readback of System Control Register...................................... 54 Measure Current Gains.............................................................. 32 Readback of PMU Register ....................................................... 55 VMID Voltage ............................................................................. 32 Readback of Comparator Status Register ................................ 56 Choosing Power Supply Rails ................................................... 33 Readback of Alarm Status Register .......................................... 56 Measure Output (MEASOUTx Pins)....................................... 33 Readback of DAC Register ........................................................ 57 Device Under Test Ground (DUTGND)................................. 33 Applications Information .............................................................. 58 Guard Amplifier ......................................................................... 34 Power-On Default ...................................................................... 58 Compensation Capacitors ......................................................... 34 Setting Up the Device on Power-On ....................................... 58 System Force and Sense Switches ............................................. 35 Changing Modes ........................................................................ 59 Temperature Sensor ................................................................... 35 Required External Components ............................................... 59 DAC Levels ...................................................................................... 36 Power Supply Decoupling ......................................................... 60 Offset DAC .................................................................................. 36 Power Supply Sequencing ......................................................... 60 Gain and Offset Registers .......................................................... 36 Typical Application for the AD5522 ........................................ 60 Cached X2 Registers ................................................................... 37 Outline Dimensions ....................................................................... 62 Reference Voltage (VREF) ......................................................... 37 Ordering Guide .......................................................................... 63 Reference Selection .................................................................... 37 Rev. F | Page 2 of 64

Data Sheet AD5522 REVISION HISTORY 6/2018—Rev. E to Rev. F 10/2008—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 7 Changes to Table 1 ............................................................................ 6 Changes to Table 2 .......................................................................... 11 Change to 4 DAC X1 Parameter, Table 2 ..................................... 11 Changes to Figure 5 ......................................................................... 13 Changes to Table 3 .......................................................................... 12 Changes to Choosing Power Supply Rails Section and Note 2, Change to Reflow Soldering Parameter, Table 4 ......................... 15 Table 10 ............................................................................................. 33 Changes to Figure 18, Figure 19, Figure 20, and Figure 21 ....... 23 Moved Table 11 ................................................................................ 34 Changes to Figure 25 ...................................................................... 24 Changes to MV Transfer Function, Table 11 and Note 3, Changes to Force Amplifier Section ............................................. 29 Table 11 ............................................................................................. 34 Changes to Clamps Section ........................................................... 29 Changes to Table 39 ........................................................................ 60 Changes to High Current Ranges Section ................................... 30 Changes to Ordering Guide ........................................................... 63 Changes to Choosing Power Supply Rails Section ..................... 32 Changes to Compensation Capacitors Section ........................... 33 5/2012—Rev. D to Rev. E Added Table 14, Renumbered Tables Sequentially ..................... 36 Change to MV Transfer Function, Table 11 ................................ 33 Changes to Reference Selection Example .................................... 36 Changes to Table 15 and BUSYEE and LOADEE Functions 2/2011—Rev. C to Rev. D Section .............................................................................................. 40 Changes to Measure Current, Gain Error Tempco Parameter .... 6 Changes to Table 17 and Register Update Rates Section ........... 41 Changes to Force Current, Common Mode Error (Gain = 5) Added Table 38 ................................................................................ 57 and Common Mode Error (Gain = 10) Parameters ..................... 7 Changes to Ordering Guide ........................................................... 60 Changes to Figure 5 ......................................................................... 13 Changes to Figure 6 ......................................................................... 14 7/2008—Revision 0: Initial Version Changes to Figure 15 ...................................................................... 22 Changes to High Current Ranges Section ................................... 31 Changes to Gain and Offset Registers Section ............................ 36 Changes to Endnote 1 in Table 17 and Figure 56 ........................ 43 Changes to Register Update Rates and Figure 57 ....................... 44 Changes to Bit 15 to Bit 0 Description in Table 28 ..................... 50 5/2010—Rev. B to Rev. C Changes to Compensation Capacitors Section ........................... 34 Changes to Gain and Offset Registers Section ............................ 36 Changes to Table 14 and Reducing Zero-Scale Error Section .. 38 Changes to Serial Interface Write Mode Section and BUSYEE and LOADEE Functions Section ............................................................... 42 Changes to Table 17 ........................................................................ 43 Added Table 18; Renumbered Sequentially ................................. 43 Changes to Register Update Rates Section .................................. 44 Changes to Table 23 ........................................................................ 46 Changes to Table 31 ........................................................................ 54 10/2009—Rev. A to Rev. B Changes to Table 1 ............................................................................ 6 Changes to Table 2 .......................................................................... 11 Added Figure 13 and Figure 15; Renumbered Sequentially ...... 22 Added Figure 16 .............................................................................. 23 Changes to Figure 21 ...................................................................... 23 Changes to Clamps Section ........................................................... 30 Changes to Table 22, Bit 21 to Bit 18 Description ...................... 44 Changes to Table 25, Bit 9 Description ........................................ 47 Changes to Table 28 ........................................................................ 49 Changes to Figure 59 ...................................................................... 59 Rev. F | Page 3 of 64

AD5522 Data Sheet GENERAL DESCRIPTION The AD5522 is a high performance, highly integrated parametric The PMU functions are controlled via a simple 3-wire serial measurement unit consisting of four independent channels. Each interface compatible with SPI, QSPI™, MICROWIRE™, and DSP per-pin parametric measurement unit (PPMU) channel includes interface standards. Interface clocks of 50 MHz allow fast updating five 16-bit, voltage output DACs that set the programmable input of modes. The low voltage differential signaling (LVDS) interface levels for the force voltage inputs, clamp inputs, and comparator protocol at 83 MHz is also supported. Comparator outputs are inputs (high and low). Five programmable force and measure provided per channel for device go-no-go testing and character- current ranges are available, ranging from ±5 µA to ±80 mA. ization. Control registers allow the user to easily change force or Four of these ranges use on-chip sense resistors; one high current measure conditions, DAC levels, and selected current ranges. range up to ±80 mA is available per channel using off-chip sense The SDO (serial data output) pin allows the user to read back resistors. Currents in excess of ±80 mA require an external ampli- information for diagnostic purposes. fier. Low capacitance DUT connections (FOHx and EXTFOHx) ensure that the device is suited to relayless test systems. Rev. F | Page 4 of 64

Data Sheet AD5522 AGND AVSS AVDD DVCC DGND CCOMP0 CH0 EN EXTFOH0 REFVGRNEDF 111666 CMX 1 RR REEEGGG×2 X2 ROEGFF×S2ET1 6DACCL1H6- BDIATC CLH INTERSNWA3L RANGE CFF0 111666 MX1 R REEGG X2 RE×6G16F1IN6 -DBAITC +– AGFNIND SW1 F+ORCE (±5µA, ±20SµAEL, E±2C0T0µA, ±2mA) FOH0 C REG MEASVH AMPLIFIER ×6 (Hi-Z) – SW2 SSWW45RSENSESW6 4kΩ 111666 CMX 1 RR REEEGGG×2 X2 REG×2 16 CL16L- BDIATC SW10 IVC RMEANIDNT GTEOER CL+L +– 2kΩ SW7 SW8 EXTMEASIH0 ER(CXSUETRNESRREENNATLS ×5 OR ×10 EXTMEASIL0 UP TO ±80mA) MEASOUT0 MUMXE AANSDO UGTAIN – +– SW9 SW12 ×1/×0.2 TEMP 4kΩ SENSOR MEASURE AGND 111666 X1 REG×6 ×6 16 16-BIT SW11 CINU-ARMRPENT +– SW16 MEASVH0 CM RREEGG X2 REG CPH DAC AGND + SW13 GUARD0 DUT 111666 MX1 R REEGG×6 X2 RE×G616CP16L- BDIATC CPL– + C–PH+ ×1– MEASURE +–DUTGND SW14 GUARD AMP GDUUTAGRNDDIN00/ DUTGND C REG VOLTAGE SW15 COMPARATOR IN-AMP CPOL0/SCLK 10kΩ AGND CPOH0/SDI EXTFOH1 CFF1 CCOMP1 FOH1 MEASOUT1 CH1 EXTMEASIH1 CPOL1/SYNC EXTMEASIL1 CPOH1/SDO MEASVH1 AGND GUARD1 GUARDIN1/DUTGND1 MUX SYS_SENSE MUX SYS_FORCE EXTFOH2 CCOMP2 CFF2 MEASOUT2 FOH2 CPOL2/CPO0 CH2 EXTMEASIH2 CPOH2/CPO1 EXTMEASIL2 AGND MEASVH2 GUARD2 GUARDIN2/DUTGND2 CCOMP3 EN EXTFOH3 111666 CMX 1 RR REEEGGG×2 X2 ROEGFF×S2ET1 6DACCL1H6- BDIATC CH3 CLH INTESWR3NAL RANGE CFF3 111666 MX1 R REEGG X2 RE×G616F1IN6 -DBAITC +– AGFNIND SW1 F+ORCE (±5µA, ±20SµAEL, E±2C0T0µA, ±2mA) FOH3 C REG ×6 M(HEi-AZS)VH A–MPLIFIER SW5RSENSE SW2 SW6 4kΩ 111666 CMX 1 RR REEEGGG×2 X2 REG×2 16 CL16L- BDIATC SW10 IVC RMEANIDNT GTEOER CL+L S+–W4 2kΩ SW7 SW8 EXTMEASIH3 ER(CXSUETRNESRREENNATLS x5 or x10 EXTMEASIL3 UP TO ±80mA) MEASOUT3 MUMXE AANSDO UGTAIN – +– SW9 SW12 x1/x0.2 TEMP 4kΩ SENSOR MEASURE AGND 111666 X1 REG×6 ×6 16 16-BIT SW11 CINU-ARMRPENT +– MEASVH3 CM RREEGG X2 REG CPH DAC AGND + SW13 SW16 GUARD3 DUT 111666 CMX 1 RR REEEGGG×6 X2 RE×G616CP16L- BDIATC CPL– + C–PH+ x1– MVOELATSAUGREEDUTG+–ND SW14 GUSAWR1D5 AMP GDUUTAGRNDDIN33/ COMPARATOR IN-AMP 10kΩ AGND DUTGND 16 1O D6FA-FBCSITET TOAOUM TPAPLLUILFT IDEARCS SW15a MEMATUSOOXUT SETENMSOPR TMPALM PORWEESRE-TON 16 INTSEERRFIAALCE AGND 10kΩ CLGAAULMAAPRR AMDND CGALM 06197-002 RESET SDO SCLKSDI SYNC BUSY LOAD SPI/ CPOL3/ CPOH3/ LVDS CPO2 CPO3 Figure 2. Detailed Block Diagram Rev. F | Page 5 of 64

AD5522 Data Sheet SPECIFICATIONS AVDD ≥ 10 V; AVSS ≤ −5 V; |AVDD − AVSS| ≥ 20 V and ≤ 33 V; DVCC = 2.3 V to 5.25 V; VREF = 5 V; REFGND = DUTGND = AGND = 0 V; gain (M), offset (C), and DAC offset registers at default values; T = 25°C to 90°C, unless otherwise noted. (FV = force voltage, FI = force J current, MV = measure voltage, MI = measure current, FS = full scale, FSR = full-scale range, FSVR = full-scale voltage range, FSCR = full-scale current range.) Table 1. Parameter Min Typ1 Max Unit Test Conditions/Comments FORCE VOLTAGE FOHx Output Voltage Range2 AVSS + 4 AVDD − 4 V All current ranges from FOHx at full-scale current, includes ±1 V dropped across sense resistor EXTFOHx Output Voltage Range2 AVSS + 3 AVDD − 3 V External high current range at full-scale current, does not include ±1 V dropped across sense resistor Output Voltage Span 22.5 V Offset Error −50 +50 mV Measured at midscale code; prior to calibration Offset Error Tempco2 −10 µV/°C Standard deviation = 20 μV/°C Gain Error −0.5 +0.5 % FSR Prior to calibration Gain Error Tempco2 0.5 ppm/°C Standard deviation = 0.5 ppm/°C Linearity Error −0.01 +0.01 % FSR FSR = full-scale range (±10 V), gain and offset errors calibrated out Short-Circuit Current Limit2 −150 +150 mA ±80 mA range −10 +10 mA All other ranges Noise Spectral Density (NSD)2 320 nV/√Hz 1 kHz, at FOHx in FV mode MEASURE CURRENT Measure current = (IDUT × RSENSE × gain), amplifier gain = 5 or 10, unless otherwise noted Differential Input Voltage Range2 −1.125 +1.125 V Voltage across RSENSE; gain = 5 or 10 Output Voltage Span 22.5 V Measure current block with VREF = 5 V, MEASOUT scaling happens after Offset Error −0.5 +0.5 % FSCR V(RSENSE) = ±1 V, measured with zero current flowing Offset Error Tempco2 1 µV/°C Referred to MI input; standard deviation = 4 µV/°C Gain Error −1 +1 % FSCR Using internal current ranges −0.5 +0.5 % FSCR Measure current amplifier alone Gain Error Tempco2 −2 ppm/°C Standard deviation = 2 ppm/°C, measure current amplifier alone; internal sense resistor 25 ppm/°C Linearity Error (MEASOUTx Gain = 1) −0.015 +0.015 % FSR MI gain = 10 −0.01 +0.01 % FSR MI gain = 5 Linearity Error (MEASOUTx Gain = 0.2) −0.06 +0.06 % FSR MI gain = 10, AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 −0.11 +0.11 % FSR MI gain = 10, AVDD = 10 V, AVSS = −23 V, offset DAC = 0x0EDB7 −0.015 +0.015 % FSR MI gain = 10, AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 −0.06 +0.06 % FSR MI gain = 5, AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 −0.01 +0.01 % FSR MI gain = 5, AVDD = 10 V, AVSS = −23 V, offset DAC = 0xEDB7 −0.01 +0.01 % FSR MI gain = 5, AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 Common-Mode Voltage Range2 AVSS + 4 AVDD − 4 V Common-Mode Error (Gain = 5) −0.01 +0.01 % FSCR/V % of full-scale change at force output per V change in DUT voltage Common-Mode Error (Gain = 10) −0.005 +0.005 % FSCR/V % of full-scale change at force output per V change in DUT voltage Sense Resistors Sense resistors are trimmed to within 1% 200 kΩ ±5 µA range 50 kΩ ±20 µA range 5 kΩ ±200 µA range 0.5 kΩ ±2 mA range Rev. F | Page 6 of 64

Data Sheet AD5522 Parameter Min Typ1 Max Unit Test Conditions/Comments Measure Current Ranges2 Specified current ranges are achieved with VREF = 5 V and MI gain = 10, or with VREF = 2.5 V and MI gain = 5 ±5 µA Set using internal sense resistor ±20 µA Set using internal sense resistor ±200 µA Set using internal sense resistor ±2 mA Set using internal sense resistor ±80 mA Set using external sense resistor; internal amplifier can drive up to ±80 mA Noise Spectral Density (NSD)2 400 nV/√Hz 1 kHz, MI amplifier only, inputs grounded FORCE CURRENT Voltage Compliance, FOHx2 AVSS + 4 AVDD − 4 V Voltage Compliance, EXTFOHx2 AVSS + 3 AVDD − 3 V Supports 64 mA sink current and 80 mA source current AVSS + 6 AVDD − 3 V Supports 80 mA sink and source current Offset Error −0.5 +0.5 % FSCR Measured at midscale code, 0 V, prior to calibration Offset Error Tempco2 5 ppm FS/°C Standard deviation = 5 ppm/°C Gain Error −1.5 +1.5 % FSCR Prior to calibration Gain Error Tempco2 −6 ppm/°C Standard deviation = 5 ppm/°C Linearity Error −0.02 +0.02 % FSCR Common-Mode Error (Gain = 5) −0.01 +0.01 % FSCR/V % of full-scale change per V change in DUT voltage Common-Mode Error (Gain = 10) −0.006 +0.006 % FSCR/V % of full-scale change per V change in DUT voltage Force Current Ranges Specified current ranges achieved with VREF = 5 V and MI gain = 10, or with VREF = 2.5 V and MI gain = 5 V ±5 µA Set using internal sense resistor, 200 kΩ ±20 µA Set using internal sense resistor, 50 kΩ ±200 µA Set using internal sense resistor, 5 kΩ ±2 mA Set using internal sense resistor, 500 Ω ±64 ±80 mA Set using external sense resistor, internal amplifier can drive up to ±80 mA with increased compliance MEASURE VOLTAGE Measure Voltage Range2 AVSS + 4 AVDD − 4 V Offset Error −10 +10 mV Gain = 1, measured at 0 V −25 +25 mV Gain = 0.2, measured at 0 V Offset Error Tempco2 −1 µV/°C Standard deviation = 6 µV/°C Gain Error −0.25 +0.25 % FSR MEASOUTx gain = 1 −0.5 +0.5 % FSR MEASOUTx gain = 0.2 Gain Error Tempco2 1 ppm/°C Standard deviation = 4 ppm/°C Linearity Error (MEASOUTx Gain = 1) −0.01 +0.01 % FSR Linearity Error (MEASOUTx Gain = 0.2) −0.01 +0.01 % FSR AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 −0.06 +0.06 % FSR AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 −0.1 +0.1 % FSR AVDD = −10 V, AVSS = −23 V, offset DAC = 0x3640 Noise Spectral Density (NSD)2 100 nV/√Hz 1 kHz; measure voltage amplifier only, inputs grounded OFFSET DAC Span Error ±30 mV COMPARATOR Comparator Span 22.5 V Offset Error −2 +1 +2 mV Measured directly at comparator; does not include measure block errors Offset Error Tempco2 1 µV/°C Standard deviation = 2 µV/°C Propagation Delay2 0.25 μs VOLTAGE CLAMPS Clamp Span 22.5 V Positive Clamp Accuracy 155 mV Negative Clamp Accuracy −155 mV CLL to CLH2 500 mV CLL < CLH and minimum voltage apart Recovery Time2 0.5 1.5 μs Activation Time2 1.5 3 μs Rev. F | Page 7 of 64

AD5522 Data Sheet Parameter Min Typ1 Max Unit Test Conditions/Comments CURRENT CLAMPS Clamp Accuracy Programmed Programmed % FSC MI gain = 10, clamp current scales with selected clamp value clamp value ± 10 range Programmed Programmed % FSC MI gain = 5, clamp current scales with selected range clamp value clamp value ± 20 CLL to CLH2 5 % of IRANGE CLL < CLH and minimum setting apart, MI gain = 10 10 % of IRANGE CLL < CLH and minimum setting apart, MI gain = 5 Recovery Time2 0.5 1.5 μs Activation Time2 1.5 3 μs FOHx, EXTFOHx, EXTMEASILx, EXTMEASIHx, CFFx PINS Pin Capacitance2 10 pF Leakage Current −3 +3 nA Individual pin on or off switch leakage, measured with ±11 V stress applied to pin, channel enabled, but tristate Leakage Current Tempco2 ±0.01 nA/°C MEASVHx PIN Pin Capacitance2 3 pF Leakage Current −3 +3 nA Measured with ±11 V stress applied to pin, channel enabled, but tristate Leakage Current Tempco2 ±0.01 nA/°C SYS_SENSE PIN SYS_SENSE connected, force amplifier inhibited Pin Capacitance2 3 pF Switch Impedance 1 1.3 kΩ Leakage Current −3 +3 nA Measured with ±11 V stress applied to pin, switch off Leakage Current Tempco2 ±0.01 nA/°C SYS_FORCE PIN SYS_FORCE connected, force amplifier inhibited Pin Capacitance2 6 pF Switch Impedance 60 80 Ω Leakage Current −3 +3 nA Measured with ±11 V stress applied to pin, switch off Leakage Current Tempco2 ±0.01 nA/°C COMBINED LEAKAGE AT DUT Includes FOHx, MEASVHx, SYS_SENSE, SYS_FORCE, EXTMEASILx, EXTMEASIHx, EXTFOHx, and CFFx, calculation of all the individual leakage contributors Leakage Current −15 +15 nA TJ = 25°C to 70°C −25 +25 nA TJ = 25°C to 90°C Leakage Current Tempco2 ±0.1 nA/°C DUTGNDx PIN Voltage Range −500 +500 mV Leakage Current −30 +30 nA MEASOUTx PIN With respect to AGND Output Voltage Span 22.5 V Software programmable output range Output Impedance 60 80 Ω Output Leakage Current −3 +3 nA With SW12 off Output Capacitance2 15 pF Maximum Load Capacitance2 0.5 μF Output Current Drive2 2 mA Short-Circuit Current −10 +10 mA Slew Rate2 2 V/μs Enable Time2 150 320 ns Closing SW12, measured from BUSY rising edge Disable Time2 400 1100 ns Opening SW12, measured from BUSY rising edge MI to MV Switching Time2 200 ns Measured from BUSY rising edge, does not include slewing or settling Rev. F | Page 8 of 64

Data Sheet AD5522 Parameter Min Typ1 Max Unit Test Conditions/Comments GUARDx PIN Output Voltage Span 22.5 V Output Offset −10 +10 mV Short-Circuit Current −15 +15 mA Maximum Load Capacitance2 100 nF Output Impedance 85 Ω Tristate Leakage Current2 −30 +30 nA When guard amplifier is disabled Slew Rate2 5 V/μs CLOAD = 10 pF Alarm Activation Time2 200 μs Alarm delayed to eliminate false alarms FORCE AMPLIFIER2 Slew Rate 0.4 V/μs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Gain Bandwidth 1.3 MHz CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Max Stable Load Capacitance 10,000 pF CCOMPx = 100 pF, larger CLOAD requires larger CCOMP capacitor 100 nF CCOMPx = 1 nF, larger CLOAD requires larger CCOMP capacitor FV SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; measured from SYNC rising edge, clamps on ±80 mA Range 22 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±2 mA Range 24 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±200 µA Range 40 80 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±20 µA Range 300 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±5 µA Range 1400 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF MI SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time, measured from SYNC rising edge, clamps on ±80 mA Range 22 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±2 mA Range 24 40 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±200 µA Range 60 100 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±20 µA Range 462 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF ±5 µA Range 1902 µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF FI SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; measured from SYNC rising edge, clamps on ±80 mA Range 24 55 µs CCOMPx = 100 pF, CLOAD = 200 pF ±2 mA Range 24 60 µs CCOMPx = 100 pF, CLOAD = 200 pF ±200 µA Range 50 120 µs CCOMPx = 100 pF, CLOAD = 200 pF ±20 µA Range 450 µs CCOMPx = 100 pF, CLOAD = 200 pF ±5 µA Range 2700 µs CCOMPx = 100 pF, CLOAD = 200 pF MV SETTLING TIME TO 0.05% OF FS2 Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time, measured from SYNC rising edge, clamps on ±80 mA Range 24 55 µs CCOMPx = 100 pF, CLOAD = 200 pF ±2 mA Range 24 60 µs CCOMPx = 100 pF, CLOAD = 200 pF ±200 µA Range 50 120 µs CCOMPx = 100 pF, CLOAD = 200 pF ±20 µA Range 450 µs CCOMPx = 100 pF, CLOAD = 200 pF ±5 µA Range 2700 µs CCOMPx = 100 pF, CLOAD = 200 pF DAC SPECIFICATIONS Resolution 16 Bits Output Voltage Span2 22.5 V VREF = 5 V, within a range of −16.25 V to +22.5 V Differential Nonlinearity2 −1 +1 LSB Guaranteed monotonic by design over temperature COMPARATOR DAC DYNAMIC SPECIFICATIONS2 Output Voltage Settling Time 1 µs 500 mV change to ±½ LSB Slew Rate 5.5 V/µs Digital-to-Analog Glitch Energy 20 nV-sec Glitch Impulse Peak Amplitude 10 mV REFERENCE INPUT VREF DC Input Impedance 1 100 MΩ VREF Input Current −10 +0.03 +10 µA VREF Range2 2 5 V Rev. F | Page 9 of 64

AD5522 Data Sheet Parameter Min Typ1 Max Unit Test Conditions/Comments DIE TEMPERATURE SENSOR Accuracy2 ±7 °C Output Voltage at 25°C 1.5 V Output Scale Factor2 4.6 mV/°C Output Voltage Range2 0 3 V INTERACTION AND CROSSTALK2 DC Crosstalk (FOHx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, FV and FI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk (MEASOUTx) 0.05 0.65 mV DC change resulting from a dc change in any DAC in the device, MV and MI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC Crosstalk Within a Channel 0.05 mV All channels in FVMI mode, one channel at midscale, measure the current for one channel in the lowest current range for a change in comparator or clamp DAC levels for that PMU SPI INTERFACE LOGIC INPUTS Input High Voltage, VIH 1.7/2.0 V (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels Input Low Voltage, VIL 0.7/0.8 V (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels Input Current, IINH, IINL −1 +1 µA Input Capacitance, CIN2 10 pF CMOS LOGIC OUTPUTS SDO, CPOx Output High Voltage, VOH DVCC − 0.4 V Output Low Voltage, VOL 0.4 V IOL = 500 µA Tristate Leakage Current −2 +2 µA SDO, CPOH1/SDO −1 +1 µA All other output pins Output Capacitance2 10 pF OPEN-DRAIN LOGIC OUTPUTS BUSY, TMPALM, CGALM Output Low Voltage, VOL 0.4 V IOL = 500 µA, CLOAD = 50 pF, RPULLUP = 1 kΩ Output Capacitance2 10 pF LVDS INTERFACE LOGIC INPUTS REDUCED RANGE LINK2 Input Voltage Range 875 1575 mV Input Differential Threshold −100 +100 mV External Termination Resistance 80 100 120 Ω Differential Input Voltage 100 mV LVDS INTERFACE LOGIC OUTPUTS REDUCED RANGE LINK Output Offset Voltage 1200 mV Output Differential Voltage 400 mV POWER SUPPLIES AVDD 10 28 V |AVDD − AVSS| ≤ 33 V AVSS −23 −5 V DVCC 2.3 5.25 V AIDD 26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AISS −26 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled AIDD 28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AISS −28 mA Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled AIDD 36 mA External range, excluding load conditions AISS −36 mA External range, excluding load conditions DICC 1.5 mA Maximum Power Dissipation2 7 W Maximum power that should be dissipated in this package under worst-case load conditions; careful consideration should be given to supply selection and thermal design Rev. F | Page 10 of 64

Data Sheet AD5522 Parameter Min Typ1 Max Unit Test Conditions/Comments Power Supply Sensitivity2 From dc to 1 kHz ΔForced Voltage/ΔAVDD −80 dB ΔForced Voltage/ΔAVSS −80 dB ΔMeasured Current/ΔAVDD −85 dB ΔMeasured Current/ΔAVSS −75 dB ΔForced Current/ΔAVDD −75 dB ΔForced Current/ΔAVSS −75 dB ΔMeasured Voltage/ΔAVDD −85 dB ΔMeasured Voltage/ΔAVSS −80 dB ΔForced Voltage/ΔDVCC −90 dB ΔMeasured Current/ΔDVCC −90 dB ΔForced Current/ΔDVCC −90 dB ΔMeasured Voltage/ΔDVCC −90 dB 1 Typical specifications are at 25°C and nominal supply, ±15.25 V, unless otherwise noted. 2 Guaranteed by design and characterization; not production tested. Tempco values are mean and standard deviation, unless otherwise noted. TIMING CHARACTERISTICS AVDD ≥ 10 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 20 V and ≤ 33 V, DVCC = 2.3 V to 5.25 V, VREF = 5 V, T = 25°C to 90°C, unless J otherwise noted. Table 2. SPI Interface DVCC, Limit at T , T MIN MAX Parameter 1, 2, 3 2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V Unit Description tWRITE4 1030 735 735 ns min Single channel update cycle time (X1 register write) 950 655 655 ns min Single channel update cycle time (any other register write) t 30 20 20 ns min SCLK cycle time 1 t 8 8 8 ns min SCLK high time 2 t 8 8 8 ns min SCLK low time 3 t4 10 10 10 ns min SYNC falling edge to SCLK falling edge setup time t54 150 150 150 ns min Minimum SYNC high time in write mode after X1 register write (one channel) 70 70 70 ns min Minimum SYNC high time in write mode after any other register write t6 10 5 5 ns min 29th SCLK falling edge to SYNC rising edge t 5 5 5 ns min Data setup time 7 t 9 7 4.5 ns min Data hold time 8 t9 120 75 55 ns max SYNC rising edge to BUSY falling edge t10 BUSY pulse width low for X1 and some PMU register writes; see Table 17 and Table 18 1 DAC X1 1.65 1.65 1.65 µs max 2 DAC X1 2.3 2.3 2.3 µs max 3 DAC X1 2.95 2.95 2.95 µs max 4 DAC X1 3.6 3.6 3.6 µs max Other Registers 270 270 270 ns max System control register/PMU registers t11 20 20 20 ns min 29th SCLK falling edge to LOAD falling edge t12 20 20 20 ns min LOAD pulse width low t13 150 150 150 ns min BUSY rising edge to FOHx output response time t14 0 0 0 ns min BUSY rising edge to LOAD falling edge t15 100 100 100 ns max LOAD falling edge to FOHx output response time t16A 4.0 4.0 4.0 µs min RESET pulse width low min t16B 4.0 4.0 4.0 µs max RESET low to BUSY low max t17 750 750 750 µs max RESET time indicated by BUSY low Rev. F | Page 11 of 64

AD5522 Data Sheet DVCC, Limit at T , T MIN MAX Parameter 1, 2, 3 2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V Unit Description t18 400 400 400 ns min Minimum SYNC high time in readback mode t 5, 6 60 45 25 ns max SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V 19 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 5 and Figure 6. 4 Writes to more than one X1 register engages the calibration engine for longer times, shown by the BUSY low time, t10. Subsequent writes to one or more X1 registers should either be timed or should wait until BUSY returns high (see Figure 56). This is required to ensure that data is not lost or overwritten. 5 t19 is measured with the load circuit shown in Figure 4. 6 SDO output slows with lower DVCC supply and may require use of a slower SCLK. Table 3. LVDS Interface DVCC, Limit at T , T MIN MAX Parameter1, 2, 3 2.7 V to 3.6 V 4.5 V to 5.25 V Unit Description t 20 12 ns min SCLK cycle time 1 t 8 5 ns min SCLK pulse width high and low time 2 t3 3 3 ns min SYNC to SCLK setup time t 3 3 ns min Data setup time 4 t 5 3 ns min Data hold time 5 t6 3 3 ns min SCLK to SYNC hold time t4 45 25 ns min SCLK rising edge to SDO valid 7 t8 150 150 ns min Minimum SYNC high time in write mode after X1 register write 70 70 ns min Minimum SYNC high time in write mode after any other register write 400 400 ns min Minimum SYNC high time in readback mode 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 7. 4 SDO output slows with lower DVCC supply and may require use of slower SCLK. Rev. F | Page 12 of 64

Data Sheet AD5522 Circuit and Timing Diagrams DVCC 200µA IOL RLOAD 2.2kΩ TO OUTPUT VOH(MIN) – VOL(MAX) PIN 2 TO CLOAD OUTPPUINT CLOAD 50pF VOL 06197-003 50pF 200µA IOH 06197-004 Figure 3. Load Circuit for CGALM, TMPALM Figure 4. Load Circuit for SDO, BUSY Timing Diagram t1 SCLK 1 2 29 1 29 t3 t2 t4 t6 SYNC t5 t7 t8 DB28 DB0 DB28 DB0 SDI (N) (N) (N+1) (N + 1) t9 t10 BUSY t11 t12 LOAD1 FOHx1 t13 t14 t12 LOAD2 FOHx2 t15 t16A RESET BUSY t16B t17 21LLOOAADD AACCTTIIVVEE ADFUTREINRG B BUUSSYY.. 06197-00506197-005 Figure 5. SPI Write Timing (Write Word Contains 29 Bits) Rev. F | Page 13 of 64

AD5522 Data Sheet SCLK 29 58 t19 t18 SYNC SDI D(BN2)8 D(NB)0 (DDNBB +22 138)/ (ND B+ 01) INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ DB23/ DB0 SDO (DNB +2 18) (N + 1) UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 06197-006 Figure 6. SPI Read Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges) t8 SYNC SYNC t3 t1 t6 SCLK SCLK SDI MDS28B t2 t4 D2M3S/DB28 LDS0B LSB D0 SDI t5 t7 SDO MSB LSB DB23/ DB0 SDO DB28 UNDEFINED SELECTED REGISTER DATA CLOCKED OUT 06197-007 Figure 7. LVDS Read and Write Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges) Rev. F | Page 14 of 64

Data Sheet AD5522 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Rating Thermal resistance values are specified for the worst-case Supply Voltage, AVDD to AVSS 34 V conditions, that is, a device soldered in a circuit board for AVDD to AGND −0.3 V to +34 V surface-mount packages. AVSS to AGND +0.3 V to −34 V Table 5. Thermal Resistance1 (JEDEC 4-Layer (1S2P) Board) VREF to AGND −0.3 V to +7 V Airflow DUTGND to AGND AVDD + 0.3 V to AVSS − 0.3 V Package Type (LFPM) θ θ Unit JA JC REFGND to AGND AVDD + 0.3 V to AVSS − 0.3 V TQFP Exposed Pad on Bottom 4.8 °C/W DVCC to DGND −0.3 V to +7 V No Heat Sink2 0 22.3 °C/W AGND to DGND −0.3 V to +0.3 V 200 17.2 °C/W Digital Inputs to DGND −0.3 V to DVCC + 0.3 V 500 15.1 °C/W Analog Inputs to AGND AVSS − 0.3 V to AVDD + 0.3 V With Cooling Plate at 45°C3 N/A4 5.4 4.8 °C/W Storage Temperature Range −65°C to +125°C TQFP Exposed Pad on Top 2 °C/W Operating Junction Temperature 25°C to 90°C No Heat Sink2 0 42.4 °C/W Range (J Version) 200 37.2 °C/W Reflow Soldering JEDEC Standard (J-STD-020) 500 35.7 °C/W Junction Temperature 150°C max With Cooling Plate at 45°C3 N/A4 3.0 2 °C/W 1 The information in this section is based on simulated thermal information. Stresses at or above those listed under Absolute Maximum 2 These values apply to the package with no heat sink attached. The actual Ratings may cause permanent damage to the product. This is a thermal performance of the package depends on the attached heat sink and environmental conditions. stress rating only; functional operation of the product at these 3 Natural convection at 55°C ambient. Assumes perfect thermal contact or any other conditions above those indicated in the operational between the cooling plate and the exposed paddle. 4 N/A means not applicable. section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. F | Page 15 of 64

AD5522 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EXTFOH0 AVSS RESET TMPALM CGALM SPI/LVDS AVDD DUTGND VREF REFGND SYS_SENSE AGND SYS_FORCE AVSS MEASOUT0 MEASOUT1 MEASOUT2 MEASOUT3 AVSS EXTFOH1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVDD 1 60 AVDD CFF0 2 PIN1 59 CFF1 CCOMP0 3 58 CCOMP1 EXTMEASIH0 4 57 EXTMEASIH1 EXTMEASIL0 5 56 EXTMEASIL1 FOH0 6 55 FOH1 GUARD0 7 54 GUARD1 GUARDIN0/DUTGND0 8 53 GUARDIN1/DUTGND1 AD5522 MEASVH0 9 52 MEASVH1 TOP VIEW AGND 10 51 AGND EXPOSED PAD ON BOTTOM AGND 11 (Not to Scale) 50 AGND MEASVH2 12 49 MEASVH3 GUARDIN2/DUTGND2 13 48 GUARDIN3/DUTGND3 GUARD2 14 47 GUARD3 FOH2 15 46 FOH3 EXTMEASIL2 16 45 EXTMEASIL3 EXTMEASIH2 17 44 EXTMEASIH3 CCOMP2 18 43 CCOMP3 CFF2 19 42 CFF3 AVDD 20 41 AVDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 EXTFOH2 AVSS BUSY SCLK CPOL0/SCLK CPOH0/SDI SDI SYNC CPOL1/SYNC DGND CPOH1/SDO SDO LOAD DVCC CPOL2/CPO0 CPOH2/CPO1 CPOL3/CPO2 CPOH3/CPO3 AVSS EXTFOH3 06197-008 NOTES 1. THE EXPOSED PAD IS INTERNALLY ELECTRICALLY CONNECTED TO AVSS. FOR ENHANCED THERMAL, ELECTRICAL, AND BOARD LEVEL PERFORMANCE, THE EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE SHOULD BE SOLDERED TO A CORRESPONDING THERMAL LAND PADDLE ON THE PCB. Figure 8. Pin Configuration, Exposed Pad on Bottom Table 6. Pin Function Descriptions Pin No. Mnemonic Description Exposed pad The exposed pad is internally electrically connected to AVSS. For enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package should be soldered to a corresponding thermal land paddle on the PCB. 1, 20, 41, AVDD Positive Analog Supply Voltage. 60, 74 2 CFF0 External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 3 CCOMP0 Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. 4 EXTMEASIH0 Sense Input (High Sense) for High Current Range (Channel 0). 5 EXTMEASIL0 Sense Input (Low Sense) for High Current Range (Channel 0). 6 FOH0 Force Output for Internal Current Ranges (Channel 0). 7 GUARD0 Guard Output Drive for Channel 0. 8 GUARDIN0/ Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the DUTGND0 serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 9 MEASVH0 DUT Voltage Sense Input (High Sense) for Channel 0. 10, 11, 50, AGND Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry. 51, 69 12 MEASVH2 DUT Voltage Sense Input (High Sense) for Channel 2. Rev. F | Page 16 of 64

Data Sheet AD5522 Pin No. Mnemonic Description 13 GUARDIN2/ Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the DUTGND2 serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 14 GUARD2 Guard Output Drive for Channel 2. 15 FOH2 Force Output for Internal Current Ranges (Channel 2). 16 EXTMEASIL2 Sense Input (Low Sense) for High Current Range (Channel 2). 17 EXTMEASIH2 Sense Input (High Sense) for High Current Range (Channel 2). 18 CCOMP2 Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. 19 CFF2 External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 21 EXTFOH2 Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 22, 39, 62, AVSS Negative Analog Supply Voltage. 67, 79 23 BUSY Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. 24 SCLK Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. 25 CPOL0/SCLK Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. 26 CPOH0/SDI Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. 27 SDI Serial Data Input for SPI or LVDS Interface. 28 SYNC Active Low Frame Synchronization Input for SPI or LVDS Interface. 29 CPOL1/SYNC Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. 30 DGND Digital Ground Reference Point. 31 CPOH1/SDO Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. 32 SDO Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. 33 LOAD Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. 34 DVCC Digital Supply Voltage. 35 CPOL2/CPO0 Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. 36 CPOH2/CPO1 Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS Interface. 37 CPOL3/CPO2 Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS Interface. 38 CPOH3/CPO3 Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS Interface. 40 EXTFOH3 Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 42 CFF3 External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 43 CCOMP3 Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section. 44 EXTMEASIH3 Sense Input (High Sense) for High Current Range (Channel 3). 45 EXTMEASIL3 Sense Input (Low Sense) for High Current Range (Channel 3). 46 FOH3 Force Output for Internal Current Ranges (Channel 3). 47 GUARD3 Guard Output Drive for Channel 3. 48 GUARDIN3/ Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the DUTGND3 serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. Rev. F | Page 17 of 64

AD5522 Data Sheet Pin No. Mnemonic Description 49 MEASVH3 DUT Voltage Sense Input (High Sense) for Channel 3. 52 MEASVH1 DUT Voltage Sense Input (High Sense) for Channel 1. 53 GUARDIN1/ Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the DUTGND1 serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 54 GUARD1 Guard Output Drive for Channel 1. 55 FOH1 Force Output for Internal Current Ranges (Channel 1). 56 EXTMEASIL1 Sense Input (Low Sense) for High Current Range (Channel 1). 57 EXTMEASIH1 Sense Input (High Sense) for High Current Range (Channel 1). 58 CCOMP1 Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section. 59 CFF1 External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 61 EXTFOH1 Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 63 MEASOUT3 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is referenced to AGND. 64 MEASOUT2 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is referenced to AGND. 65 MEASOUT1 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is referenced to AGND. 66 MEASOUT0 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is referenced to AGND. 68 SYS_FORCE External Force Signal Input. This pin enables the connection of the system PMU. 70 SYS_SENSE External Sense Signal Output. This pin enables the connection of the system PMU. 71 REFGND Accurate Analog Reference Input Ground. 72 VREF Reference Input for DAC Channels (5 V for specified performance). 73 DUTGND DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for each PMU channel. 75 SPI/LVDS Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default to differential interface pins. 76 CGALM Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control register allows the user to enable this function and to set the open-drain output as a latched output. The user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the alarm is still present. 77 TMPALM Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers. 78 RESET Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their power- on reset values. 80 EXTFOH0 Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. Rev. F | Page 18 of 64

Data Sheet AD5522 0 2 D D N N G G T T AVDD CFF0 CCOMP0 EXTMEASIH0 EXTMEASIL0 FOH0 GUARD0 GUARDIN0/DU MEASVH0 AGND AGND MEASVH2 GUARDIN2/DU GUARD2 FOH2 EXTMEASIL2 EXTMEASIH2 CCOMP2 CFF2 AVDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 EXTFOH0 1 60 EXTFOH2 AVSS 2 PIN1 59 AVSS RESET 3 58 BUSY TMPALM 4 57 SCLK CGALM 5 56 CPOL0/SCLK SPI/LVDS 6 55 CPOH0/SDI AVDD 7 54 SDI AD5522 DUTGND 8 53 SYNC TOPVIEW VREF 9 52 CPOL1/SYNC EXPOSEDPAD ON TOP REFGND 10 51 DGND (Notto Scale) SYS_SENSE 11 50 CPOH1/SDO AGND 12 49 SDO SYS_FORCE 13 48 LOAD AVSS 14 47 DVCC MEASOUT0 15 46 CPOL2/CPO0 MEASOUT1 16 45 CPOH2/CPO1 MEASOUT2 17 44 CPOL3/CPO2 MEASOUT3 18 43 CPOH3/CPO3 AVSS 19 42 AVSS EXTFOH1 20 41 EXTFOH3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 AVDD CFF1 CCOMP1 EXTMEASIH1 EXTMEASIL1 FOH1 GUARD1 N1/DUTGND1 MEASVH1 AGND AGND MEASVH3 N3/DUTGND3 GUARD3 FOH3 EXTMEASIL3 EXTMEASIH3 CCOMP3 CFF3 AVDD DI DI R R A A U U N1.O TTHEES EXPOSED PAD IS ELECTRICALLY CONGNECTED TO AVSGS. 06197-009 Figure 9. Pin Configuration, Exposed Pad on Top Table 7. Pin Function Descriptions Pin No. Mnemonic Description Exposed pad The exposed pad is electrically connected to AVSS. 1 EXTFOH0 Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 2, 14, 19, AVSS Negative Analog Supply Voltage. 42, 59 3 RESET Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their power- on reset values. 4 TMPALM Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers. 5 CGALM Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control register allows the user to enable this function and to set the open-drain output as a latched output. The user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the alarm is still present. Rev. F | Page 19 of 64

AD5522 Data Sheet Pin No. Mnemonic Description 6 SPI/LVDS Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default to differential interface pins. 7, 21, 40, AVDD Positive Analog Supply Voltage. 61, 80 8 DUTGND DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for each PMU channel. 9 VREF Reference Input for DAC Channels. 5 V for specified performance. 10 REFGND Accurate Analog Reference Input Ground. 11 SYS_SENSE External Sense Signal Output. This pin enables the connection of the system PMU. 12, 30, 31, AGND Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry. 70, 71 13 SYS_FORCE External Force Signal Input. This pin enables the connection of the system PMU. 15 MEASOUT0 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is referenced to AGND. 16 MEASOUT1 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is referenced to AGND. 17 MEASOUT2 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is referenced to AGND. 18 MEASOUT3 Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is referenced to AGND. 20 EXTFOH1 Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 22 CFF1 External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 23 CCOMP1 Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section. 24 EXTMEASIH1 Sense Input (High Sense) for High Current Range (Channel 1). 25 EXTMEASIL1 Sense Input (Low Sense) for High Current Range (Channel 1). 26 FOH1 Force Output for Internal Current Ranges (Channel 1). 27 GUARD1 Guard Output Drive for Channel 1. 28 GUARDIN1/ Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the DUTGND1 serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 29 MEASVH1 DUT Voltage Sense Input (High Sense) for Channel 1. 32 MEASVH3 DUT Voltage Sense Input (High Sense) for Channel 3. 33 GUARDIN3/ Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the DUTGND3 serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 34 GUARD3 Guard Output Drive for Channel 3. 35 FOH3 Force Output for Internal Current Ranges (Channel 3). 36 EXTMEASIL3 Sense Input (Low Sense) for High Current Range (Channel 3). 37 EXTMEASIH3 Sense Input (High Sense) for High Current Range (Channel 3). 38 CCOMP3 Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section. 39 CFF3 External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 41 EXTFOH3 Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 43 CPOH3/CPO3 Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS Interface. 44 CPOL3/CPO2 Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS Interface. 45 CPOH2/CPO1 Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS Interface. Rev. F | Page 20 of 64

Data Sheet AD5522 Pin No. Mnemonic Description 46 CPOL2/CPO0 Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. 47 DVCC Digital Supply Voltage. 48 LOAD Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. 49 SDO Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. 50 CPOH1/SDO Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. 51 DGND Digital Ground Reference Point. 52 CPOL1/SYNC Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. 53 SYNC Active Low Frame Synchronization Input for SPI or LVDS Interface. 54 SDI Serial Data Input for SPI or LVDS Interface. 55 CPOH0/SDI Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. 56 CPOL0/SCLK Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. 57 SCLK Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. 58 BUSY Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. 60 EXTFOH2 Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. 62 CFF2 External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. 63 CCOMP2 Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. 64 EXTMEASIH2 Sense Input (High Sense) for High Current Range (Channel 2). 65 EXTMEASIL2 Sense Input (Low Sense) for High Current Range (Channel 2). 66 FOH2 Force Output for Internal Current Ranges (Channel 2). 67 GUARD2 Guard Output Drive for Channel 2. 68 GUARDIN2/ Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the DUTGND2 serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 69 MEASVH2 DUT Voltage Sense Input (High Sense) for Channel 2. 72 MEASVH0 DUT Voltage Sense Input (High Sense) for Channel 0. 73 GUARDIN0/ Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the DUTGND0 serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. 74 GUARD0 Guard Output Drive for Channel 0. 75 FOH0 Force Output for Internal Current Ranges (Channel 0). 76 EXTMEASIL0 Sense Input (Low Sense) for High Current Range (Channel 0). 77 EXTMEASIH0 Sense Input (High Sense) for High Current Range (Channel 0). 78 CCOMP0 Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. 79 CFF0 External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Rev. F | Page 21 of 64

AD5522 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.0020 TA = 25°C 0.8 NOM: AVDD = +16.5V, AVSS = –16.6V, OFFSET DAC = 0XA492 0.6 0.0015 HIGH: AVDD = +28V, AVSS = –5V, OFFSET DAC = 0X0 ARITY (LSB) 00..420 RITY (% FSR) 0.0010 LOOFWFS:EATV DDDA C= =+ 100xVE,DABV7SS = –23V, NE –0.2 EA 0.0005 LI –0.4 LIN –0.6 0 ––01..800 10,DI0N0NL0L 20,000 30,0C0O0DE40,000 50,000 60,000 06197-010 –0.00050 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06197-140 Figure 10. Force Voltage Linearity vs. Code, All Ranges, Figure 13. Measure Voltage Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR) MEASOUTx Gain = 0.2 2.0 5 TA = 25°C TA = 25°C 4 1.5 3 DNL INL 1.0 2 B) B) LS 0.5 LS 1 Y ( Y ( RIT 0 RIT 0 A A LINE –0.5 LINE –1 –2 –1.0 –3 ––12..50 DINNLL 06197-011 ––45 06197-013 0 10,000 20,000 30,000 40,000 50,000 60,000 0 10,000 20,000 30,000 40,000 50,000 60,000 CODE CODE Figure 11. Force Current Linearity vs. Code, All Ranges, Figure 14. Measure Current Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR) 1 LSB = 0.0015% FSR (20 V FSR), MI Gain = 10, MEASOUTx Gain = 1 2.0 0.035 TA = 25°C 1.5 0.030 AOVFDFSDE =T + D1A5.C5 V=, 0AxVAS4S9 2= –15.5V, AVDD = +28V,AVSS = –5V, 1.0 0.025 OFFSET DAC = 0x0 AVDD = +10V,AVSS = –23V, ARITY (LSB) 0.50 RITY (% FSR) 000...000112050 OFFSET DAC = 0xEDB7 E A LIN –0.5 LINE 0.005 –1.0 0 ––12..500 10,DI0N0NL0L 20,000 30,0C0O0DE40,000 50,000 60,000 06197-012 ––00..0000150 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 06197-141 Figure 12. Measure Voltage Linearity vs. Code, All Ranges, Figure 15. Measure Current Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR), MEASOUTx Gain = 1 MEASOUTx Gain = 0.2, MI Gain = 10 Rev. F | Page 22 of 64

Data Sheet AD5522 0.005 0.2 AVDD = +15.5V, AVSS = –15.5V, 0.004 OFFSET DAC = 0xA492 0 AVDD = +28V,AVSS = –5V, % FSR) 00..000023 OAOVFFDFFDSSEE =TT + DD1AA0VCC, A== V00Sxx0ESD =8 –723V, RENT (nA)––00..24 Y ( 0.001 UR T C LINEARI 0 AKAGE –0.6 ECFOXFTFHFxxOHx E–0.8 EXTMEASIHx –0.001 L EXTMEASILx V = –12V MEASVHx ––00..0000320 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 06197-142 ––11..0225 35GCOUAMRBDIN4IN5ExD/ DTLUEETMAGK5P5NAEDRGxAETUR65E (°C) 75 85 9506197-016 Figure 16. Measure Current Linearity vs. Code, All Ranges, Figure 19. Leakage Current vs. Temperature (Stress Voltage = −12 V) MEASOUTx Gain = 0.2, MI Gain = 5 1.0 0.15 V = 0V TA = 25°C EXTFOHx 0.10 0.8 CFFx nA) FEOXTHMxEASIHx nA) 0.05 T ( 0.6 EXTMEASILx T ( N N E MEASVHx E R R 0 R GUARDINx/DUTGNDx R CU 0.4 COMBINED LEAKAGE CU AGE AGE –0.05 ECXFTFFxOHx AK 0.2 AK FOHx LE LE–0.10 EXTMEASIHx EXTMEASILx –0.20 06197-014 ––00..1250 MGCOUEAMARSBVDINHINExxD/ DLUETAGKNADGxE 06197-017 25 35 45 55 65 75 85 95 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 TEMPERATURE (°C) STRESS VOLTAGE (V) Figure 17. Leakage Current vs. Temperature (Stress Voltage = 0 V) Figure 20. Leakage Current vs. Stress Voltage 2.0 0 V = 12V AVDD ACPSRR EXTFOHx AVSS ACPSRR CFFx –20 DVCC ACPSRR 1.5 A) FOHx n EXTMEASIHx T ( EXTMEASILx –40 RREN 1.0 MGUEAARSVDHINxx/DUTGNDx R (dB) CU COMBINED LEAKAGE SR–60 AGE 0.5 ACP AK –80 E L 0 –100 –0.525 35 45 TEM5P5ERATUR65E (°C) 75 85 9506197-015 –12010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 06197-018 Figure 18. Leakage Current vs. Temperature (Stress Voltage = 12 V) Figure 21. ACPSRR at FOHx in Force Voltage Mode vs. Frequency Rev. F | Page 23 of 64

AD5522 Data Sheet 0 0 –10 –10 –20 VSS –20 VSS –30 –30 ACPSRR (dB)–––654000 VVCDCD ACPSRR (dB)––––76540000 VVCDCD –70 –80 –80 –90 –90 –100 –10010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-019 –11010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-120 Figure 22. ACPSRR at FOHx in Force Current Mode vs. Frequency Figure 25. ACPSRR at MEASOUTx in Measure Voltage Mode vs. Frequency (MI Gain = 10) (MEASOUT Gain = 0.2) 0 0 –10 –10 –20 VSS –20 VSS –30 VDD –30 VDD –40 B)–40 B) R (d–50 VCC R (d–50 VCC R R–60 PS–60 PS C C–70 A–70 A –80 –80 –90 –90 –100 –100 –110 –11010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-119 –12010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-021 Figure 23. ACPSRR at FOHx in Force Current Mode vs. Frequency Figure 26. ACPSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 5) (MI Gain = 10, MEASOUT Gain = 1) 0 0 –10 –10 –20 VSS –20 VSS –30 –30 B)–40 VDD B)–40 VDD RR (d––6500 VCC RR (d––6500 VCC S S CP–70 CP–70 A A –80 –80 –90 –90 –100 –100 –110 –110 –12010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-020 –12010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-121 Figure 24. ACPSRR at MEASOUTx in Measure Voltage Mode vs. Frequency Figure 27. ACPSRR at MEASOUTx in Measure Current Mode vs. Frequency (MEASOUT Gain = 1) (MI Gain = 5, MEASOUT Gain = 1) Rev. F | Page 24 of 64

Data Sheet AD5522 0 –10 TA = 25°C –20 –30 FOH0 –40 1 B) VSS d–50 R ( SR–60 VCC P C–70 A VDD MEASOUT0 –80 2 –90 LOAD –100 4 ––11210010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-122 CH1 20.0mV BW CCHH24 150.000mVV BW MT 4 . 0 0 µ1s0.0000µs 06197-023 CH1 Pk-Pk 39.00mV CH2 Pk-Pk 325.8mV Figure 28. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency Figure 31. AC Crosstalk, FVMI Mode, PMU 0, Full-Scale Transition on One CPH (MI Gain = 10, MEASOUT Gain = 0.2) DAC, MI Gain = 10, MEASOUT Gain = 1, ±2 mA Range, CLOAD = 200 pF 0 –10 TA = 25°C –20 –30 VDD FOH1 –40 1 dB)–50 VSS R ( VCC R–60 S P C–70 A MEASOUT1 –80 2 –90 LOAD –100 4 ––11210010 100 FR1kEQUENCY 1(H0kz) 100k 1M 06197-123 CH1 20.0mV BW CCHH24 150.000mVV BW MT 4 . 0 0 µ1s0.0000µs 06197-024 CH1 Pk-Pk 18.80mV CH2 Pk-Pk 140.0mV Figure 29. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency Figure 32. AC Crosstalk, FVMI Mode, PMU 1, Full-Scale Transition on One CPH (MI Gain = 5, MEASOUT Gain = 0.2) DAC, MI Gain = 10, MEASOUT Gain = 1, ±2 mA Range, CLOAD = 200 pF 900 MEASURE CURRENT IN-AMP T MEASURE VOLTAGE IN-AMP 800 FORCE AMP ATT1A6C.7K0 FmRVO pM-p FIN1 700 FOH0 1 600 Hz) ATT1A0C.3K5 FmRVO pM-p FIN2 nV/ 500 1 FOH0 D ( 400 ATTACK FROM FIN3 NS 11.75mV p-p 300 FOH0 1 200 1000 06197-022 06197-025 10 100 1k 10k 100k 1M CH1 10mV BW M10µs FREQUENCY (Hz) T 30.0µs Figure 30. NSD vs. Frequency (Measured in FVMV and FVMI Mode) Figure 33. AC Crosstalk at FOH0 in FI Mode from FIN DAC of Each Other PMU (Full- Scale Transition), MI Gain = 10, MEASOUT Gain = 1, ±2 mA Range, CLOAD = 200 pF Rev. F | Page 25 of 64

AD5522 Data Sheet TA = 25°C SYNC 4 BUSY 3 1 FOHx VICTIM 2 MEASOUTx VICTIM FOH0 1 MEASOUTx 3 ATTACK 4 TRIGGER 06197-026 06197-129 CH1 10.0mV BW CH2 50.0mV BW M100µs CH1 50.0mV BWCH3 5.00V BW M800ns CH4 2.10V CHC3H 52. 0P0kV-Pk 14.38mCVH4 5.00V T 200.000µs CH45.00V BW T 2.40000µs Figure 34. Shorted DUT AC Crosstalk, Victim PMU in FVMI Mode Figure 37. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 1 nF, (±200 μA Range) RLOAD = 620 kΩ, FV = 3 V 1.80 1.75 SYNC 4 V) 1.70 BUSY E ( 3 G A 1.65 T L O V 1.60 Tx FOH0 U SO 1.55 A E 1 M 1.50 NOMINAL SUPPLIES 11..445025 35 45 55 ±561 D55I.F25FVERE7N5T DEVIC8E5S 06197-127 CH1 20.0mV BWCH3 5.00V BW M20.0µs CH4 2.10V 06197-130 FORCED TEMPERATURE (°C) CH45.00V BW T 60.0000µs Figure 35. Temperature Sensor Voltage on MEASOUTx Figure 38. Range Change, PMU0, ±5 μA to ±2 mA, CLOAD = 100 nF, vs. Forced Temperature RLOAD = 620 kΩ, FV = 3 V SYNC SYNC 4 4 3 BUSY BUSY 3 FOH0 FOH0 11 1 06197-128 06197-131 CH1 100mV BW CH3 5.00V BW M2.00µs CH4 2.10V CH1 20.0mV BWCH3 5.00V BW M20.0µs CH4 2.10V CH45.00V BW T 6.0000µs CH45.00V BW T 60.0000µs Figure 36. Range Change, PMU0, ±5 μA to ±2 mA, CLOAD = 1 nF, Figure 39. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 100 nF, RLOAD = 620 kΩ, FV = 3 V RLOAD = 620 kΩ, FV = 3 V Rev. F | Page 26 of 64

Data Sheet AD5522 SYNC 4 SYNC 4 BUSY 3 BUSY 3 MEASOUTx (MI) FOH0 2 1 FOHx 1 06197-132 06197-135 CH1 100.0mV BW CH3 5.00V BW M2.00µs CH4 2.10V CH1 2.00V CH2 2.00V M5.0µs CH1 3.84V CH45.00V BW T 6.00000µs CH3 5.00V CH45.00V Figure 40. Range Change, PMU0, ±20 μA to ±2 mA, CLOAD = 1 nF, Figure 43. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF, RLOAD = 150 kΩ, FV = 3 V CCOMPx = 100 pF, RLOAD = 5.6 kΩ SYNC 4 SYNC 4 BUSY 3 BUSY 3 MEASOUTx (MI) FOH0 2 FOHx 1 1 06197-133 06197-136 CH1 50.0mV BWCH3 5.00V BW M2.000µs CH4 2.10V CH1 2.00V CH2 10.00V M100µs CH1 3.20V CH45.00V BW T 6.00000µs CH3 5.00V CH45.00V Figure 41. Range Change, PMU0, ±2 mA to ±20 μA, CLOAD = 1 nF, Figure 44. FV Settling, 0 V to 5 V, ±5 μA Range, CLOAD = 220 pF, RLOAD = 150 kΩ, FV = 3 V CCOMPx = 100 pF, RLOAD = 1 MΩ SYNC SYNC 4 4 BUSY BUSY 3 3 MEASOUTx (MI) MEASOUTx (MI) 2 2 FOHx FOHx 1 1 06197-134 06197-137 CH1 2.00V CH2 2.00V M10.0µs CH1 3.84V CH1 2.00V CH2 10.0V M25.0µs CH1 3.20V CH3 5.00V CH45.00V CH3 5.00V CH45.00V Figure 42. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF, Figure 45. FV Settling, 0 V to 5 V, ±20 μA Range, CLOAD = 220 pF, CCOMPx = 1 nF, RLOAD = 5.6 kΩ CCOMPx = 100 pF, RLOAD = 270 kΩ Rev. F | Page 27 of 64

AD5522 Data Sheet SYNC 4 BUSY 3 MEASOUTx (MI) 2 FOHx 1 06197-138 CH1 2.00V CH2 10.0V M10.0µs CH1 3.20V CH3 5.00V CH45.00V Figure 46. FV Settling, 0 V to 5 V, ±200 μA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 27 kΩ Rev. F | Page 28 of 64

Data Sheet AD5522 TERMINOLOGY Offset Error Pin Capacitance Offset error is a measure of the difference between the actual Pin capacitance is the capacitance measured at a pin when that voltage and the ideal voltage at midscale or at zero current function is off or high impedance. expressed in mV or % FSR. Slew Rate Gain Error The slew rate is the rate of change of the output voltage Gain error is the difference between full-scale error and zero- expressed in V/μs. scale error. It is expressed in % FSR. Output Voltage Settling Time Gain Error = Full-Scale Error − Zero-Scale Error Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale where: input change. Full-Scale Error is the difference between the actual voltage and the ideal voltage at full scale. Digital-to-Analog Glitch Energy Zero-Scale Error is the difference between the actual voltage and Digital-to-analog glitch energy is the amount of energy that is the ideal voltage at zero scale. injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-sec. It is measured by Linearity Error toggling the DAC register data between 0x7FFF and 0x8000. Linearity error, or relative accuracy, is a measure of the maximum deviation from a straight line passing through the Digital Crosstalk endpoints of the full-scale range. It is measured after adjusting Digital crosstalk is defined as the glitch impulse transferred to for gain error and offset error and is expressed in % FSR. the output of one converter due to a change in the DAC register code of another converter. It is specified in nV-sec. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured AC Crosstalk change and the ideal 1 LSB change between any two adjacent AC crosstalk is defined as the glitch impulse transferred to the codes. A specified differential nonlinearity of ±1 LSB maximum output of one PMU due to a change in any of the DAC registers ensures monotonicity. in the package. Common-Mode (CM) Error ACPSRR Common-mode (CM) error is the error at the output of the ACPSRR is a measure of the ability of the device to avoid amplifier due to the common-mode input voltage. It is coupling noise and spurious signals that appear on the supply expressed in % of FSVR/V. voltage pin to the output of the switch. The dc voltage on the Leakage Current device is modulated by a sine wave of 0.2 V p-p. The ratio of the Leakage current is the current measured at an output pin when amplitude of the signal on the output to the amplitude of the that function is off or high impedance. modulation is the ACPSRR. Rev. F | Page 29 of 64

AD5522 Data Sheet THEORY OF OPERATION The AD5522 is a highly integrated, quad per-pin parametric window. Information on whether the measurement was high or measurement unit (PPMU) for use in semiconductor automated low is available via the serial interface (comparator status register). test equipment. It provides programmable modes to force a pin Table 9. Comparator Output Function Using LVDS Interface voltage and measure the corresponding current (FVMI) and to Test Condition CPOx Output force a pin current and measure the corresponding voltage (CPL < (V or I )) and ((V or I ) < CPH) 1 (FIMV). The device is also capable of all other combinations, DUT DUT DUT DUT (CPL > (V or I )) or ((V or I ) > CPH) 0 including force high-Z and measure high-Z. The PPMU can DUT DUT DUT DUT force or measure a voltage range of 22.5 V. It can force or measure currents up to ±80 mA per channel using the internal CLAMPS amplifier; the addition of an external amplifier enables higher Current and voltage clamps are included on chip, one clamp for current ranges. All the DAC levels required for each PMU each PMU channel. The clamps protect the DUT in the event of channel are on chip. an open-circuit or short-circuit condition. Internal DAC levels FORCE AMPLIFIER set the CLL (clamp low) and CLH (clamp high) levels. The clamps work to limit the force amplifier if a voltage or current at the The force amplifier drives the analog output, FOHx, which DUT exceeds the set levels. The clamps also protect the DUT if drives a programmed current or voltage to the device under test a transient voltage or current spike occurs when changing to a (DUT). Headroom and foot room requirements for this different operating mode or when programming the device to a amplifier are 3 V on either end. An additional ±1 V is dropped different current range. across the sense resistor when maximum (rated) current is flowing through it. The voltage clamps are available while forcing current, and the current clamps are available while forcing voltage. The user can The force amplifier is designed to drive DUT capacitances up to set up the voltage or current clamp status (enabled or disabled) 10 nF, with a compensation value of 100 pF. Larger DUT using the serial interface (system control register or PMU register). capacitive loads require larger compensation capacitances. Each clamp has a smooth, finite transition region between Local feedback ensures that the amplifiers are stable when normal (unclamped) operation and the final clamped level, and disabled. A disabled channel reduces power consumption by an internal flag is activated within this transition zone. The 2.5 mA per channel. open-drain CGALM pin indicates whether one or more PMU COMPARATORS channels has clamped. The clamp status of an individual PMU Per channel, the DUT measured voltage or current is monitored can be determined by polling the alarm status register using the by two comparators configured as window comparators. Internal SPI or LVDS interface. DAC levels set the CPL (comparator low) and CPH (comparator CLL should never be greater than CLH. For the voltage clamps, high) threshold values. There are no restrictions on the voltage there should be 500 mV between the CLL and CLH levels to settings of the comparator highs and lows. CPL going higher ensure that a region exists in the middle of the clamps where than CPH is not a useful operation; however, it does not cause both are off. Similarly, set current clamps ±250 mV away from 0 A. any problems with the device. CPOLx (comparator output low) The transfer function for voltage clamping in FI mode is and CPOHx (comparator output high) are continuous time comparator outputs. VCLL or VCLH = 4.5 × VREF × (DAC_CODE/216) − (3.5 × VREF × (OFFSET_DAC_CODE/216)) + DUTGND Table 8. Comparator Output Function Using SPI Interface See the DAC Levels section for more information. Test Condition CPOLx CPOHx V or I > CPH 0 The transfer function for current clamping in FV mode is DUT DUT V or I < CPH 1 DUT DUT ICLL or ICLH = 4.5 × VREF × ((DAC_CODE − VDUT or IDUT > CPL 1 32,768)/216)/(R × MI_Amplifier_Gain) SENSE V or I < CPL 0 DUT DUT where: CPH > V or I > CPL 1 1 DUT DUT R is the sense resistor of the selected current range. SENSE When using the SPI interface, full comparator functionality is MI_Amplifier_Gain is the gain of the measure current available. When using the LVDS interface, the comparator instrumentation amplifier, either 5 or 10. function is limited to one output per comparator, due to the Do not change clamp levels while the channel is in force mode large pin count requirement of the LVDS interface. because this can affect the forced voltage or current applied to When using the LVDS interface, the comparator output available the DUT. Similarly, the clamps should not be enabled or pins, CPO0 to CPO3, provide information on whether the meas- disabled during a force operation. ured voltage or current is inside or outside the set CPH and CPL Rev. F | Page 30 of 64

Data Sheet AD5522 When the AD5522 is placed in high-Z mode, the clamp circuit where: is always configured to monitor the measure current signal FI is the forced current. (irrespective of which high-Z mode is selected, high-Z V or R is the selected sense resistor. SENSE high-Z I). At this time, the clamp circuit is also comparing to MI_Amplifier_Gain is the gain of the measure current the voltage clamp levels. Because the device is in high-Z mode, instrumentation amplifier. This gain can be set to 5 or 10 via the the measure current signal is at zero, but zero for the measure serial interface. current is always the VMID voltage set by the offset DAC. For In the ±200 μA range with the 5 kΩ sense resistor and an I SENSE default offset DAC conditions, this causes no concern. For other gain of 10, the maximum current range possible is ±225 μA. settings of the offset DAC, the zero point follows the VMID, Similarly, for the other current ranges, there is an overrange of and as the clamp circuit is comparing the voltage clamp levels to 12.5% to allow for error correction. the measure current signal, there may be instances where the Also, the forced current range is the quoted full-scale range only voltage clamp levels cause the alarm to flag during high-Z with an applied reference of 5 V or 2.5 V (with I amplifier mode. To avoid this, the clamps can be disabled when going SENSE gain = 5). The I amplifier is biased by the VMID DAC into high-Z mode. SENSE voltage in such a way as to center the measure current output CURRENT RANGE SELECTION irrespective of the voltage span used. Integrated thin film resistors minimize the need for external When using the EXTFOHx outputs for current ranges up to components and allow easy selection of any of these current ±80 mA, there is no switch in series with the EXTFOHx line, ranges: ±5 µA (200 kΩ), ±20 μA (50 kΩ), ±200 μA (5 kΩ), and ensuring minimum capacitance present at the output of the ±2 mA (500 Ω). One current range up to ±80 mA can be force amplifier. This feature is important when using a pin accommodated per channel by connecting an external sense electronics driver to provide high current ranges. resistor. For current ranges in excess of ±80 mA, it is necessary HIGH CURRENT RANGES that an external amplifier be used. With the use of an external high current amplifier, one high For the suggested current ranges, the maximum voltage drop current range in excess of ±80 mA is possible. The high current across the sense resistors is ±1 V. However, to allow for error amplifier buffers the force output and provides the drive for the correction, there is some overrange available in the current required current. ranges (±12.5% or ±0.125 V across R ). The full-scale SENSE voltage range that can be loaded to the FIN DAC is ±11.5 V; the To eliminate any timing concerns when switching between the forced current can be calculated as follows: internal ranges and the external high current range, there is a mode where the internal ±80 mA stage can be enabled at all FI = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(R × SENSE times. See Table 26 for more information. MI_Amplifier_Gain) HIGH CURRENT AMPLIFIER EN EXTFOHx CFFx INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) FIN DAC + FOHx – RSENSE VMID TO 4kΩ EXTMEASIHx CENTER + I RANGE – 2kΩ RSENSE + MEASOUTx ×1 OR ×5 or ×1–0 + EXTMEASILx ×0.2 – 4kΩ AGND MEASVHx + – + DUT ×1 DUTGND – + – 06197-028 Figure 47. Addition of High Current Amplifier for Wider Current Range (>±80 mA) Rev. F | Page 31 of 64

AD5522 Data Sheet MEASURE CURRENT GAINS VREF = 3.5 V results in a ±7.87 V range. Using a gain setting of 10, there is ±0.785 V maximum across R , resulting in The measure current amplifier has two gain settings, 5 and 10. SENSE current ranges of ±3.92 μA, ±15.74 μA, and so on (including The two gain settings allow users to achieve the quoted/specified overrange of ±12.5% to allow for error correction). current ranges with large or small voltage swing. Use the 10 gain setting with a 5 V reference, and use the 5 gain setting with a VMID VOLTAGE 2.5 V reference. Both combinations ensure the specified current The midcode voltage (VMID) is used in the measure current ranges. Using other VREF/gain setting combinations should amplifier block to center the current ranges about 0 A. This is achieve smaller current ranges only. Achieving greater current required to ensure that the quoted current ranges can be achieved ranges than the specified ranges is outside the intended opera- when using offset DAC settings other than the default. VMID tion of the AD5522. The maximum guaranteed voltage across corresponds to 0x8000 or the DAC midcode value, that is, the R = ±1.125 V. SENSE middle of the voltage range set by the offset DAC setting (see Following are examples of VREF/gain setting combinations. In Table 13). See the block diagram in Figure 48. these examples, the offset DAC is at its default value of 0xA492. VMID = 4.5 × VREF × (32,768/216) − (3.5 × VREF × VREF = 5 V results in a ±11.25 V range. Using a gain setting of (OFFSET_DAC_CODE/216)) 10, there is ±1.125 V maximum across RSENSE, resulting in or current ranges of ±5.625 μA, ±22.5 μA, and so on (including VMID = 3.5 × VREF × ((42,130 − OFFSET_DAC_CODE)/216) overrange of ±12.5% to allow for error correction). VREF = 2.5 V results in a ±5.625 V range. Using a gain setting of VMIN = −3.5 × VREF × (OFFSET_DAC_CODE/216) 5 results in current ranges of ±5.625 μA, ±22.5 μA, and so on (including overrange of ±12.5% to allow for error correction). VREF VTOP VDAC_MID VMID DATA ADDRESS DAC DAC HVAMP VOFFSET 2R 7R VDAC_MIN VMIN REFGND DAC HVAMP MEASURE VOFFSET CURRENT 2R 7R 10R IN-AMP SEL×10 ATTB SEL×5 1R ATT 5R 1R INT/EXTMEASIHx INAMP10 MEASOUTx 1R INT/EXTMEASILx 50Ω 1R MI 5R 10R SEL×5 ATTB 1R SEL×10 ATTB AGND 1R 5R MEASVHx INAMP1 MV DUTGND ATT 1R 1R R MEASURE AGND MMATVI T= = =M MAEETAATSESUNURUREAE CT VIUOORNLRT FEAONGRTE MEASOUTx ×0.2 VIONL-ATAMGPE 06197-043 SEL×5 = MI GAIN = 5 SEL×10 = MI GAIN = 10 Figure 48. Measure Block and VMID Influence Rev. F | Page 32 of 64

Data Sheet AD5522 CHOOSING POWER SUPPLY RAILS MEASURE OUTPUT (MEASOUTx PINS) As noted in the Specifications section, the minimum supply The measured DUT voltage or current (voltage representation variation across the part |AVDD − AVSS| ≥ 20 V. For the of DUT current) is available on the MEASOUTx pin with respect AD5522 circuits to operate correctly, the supply rails must take to AGND. The default MEASOUTx range is the forced voltage into account not only the force voltage range, but also the range for voltage measure and current measure (nominally internal DAC minimum voltage level, as well as headroom and ±11.25 V, depending on the reference voltage and offset DAC) so on. The DAC amplifier gains VREF by 4.5, and the offset and includes some overrange to allow for offset correction. DAC centers that range about some chosen point. The serial interface allows the user to select another MEASOUTx The supplies need to cater to the DAC output voltage range to range of 0.9 × VREF to AGND, allowing an ADC with a 5 V avoid impinging on other parts of the circuit (for example, if the input range to be used. The MEASOUTx line for each PMU measure current block for rated current ranges has a gain of channel can be made high impedance via the serial interface. 10/5, the supplies need to provide sufficient headroom and foot The offset DAC directly offsets the measured output voltage level, room to not clip the measure current circuit when full current but only when GAIN1 = 0. When the MEASOUT gain is 0.2, the range is required). minimum code from the DAC is used to center the MEASOUTx Also, the MEASOUT gain = 0.2 setting uses the VMIN level for voltage and to ensure that the voltage is within the range of 0 to scaling purposes; if there is not enough foot room for this 0.9 × VREF (see Figure 48). VMIN level, then the MV and MI output voltage range is When using low supply voltages, ensure that there is sufficient affected. headroom and foot room for the DAC output range (set by the For the MEASOUT gain = 0.2 setting, it is important to choose VREF and offset DAC setting). AVSS based on the following: DEVICE UNDER TEST GROUND (DUTGND) AVSS ≤ −3.5 × (VREF × (OFFSET_DAC_CODE/216)) − By default, there is one DUTGND input available for all four AVSS_footroom − V − (R × I ) DUTGND CABLE LOAD PMU channels. However, in some PMU applications, it is where: necessary that each channel operate from its own DUTGND AVSS_footroom = 4 V. level. The dual function pin, GUARDINx/DUTGNDx, can be configured as an input to the guard amplifier (GUARDIN) or as V is the voltage range anticipated at DUTGND. DUTGND a DUTGND input for each channel. R is the cable/path resistance. CABLE The pin function can be configured through the serial interface I is the maximum load current. LOAD on power-on for the required operation. The default connection To achieve full output current in both the internal and external is SW13b (GUARDIN) and SW14b (shared DUTGND). current ranges, consider power supply headroom and foot room (see Table 1). For example, to achieve full 80 mA sink capability, the foot room needs to increase from AVSS + 3 V to AVSS + 6 V. Table 10. MEASOUTx Output Ranges for GAIN1 = 0, MEASOUT Gain = 1 Measure Output Voltage Range for VREF = 5 V1 MEASOUT Function Current Gain Transfer Function Offset DAC = 0x0 Offset DAC = 0xA492 Offset DAC = 0xED67 MV 5 or 10 ±V 0 V to 22.5 V ±11.25 V −16.26 V to +6.25 V DUT MI GAIN0 = 0 10 (I × R × 10) +VMID2 0 V to 22.5 V ±11.25 V −16.26 V to +6.25 V DUT SENSE GAIN0 = 1 5 (I × R × 5) + VMID 0 V to 11.25 V, ±5.625 V, (VREF = 2.5 V) −8.13 V to +3.12 V, DUT SENSE (VREF = 2.5 V) (VREF = 2.5 V) 1 VREF = 5 V unless otherwise noted. 2 VMID = 3.5 × VREF × ((42,130 − OFFSET_DAC_CODE)/216), see VMID Voltage section for more information. Rev. F | Page 33 of 64

AD5522 Data Sheet Table 11. MEASOUTx Output Ranges for GAIN1 = 1, MEASOUT Gain = 0.2 Measure MEASOUT Function Current Gain Transfer Function Output Voltage Range for VREF = 5 V1, 2 MV 5 or 10 0.2 × (V -DUTGND – VMIN3) 0 V to 4.5 V (±2.25 V centered around 2.25 V) DUT MI GAIN0 = 0 10 (I × R × 10 × 0.2) + (0.45 × VREF) 0 V to 4.5 V (±2.25 V centered around 2.25 V) DUT SENSE GAIN0 = 1 5 (I × R × 5 × 0.2) + (0.45 × VREF) 1.125 V to 3.375 V (±1.125 V, centered around 2.25 V), DUT SENSE 0 V to 2.25 V (±1.125 V, centered around 1.125 V), (VREF = 2.5 V) 1 VREF = 5 V unless otherwise noted. 2 The offset DAC setting has no effect on the output voltage range. 3 VMIN = 3.5 × VREF × (OFFSET_DAC_CODE/216), see VMID Voltage section for more information. When configured as DUTGND per channel, this dual function output, but it can be configured as a latched output via the serial pin is no longer connected to the input of the guard amplifier. interface (system control register). Instead, it is connected to the low end of the instrumentation COMPENSATION CAPACITORS amplifier (SW14a), and the input of the guard amplifier is Each channel requires an external compensation capacitor connected internally to MEASVHx (SW13a). (CCOMP) to ensure stability into the maximum load capacitance while ensuring that settling time is optimized. In addition, one MEASVH[0:3] +– a SW16 DUT CFF pin per channel is provided to further optimize stability and SW13 settling time performance when in force voltage (FV) mode. When AGND b GUARDGUARD[0:3] changing from force current (FI) mode to FV mode, the internal + SW14 a AMP ×1– + GUARDIN[0:3]/ switch connecting the CFF capacitor is automatically closed. – DUTGND[0:3] b DUTGND Although the force amplifier is designed to drive load capacitances MVIOENAL-ATSMAUGRPEE 06197-029 uupse t loa r1g0e rn Fco (mwpitehn CsaCtiOonM cPa pcaapciatcoirt ovra l=u e1s0 t0o p dFr)i,v iet liasr pgoers sliobaled st,o Figure 49. Using the DUTGND per Channel Feature at the expense of an increase in settling time. If a wide range of load capacitances must be driven, an external multiplexer GUARD AMPLIFIER connected to the CCOMPx pin allows optimization of settling A guard amplifier allows the user to bootstrap the shield of the time vs. stability. The series resistance of a switch placed on cable to the voltage applied to the DUT, ensuring minimal CCOMPx should typically be <50 Ω. drops across the cable. This is particularly important for Suitable multiplexers for use are the ADG1404, ADG1408, or measurements requiring a high degree of accuracy and in leakage one of the multiplexers in the ADG4xx family, which typically current testing. have on resistances of less than 50 Ω. If not required, all four guard amplifiers can be disabled via the Similarly, connecting the CFF node to an external multiplexer serial interface (system control register). Disabling the guard accommodates a wide range of C in FV mode. The ADG1204 amplifiers decreases power consumption by 400 μA per channel. DUT or ADG1209 family of multiplexers meet these requirements. As described in the Device Under Test Ground (DUTGND) The series resistance of the multiplexer used should be such that section, GUARDINx/DUTGNDx are dual function pins. Each 1/(2π × R × C ) > 100 kHz pin can function either as a guard amplifier input for one chan- ON DUT nel or as a DUTGND input for one channel, depending on the The voltage range of the CFFx and CCOMPx pins is the same as requirements of the end application (see Figure 49). the voltage range expected on the FOHx pin; therefore, choice of capacitor must take this into account. A guard alarm event occurs when the guard output moves more than 100 mV away from the guard input voltage for more than Table 12. Suggested Compensation Capacitor Selection 200 μs. In this case, the event is flagged via the open-drain output C CCOMP Capacitor CFF Capacitor LOAD CGALM. Because the guard and clamp alarm functions share ≤1 nF 100 pF 220 pF the same alarm output, CGALM, the alarm information (alarm ≤10 nF 100 pF 1 nF trigger and alarm channel) is available via the serial interface in ≤100 nF C /100 C /10 LOAD LOAD the alarm status register. Alternatively, the serial interface allows the user to set up the CGALM output to flag either the clamp status or the guard status. By default, this open-drain alarm pin is an unlatched Rev. F | Page 34 of 64

Data Sheet AD5522 SYSTEM FORCE AND SENSE SWITCHES TEMPERATURE SENSOR Each channel has switches to allow connection of the force An on-board temperature sensor monitors die temperature. The (FOHx) and sense (MEASVHx) lines to a central PMU for temperature sensor is located at the center of the die. If the calibration purposes. There is one set of SYS_FORCE and temperature exceeds the factory specified value (130°C) or a SYS_SENSE pins per device. It is recommended that these user programmable value, the device protects itself by shutting connections be made individually to each PMU channel. down all channels and flagging an alarm through the latched, open-drain TMPALM pin. Alarm status can be read back from FOH0 the alarm status register or the PMU register, where latched and unlatched bits indicate whether an alarm has occurred and FOH1 whether the temperature has dropped below the set alarm SYS_FORCE temperature. The shutdown temperature is set using the system FOH2 control register. FOH3 MEASVH0 MEASVH1 SYS_SENSE MEASVH2 MEASVH3 06197-042 Figure 50. SYS_FORCE and SYS_SENSE Connections to FOHx and MEASVHx Pins Rev. F | Page 35 of 64

AD5522 Data Sheet DAC LEVELS Each channel contains five dedicated DAC levels: one for the The power supplies should be selected to support the required force amplifier, one each for the clamp high and clamp low levels, range and should take into account amplifier headroom and and one each for the comparator high and comparator low levels. foot room and sense resistor voltage drop (±4 V). The architecture of a single DAC channel consists of a 16-bit Therefore, depending on the headroom available, the input to resistor-string DAC followed by an output buffer amplifier. This the force amplifier can be unipolar positive or bipolar, either resistor-string architecture guarantees DAC monotonicity. The symmetrical or asymmetrical about DUTGND, but always 16-bit binary digital code loaded to the DAC register determines within a voltage span of 22.5 V. at which node on the string the voltage is tapped off before The offset DAC offsets all DAC functions. It also centers the being fed into the output amplifier. current range so that zero current always flows at midscale The transfer function for DAC outputs is as follows: code, regardless of the offset DAC setting. VOUT = 4.5 × VREF × (X2/216) − (3.5 × VREF × Rearranging the transfer function for the DAC output gives the (OFFSET_DAC_CODE/216)) + DUTGND following equation to determine which offset DAC code is required for a given reference and output voltage range. where: VREF is the reference voltage and is in the range of 2 V to 5 V. OFFSET_DAC_CODE = (216 × (VOUT − DUTGND))/ X2 is the calculated DAC code value and is in the range of 0 to (3.5 × VREF) − ((4.5 × DAC_CODE)/3.5) 65,535 (see the Gain and Offset Registers section). OFFSET_DAC_ When the output range is adjusted by changing the default value CODE is the code loaded to the offset DAC. It is multiplied by of the offset DAC, an extra offset is introduced due to the gain 3.5 in the transfer function. On power-up, the default code error of the offset DAC channel. The amount of offset is depen- loaded to the offset DAC is 0xA492; with a 5 V reference, this dent on the magnitude of the reference and how much the gives a span of ±11.25 V. offset DAC channel deviates from its default value. See the OFFSET DAC Specifications section for this offset. The worst-case offset occurs when the offset DAC channel is at positive or negative The AD5522 is capable of forcing a 22.5 V (4.5 × VREF) voltage full scale. This value can be added to the offset present in the span. Included on chip is one 16-bit offset DAC (one for all four main DAC channel to give an indication of the overall offset for channels) that allows for adjustment of the voltage range. that channel. In most cases, the offset can be removed by The usable range is −16.25 V to +22.5 V. Zero scale loaded to programming the C register of the channel with an appropriate the offset DAC gives a full-scale range of 0 V to 22.5 V, midscale value. The extra offset caused by the offset DAC needs to be gives ±11.25 V, and the most useful negative range is −16.25 V taken into account only when the offset DAC is changed from to +6.25 V. Full scale loaded to the offset DAC does not give a its default value. useful output voltage range, because the output amplifiers are GAIN AND OFFSET REGISTERS limited by the available foot room. Table 13 shows the effect of the offset DAC on the other DACs in the device. Each DAC level has an independent gain (M) register and an independent offset (C) register, which allow trimming out of Table 13. Relationship of Offset DAC to Other DACs the gain and offset errors of the entire signal chain, including (VREF = 5 V) the DAC. All registers in the AD5522 are volatile, so they must Offset DAC Code DAC Code DAC Output Voltage (V) be loaded on power-on during a calibration cycle. Data from 0 0 0 the X1 register is operated on by a digital multiplier and adder 32,768 +11.25 controlled by the contents of the M and C registers. The cali- 65,535 +22.50 brated DAC data is then stored in the X2 register. 32,768 0 −8.75 The digital input transfer function for each DAC can be 32,768 +2.50 represented as follows: 65,535 +13.75 42,130 0 −11.25 X2 = [(M + 1)/2n × X1] + (C − 2n − 1) 32,768 0 where: 65,535 +11.25 X2 is the data-word loaded to the resistor-string DAC. 60,855 0 −16.25 X1 is the 16-bit data-word written to the DAC input register. 32,768 −5.00 M is the code in the gain register (default code = 216 − 1). The M 65,535 +6.25 register is 15 bits (D15 to D1, the LSB is a don’t care). 65,535 Foot room limitations C is the code in the offset register (default code = 215). n is the DAC resolution (n = 16). Rev. F | Page 36 of 64

Data Sheet AD5522 The calibration engine is engaged only when data is written to Gain and Offset Registers for the Clamp DACs the X1 register and for some PMU writes (see Table 18). The The clamp DAC levels contain independent gain and offset calibration engine is not engaged when data is written to the M control registers that allow the user to digitally trim gain and or C register. This has the advantage of minimizing the initial offset. There are two sets of X1, M, and C registers: one set for setup time of the device. To calculate a result that includes new the force voltage mode and one set for all five current ranges. M or C data, a write to X1 is required. Two X2 registers store the calculated DAC values, ready to load CACHED X2 REGISTERS to the DAC register upon a PMU mode change. Each DAC has a number of cached X2 registers. These registers VREF 16 16 16-BIT CLH store the result of a gain and offset calibration in advance of a mode CLHDAC 16 X1REG X2REG change. This enables the user to preload registers, allowing the 16 MREG CREG calibration engine to calculate the appropriate X2 value and store ×2 it until a change in mode occurs. Because the data is ready and 16 16 C1L6L-BDIATC CLL 16 X1REG X2REG held in the appropriate register, mode changing is as time efficient 16 MREG CREG acus rproesnstilbyl ep.a Irft a onf uthped oatpee oractciunrgs P toM aU D mAoCd ree, gtihsete Dr AseCt tohuattp ius t is SERIALI/F ×2 06197-032 updated immediately (depending on the LOAD condition). Figure 53. Clamp Registers Gain and Offset Registers for the FIN DAC REFERENCE VOLTAGE (VREF) The force amplifier input (FIN) DAC level contains independent One buffered analog input, VREF, supplies all 21 DACs with the gain and offset control registers that allow the user to digitally necessary reference voltage to generate the required dc levels. trim gain and offset. There are six sets of X1, M, and C registers: REFERENCE SELECTION one set for the force voltage range and one set for each force current range (four internal current ranges and one external The voltage applied to the VREF pin determines the output current range). Six X2 registers store the calculated DAC values, voltage range and span applied to the force amplifier, clamp, and ready to load to the DAC register upon a PMU mode change. comparator inputs. The AD5522 can be used with a reference input ranging from 2 V to 5 V; however, for most applications, a OFFSETDAC reference input of 5 V or 2.5 V is sufficient to meet all voltage 16 VREF range requirements. The DAC amplifier gain is 4.5, which gives 16 16 X1REG 16 F1IN6-DBAITC FIN a DAC output span of 22.5 V. The DACs have gain and offset SERIALI/F MCRREEGG ×6 X2REG 06197-030 rIneg aisdtdeirtsi othna, tt hcea ng abien urseegdis ttoer t criamn boeu tu ssyesdt etmo r eerdruocres .t he DAC Figure 51. FIN DAC Registers output range to the desired force voltage range. The FIN DAC Gain and Offset Registers for the Comparator DACs retains 16-bit resolution even with a gain register setting of quarter scale (0x4000). Therefore, from a single 5 V reference, it The comparator DAC levels contain independent gain and is possible to obtain a voltage span as high as 22.5 V or as low as offset control registers that allow the user to digitally trim gain 5.625 V. and offset. There are six sets of X1, M, and C registers: one set for the force voltage mode and one set for each force current When using the gain and offset registers, the selected output range (four internal current ranges and one external current range should take into account the system gain and offset errors range). In this way, X2 can be preprogrammed, which allows for that need to be trimmed out. Therefore, the selected output efficient switching into the required compare mode. Six X2 range should be larger than the actual required range. registers store the calculated DAC values, ready to load to the When using low supply voltages, ensure that there is sufficient DAC register upon a PMU mode change. headroom and foot room for the required force voltage range. 16 Also, the forced current range is the quoted full-scale range only 16 16 X1REG 16 CP16H-BDIATC CPH with an applied reference of 5 V (ISENSE amplifier gain = 10) or MREG X2REG 2.5 V (I amplifier gain = 5). SENSE CREG ×6 VREF 16 16 16 X1REG 16 C1P6L-BDIATC CPL SERIALI/F MCRREEGG ×6 X2REG 06197-031 Figure 52. Comparator Registers Rev. F | Page 37 of 64

AD5522 Data Sheet Table 14. References Suggested For Use with AD55221 Initial Ref Out Ref Output Supply Voltage Part No. Voltage (V) Accuracy % TC (ppm/°C) Current (mA) Range (V) Package ADR435 5 ±0.04 1 30 +7 to +18 MSOP, SOIC ADR445 5 ±0.04 1 10 +5.5 to +18 MSOP, SOIC ADR431 2.5 ±0.04 1 30 +4.5 to +18 MSOP, SOIC ADR441 2.5 ±0.04 1 10 +3 to +18 MSOP, SOIC 1 Subset of the possible references suitable for use with the AD5522. Visit www.analog.com for more options. For other voltage and current ranges, the required reference In this case, the optimum reference is a 2.5 V reference; the user level can be calculated as follows: can use the M and C registers and the offset DAC to achieve the required −2 V to +8 V range. Change the I amplifier gain to 1. Identify the nominal range required. SENSE 5 to ensure a full-scale current range of the specified values (see 2. Identify the maximum offset span and the maximum gain the Current Range Selection section). This gain also allows opti- required on the full output signal range. mization of power supplies and minimizes power consumption 3. Calculate the new maximum output range, including the within the device. expected maximum gain and offset errors. 4. Choose the new required VOUT and VOUT , keeping It is important to bear in mind when choosing a reference value MAX MIN the VOUT limits centered on the nominal values. Note that that values other than 5 V (MI gain = 10) and 2.5 V (MI gain = 5) AVDD and AVSS must provide sufficient headroom. result in current ranges other than those specified. See the 5. Calculate the value of VREF as follows: Measure Current Gains section for more details. CALIBRATION VREF = (VOUT − VOUT )/4.5 MAX MIN Reference Selection Example Calibration involves determining the gain and offset of each channel in each mode and overwriting the default values in the If, given the following conditions: M and C registers of the individual DACs. In some cases (for Nominal output range = 10 V (−2 V to +8 V) example, FI mode), the calibration constants, particularly those Offset error = ±100 mV for gains, may be range dependent. Gain error = ±0.5% Reducing Zero-Scale Error REFGND = AGND = 0 V Zero-scale error can be reduced as follows: Then, with gain error = ±0.5%, the maximum positive gain error = +0.5%, and the output range including gain error = 10 V 1. Set the output to the lowest possible value. + 0.005(10 V) = 10.05 V. 2. Measure the actual output voltage and compare it to the required value. This gives the zero-scale error. With offset error = ±100 mV, the maximum offset error span = 3. Calculate the number of LSBs equivalent to the zero-scale 2(100 mV) = 0.2 V, and the output range including gain error error and add/subtract this number to the default value of and offset error = 10.05 V + 0.2 V = 10.25 V. the C register. To calculate VREF with actual output range = 10.25 V, that is, Reducing Gain Error −2.125 V to +8.125 V (centered), Gain error can be reduced as follows: VREF = (8.125 V + 2.125 V)/4.5 = 2.28 V 1. Measure the zero-scale error. If the solution yields an inconvenient reference level, the user 2. Set the output to the highest possible value. can adopt one of the following approaches: 3. Measure the actual output voltage and compare it to the • Use a resistor divider to divide down a convenient, higher required value. This is the gain error. reference level to the required level. 4. Calculate the number of LSBs equivalent to the gain error • Select a convenient reference level above VREF and modify and subtract this number from the default value of the M the gain and offset registers to digitally downsize the reference. register. Note that only positive gain error can be reduced. In this way, the user can use almost any convenient refer- ence level. • Use a combination of these two approaches. Rev. F | Page 38 of 64

Data Sheet AD5522 Calibration Example The calibration procedure for the force and measure circuitry is as follows: Nominal offset coefficient = 32,768 Nominal gain coefficient = 65,535 1. Calibrate the force voltage (2 points). In FV mode, write zero scale to the FIN DAC. Connect For example, the gain error = 0.5%, and the offset error = 100 mV. SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, and Gain error (0.5%) calibration: close the internal force/sense switch (SW7). 65,535 × 0.995 = 65,207 Using the system PMU, measure the error between the voltage at FOHx/MEASVHx and the desired value. Therefore, load Code 1111 1110 1011 0111 to the M register. Similarly, load full scale to the FIN DAC and measure the Offset error (100 mV) calibration: error between the voltage at FOHx/MEASVHx and the LSB size = 10.25/65,535 = 156 µV desired value. Calculate the M and C values. Load these values to the appropriate M and C registers of the FIN DAC. Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs 2. Calibrate the measure voltage (2 points). Therefore, load Code 0111 1101 0111 1111 to the C register. Connect SYS_FORCE to FOHx and SYS_SENSE to ADDITIONAL CALIBRATION MEASVHx, and close the internal force/sense switch (SW7). Force voltage on FOHx via SYS_FORCE and measure the The techniques described in the Calibration section are usually voltage at MEASOUTx. The difference is the error between sufficient to reduce the zero-scale and gain errors. However, the actual forced voltage and the voltage at MEASOUTx. there are limitations whereby the errors may not be sufficiently 3. Calibrate the force current (2 points). reduced. For example, the offset (C) register can only be used to In FI mode, write zero scale to the FIN DAC. Connect reduce the offset caused by negative zero-scale error. A positive SYS_FORCE to an external ammeter and to the FOHx pin. offset cannot be reduced. Likewise, if the maximum voltage is Measure the error between the ammeter reading and the below the ideal value, that is, a negative gain error, the gain (M) MEASOUTx reading. Repeat this step with full scale register cannot be used to increase the gain to compensate for loaded to the FIN DAC. Calculate the M and C values. the error. These limitations can be overcome by increasing the 4. Calibrate the measure current (2 points). reference value. In FI mode, write zero scale to the FIN DAC. Connect SYSTEM LEVEL CALIBRATION SYS_FORCE to an external ammeter and to the FOHx pin. There are many ways to calibrate the device on power-on. Measure the error between the ammeter reading and the Following is an example of how to calibrate the FIN DAC of the MEASOUTx reading. Repeat this step with full scale device without a DUT or DUT board connected. loaded to the FIN DAC. 5. Repeat this procedure for all four channels. Similarly, calibrate the comparator and clamp DACs, and load the appropriate gain and offset registers. Calibrating these DACs requires some successive approximation to find where the comparator trips or the clamps engage. Rev. F | Page 39 of 64

AD5522 Data Sheet CIRCUIT OPERATION FORCE VOLTAGE (FV) MODE The forced voltage can be calculated as follows: Most PMU measurements are performed in force voltage/measure Forced Voltage at DUT = VOUT current (FVMI) mode, for example, when the device is used as a VOUT = 4.5 × VREF × (DAC_CODE/216) − (3.5 × VREF × device power supply, or in continuity or leakage testing. In force (OFFSET_DAC_CODE/216)) + DUTGND voltage (FV) mode, the voltage forced is mapped directly to the where: DUT. The measure voltage amplifier completes the loop, giving VOUT is the voltage of the FIN DAC (see the DAC Levels negative feedback to the forcing amplifier (see Figure 54). section). EXTFOHx CFFx FORCE INTERNAL RANGE SELECT AMPLIFIER (±5µA, ±20µA, ±200µA, ±2mA) FIN DAC + FOHx – RSENSE VCMENIDT ETRO 4kΩ EXTMEASIHx I RANGE + – 2kΩ RSENSE + (UP TO MEASOUTx ××10 O.2R × 5× 1O0R– +– EXTMEASILx ±80mA) 4kΩ AGND MEASVHx + – + DUT ×1 DUTGND – + MEASURE VOLTAGE AMPLIF–IER 06197-033 Figure 54. Forcing Voltage, Measuring Current Rev. F | Page 40 of 64

Data Sheet AD5522 FORCE CURRENT (FI) MODE In force current (FI) mode, the voltage at the FIN DAC is where: converted to a current and is applied to the DUT. The feedback FI is the forced current. path is the measure current amplifier, feeding back the voltage R is the selected sense resistor. SENSE measured across the sense resistor. MEASOUTx reflects the MI_Amplifier_Gain is the gain of the measure current voltage measured across the DUT (see Figure 55). instrumentation amplifier. This gain can be set to 5 or 10 via the serial interface. For the suggested current ranges, the maximum voltage drop across the sense resistors is ±1 V. However, to allow for error The I amplifier is biased by the offset DAC output voltage in SENSE correction, there is some overrange available in the current such a way as to center the measure current output regardless of ranges. The maximum full-scale voltage range that can be the voltage span used. loaded to the FIN DAC is ±11.5 V. The forced current can be In the ±200 μA range with the 5 kΩ sense resistor and an I SENSE calculated as follows: gain of 10, the maximum current range possible is ±225 μA. FI = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(R × Similarly, for the other current ranges, there is an overrange of SENSE MI_Amplifier_Gain) 12.5% to allow for error correction. EXTFOHx CFFx FORCE INTERNAL RANGE SELECT AMPLIFIER (±5µA, ±20µA, ±200µA, ±2mA) FIN DAC + FOHx – RSENSE MEASURE CURRENT VMID TO AMPLIFIER CENTER 4kΩ EXTMEASIHx I RANGE + – RSENSE 2kΩ (UP TO + ±80mA) MEASOUTx ××10 O.2R ×5× 1O0R– +– EXTMEASILx 4kΩ MEASVHx AGND + – + DUT ×1 DUTGND – + – 06197-034 Figure 55. Forcing Current, Measuring Voltage Rev. F | Page 41 of 64

AD5522 Data Sheet SERIAL INTERFACE The AD5522 provides two high speed serial interfaces: an SPI- The input register addressed is updated on the rising edge of compatible interface operating at clock frequencies up to 50 MHz SYNC. For another serial transfer to take place, SYNC must be and an EIA-644-compliant LVDS interface. To minimize both taken low again. the power consumption of the device and the on-chip digital The shift register can accept longer words (for example, 32-bit noise, the serial interface powers up fully only when the device words), framed by SYNC, but the data should always be in the is being written to, that is, on the falling edge of SYNC. 29th LSB positions. SPI INTERFACE RESET FUNCTION The serial interface operates from a 2.3 V to 5.25 V DVCC supply Bringing the level-sensitive RESET line low resets the contents range. The SPI interface is selected when the SPI/LVDS pin is of all internal registers to their power-on reset state (see the held low. It is controlled by four pins, as described in Table 15. Power-On Default section). This sequence takes approximately Table 15. Pins That Control the SPI Interface 600 µs. BUSY goes low for the duration, returning high when Pin Description RESET is brought high again and the initialization is complete. SYNC Frame synchronization input While BUSY is low, all interfaces are disabled. When BUSY SDI Serial data input pin returns high, normal operation resumes, and the status of the SCLK Clocks data in and out of the device RESET pin is ignored until it goes low again. The SDO output is SDO Serial data output pin for data readback (weak high impedance during a power-on reset or a RESET. A power- SDO output driver, may require reduction in SCLK on reset functions the same way as RESET. frequency to correctly read back, see Table 2) BUSY AND LOAD FUNCTIONS LVDS INTERFACE The BUSY pin is an open-drain output that indicates the status The LVDS interface uses the same input pins, with the same of the AD5522 interface. When writing to any register, BUSY designations, as the SPI interface. In addition, four other pins goes low and stays low until the command completes. are provided for the complementary signals needed for differ- ential operation, as described in Table 16. A write operation to a DAC X1 register and some PMU register bits (see Table 18) drives the BUSY signal low for longer than a Table 16. Pins That Control the LVDS Interface write M, C, or system control register. For DACs, the value of Pin Description the internal cached (X2) data is calculated and stored each time SYNC Differential frame synchronization signal that the user writes new data to the corresponding X1 register. SYNC Differential frame synchronization signal During the calculation and writing of X2, the BUSY output is (complement) driven low. While BUSY is low, the user can continue writing SDI Differential serial data input SDI Differential serial data input (complement) new data to the any register, but this write should not be SCLK Differential serial clock input completed with SYNC going high until BUSY returns high (see SCLK Differential serial clock input (complement) Figure 56 and Figure 57). SDO Differential serial data output for data readback X2 values are stored and held until a PMU word is written that SDO Differential serial data output for data readback calls the appropriate cached X2 register. Only then is a DAC (complement) output updated. SERIAL INTERFACE WRITE MODE The DAC outputs and PMU modes are updated by taking the The AD5522 allows writing of data via the serial interface to LOAD input low. If LOAD goes low while BUSY is active, the every register directly accessible to the serial interface, that is, LOAD event is stored and the DAC outputs or PMU modes are all registers except the DAC registers. updated immediately after BUSY goes high. A user can also hold The serial word is 29 bits long. The serial interface works with the LOAD input permanently low. In this case, the DAC outputs both a continuous and a burst (gated) serial clock. Serial data or PMU modes are updated immediately after BUSY goes high. applied to SDI is clocked into the AD5522 by clock pulses The BUSY pin is bidirectional and has a 50 kΩ internal pull-up applied to SCLK. The first falling edge of SYNC starts the write resistor. When multiple AD5522 devices are used in one system, cycle. At least 29 falling clock edges must be applied to SCLK to the BUSY pins can be tied together. This is useful when it is clock in 29 bits of data before SYNC is taken high again. required that no DAC or PMU in any device be updated until all others are ready to be updated. When each device finishes updating its X2 registers, it releases the BUSY pin. If another device has not finished updating its X2 registers, it holds BUSY low, thus delaying the effect of LOAD going low. Rev. F | Page 42 of 64

Data Sheet AD5522 Because there is only one calibration engine shared among four BUSY also goes low during a power-on reset and when a falling channels, the task of calculating X2 values must be done sequentially, edge is detected on the RESET pin. so that the length of the BUSY pulse varies according to the CALIBRATION ENGINE TIME number of channels being updated. Following any register ~650ns 650ns 650ns 350ns update, including multiple channel updates, subsequent writes WRITE 1 SFTIRASGTE SSETCAOGNED STTHAIRGDE should either be timed or should wait until BUSY returns high FIRST SECOND THIRD FOR EXAMPLE, (see Figure 56). If subsequent writes are presented before the STAGE STAGE STAGE WRITETO 3 FIN DAC REGISTERS calibration engine completes the first stage of the last Channel X2 FIRST SECOND THIRD STAGE STAGE STAGE calculation, data may be lost. Table 17. BUSY Pulse Widths WRITE 2 SFTIRASGTE SSETCAOGNED STTHAIRGDE 06197-035 Figure 56. Multiple Writes to DAC X1 Registers Action BUSY Pulse Width1 Writing data to the system control register, some PMU control Loading Data to System Control 0.27 µs maximum Register, or Readback2 bits (see Table 18), the M register, and the C register do not Loading X1 to 1 PMU DAC Channel 1.65 µs maximum involve the digital calibration engine, thus speeding up Loading X1 to 2 PMU DAC Channels 2.3 µs maximum configuration of the device on power-on. However, care should Loading X1 to 3 PMU DAC Channels 2.95 µs maximum be taken not to issue these commands while BUSY is low, as Loading X1 to 4 PMU DAC Channels 3.6 µs maximum previously described. 1 BUSY pulse width = ((number of channels + 1) × 650 ns) + 350 ns. 2 Refer to Table 18 for details of PMU register effect on BUSY pulse width. Table 18. BUSY Pulse Widths for PMU Register Updates PMU Register Update (See Table 26) Maximum BUSY Low Time per Channel Update One Two Three Four Bit Bit Name Channel Channels Channels Channels 21 CH EN 270 ns 20, 19 FORCE1, FORCE0 (depends on mode change) Transition From Transition To High-Z FOHx current (11) Force current (01) 270 ns High-Z FOHx current (11) Force voltage (00) 1.65 µs 2.3 µs 2.95 µs 3.6 µs High-Z FOHx current (11) High-Z FOHx voltage (10) 1.65 µs 2.3 us 2.95 us 3.6 µs Force current (01) High-Z FOHx current (11) 270 ns Force current (01) High-Z FOHx voltage (10) 1.65 µs 2.3 µs 2.95 µs 3.6 µs Force current (01) Force voltage (00) 1.65 µs 2.3 µs 2.95 µs 3.6 µs High-Z FOHx voltage (10) Force voltage (00) 270 ns High-Z FOHx voltage (10) Force current (01) 1.65 µs 2.3 µs 2.95 µs 3.6 µs High-Z FOHx voltage (10) High-Z FOHx current (11) 1.65 µs 2.3 µs 2.95 µs 3.6 µs Force voltage (00) High-Z FOHx voltage (10) 270 ns Force voltage (00) High-Z FOHx current (11) 1.65 µs 2.3 µs 2.95 µs 3.6 µs Force voltage (00) Force current (01) 1.65 µs 2.3 µs 2.95 µs 3.6 µs 17, 16, 15 C2 to C0; current range selection (any range change) 1.65 µs 2.3 µs 2.95 µs 3.6 µs 14, 13 MEASx (measure mode selection) 270 ns 12 FIN 270 ns 11 SFO 270 ns 10 SS0 270 ns 9 CL 270 ns 8 CPOLH 270 ns 7 Compare V/I 1.65 µs 2.3 µs 2.95 µs 3.6 µs 6 Clear 270 ns Rev. F | Page 43 of 64

AD5522 Data Sheet REGISTER UPDATE RATES Table 19. Mode Bits The value of the X2 register is calculated each time the user writes B23 B22 new data to the corresponding X1 register and for some PMU MODE1 MODE0 Action register updates. The calculation is performed in a three-stage 0 0 Write to the system control register or the PMU register process. The first two stages take approximately 650 ns each, and 0 1 Write to the DAC gain (M) register the third stage takes approximately 350 ns. When the write to the X1 1 0 Write to the DAC offset (C) register register is complete, the calculation process begins. If the write 1 1 Write to the DAC input data (X1) register operation involves the update of a single DAC channel, the user is free to write to another X1 register, provided that the write Readback Control, RD/WR operation does not finish (SYNC returns high) until after the Setting the RD/WR bit (Bit 28) high initiates a readback first-stage calculation is complete, that is, 650 ns after the sequence of the PMU, alarm status, comparator status, system completion of the first write operation. control, or DAC register, as determined by the address bits. CALIBRATION ENGINE TIME PMU Address Bits: PMU3, PMU2, PMU1, PMU0 ~650ns 650ns 650ns 350ns The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each FIRST SECOND THIRD WRITE 1 STAGE STAGE STAGE PMU channel on chip. These bits allow individual control of each PMU channel or any combination of channels, in addition FIRST SECOND THIRD WRITE 2 STAGE STAGE STAGE to multichannel programming. PMU bits also allow access to WRITE 3 SFTIRASGTE SSETCAOGNED STTHAIRGDE 06197-036 wrergiitset erresg, iisnt eardsd situiochn atos rtehaed siynsgt efrmom co anllt rthole rreeggiisstteerrs a (nsede t Thaeb DleA 2C0 ). Figure 57. Multiple Single-Channel Writes Engaging the Calibration Engine NOP (No Operation) REGISTER SELECTION If an NOP (no operation) command is loaded, no change is The serial word assignment consists of 29 bits. Bit 28 to Bit 22 made to the DAC or PMU registers. This code is useful when are common to all registers, whether writing to or reading from performing a readback of a register within the device (via the the device. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address SDO pin) where a change of DAC code or PMU function may each PMU channel (or associated DAC register). When the not be required. PMU3 to PMU0 bits are all 0s, the system control register is Reserved Commands addressed. Any bit combination that is not described in the register address The mode bits, MODE0 and MODE1, address the different sets tables for the PMU, DAC, and system control registers indicates of DAC registers and the PMU register. a reserved command. These commands are unassigned and are reserved for factory use. To ensure correct operation of the device, do not use reserved commands. Rev. F | Page 44 of 64

Data Sheet AD5522 All codes not explicitly referenced in this table are reserved and should not be used (see Table 29). Table 20. Read and Write Functions of the AD5522 B28 B27 B26 B25 B24 B23 B22 B21 to B0 Selected Channel RD/WR PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 Data bits CH3 CH2 CH1 CH0 Write Functions 0 0 0 0 0 0 0 Data bits Write to system control register (see Table 23) 0 0 0 0 0 0 1 Data bits Reserved 0 0 0 0 0 1 0 Data bits Reserved 0 0 0 0 0 1 1 All 1s NOP (no operation) 0 0 0 0 0 1 1 Data bits other than all 1s Reserved Write Addressed DAC or PMU Register 0 0 0 0 1 Select DAC or Address and data bits CH0 0 0 0 1 0 PMU register CH1 (see Table 19) 0 0 0 1 1 CH1 CH0 0 0 1 0 0 CH2 0 0 1 0 1 CH2 CH0 0 0 1 1 0 CH2 CH1 0 0 1 1 1 CH2 CH1 CH0 0 1 0 0 0 CH3 0 1 0 0 1 CH3 CH0 0 1 0 1 0 CH3 CH1 0 1 0 1 1 CH3 CH1 CH0 0 1 1 0 0 CH3 CH2 0 1 1 0 1 CH3 CH2 CH0 0 1 1 1 0 CH3 CH2 CH1 0 1 1 1 1 CH3 CH2 CH1 CH0 Read Functions 1 0 0 0 0 0 0 All 0s Read from system control register 1 0 0 0 0 0 1 All 0s Read from comparator status register 1 0 0 0 0 1 0 X (don’t care) Reserved 1 0 0 0 0 1 1 All 0s Read from alarm status register Read Addressed DAC or PMU Register (Only One PMU or DAC Register Can Be Read at One Time) 1 0 0 0 1 Select PMU or All 0s if reading PMU CH0 1 0 0 1 0 DAC register registers; DAC address CH1 (see Table 19) plus all 0s if reading a 1 0 1 0 0 CH2 DAC register DAC address 1 1 0 0 0 CH3 (see Table 29) Rev. F | Page 45 of 64

AD5522 Data Sheet WRITE SYSTEM CONTROL REGISTER The system control register is accessed when the PMU channel functions in the device. The system control register operates on address bits (PMU3 to PMU0) and the mode bits (MODE1 and a per-device basis. MODE0) are all 0s. This register allows quick setup of various Table 21. System Control Register Bits—Bit B28 to Bit B15 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 RD/WR PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 CL3 CL2 CL1 CL0 CPOLH3 CPOLH2 CPOLH1 Table 22. System Control Register Bits—Bit B14 to Bit B0 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B11 B01 CPOLH0 CPBIASEN DUTGND/CH Guard Clamp INT10K Guard GAIN1 GAIN0 TMP TMP1 TMP0 Latched 0 0 ALM ALM EN enable 1 Bit B1 and Bit B0 are unused data bits. Table 23. System Control Register Functions Bit Bit Name Description 28 (MSB) RD/WR When low, a write function takes place to the selected register; setting the RD/WR bit high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. 27 PMU3 Set Bit PMU3 to Bit PMU0 to 0 to address the system control register. 26 PMU2 25 PMU1 24 PMU0 23 MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register. 22 MODE0 System Control Register-Specific Bits 21 CL3 Current or voltage clamp enable. Bit CL3 to Bit CL0 enable and disable the current or voltage clamp function per 20 CL2 channel (0 = disable; 1 = enable). The clamp enable function is also available in the PMU register on a per- channel basis. This dual functionality allows flexible enabling or disabling of this function. When reading back 19 CL1 information about the status of the clamp enable function, the data that was most recently written to the clamp 18 CL0 register is available in the readback word from either the PMU register or the system control register. 17 CPOLH3 Comparator output enable. By default, the comparator outputs are high-Z on power-on. A 1 in each bit position 16 CPOLH2 enables the comparator output for the selected channel. Bit 13 (CPBIASEN) must be enabled to power on the comparator functions. The comparator enable function is also available in the PMU register on a per-channel 15 CPOLH1 basis. This dual functionality allows flexible enabling or disabling of this function. When reading back information 14 CPOLH0 about the status of the comparator enable function, the data that was most recently written to the comparator status register is available in the readback word from either the PMU register or the system control register. 13 CPBIASEN Comparator enable. By default, the comparators are powered down when the device is powered on. To enable the comparator function for all channels, write a 1 to this bit. A 0 disables the comparators and shuts them down. The comparator output enable bits (CPOLHx, Bit 17 to Bit 14) allow the user to turn on each comparator output individually, enabling busing of comparator outputs. 12 DUTGND/CH DUTGND per channel enable. The GUARDINx/DUTGNDx pins are shared pins that can be configured to enable a DUTGND per PMU channel or a guard input per PMU channel. Setting this bit to 1 enables DUTGND per channel. In this mode, the pin functions as a DUTGND pin on a per-channel basis. The guard inputs are disconnected from this pin and instead are connected directly to the MEASVHx line by an internal connection. The default power-on condition is GUARDINx. 11 GUARD ALM Clamp and guard alarm functions share one open-drain alarm pin (CGALM). By default, the CGALM pin is 10 CLAMP ALM disabled. The guard ALM and clamp ALM bits allow the user to choose whether clamp alarm information, guard alarm information, or both sets of alarm information are flagged by the CGALM pin. Set high to enable either alarm function. 9 INT10K Internal sense short. Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ (4 kΩ + 2 kΩ switch + 4 kΩ) between the FOHx and the MEASVHx lines (SW7 is closed). Setting this bit high also closes SW15, allowing the user to connect another 10 kΩ resistor between DUTGNDx and AGND. 8 Guard EN Guard enable. The guard amplifier is disabled on power-on; to enable the guard amplifier, set this bit to 1. If the guard function is not in use, disabling it saves power (typically 400 μA per channel). Rev. F | Page 46 of 64

Data Sheet AD5522 Bit Bit Name Description 7 GAIN1 MEASOUTx output range. The MEASOUTx range defaults to the force voltage span for voltage and current 6 GAIN0 measurements, which includes some overrange to allow for offset correction. The nominal output voltage range is ±11.25 V with the default offset DAC setting, but changes for other offset DAC settings when GAIN1 = 0. Therefore, the MEASOUTx range can be an asymmetrical bipolar voltage range. GAIN1 = 1 enables a unipolar output voltage range, which allows the use of asymmetrical supplies or a smaller input range ADC. See Table 10 and Table 11 for more details. Measure Output Voltage Range for VREF = 5 V, Offset DAC = 0xA492 MEASOUT Current Function Gain GAIN1 = 0, MEASOUT Gain = 1 GAIN1 = 1, MEASOUT Gain = 0.2 MV 5 or 10 ±V (up to ±11.25 V) 0 V to 4.5 V DUT MI (GAIN0 = 0) 10 ±I × R × 10 + VMID (up to ±11.25 V) 0 V to 4.5 V DUT RSENSE MI (GAIN0 = 1) 5 ±I × R × 5 + VMID (up to ±5.625 V) 0 V to 2.25 V DUT RSENSE 5 TMP ENABLE Thermal shutdown feature. To disable the thermal shutdown feature, set the TMP ENABLE bit to 0 (thermal shutdown is enabled by default). 4 TMP1 The TMP1 and TMP0 bits allow the user to program the temperature that triggers thermal shutdown. 3 TMP0 TMP ENABLE TMP1 TMP0 Action 0 X X Thermal shutdown disabled. 1 X X Thermal shutdown enabled. 1 0 0 Shutdown at junction temperature of 130°C (power-on default). 1 0 1 Shutdown at junction temperature of 120°C. 1 1 0 Shutdown at junction temperature of 110°C. 1 1 1 Shutdown at junction temperature of 100°C. 2 Latched Configure the open-drain pin (CGALM) as a latched or unlatched output pin. When high, this bit configures the CGALM alarm output as a latched output, allowing it to drive a controller I/O without needing to poll the line constantly. The power-on default for this pin is unlatched. 1 0 Unused bits. Set to 0. 0 (LSB) 0 Rev. F | Page 47 of 64

AD5522 Data Sheet WRITE PMU REGISTER To address PMU functions, set the MODE1 and MODE0 bits combination of PMU channels, or all PMU channels. This to 0. This setting selects the PMU register (see Table 19 and functionality enables multipin broadcasting to similar pins on a Table 20). The AD5522 has very flexible addressing, which DUT. Bit 27 to Bit 24 select the PMU or group of PMUs that is allows writing of data to a single PMU channel, any addressed. Table 24. PMU Register Bits—Bit B28 to Bit B15 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B181 B17 B16 B15 RD/WR PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 CH EN FORCE1 FORCE0 0 C2 C1 C0 1 Bit B18 is reserved. Table 25. PMU Register Bits—Bit B14 to Bit B0 B14 B13 B12 B11 B10 B9 B8 B7 B6 B51 B41 B31 B21 B11 B01 MEAS1 MEAS0 FIN SF0 SS0 CL CPOLH Compare V/I Clear 0 0 0 0 0 0 1 Bit B5 to Bit B0 are unused data bits. Table 26. PMU Register Functions Bit Bit Name Description 28 (MSB) RD/WR When low, a write to the selected register takes place; setting the RD/WR bit high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. 27 PMU3 Bit PMU3 to Bit PMU0 address each PMU channel in the device. These bits allow control of an individual PMU 26 PMU2 channel or any combination of channels, in addition to multichannel programming (see Table 20). 25 PMU1 24 PMU0 23 MODE1 Set the MODE1 and MODE0 bits to 0 to access the PMU register selected by the PMU3 to PMU0 bits (Bit 27 to 22 MODE0 Bit 24). PMU Register-Specific Bits 21 CH EN Channel enable. Set high to enable the selected channel or group of channels; set low to disable the selected channel or channels. When disabled, SW2 is closed and SW5 is open (outputs are high-Z). The measure mode is determined by the MEAS1 and MEAS0 bits at all times and is not affected by the CH EN bit. The guard amplifier and the comparators are not affected by this bit. 20 FORCE1 The FORCE1 and FORCE0 bits set the force function for each PMU channel (in association with the PMUx bits). 19 FORCE0 All combinations of forcing and measuring (using the MEAS1 and MEAS0 bits) are available. The high-Z (voltage and current) modes allow the user to optimize glitch response during mode changes. While in high-Z voltage or current mode, with the PMU high-Z, new X1 codes loaded to the FIN DAC register and to the clamp DAC register are calibrated, stored in the X2 register, and loaded directly to the DAC outputs. FORCE1 FORCE0 Action 0 0 FV and current clamp (if clamp is enabled). 0 1 FI and voltage clamp (if clamp is enabled). 1 0 High-Z FOHx voltage (preload FIN DAC and clamp DAC). 1 1 High-Z FOHx current (preload FIN DAC and clamp DAC). 18 Reserved 0 17 C2 Bit C2 to Bit C0 specify the required current range. High-Z FV/FI commands ignore the current range address 16 C1 bits (C2, C1, and C0); therefore, these bit combinations cannot be used to enable or disable the force function for a PMU channel. 15 C0 C2 C1 C0 Selected Current Range 0 0 0 ±5 µA current range. 0 0 1 ±20 µA current range. 0 1 0 ±200 µA current range. 0 1 1 ±2 mA current range (default). 1 0 0 ±external current range. 1 0 1 Disable the always on mode for the external current range buffer1. 1 1 0 Enable the always on mode for the external current range buffer2. 1 1 1 Reserved. Rev. F | Page 48 of 64

Data Sheet AD5522 Bit Bit Name Description 14 MEAS1 The MEAS1 and MEAS0 bits specify the required measure mode, allowing the MEASOUTx line to be disabled, 13 MEAS0 connected to the temperature sensor, or enabled for measurement of current or voltage. MEAS1 MEAS0 Action 0 0 MEASOUTx is connected to I SENSE 0 1 MEASOUTx is connected to V SENSE 1 0 MEASOUTx is connected to the temperature sensor 1 1 MEASOUTx is high-Z (SW12 open) 12 FIN This bit sets the status of the force input (FIN) amplifier. 0 = input of the force amplifier switched to GND. 1 = input of the force amplifier connected to the FIN DAC output. 11 SF0 The SF0 and SS0 bits specify the switching of system force and sense lines to the force and sense paths at the 10 SS0 DUT. The channel to which the system force and system sense lines are connected is set by the PMU3 to PMU0 bits. For correct operation, only one PMU channel should be connected to the SYS_FORCE and SYS_SENSE paths at any one time. SF0 SS0 Action 0 0 SYS_FORCE and SYS_SENSE are high-Z for the selected channel 0 1 SYS_FORCE is high-Z and SYS_SENSE is connected to MEASVHx for the selected channels 1 0 SYS_FORCE is connected to FOHx and SYS_SENSE is high-Z for the selected channel 1 1 SYS_FORCE is connected to FOHx and SYS_SENSE is connected to MEASVHx for the selected channel 9 CL Per-PMU current or voltage clamp enable bit. A logic high enables the clamp function for the selected PMU. The clamp enable function is also available in the system control register. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the clamp enable function on a per-channel basis, the data that was most recently written to the clamp register is available in the readback word from either the PMU register or the system control register. 8 CPOLH Comparator output enable bit. By default, the comparator outputs are high-Z on power-on. A logic high enables the comparator output for the selected PMU. The comparator function CPBIASEN (Bit 13 in the system control register), must be enabled. The comparator output enable function is also available in the system control register. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the comparator enable function, the data that was most recently written to the comparator status register is available in the readback word from either the PMU register or the system control register. 7 Compare A logic high selects the compare voltage function; a logic low selects the compare current function. V/I 6 Clear To clear or reset a latched alarm bit and pin (temperature, guard, or clamp), write a 1 to this bit. This bit applies to latched alarm conditions (clamp and guard) on all four PMU channels. 5 Unused Unused bits. Set to 0. 4 3 2 1 0 (LSB) 1 Writing 101 in Bit 17 to Bit 15 disables the always on mode for the external current range buffer. Use with FV mode (FORCE1 = FORCE0 = 0) only. To complete the disabling of the always on mode, the PMU channel is placed into high-Z mode and the external current range buffer is returned to its default operation (off). 2 Writing 110 in Bit 17 to Bit 15 places the external current range buffer into always on mode. In this mode, the buffer is always active with no regard to the selected current range. The always on mode is intended for use where an external high current stage is being used for a current drive in excess of ±80 mA; having the internal stage always on should help to eliminate timing concerns when transitioning between this current range and other ranges. When first enabling the always on mode, use it in conjunction with FV mode (FORCE1 = FORCE0 = 0); the device now enables the external current range buffer. The 110 code also places the device into high-Z mode (necessary to complete the enabling function). To return to an FV or FI operating mode, select the appropriate mode and current range. The external range sense resistor is connected to an MI circuit only when the external current range address is selected (C2 to C0 are set to 100). The default operation at power-on is disabled (or off). Rev. F | Page 49 of 64

AD5522 Data Sheet WRITE DAC REGISTER The DAC input, gain, and offset registers are addressed through chip. Bit D15 to Bit D0 are the DAC data bits used when writing a combination of PMU bits (Bit 27 to Bit 24) and mode bits to these registers. The PMU address bits allow addressing of a (Bit 23 and Bit 22). Bit A5 to Bit A0 address each DAC level on particular DAC for any combination of PMU channels. Table 27. DAC Register Bits B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 to B0 RD/WR PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 A5 A4 A3 A2 A1 A0 Data Bits[D15 (MSB):D0 (LSB)] Table 28. DAC Register Functions Bit Bit Name Description 28 (MSB) RD/WR When this bit is low, a write function takes place to the selected register; setting the RD/WR bit high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. 27 PMU3 Bit PMU3 to Bit PMU0 address each PMU and DAC channel in the device. These bits allow control of each 26 PMU2 individual DAC channel or any combination of channels, in addition to multichannel programming. 25 PMU1 24 PMU0 23 MODE1 The MODE1 and MODE0 bits allow addressing of the DAC gain (M), offset (C), or input (X1) register. 22 MODE0 MODE1 MODE0 Action 0 0 Write to the system control register or the PMU register 0 1 Write to the DAC gain (M) register 1 0 Write to the DAC offset (C) register 1 1 Write to the DAC input data (X1) register DAC Register-Specific Bits 21 A5 DAC address bits. The A5 to A3 bits select the register set that is addressed. See the DAC Addressing section. 20 A4 19 A3 18 A2 DAC address bits. The A2 to A0 bits select the DAC that is addressed. See the DAC Addressing section. 17 A1 16 A0 15 to 0 D15 (MSB) to 16 DAC data bits for X1 and C registers. M register is 15 bits wide, D15 to D1. D0 (LSB) Rev. F | Page 50 of 64

Data Sheet AD5522 DAC Addressing The same address table is also used for readback of a particular DAC address. For the FIN and comparator (CPH and CPL) DACs, there is a set of X1, M, and C registers for each current range, and one set Note that CLL is clamp level low and CLH is clamp level high. for the voltage range; for the clamp DACs (CLL and CLH), • When forcing a voltage, the current clamps are engaged; there are only two sets of X1, M, and C registers. therefore, both the CLL current ranges register set and the When calibrating the device, the M and C registers allow volatile CLH current ranges register set are loaded to the clamp storage of gain and offset coefficients. Calculation of the corres- DACs. ponding DAC X2 register occurs only when the X1 data is loaded • When forcing a current, the voltage clamps are engaged; (no internal calculation occurs on M or C updates). therefore, both the CLL voltage range register set and the There is one offset DAC for all four channels in the device that CLH voltage range register set are loaded to the clamp is addressed using the PMUx bits. The offset DAC has only an DACs. input register associated with it; no M or C registers are asso- All codes not explicitly referenced Table 29 are reserved and ciated with this DAC. When writing to the offset DAC, set the should not be used. MODE1 and MODE0 bits high to address the DAC input register (X1). Table 29. DAC Register Addressing A5 A4 A3 A2 A1 A0 MODE1 MODE0 Register Set Addressed Register 0 0 0 0 0 0 1 1 N/A Offset DAC X 0 0 1 0 0 0 0 1 ±5 µA current range FIN M 1 0 FIN C 1 1 FIN X1 0 0 1 0 0 1 0 1 ±20 µA current range FIN M 1 0 FIN C 1 1 FIN X1 0 0 1 0 1 0 0 1 ±200 µA current range FIN M 1 0 FIN C 1 1 FIN X1 0 0 1 0 1 1 0 1 ±2 mA current range FIN M 1 0 FIN C 1 1 FIN X1 0 0 1 1 0 0 0 1 ±external current range FIN M 1 0 FIN C 1 1 FIN X1 0 0 1 1 0 1 0 1 Voltage range FIN M 1 0 FIN C 1 1 FIN X1 0 1 0 1 0 0 0 1 Current ranges CLL M 1 0 CLL C 1 1 CLL X11 0 1 0 1 0 1 0 1 Voltage range CLL M 1 0 CLL C 1 1 CLL X1 0 1 1 1 0 0 0 1 Current ranges CLH M 1 0 CLH C 1 1 CLH X12 0 1 1 1 0 1 0 1 Voltage range CLH M 1 0 CLH C 1 1 CLH X1 1 0 0 0 0 0 0 1 ±5 µA current range CPL M 1 0 CPL C 1 1 CPL X1 Rev. F | Page 51 of 64

AD5522 Data Sheet A5 A4 A3 A2 A1 A0 MODE1 MODE0 Register Set Addressed Register 1 0 0 0 0 1 0 1 ±20 µA current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 0 1 0 0 1 ±200 µA current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 0 1 1 0 1 ±2 mA current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 1 0 0 0 1 ±external current range CPL M 1 0 CPL C 1 1 CPL X1 1 0 0 1 0 1 0 1 Voltage range CPL M 1 0 CPL C 1 1 CPL X1 1 0 1 0 0 0 0 1 ±5 µA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 0 0 1 0 1 ±20 µA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 0 1 0 0 1 ±200 µA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 0 1 1 0 1 ±2 mA current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 1 0 0 0 1 ±external current range CPH M 1 0 CPH C 1 1 CPH X1 1 0 1 1 0 1 0 1 Voltage range CPH M 1 0 CPH C 1 1 CPH X1 1 CLL should be within the range of 0x0000 to 0x7FFF. 2 CLH should be within the range of 0x8000 to 0xFFFF. Rev. F | Page 52 of 64

Data Sheet AD5522 READ REGISTERS A minimum of 24 clock rising edges is required to shift the readback data out of the shift register. If writing a 24-bit word to Readback of all the registers in the device is possible via the SPI shift data out of the device, the user must ensure that the 24-bit and the LVDS interfaces. To read data from a register, it is first write is effectively an NOP (no operation) command. The last necessary to write a readback command to tell the device which five bits in the shift register are always 00000: these five bits register is required for readback. See Table 30 to address the become the MSBs of the shift register when the 24-bit write is appropriate channel. loaded. To ensure that the device receives an NOP command as When the required channel is addressed, the device loads the described in Table 20, the recommended flush command is 24-bit readback data into the MSB positions of the 29-bit serial 0xFFFFFF; thus, no change is made to any register in the device. shift register (the five LSBs are filled with 0s). SCLK rising edges Readback data can also be shifted out by writing another 29-bit clock this readback data out on SDO (framed by the SYNC write or read command. If writing a 29-bit command, the read- signal). back data is MSB data available on SDO, followed by 00000. Table 30. Read Functions of the AD5522 B28 B27 B26 B25 B24 B23 B22 B21 to B0 Selected Channel RD/WR PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 Data bits CH3 CH2 CH1 CH0 Read Functions 1 0 0 0 0 0 0 All 0s Read from system control register 1 0 0 0 0 0 1 All 0s Read from comparator status register 1 0 0 0 0 1 0 X (don’t care) Reserved 1 0 0 0 0 1 1 All 0s Read from alarm status register Read Addressed PMU Register (Only One PMU Register Can Be Read at One Time) 1 0 0 0 1 0 0 All 0s CH0 1 0 0 1 0 0 0 CH1 1 0 1 0 0 0 0 CH2 1 1 0 0 0 0 0 CH3 Read Addressed DAC M Register (Only One DAC Register Can Be Read at One Time) 1 0 0 0 1 0 1 DAC address CH0 1 0 0 1 0 0 1 (see Table 29) CH1 1 0 1 0 0 0 1 CH2 1 1 0 0 0 0 1 CH3 Read Addressed DAC C Register (Only One DAC Register Can Be Read at One Time) 1 0 0 0 1 1 0 DAC address CH0 1 0 0 1 0 1 0 (see Table 29) CH1 1 0 1 0 0 1 0 CH2 1 1 0 0 0 1 0 CH3 Read Addressed DAC X1 Register (Only One DAC Register Can Be Read at One Time) 1 0 0 0 1 1 1 DAC address CH0 1 0 0 1 0 1 1 (see Table 29) CH1 1 0 1 0 0 1 1 CH2 1 1 0 0 0 1 1 CH3 Rev. F | Page 53 of 64

AD5522 Data Sheet READBACK OF SYSTEM CONTROL REGISTER The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 31. Table 31. System Control Register Readback Bit Bit Name Description 23 (MSB) MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register. 22 MODE0 System Control Register-Specific Readback Bits 21 CL3 Read back the status of the individual current clamp enable bits. 20 CL2 0 = clamp is disabled. 1 = clamp is enabled. 19 CL1 When reading back information about the status of the clamp enable function, the data that was most 18 CL0 recently written to the current clamp register from either the system control register or the PMU register is available in the readback word. 17 CPOLH3 Read back information about the status of the comparator output enable bits. 16 CPOLH2 1 = PMU comparator output is enabled. 0 = PMU comparator output is disabled. 15 CPOLH1 When reading back information about the status of the comparator output enable function, the data 14 CPOLH0 that was most recently written to the comparator status register from either the system control register or the PMU register is available in the readback word. 13 CPBIASEN This readback bit indicates the status of the comparator enable function. 1 = comparator function is enabled. 0 = comparator function is disabled. 12 DUTGND/CH DUTGND per channel enable. 1 = DUTGND per channel is enabled. 0 = individual guard inputs are available per channel. 11 GUARD ALM These bits provide information about which of these alarm bits trigger the CGALM pin. 10 CLAMP ALM 1 = guard/clamp alarm is enabled. 0 = guard/clamp alarm is disabled. 9 INT10K If this bit is high, the internal 10 kΩ resistor (SW7) is connected between FOHx and MEASVHx, and between DUTGND and AGND. If this bit is low, SW7 is open. 8 Guard EN Read back the status of the guard amplifiers. If this bit is high, the amplifiers are enabled. 7 GAIN1 Status of the selected MEASOUTx output range. See Table 10 and Table 11. 6 GAIN0 5 TMP ENABLE Read back the status of the thermal shutdown function. 4 TMP1 Bits[5:3] Action 3 TMP0 0XX Thermal shutdown disabled. 100 Thermal shutdown enabled at junction temperature of 130°C (power-on default). 101 Thermal shutdown enabled at junction temperature of 120°C. 110 Thermal shutdown enabled at junction temperature of 110°C. 111 Thermal shutdown enabled at junction temperature of 100°C. 1XX Thermal shutdown enabled. 2 Latched This bit indicates the status of the open-drain alarm outputs, TMPALM and CGALM. 1 = open-drain alarm outputs are latched. 0 = open-drain alarm outputs are unlatched. 1 Unused Loads with 0s. 0 (LSB) readback bits Rev. F | Page 54 of 64

Data Sheet AD5522 READBACK OF PMU REGISTER The PMU register readback function is a 24-bit word that includes the mode and PMU data bits. Only one PMU register can be read back at any one time. Table 32. PMU Register Readback Bit Bit Name Description 23 (MSB) MODE1 Set the MODE1 and MODE0 bits to 0 to access the selected PMU register. 22 MODE0 PMU Register-Specific Bits 21 CH EN Channel enable. If this bit is high, the selected channel is enabled; if this bit is low, the channel is disabled. 20 FORCE1 These bits indicate which force mode the selected channel is in. 19 FORCE0 00 = FV and current clamp (if clamp is enabled). 01 = FI and voltage clamp (if clamp is enabled). 10 = high-Z FOHx voltage. 11 = high-Z FOHx current. 18 Reserved 0. 17 C2 These three bits indicate which forced or measured current range is set for the selected channel (see 16 C1 Table 26). 15 C0 14 MEAS1 These bits indicate which measure mode is selected: voltage, current, temperature sensor, or high-Z. 13 MEAS0 00 = MEASOUTx is connected to ISENSE. 01 = MEASOUTx is connected to V . SENSE 10 = MEASOUTx is connected to the temperature sensor. 11 = MEASOUTx is high-Z (SW12 open). 12 FIN This bit shows the status of the force input (FIN) amplifier. 0 = input of the force amplifier switched to GND. 1 = input of the force amplifier connected to the FIN DAC output. 11 SF0 The system force and sense lines can be connected to any of the four PMU channels. These bits indicate 10 SS0 whether the system force and sense lines are switched in (see Table 26). 9 CL Read back the status of the individual current clamp enable bits. 1 = clamp is enabled on this channel. 0 = clamp is disabled on this channel. When reading back information about the status of the current clamp enable function, the data that was most recently written to the current clamp register from either the system control register or the PMU register is available in the readback word. 8 CPOLH Read back the status of the comparator output enable bit. 1 = PMU comparator output is enabled. 0 = PMU comparator output is disabled. When reading back information about the status of the comparator output enable function, the data that was most recently written to the comparator register from either the system control register or the PMU register is available in the readback word. 7 Compare V/I 1 = compare voltage function is enabled on the selected channel. 0 = compare current function is enabled on the selected channel. 6 LTMPALM TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event exceeding 5 TMPALM the default or user programmed level. The temperature alarm is a per-device alarm; the latched (LTMPALM) and unlatched (TMPALM) bits indicate whether a temperature event occurred and whether the alarm still exists (that is, whether the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6) in the PMU register. 4 to 0 (LSB) Unused Loads with 0s. readback bits Rev. F | Page 55 of 64

AD5522 Data Sheet READBACK OF COMPARATOR STATUS REGISTER READBACK OF ALARM STATUS REGISTER The comparator status register is a read-only register that The alarm status register is a read-only register that provides provides access to the output status of each comparator pin on information about temperature, clamp, and guard alarm events the chip. Table 33 shows the format of the comparator register (see Table 34). Temperature alarm status is also available in any readback word. of the four PMU readback registers. Table 33. Comparator Status Register (Read-Only) Bit Bit Name Description 23 (MSB) MODE1 0 22 MODE0 1 Comparator Status Register-Specific Bits 21 CPOL0 Comparator output conditions per channel corresponding to the comparator output pins. 20 CPOH0 1 = PMU comparator output is high. 19 CPOL1 0 = PMU comparator output is low. 18 CPOH1 17 CPOL2 16 CPOH2 15 CPOL3 14 CPOH3 13 to 0 (LSB) Unused Loads with zeros. readback bits Table 34. Alarm Status Register Readback Bit Bit Name Description 23 MODE1 1 (MSB) 22 MODE0 1 Alarm Status Register-Specific Bits 21 LTMPALM TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event exceeding the default 20 TMPALM or user programmed level. The temperature alarm is a per-device alarm; the latched (LTMPALM) and unlatched (TMPALM) bits indicate whether a temperature event occurred and whether the alarm still exists (that is, whether the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6) in the PMU register. 19 LG0 LGx is the per-channel latched guard alarm bit, and Gx is the unlatched guard alarm bit. These bits indicate which 18 G0 channel flagged the alarm on the open-drain alarm pin, CGALM, and whether the alarm condition still exists. 17 LG1 16 G1 15 LG2 14 G2 13 LG3 12 G3 11 LC0 LCx is the per-channel latched clamp alarm bit, and Cx is the unlatched clamp alarm bit. These bits indicate which 10 C0 channel flagged the alarm on the open-drain alarm pin CGALM and whether the alarm condition still exists. 9 LC1 8 C1 7 LC2 6 C2 5 LC3 4 C3 3 to 0 Unused Loads with 0s. (LSB) readback bits Rev. F | Page 56 of 64

Data Sheet AD5522 READBACK OF DAC REGISTER The DAC register readback function is a 24-bit word that includes the mode, address, and DAC data bits. Table 35. DAC Register Readback Bit Bit Name Description 23 (MSB) MODE1 The MODE1 and MODE0 bits indicate the type of DAC register (X1, M, or C) that is read. 22 MODE0 01 = DAC gain (M) register. 10 = DAC offset (C) register. 11 = DAC input data (X1) register. DAC Register-Specific Bits 21 to 16 A5 to A0 Address bits indicating the DAC register that is read (see Table 29). 15 to 0 (LSB) D15 to D0 Contents of the addressed DAC register (X1, M, or C). Rev. F | Page 57 of 64

AD5522 Data Sheet APPLICATIONS INFORMATION POWER-ON DEFAULT Table 37. Power-On Default for System Control Register The power-on default for all DAC channels is that the contents Bit Bit Name Default Value of each M register are set to full scale (0xFFFF), and the contents 21 (MSB) CL3 0 of each C register are set to midscale (0x8000). The contents of 20 CL2 0 the DAC X1 registers at power-on are listed in Table 36. 19 CL1 0 The power-on default for the alarm status register is 0xFFFFF0, 18 CL0 0 and the power-on default for the comparator status register is 17 CPOLH3 0 0x400000. The power-on default values of the PMU register and 16 CPOLH2 0 the system control register are shown in Table 37 and Table 38. 15 CPOLH1 0 SETTING UP THE DEVICE ON POWER-ON 14 CPOLH0 0 13 CPBIASEN 0 On power-on, default conditions are recalled from the power- 12 DUTGND/CH 0 on reset register to ensure that each PMU and DAC channel is 11 Guard ALM 0 powered up in a known condition. To operate the device, the 10 Clamp ALM 0 user must follow these steps: 9 INT10K 0 1. Configure the device by writing to the system control 8 Guard EN 0 register to set up different functions as required. 7 GAIN1 0 2. Calibrate the device to trim out errors, and load the 6 GAIN0 0 required calibration values to the gain (M) and offset (C) 5 TMP enable 1 registers. Load codes to each DAC input (X1) register. 4 TMP1 0 When X1 values are loaded to the individual DACs, the 3 TMP0 0 calibration engine calculates the appropriate X2 value and 2 Latched 0 stores it, ready for the PMU address to call it. 1 Unused data bit 0 3. Load the required PMU channel with the required force 0 (LSB) Unused data bit 0 mode, current range, and so on. Loading the PMU channel configures the switches around the force amplifier, Table 38. Power-On Default for PMU Register measure function, clamps, and comparators, and also acts Bit Bit Name Default Value as a load signal for the DACs, loading the DAC register 21 (MSB) CH EN 0 with the appropriate stored X2 value. 20 FORCE1 0 4. Because the voltage and current ranges have individual 19 FORCE0 0 DAC registers associated with them, each PMU register 18 Reserved 0 mode of operation calls a particular X2 register. Therefore, 17 C2 0 only updates (that is, changes to the X1 register) to DACs 16 C1 1 associated with the selected mode of operation are reflected 15 C0 1 in the output of the PMU. If there is a change to the X1 14 MEAS1 1 value associated with a different PMU mode of operation, 13 MEAS0 1 this X1 value and its M and C coefficients are used to 12 FIN 0 calculate a corresponding X2 value, which is stored in the 11 SF0 0 correct X2 register, but this value is not loaded to the DAC. 10 SS0 0 9 CL 0 Table 36. Default Contents of DAC Registers at Power-On 8 CPOLH 0 DAC Register Default Value 7 Compare V/I 0 Offset DAC 0xA492 6 LTMPALM 1 FIN DAC 0x8000 5 TMPALM 1 CLL DAC 0x0000 4 Unused data bit 0 CLH DAC 0xFFFF 3 Unused data bit 0 CPL DAC 0x0000 2 Unused data bit 0 CPH DAC 0xFFFF 1 Unused data bit 0 0 (LSB) Unused data bit 0 Rev. F | Page 58 of 64

Data Sheet AD5522 CHANGING MODES 3. When the high-Z (voltage or current) mode is used, the relevant DAC outputs are automatically updated (FIN, There are different ways of handling a mode change. CLL, and CLH DACs). For example, in high-Z voltage 1. Load any DAC X1 values that require changes. Remember mode, when new X1 writes occur, the FIN voltage X2 result that for force amplifier and comparator DACs, X1 registers is calculated, cached, and loaded to the FIN DAC. When are available per voltage and current range, so the user can forcing a voltage, current clamps are engaged, so the CLL preload new DAC values to make DAC updates ahead of current register can be loaded, and the gain and offset time; the calibration engine calculates the X2 values and corrected and loaded to the DAC register. (The CLH stores them. current register works the same way.) 2. Change to the new PMU mode (FI or FV). This action 4. Change to the new PMU mode (FI or FV). This action loads the new switch conditions to the PMU circuitry and loads the new switch conditions to the PMU circuitry. loads the DAC register with the stored X2 data. Because the DAC outputs are already loaded, transients are The following steps describe another method for changing modes: minimized when changing current or voltage mode. 1. In the PMU register (Bit 20 and Bit 19), enable the high-Z REQUIRED EXTERNAL COMPONENTS voltage or high-Z current mode to make the amplifier high The minimum required external components for use with the impedance (SW5 open). AD5522 are shown in Figure 58. Decoupling is greatly dependent 2. Load any DAC X1 values that require changes. Remember on the type of supplies used, other decoupling on the board, that for force amplifier and comparator DACs, X1 registers and the noise in the system. It is possible that more or less are available per voltage and current range, so the user can decoupling may be required. preload new DAC values to make DAC updates ahead of time; the calibration engine calculates the X2 values and stores them. AVSS AVDD DVCC 10µF 10µF 10µF 0.1µF 0.1µF 0.1µF REF 0.1µF AVSS AVDD DVCC VREF CCOMP[0:3] EXTFOH0 EXTFOH3 CFF0 CFF3 FOH0 FOH3 MEASVH0 MEASVH3 EXTMEASIH0 EXTMEASIH3 RSENSE RSENSE (UP TO (UP TO ±80mA) ±80mA) EXTMEASIL0 EXTMEASIL3 DUT DUT EXTFOH1 EXTFOH2 CFF1 CFF2 FOH1 FOH2 MEASVH1 MEASVH2 EXTMEASIH1 EXTMEASIH2 RSENSE RSENSE (UP TO (UP TO ±80mA) ±80mA) EXTMEASIL1 EXTMEASIL2 DUTGND DUT DUT 06197-037 Figure 58. External Components Required for Use with the AD5522 Rev. F | Page 59 of 64

AD5522 Data Sheet Table 39. ADCs and ADC Drivers Suggested For Use with AD55221 Sample Part No. Resolution Rate Ch. No. AIN Range Interface ADC Driver Multiplexer2 Package AD7685 16 250 kSPS 1 0 V to VREF Serial, SPI ADA4841-1, ADG704, ADG708 MSOP, ADA4841-2 LFCSP AD7686 16 500 kSPS 1 0 V to VREF Serial, SPI ADA4841-1, ADG704, ADG708 MSOP, ADA4841-2 LFCSP AD76933 16 500 kSPS 1 −VREF to +VREF Serial, SPI ADA4841-1, ADG1404, ADG1408, MSOP, ADA4841-2, ADG1204 LFCSP ADA4941-1 AD7610 16 250 kSPS 1 Bipolar 10 V, Bipolar Serial/Parallel AD8021 ADG1404, ADG1408, LFCSP, 5 V, Unipolar 10 V, ADG1204 LQFP Unipolar 5 V AD7655 16 1 MSPS 4 0 V to 5 V Serial/Parallel ADA4841-1, ADA4841-2, AD8021 1 Subset of the possible ADCs suitable for use with the AD5522. Visit www.analog.com for more options. 2 For purposes of sharing an ADC among multiple PMU channels. Note that the multiplexer is not absolutely necessary because the AD5522 MEASOUTx path has a tri- state mode per channel. 3 Do not allow the MEASOUTx output range to exceed the analog input (AIN) range of the ADC. POWER SUPPLY DECOUPLING shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the refer- Careful consideration of the power supply and ground return ence inputs. It is essential to minimize noise on all VREF lines. layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5522 is mounted Avoid crossover of digital and analog signals. Traces on opposite so that the analog and digital sections are separated and sides of the board should run at right angles to each other to confined to certain areas of the board. If the AD5522 is in a reduce the effects of feedthrough through the board. As is the system where multiple devices require an AGND-to-DGND case for all thin packages, care must be taken to avoid flexing connection, the connection should be made at one point only. the package and to avoid a point load on the surface of this Establish the star ground point as close as possible to the device. package during the assembly process. For supplies with multiple pins (AVSS and AVDD), it is Also, note that the exposed paddle of the AD5522 is connected recommended that these pins be tied together and that each to the negative supply, AVSS. supply be decoupled only once. POWER SUPPLY SEQUENCING The AD5522 should have ample supply decoupling of 10 μF in When the supplies are connected to the AD5522, it is important parallel with 0.1 μF on each supply located as close to the that the AGND and DGND pins be connected to the relevant package as possible, ideally right up against the device. The ground planes before the positive or negative supplies are applied. 10 μF capacitors are the tantalum bead type. The 0.1 μF capac- This is the only power sequencing requirement for this device. itors should have low effective series resistance (ESR) and low TYPICAL APPLICATION FOR THE AD5522 effective series inductance (ESL)—typical of the common ceramic types that provide a low impedance path to ground at Figure 59 shows the AD5522 used in an ATE system. The device high frequencies—to handle transient currents due to internal can be used as a per-pin parametric unit to speed up the rate at logic switching. which testing can be done. Avoid running digital lines under the device because they can The central PMU (shown in the block diagram) is usually a couple noise onto the device. However, allow the analog ground highly accurate PMU and is shared among a number of pins in plane to run under the AD5522 to avoid noise coupling (applies the tester. In general, many discrete levels are required in an only to the package with paddle up). The power supply lines of ATE system for the pin drivers, comparators, clamps, and active the AD5522 should use as large a trace as possible to provide loads. DAC devices such as the AD537x family offer a highly low impedance paths and reduce the effects of glitches on the integrated solution for a number of these levels. power supply line. Fast switching digital signals should be Rev. F | Page 60 of 64

Data Sheet AD5522 DRIVEN SHIELD DAC CENTRAL GUARDAMP AD5522 PMU ADC DAC DAC VCH DAC PMU PMU DAC DAC VTERM ADC DAC PMU PMU TIMING DATA MEMORY DAC VH DUT 50Ω TIMING RELAYS COAX GENERATOR FORMATTER DRIVER DLL, LOGIC DESKEW VL DAC DAC VCL GND SENSE DAC VTH COMPARE FORMATTER COMP MEMORY DESKEW VTL DAC GUARD DAC ADC AMP ACTIVE LOAD AD5560 IOL DEVICE POWER DAC SUPPLY VCOM DAC DAC IOH 06197-038 Figure 59. Typical Applications Circuit Using the AD5522 as a Per-Pin Parametric Unit Rev. F | Page 61 of 64

AD5522 Data Sheet OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 12.20 0.75 1.20 12.00 SQ 0.60 MAX 11.80 0.45 80 61 61 80 1 60 60 1 PIN 1 TOP VIEW EXPOSED 9.50 (PINS DOWN) PAD BSC SQ 1.05 0° MIN 0.20 BOT(PTIONSM U VP)IEW 10..0905 0.079° 2021 4041 4140 2120 3.5° 0.15 SEATING 0° VIEW A 0.50 BSC 0.27 0.05 PLANE 0.08 MAX LEAD PITCH 0.22 COPLANARITY 0.17 VIEW A FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO ROTATED 90° CCW THE PIN CONFIGURATION AND COMPLIANTTO JEDEC STANDARDS MS-026-ADD-HD FSUENCCTITOIONN O DFE TSHCISR IDPATTIOAN SSHEET. 071808-A Figure 60. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-3 Dimensions shown in millimeters 14.20 14.00 SQ 13.80 12.20 0.75 1.20 12.00 SQ 0.60 MAX 11.80 0.45 80 61 61 80 1 60 60 1 PIN 1 EXPOSED 9.50 BOTTOM VIEW PAD BSC (PINS UP) 1.05 0° MIN 0.20 TOP VIEW 10..0905 0.079° 2021 (PINS DOWN) 4041 4140 2120 3.5° 00..1055 SPELAANTEING 0.08 M0°AX VIEW A B6.S5C0 LE0A.5D0 PBISTCCH 00..2272 COPLANARITY 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO VIEW A THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ROTATED 90° CCW SECTION OF THIS DATA SHEET. COMPLIANTTO JEDEC STANDARDS MS-026-ADD-HU 071808-A Figure 61. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-2 Dimensions shown in millimeters Rev. F | Page 62 of 64

Data Sheet AD5522 ORDERING GUIDE Model1 Temperature Range (T) Package Description Package Option J AD5522JSVDZ 25°C to 90°C 80-Lead TQFP_EP with Exposed Pad on Bottom SV-80-3 AD5522JSVUZ 25°C to 90°C 80-Lead TQFP_EP with Exposed Pad on Top SV-80-2 AD5522JSVUZ-RL 0°C to 70°C 80-Lead TQFP_EP with Exposed Pad on Top SV-80-2 EVAL-AD5522EBDZ Evaluation Board with Exposed Pad on Bottom EVAL-AD5522EBUZ Evaluation Board with Exposed Pad on Top 1 Z = RoHS Compliant Part. Rev. F | Page 63 of 64

AD5522 Data Sheet NOTES ©2008–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06197-0-6/18(F) Rev. F | Page 64 of 64

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5522JSVDZ AD5522JSVUZ EVAL-AD5522EBDZ EVAL-AD5522EBUZ AD5522JSVUZ-RL