Per Pin Parametric Measurement Unit/Source Measure Unit AD5520 FEATURES GENERAL DESCRIPTION Force/measure functions The AD5520 is a single-channel, per pin parametric measure- FIMV, FVMI, FVMV, FIMI, FNMV ment unit (PPMU) for use in semiconductor automatic Force/measure voltage range ±11 V test equipment. The part is also suited for use as a source 4 user programmable force/measure current ranges measurement unit for instrumentation applications. It ±4 μA, ±40 μA, ±400 μA, ±4 mA (external resistors) contains programmable modes to force a pin voltage and 2 user programmable extended current ranges measure the corresponding current, or force a current and Up to 6 mA without external driver measure the voltage. The AD5520 can force/measure over a Higher currents with external driver ±11 V range or user-programmable currents up to ±4 mA Clamp circuitry and window comparators on board with its on-board force amplifier. An external amplifier is Guard amplifier required for wider current ranges. The device provides a force 64-lead LQFP package sense capability to ensure accuracy at the tester pin. A guard APPLICATIONS output is also available to drive the shield of a force/sense pair. The AD5520 is available in a 64-lead LQFP package. Automatic test equipment Per pin PMU, shared pin PMU, device power supply instrumentation Source measure, parametric measurement, precision measurement FUNCTIONAL BLOCK DIAGRAM AD5520 OMPIN0 OMPIN1 OMPIN2 MPOUT0 MPOUT1 MPOUT2 AVEE AVCC C C C O O O C C C FOH BW SELECT FOH3 FOH2 FIN FOH1 FOH0 MEASI5H CLAMP MEASI4H DETECT MEASI3H MEASI2H CLH MEASI1H CLL MEASI0H REFGND G = 16 MEASIOUT ISENSE MEASIL INST AMP GUARDIN MEASOUT VSENSE G = 1 INST AMP GUARD G = 1 MEASVH MEASVOUT COMPARATOR MEASVL CPH CPOH LOGICS AGND CCPPOLL CPCK STB STANDBY CPSEL FSEL MSEL AM2 AM1 AM0 MOE CLHDETECT CLLDETECT AC0AC1 CSDVDDQQMMDGND54 03701-001 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 www.analog.com Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD5520 TABLE OF CONTENTS Features..............................................................................................1 Force Control Amplifier............................................................15 Applications.......................................................................................1 Comparator Function and Strobing........................................15 General Description.........................................................................1 Clamp Function..........................................................................15 Functional Block Diagram..............................................................1 High Current Ranges.................................................................15 Specifications.....................................................................................3 Circuit Operation...........................................................................16 Timing Characteristics.....................................................................6 Force Voltage...............................................................................16 Absolute Maximum Ratings............................................................7 Measure Current.........................................................................16 ESD Caution..................................................................................7 Force Current..............................................................................17 Pin Configuration and Function Descriptions.............................8 Measure Voltage.........................................................................17 Typical Performance Characteristics...........................................10 Short Circuit Protection............................................................17 Theory of Operation......................................................................13 Settling Time Considerations.......................................................18 Interface...........................................................................................14 PCB Layout and Power Supply Decoupling................................19 Standby Mode.............................................................................14 Typical Connection Circuit for the AD5520..............................20 Force Voltage or Force Current................................................14 Typical Application Circuit...........................................................21 Measured Parameter..................................................................14 Evaluation Board for the AD5520................................................22 Current Ranges...........................................................................14 Outline Dimensions.......................................................................24 R Selection..................................................................................14 Ordering Guide..........................................................................24 S REVISION HISTORY 9/05—Rev. A to Rev. B 10/03—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Specifications.................................................................3 Changes to Features..........................................................................1 Updated Ordering Guide.................................................................5 Changes to Figure 1..........................................................................1 9/03—Revision 0: Initial Version Changes to Specifications................................................................3 Changes to Force Current Section................................................17 Changes to Figure 26 .....................................................................20 Updated Outline Dimensions.......................................................24 Changes to Ordering Guide..........................................................24 Rev. B | Page 2 of 24

AD5520 SPECIFICATIONS AV = +15 V ± 5%, AV = −15 V ± 5%, DV = 5 V ± 10%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0°C to 70°C, CC EE DD unless otherwise noted. Table 1. Parameter Min Typ1 Max Unit Test Conditions/Comments VOLTAGE FORCE MODE Force Control Output Voltage Range ±11 V R = 10 kΩ, C = 50 pF LOAD LOAD FOH Output Impedance 70 Ω FOH0 2.5 kΩ FOH1 3 kΩ FOH2 500 Ω FOH3 60 Ω Input Offset Error ±1 ±5 mV Input Offset Error Temperature Coefficient ±10 μV/°C Gain Error 1 % Clamp Current Error2 ±1 % FS of FIN CURRENT MEASURE/FORCE Suggested values; set with external sense resistors FOH0 ±4 μA MODE0, R = 125 kΩ S FOH1 ±40 μA MODE1, R = 12.5 kΩ S FOH2 ±400 μA MODE2, R = 12.5 kΩ S FOH3 ±4 mA MODE3, R = 125 Ω S CURRENT MEASURE MODE High Sense Input Range, V ±11 V MEASIxH Linearity3 ±0.01 % FSR +11 V > V > −11 V FOL Input Bias Current ±1 ±3 nA Input Bias Current Drift1 50 pA/°C Output Offset Error ±100 mV MODE0 (±4 μA) ±100 mV MODE1 (±40 μA) ±100 mV MODE2 (±400 μA) ±100 mV MODE3 (±4 mA) Output Offset Error Temperature Coefficient ±10 μV/°C Gain Error ±0.1 ±0.35 % Gain of 16 Gain Error Temperature Coefficient4 30 ppm/°C MEASIOUT Output Load Current ±4 mA CMRR 95 dB @ DC CURRENT FORCE MODE Input Offset Error ±10 mV with MODE0, MODE1, MODE2, MODE3 Gain Error 1 % Clamp Voltage Error2 ±1 % FS of FIN VOLTAGE MEASURE MODE Differential Input Range ±11 V Low Sense Input Voltage Range ±100 mV MEASVL Linearity3 +0.005 % FSR +11 V > V to V > −11 V MEASVH MEASVL Input Offset Error ±5 ±10 mV FIN = 0 V, measured @ MEASVOUT Input Offset Error Temperature Coefficient1 ±15 μV/°C Gain Error ±0.03 ±0.15 % Gain of 1 Gain Error Temperature Coefficient4 2 ppm/°C Input Bias Current ±1 ±3 nA Input Bias Current Drift4 50 pA/°C MEASVOUT Output Load Current ±4 mA CMRR4 73 dB @ DC Rev. B | Page 3 of 24

AD5520 Parameter Min Typ1 Max Unit Test Conditions/Comments AMPLIFIER SETTLING TIME4, 5 V Amp 20 μs to 0.2% SENSE I Amp 12 μs to 0.2% SENSE LOOP SETTLING4, 5 Settling to within 0.024% of 8 V step COMPIN2 = 100 pF 450 600 μs MODE0 285 390 μs MODE1 170 240 μs MODE2, MODE3 COMPIN1 = 1000 pF 2 2.5 ms MODE0 1.8 2.4 ms MODE1, MODE2, MODE3 COMPIN0 = 3000 pF 5.75 8.7 ms MODE0, MODE1, MODE2, MODE3 SLEW RATE4, 5 50 mV/μs COMPIN2 = 100 pF 4.3 mV/μs COMPIN1 = 1000 pF 1.28 mV/μs COMPIN0 = 3000 pF COMPARATOR CPH, CPL Input Range ±11 V VCPH > VCPL Input Offset ±7 mV GUARD DRIVER Output Voltage ±11 V Output Impedance 130 Ω Capacitive load only Output Offset Voltage 400 mV Load Current4 ±4 mA Output Settling Time4 0.5 2 μs 100 pF capacitive load ANALOG REFERENCE INPUTS Force Control Input Range ±11 V Force Control Input Impedance 1 MΩ Clamp Control Input Range ±11 V VCLH > VCLL Clamp Control Input Impedance 1 MΩ Comparator Threshold Input Range ±11 V Comparator Threshold Input Impedance 1 MΩ Input Capacitance4 3 pF LEAKAGE CURRENT MEASIxx, MEASVx, MEASOUT Leakage ±3 ±20 nA ANALOG MEASUREMENT OUTPUTS Voltage Measure Output Impedance 2 Ω Current Measure Output Impedance 3 Ω Multiplexed Sense Output Impedance 1 kΩ Input Capacitance MEASIxH, MEASVH, FOHx 8 pF LOGIC INPUTS Input Current ±1 μA All digital inputs together Input Low Voltage, VINL 0.8 V Input High Voltage, VIHL 2.0 V Input Capacitance4 3 pF LOGIC OUTPUTS Output Low Voltage, VOL4 0.4 V ISINK = 2 mA Output High Voltage, VOH4 2.4 V ISOURCE = 2 mA Rev. B | Page 4 of 24

AD5520 Parameter Min Typ1 Max Unit Test Conditions/Comments POWER REQUIREMENTS AV 14.25 15 15.75 V for specific performance6 CC AVEE −14.25 −15 +15.75 V Power Supply Rejection Ratio, PSRR1 FOH −25 dB 100 kHz −16 dB 500 kHz −15 dB 1 MHz MEASOUT −55 dB 100 kHz −10 dB 500 kHz DC PSR 90 dB DVDD 5 V IAVCC 12 mA IAVEE 12 mA IDVDD 0.5 mA Digital inputs at supply rails 1 Typical values are at 25°C and nominal supply, unless otherwise noted. 2 Full-scale = 11 V. 3 Full-scale range = 22 V. 4 Guaranteed by design and characterization, but not subject to production test. 5 Force control amplifier dominates slew rate and settling time. 6 Operational with ±12 V supplies, force/measure range is reduced to ±8.5 V. Rev. B | Page 5 of 24

AD5520 TIMING CHARACTERISTICS AV = +15 V ± 5%, AV = −15 V ± 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All specifications 0°C to 70°C, unless otherwise CC EE noted.1, 2 Table 2. DV DD Parameter 5 V ± 10% 3.3 V Unit Conditions/Comments t 0 0 ns min CS falling edge to STB falling edge setup time 1 t 30 200 ns min STB pulse width 2 t 40 70 ns min STB rising edge to CS rising edge setup time 3 t 0 40 ns min Data setup time 4 t 550 560 ns min CS falling edge to CPCK rising edge setup time 5 t 320 320 ns min CPCK pulse width 6 t 450 500 ns min CPCK to STB falling edge setup time 7 t 150 800 ns min STB rising edge to QMx, CLxDETECT valid 8 t 100 440 ns min STB rising edge to CPOH, CPOL valid 9 t 240 240 μs min Comparator setup time, MODE2, MODE3 settling 10 t 150 500 ns min Comparator hold time 11 t 100 440 ns min Comparator output delay time 12 t 320 320 ns min Comparator strobe pulse width 13 1 See Figure 2. 2 All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. CS t t t 1 2 3 STB t 4 AMx, ACx, FSEL, MSEL, CPSEL t t t 5 6 7 CPCK t t 6 9 QM4, QM5, CLHDETECT, CLLDETECT CPOL, CPOH 03701-002 Figure 2. Timing Diagram t MEASVOUT 11 OR MEASIOUT CPCK CPOH, CPOL t10 t13 t12 03701-003 Figure 3. Comparator Timing Rev. B | Page 6 of 24

AD5520 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress AV to AV 34 V CC EE rating only; functional operation of the device at these or any AV to AGND −0.3 V, +17 V CC other conditions above those indicated in the operational AV to AGND +0.3 V, −17 V EE section of this specification is not implied. Exposure to absolute DV −0.3 V to +6 V DD maximum rating conditions for extended periods may affect Digital Inputs to DGND −0.3 V to DV + 0.3 V DD device reliability. Analog Inputs to AGND AV + 0.3 V to AV – 0.3 V CC EE CLH to CLL −0.3 V to +34 V CPH to CPL −0.3 V to +34 V REFGND, DGND AV + 0.3 V to AV – 0.3 V CC EE Operating Temperature Range Commercial (J Version) 0°C to 70°C Storage Temperature Range −65°C to +150°C Maximum Junction Temperature, 150°C (T max) J Package Power Dissipation (T max – T )/θ J A JA Thermal Impedance θJA 47.8°C /W Lead Temperature 300°C (Soldering 10 sec) IR Reflow, Peak Temperature 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 7 of 24

AD5520 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLL CLH FIN MEASVOUT MEASIOUT REFGND MEASOUT REFGND COMPIN2 COMPIN1 COMPIN0 COMPOUT2 COMPOUT1 COMPOUT0 AVCC_BFOH 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CPH 1 48 AVEE_B CPL 2 PIN 1 47 MEASI5H DVDD 3 46 MEASI4H CPOH 4 45 FOH3 CPOL 5 44 MEASI3H CPCK 6 43 FOH2 AD5520 DGND 7 TOP VIEW 42 MEASI2H CLHDETECT 8 (Not to Scale) 41 FOH1 CLLDETECT 9 40 MEASI1H QM4 10 39 FOH0 QM5 11 38 MEASI0H MOE 12 37 MEASIL CS 13 36 MEASVH STB 14 35 GUARD(NC) AC0 15 34 MEASVL AC1 16 33 AVCC_G 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC = NO CONNECT D D2 1 0 Y L L L E CD GD C N DGN DVDAM AM AM STANDB FSE MSE CPSE AVEAVCAGN AVEE_GUAR N GUARDI 03701-004 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CPH Upper Comparator Threshold Voltage Input, CPH > CPL. 2 CPL Lower Comparator Threshold Voltage Input, CPL < CPH. 3, 18 DV Digital Supply Voltage. DD 4 CPOH Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH. 5 CPOL Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL. 6 CPCK Logic Input. Used to initiate comparator sampling and update CPOH and CPOL. 7, 17 DGND Digital Ground. 8 CLHDETECT Logic Output. When high, indicates upper clamp active. See the Clamp Function section. 9 CLLDETECT Logic Output. When high, indicates lower clamp active. See the Clamp Function section. 10 QM4 Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external relay or switch. See the High Current Ranges section. 11 QM5 Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external relay or switch. See the High Current Ranges section. 12 MOE Active Low MEASOUT Enable. 13 CS Active Low Logic Input. The device is selected when this pin is low. See the Interface section. 14 STB Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for different configurations. Rising edge of STB triggers sequence inputs. See the Interface section. 15 AC0 Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors. See the Force Control Amplifier section. 16 AC1 Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors. See the Force Control Amplifier section. 19 AM2 Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable standby mode. See the Current Ranges section. 20 AM1 Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable standby mode. See the Current Ranges section. 21 AM0 Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable standby mode. See the Current Ranges section. 22 STANDBY Logic Input. When high, device is in standby mode of operation. See the Standby Mode section. Rev. B | Page 8 of 24

AD5520 Pin No. Mnemonic Description 23 FSEL Logic Input. Force mode select. Used to select between current or voltage force operation. See the Force Voltage or Force Current section. 24 MSEL Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or MEASVOUT when low. 25 CPSEL Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to MEASIOUT when high. See the Comparator Function and Strobing section. 26 AV Most Negative Supply Voltage. EE 27 AV Most Positive Supply Voltage. CC 28 AGND MEASx Input Ground. 29 AV Most Negative Supply Voltage. EE_G 30 GUARD Guard Output. 31 NC No Connect. 32 GUARDIN Guard Input. 33 AV Most Positive Supply Voltage. CC_G 34 MEASVL DUT Voltage Sense Inputs (Low Sense). 35 GUARD(NC) No Connect. 36 MEASVH DUT Voltage Sense Inputs (High Sense). 37 MEASIL DUT Current Sense Inputs (Low Sense). 38 MEASI0H DUT Current Sense Inputs (High Sense). 39 FOH0 Force Control Voltage Output. 40 MEASI1H DUT Current Sense Inputs (High Sense). 41 FOH1 Force Control Voltage Output. 42 MEASI2H DUT Current Sense Inputs (High Sense). 43 FOH2 Force Control Voltage Output. 44 MEASI3H DUT Current Sense Inputs (High Sense). 45 FOH3 Force Control Voltage Output. 46 MEASI4H DUT Current Sense Inputs (High Sense). 47 MEASI5H DUT Current Sense Inputs (High Sense). 48 AV Most Negative Supply Voltage. EE_B 49 FOH External Force Driver Control Voltage Output. 50 AV Most Positive Supply Voltage. CC_B 51 COMPOUT0 Compensation Capacitor 0 Output. 52 COMPOUT1 Compensation Capacitor 1 Output. 53 COMPOUT2 Compensation Capacitor 2 Output. 54 COMPIN0 Compensation Capacitor 0 Input. 55 COMPIN1 Compensation Capacitor 1 Input. 56 COMPIN2 Compensation Capacitor 2 Input. 57, 59 REFGND Analog Input/Output Reference Ground. 58 MEASOUT Multiplexed DUT Voltage/Current Sense Output. See the Measured Parameter section. 60 MEASIOUT DUT Current Sense Output. 61 MEASVOUT DUT Voltage Sense Output. 62 FIN Force Control Voltage Input. 63 CLH Upper Clamp Voltage Input CLH > CLL. 64 CLL Lower Clamp Voltage CLL < CLH. Rev. B | Page 9 of 24

AD5520 TYPICAL PERFORMANCE CHARACTERISTICS 0.0030 0.0030 VDD = +15V VDD = +15V VSS =–15V VSS =–15V 0.0025 MODE 3 0.0025 MODE 3 %)0.0020 %)0.0020 RITY ( RITY ( A0.0015 A0.0015 NE NE VM LI0.0010 IM LI0.0010 0.0005 0.0005 0 03701-005 0 03701-008 0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 TEMPERATURE (°C) TEMPERATURE (°C) Figure 5. Voltage Sense Amplifier Linearity vs. Temperature Figure 8. Current Sense Linearity vs. Temperature 80 140 70 TVVADS SD= = =2 5–+°11C55VV 120 TVVADS SD= = =2 5–+°11C55VV ISENSE CMRR 60 100 UDE (dB) 5400 R (dB) 80 T R PLI CM 60 M 30 A 40 20 100 03701-006 200 03701-009 1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Voltage Sense Amplifier CMRR vs. Frequency Figure 9. Current Sense Amplifier CMRR vs. Frequency 10 5 0 CCOMP = 0.1nF 0 –5 –10 B) B) –10 CCOMP = 0.1nF d d E ( –20 E ( –15 TUD CCOMP = 1.0nF TUD CCOMP = 1.0nF PLI –30 PLI –20 M M A A –25 –40 CCOMP = 3.3nF –30 CCOMP = 3.3nF ––5600 TVVADS SD= = =2 5–+°11C55VV 03701-007 ––3450 TVVADS SD= = =2 5–+°11C55VV 03701-010 100 1k 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Force Amplifier Bandwidth, Mode 0 (4 μA) Figure 10. Force Amplifier Bandwidth, Mode 1 (40 μA) Rev. B | Page 10 of 24

AD5520 0 0 VDD = +15V VDD = +15V –5 VSS =–15V –5 VSS =–15V TA = 25°C TA = 25°C –10 CCOMP = 0.1nF –10 CCOMP = 0.1nF B) –15 B) –15 d d DE ( –20 DE ( –20 TU CCOMP = 1.0nF TU CCOMP = 1.0nF LI –25 LI –25 P P M M A –30 A –30 –35 CCOMP = 3.3nF –35 CCOMP = 3.3nF ––4450 03701-011 ––4450 03701-014 100 1k 10k 100k 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 11. Force Amplifier Bandwidth, Mode 2 (400 μA) Figure 14. Force Amplifier Bandwidth, Mode 3 (4 mA) 5 30 VDD = +15V 0 VSS =–15V TA = 25°C 20 ISENSE –5 B) –10 B) 10 d d E ( –15 E ( D D U U 0 T T LI –20 LI P P M M A –25 A –10 VSENSE –30 ––4305 03701-012 ––2300 TVVADS SD= = =2 5–+°11C55VV 03701-015 1 10 100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 12. Guard Amplifier Bandwidth Figure 15. Voltage Sense and Current Sense Amplifier Bandwidths 20 0 VDD = +15V VDD = +15V VSS =–15V VSS =–15V 10 TA = 25°C –5 TA = 25°C 0 dB) –10 dB) –10 E ( E ( D D U –20 U –15 T T LI LI P P M –30 M A A –20 –40 –25 ––5600 03701-013 –30 03701-016 100k 1M 10M 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 13. Current Sense Amplifier AC PSRR Figure 16. Force Amplifier AC PSRR, Mode 3, CCOMP = 100 pF Rev. B | Page 11 of 24

AD5520 20 16 VDD = +15V 10 TVAS S= = 25–°1C5V 14 VCC 12 0 dB) –10 V) 10 E ( E ( 8 D G U –20 A LIT LT 6 P O M –30 V A 4 –40 2 VDUT ––5600 03701-017 –20 03701-019 100k 1M 10M 0 5 10 15 20 25 30 35 40 45 FREQUENCY (Hz) TIME (ms) Figure 17. Voltage Sense Amplifier AC PSRR Figure 19. Power Up 700 9 COMPIN2 = 100pF 8 COMPIN1 = 1000pF 600 GUARD 7 500 6 V) 5 Hz 400 GE ( COMPIN2 = 3000pF nV/√ 300 VSENSE VOLTA 34 200 FOH 2 1 100 0 ISENSE 03701-018 –01 03701-020 10 100 1k 10k 100k 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 FREQUENCY (Hz) TIME (s) Figure 18. Noise Spectral Density Figure 20. Settling Time, Mode 2 Rev. B | Page 12 of 24

AD5520 THEORY OF OPERATION The AD5520 is a single-channel per pin parametric measure- The AD5520 has an on-board window comparator that ment unit (PPMU) for use in semiconductor automatic test provides two bits of useful information, DUT too low or too equipment. It contains programmable modes to force a pin high. Also provided on the chip is clamp circuitry that flags via voltage and measure the corresponding current (FVMI), force CLHDETECT and CLLDETECT if the voltage applied to FIN current measure voltage (FIMV), force current measure current or across the DUT exceeds the voltage applied to CLL and CLH. (FIMI), force voltage measure voltage (FVMV), and force On-chip is clamp circuitry that clamps the output of the force nothing measure voltage (FNMV). The PPMU can force or amplifier if the voltage at MEASIOUT and MEASVOUT measure a voltage from −11 V to +11 V. It can force or measure exceeds CLL or CLH. currents up to 6 mA using the internal amplifier, while the addition of an external amplifier enables higher current ranges. External resistors allow users to choose the optimum ranges for their needs. The device provides a force sense capability to ensure accuracy at the tester pin. A guard output is also available to drive the shield of a force/sense pair. Rev. B | Page 13 of 24

AD5520 INTERFACE The AD5520 PPMU is controlled via a number of digital inputs, MEASURED PARAMETER which are discussed in detail in the following sections. All MEASOUT is a muxed output that tracks the sensed parameter. inputs are TTL-compatible. CS is used to select the device while MSEL (digital input) connects the MEASOUT to the output of STB (active low input) latches data available on the other digital the current sense amplifier or the voltage sense amplifier, inputs and updates any required digital outputs. The rising edge depending on which is the measured parameter of interest. of STB triggers sequence inputs. The remaining digital inputs The MEASOUT pin is connected back to an ADC to allow the control the function of the PMU. They also determine which measured value to be converted to a digital code. measure mode the PMU is in, the compensation capacitor used, and the selected current range. Table 7. MEASOUT Connected to Voltage or Current MSEL Function STANDBY MODE Low MEASOUT = DUT Voltage The AD5520 can be placed into standby mode via the standby High MEASOUT = DUT Current logic input. In this mode, the force amplifier is disconnected The MEASOUT pin can also be made high impedance through from the force input (FIN). In addition, the switch in series with the MOEB logic input. the force output pins (FOHx) is opened, and the current measure amplifier is disconnected from the sense resistors. The Table 8. MOEB Allows MEASOUT to Go High Impedance voltage measure amplifier is still connected across the DUT; MOEB Function therefore, DUT voltage measurements may still be made while Low Enable MEASOUT Output in standby mode. Figure 21 shows the configuration of the High Hi-Z MEASOUT Output PMU while in standby mode. CURRENT RANGES Table 5. Standby Mode A number of current ranges are possible with the AD5520. The Standby Function AM0, AM1, and AM2 pins are digital inputs used to establish Low Normal Force Mode full-scale current range of the PMU. High Standby Mode Table 9. Selection of Current Range AM0 AM1 AM2 Function DAC Low Low Low Current Range MODE0 (4 μA) FIN FOHx High Low Low Current Range MODE1 (40 μA) Low High Low Current Range MODE2 (400 μA) High High Low Current Range MODE3 (4 mA) Low Low High Current Range MODE4 MEASIOUT G = 16 MEASIHx RS (External Buffer Mode) High Low High Current Range MODE5 MEASIL (External Buffer Mode) MEASVOUT G = 1 MEASVH DUT Low High High Standby (Same as STANDBY = High) MEASVL 03701-021 HRig Sh ELEHCigThI ONH igh Standby (Same as STANDBY = High) S Figure 21. PMU in Standby Mode The AD5520 is designed to ensure the voltage drop across each FORCE VOLTAGE OR FORCE CURRENT of the R resistors is less than ±500 mV when maximum current S FSEL is an input that determines whether the PPMU forces a is flowing through them. To support other current ranges, these voltage or current. sense resistor values can be changed. The force amplifier can drive a maximum of 6 mA. It is not recommended to increase Table 6. FSEL Function the maximum current above the nominal range. FSEL Function Low Voltage Force and Current Clamp with MEASIOUT Voltage The two external current ranges use an external buffer to drive High Current Force and Voltage Clamp with MEASVOUT Voltage higher current. The example in Figure 26 uses 40 mA and 160 mA ranges. These ranges can be changed to suit user requirements for a high current range. Rev. B | Page 14 of 24

AD5520 FORCE CONTROL AMPLIFIER CLAMP FUNCTION The force control amplifier requires external capacitors Clamp circuitry, which is also included on-chip, clamps the connected between the COMPOUTx and COMPINx pins. force amplifier’s output if the voltage or current applied to the For stability with large capacitance at the DUT, the largest DUT exceeds the clamp levels, CLL and CLH. The clamp capacitance value (3000 pF) should be selected. The force circuitry also comes into play in the event of a short or open control amplifier should always contribute the dominant circuit. When in force current range, the voltage clamps protect pole in the control loop. Settling times increase with the DUT from an open circuit. Likewise, when forcing a voltage larger capacitances. ACx inputs select which external and a short circuit occurs, the current clamps protect the DUT. compensation capacitor is used. The clamps also function to protect the DUT if a transient voltage or current spike occurs when changing to a different Table 10. AC0, AC1 Compensation Capacitor Selection operating mode, or when programming the device to a different AC0 AC1 Function current range. Low Low Select External Compensation Capacitor 0 High Low Select External Compensation Capacitor 1 The digital output flags, which indicate a clamp limit has been Low High Select External Compensation Capacitor 2 hit, are CLHDETECT for the upper clamp, and CLLDETECT output for the lower clamp. COMPARATOR FUNCTION AND STROBING Table 13. Clamp Detect Outputs The AD5520 has an on-board window comparator that CLHDETECT Function provides two bits of useful information, DUT too low or Low Upper Clamp Inactive DUT too high. CPSEL is the digital input that controls High Upper Clamp Active this function, selecting whether it should compare to the CLLDETECT Function voltage sense or the current sense amplifier. Low Lower Clamp Inactive Table 11. Comparator Function Select High Lower Clamp Active CPSEL Function Low Compare CPL, CPH to MEASVOUT HIGH CURRENT RANGES High Compare CPL, CPH to MEASIOUT With the use of an external high current amplifier, two high After CPSEL has selected which amplifier output is of interest, current ranges are possible. The current range values can be set logic input CPCK is used to initiate comparator sampling and as required in the application through appropriate selection of update the logic outputs CPOH and CPOL. This indicates the sense resistors connected between MEASI5H, MEASI4H, whether the voltages at MEASIOUT or MEASVOUT have and MEASIL. When one of these high current ranges (Mode 4 exceeded voltages set at CPL or CPH (thus providing DUT too or Mode 5) is selected via the AMx control lines, the appro- high or DUT too low information). A rising edge on STB is priate QM4 or QM5 output is enabled. As a result, these outputs required to clock the CPOH and CPOL data out. can be used to control relays connected in series with the high current amplifier, as shown in Figure 26. Table 12. CPCK Synchronous Logic Outputs Table 14. High Current Range Logic Outputs CPOH Function QM4 QM5 Function Low MEASVOUT or MEASIOUT < CPH MEASVOUT or High MEASIOUT > CPH High Low Current Range Mode 4 Enable Output Low High Current Range Mode 5 Enable Output CPOL Function Low MEASVOUT or MEASIOUT > CPL MEASVOUT or High MEASIOUT < CPL Rev. B | Page 15 of 24

AD5520 CIRCUIT OPERATION FORCE VOLTAGE MEASURE CURRENT Most PMU measurements are performed while in force voltage Figure 23 shows a simplified diagram of the PMU when in force and measure current modes; for example, when the device is voltage mode. The control loop consists of the force amplifier used as a device power supply, or in continuity or leakage with the voltage sense amplifier making up the feedback path. testing. In the force voltage mode, the voltage at analog input Current flowing through the DUT is measured by sensing the FIN is mapped directly to the voltage forced at the DUT. current flowing through a selectable sense resistor, which is in series with the DUT. The current sense amplifier (Gain = 16) When in force voltage and measure current modes, the generates a voltage at its output, which is proportional to the maximum voltage applied to the input corresponds to the current flowing through the DUT. This voltage is compared to maximum current outputs. Figure 22 shows the transfer the CLL and CLH levels to ensure the clamp voltages have not function when forcing a voltage. been exceeded. Strobing CPCK and STB provides information VDUT about the voltage level with respect to the comparator levels, CPH and CPL. FIN VCLH×RRSD×U 1T6 FOHx MEASIHx VFIN VFIN CLH G=16 MEASIL RS CLL MEASVH VCLL× RRSD×U 1T6 VCLH VCLL UT UT G = 1 MEASVL RDUT O O REFGNDI/V MEASV MEASI V VMEASVOUT V VMEASIOUT IDUT CONDITION VCLH > IDUT× RS× 16 VCLH < IDUT× RS× 16 VCLH > IDUT× RS× 16 OUTPUT VCLLV <D IUDTU =T ×V FRINS× 16 VCLLV D< UIDT U=T V×C RLHS× 16 VCLLV >D UIDT U=T V×C RLLS× 16 03701-023 VCLH Figure 23. Force Voltage, Measure Current Mode RS× 16 VCLH VCLH VFIN VCLL RS× 16 03701-022 Figure 22. Force Voltage Transfer Function Rev. B | Page 16 of 24

AD5520 FORCE CURRENT SHORT CIRCUIT PROTECTION In force current mode, the voltage at FIN is now converted to a The AD5520 is designed to withstand a direct short circuit on current through the following relationship: any of the amplifier outputs. Force Current = V /(R × 16) FIN SENSE Figure 25 illustrates the transfer function of the current force mode. Figure 24 shows a simplified diagram of the PMU when in force current mode. The control loop consists of the force amplifier IDUT with the current sense amplifier making up the feedback path. In this case, voltage at the DUT is sensed across the voltage measure amplifier (Gain = 1) and presented at the MEASVOUT output. VCLH RDUT FIN FOHx VFIN MEASIHx VCLL RDUT VFIN CLH G=16 RS MEASIL CLL MEASVH VCLH VCLL UT UT G = 1 MEASVL RDUT O O REFGNDI/V MEASV MEASI VDUT V VMEASVOUT V VMEASIOUT CONDITION VCLH > VDUT VCLH < VDUT VCLH > VDUT VCLH VCLL < VDUT VCLL < VDUT VCLL > VDUT OUTPUT IDUT = VRFISN IDUT = VRCSLH IDUT = VRCSLL 03701-024 VCLH Figure 24. Current Force, Voltage Measure Mode VCLH VFIN MEASURE VOLTAGE VCLH A DUT voltage is tested via the voltage measure amplifier by a window comparator to ensure that CPH and CPL levels are not exceeded. In addition, the DUT voltage is automatically tested aengaaibnlsetd t ihfe t hveo lDtaUgeT l evvoelltsa gaet tehxec eceladms epi,t ahnerd ocfl atmhep l eflvaeglss .a re 03701-025 Figure 25. Current Force Transfer Function Rev. B | Page 17 of 24

AD5520 SETTLING TIME CONSIDERATIONS Fast throughput is a key requirement in automatic test When selecting a faster settling time, there is a trade-off. equipment because it relates directly to the cost of manufac- A small compensation value results in faster settling, but turing the DUT; thus reducing the time required to make a may incur penalties in overshoots or ringing at the DUT. measurement is of greatest importance. When taking Compensation capacitor selection should be optimized to measurements using a PMU, the limiting factor is usually the ensure minimum overshoots while still giving decent settling time it takes the output to settle to the required accuracy so a time performance. measurement can be taken. DUT capacitance, measurement While careful selection of the compensation capacitor is accuracy, and the design of the PMU are the major contributors required to minimize the settling time, another factor can to this time. greatly contribute to the overall settling of the loop if the Figure 26 shows a simplified block diagram of the AD5520 feedback loop is broken in some manner, and the force control PMU. In brief, the device consists of a force control amplifier, amplifier goes to either the positive or negative rails. There is a access to a number of selectable sense resistors, a voltage finite amount of time required for the amplifier to recover from measure instrumentation amplifier, and a current measure this condition, typically 85 μs, which adds to the settling of the instrumentation amplifier. To optimize the performance of the loop. Ensuring that the force control amplifier never goes into device, there are also nodes provided where external compensa- saturation is the best solution. This solution can be helped by tion capacitors are added. As mentioned, making an accurate putting the device into standby mode any time the operating measurement in the fastest time while avoiding overshoots and mode or range selection is changed. In addition, ensure that the ringing is the key requirement in any automatic test equipment selected output range can supply the required current needed by (ATE) system. Doing so provides challenges, however. The the DUT. external compensation capacitors set up different settling times or bandwidths on the force control amplifier, and while one compensation capacitor value may suit one range, it may not suit other ranges. To optimize measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be taken into account. Rev. B | Page 18 of 24

AD5520 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- Fast switching signals, such as clocks, should be shielded with tion to the power supply and the ground return layout helps to digital ground to avoid radiating noise to other parts of the ensure the rated performance. The printed circuit board on board and should never be run near the reference inputs. which the AD5520 is mounted should be designed so that the Avoid crossover of digital and analog signals. Traces on analog and digital sections are separated and confined to opposite sides of the board should run at right angles to each certain areas of the board. If the PMU is in a system where other. This reduces the effects of feedthrough through the multiple devices require an AGND-to-DGND connection, the board. A microstrip technique is by far the best but not always connection should be made at one point only. The star ground possible with a double-sided board. In this technique, the point should be established as close as possible to the device. component side of the board is dedicated to the ground plane This PMU should have ample supply bypassing of 10 μF in while signal traces are placed on the solder side. parallel with 0.1 μF on the supply and should be located as close It is good practice to use compact, minimum lead length PCB as possible to the package, ideally right up against the device. The layout design. Leads to the input should be as short as possible 0.1 μF capacitor should have low effective series resistance (ESR) to minimize IR drops and stray inductance. and effective series inductance (ESI), such as the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR (1 μF to 10 μF) tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Rev. B | Page 19 of 24

AD5520 TYPICAL CONNECTION CIRCUIT FOR THE AD5520 Figure 26 shows the AD5520 as connected in a typical applica- The PMU requires a number of discrete voltage levels: five DAC tion. The external components required are three compensation levels for each PMU used in the system, two levels each for the capacitors and six sense resistors, depending on the number of comparator and clamps, and one voltage level for the AD5520 ranges required. If high current ranges >6 mA are required, an force input voltage. To use the information measured at the external amplifier must be used with relays (or some form of DUT, an ADC such as the AD7665 (a 16-bit ADC), must be high current switch) to switch in the different current ranges to connected to the MEASOUT pin to convert the measured the DUT. Other components are also required to make the current or voltage to digital for analysis. PMU function. 3000pF 1000pF 100pF +15V –15V MPIN0 MPIN1 MPIN2 POUT0 POUT1 POUT2 AVEE AVCC AD5520 CO CO CO OM OM OM AD815 C C C FOH BW SELECT RELAY FOH3 FOH2 FIN FOH1 FOH0 FORCE AMPLIFIER MEASI5H <±11.5V CLAMP MEASI4H 3.126Ω DETECT MEASI3H 12.5Ω MEASI2H 125Ω CLH MEASI1H 1.25kΩ CLL MEASI0H 12.5kΩ REFGND 125kΩ G = 16 MEASIOUT ISENSE MEASIL INST AMP GUARDIN MEASOUT INVSSTE NASMEP G = 1 GUARD ≥±11V MEASVH G = 1 DUT MEASVOUT COMPARATOR MEASVL CPH CPOH AGND <±100mV LOGICS QM5 CPOL CT CT QM4 CPL BY TE TE CPCK STB STAND CPSEL FSEL MSEL AM2 AM1 AM0 MOE CLHDE CLLDE AC0AC1 CSDVDDDGND 03701-026 Figure 26. Typical Configuration of the AD5520 as Used in an ATE Circuit Rev. B | Page 20 of 24

AD5520 TYPICAL APPLICATION CIRCUIT Figure 27 shows the AD5520 as in an ATE system. This device The flexible function of the AD5520 also makes it suited for use can used as a per pin parametric unit in order to speed up the in instrumentation applications such as source measure units. rate at which testing can be done. It can also be used as a DUT Source measure units are programmable instruments capable of power supply, as shown in the application circuit. sourcing and measuring voltage or current simultaneously. The AD5520 provides a more integrated solution in such The central PMU shown in the block diagram (Figure 27) is equipment. usually a highly accurate PMU and is shared among a number of pins in the tester. In general, many discrete levels are required in an ATE system for the pin drivers, comparators, clamps, and active loads. DAC devices, such as the AD5379, offer a highly integrated solution for a number of these levels. The AD5379 is a dense 40-channel DAC designed with high channel requirements, such as ATE. CENTRAL PMU DAC GUARD AMP PPMU ADC DAC VCH DAC ADC VTERM DAC TIMING DATA VH DEVICE UNDER DAC MEMORY TEST (DUT) RELAYS 50Ω COAX GENTIEMRINAGTOR FODREM-SAKTETWER DRIVER DLL, LOGIC DAC VL VCL GUARD AAMMPP DAC GND SENSE DAC DEVICE POWER SUPPLIES COMPARE FORMATTER COMP VTH DAC MEMORY DE-SKEW VTL ADC DAC ACTIVE LOAD IOL DAC VCOM DAC DAC IOH 03701-027 Figure 27. Typical Application ATE Circuit Rev. B | Page 21 of 24

AD5520 EVALUATION BOARD FOR THE AD5520 A full-featured evaluation kit is available for the AD5520. It Both AGND and DGND inputs are provided on the board. The includes an evaluation board with direct hookup via a 36-way AGND and DGND planes are connected at one location close Centronics connector to a PC. PC-based software to control the to the AD5520. It is recommended not to connect AGND and AD5520 is also part of the evaluation kit. The evaluation board DGND elsewhere in the system to avoid ground loop problems. schematic is shown in Figure 28. REFGND is routed back to AGND at the power block to maintain a clean ground reference for accurate measurements. Note that V and V must provide sufficient headroom for the DD SS force and measure voltage range. In addition to the supply Each supply is decoupled to the relevant ground plane with voltages for the evaluation board, it is necessary to provide the 10 μF and 0.1 μF capacitors. The device supply pin is again voltage levels for the clamp, comparator, and the force input decoupled with a 10 μF and 0.1 μF capacitor pair to the relevant pins (CLL, CLH, CPL, CPH, and FIN). SMB connections are ground plane. provided for these voltage inputs. To use the evaluation board, it Care should be taken when replacing devices to ensure that the is also necessary to provide a DUT connected via the gold pins. pins line up correctly with the PCB pads. Rev. B | Page 22 of 24

AD5520 5 M D2 R910kΩ Q T3 14 5ARB–24 D 2LR B C1610pF U5–B AD81 +5V 1 10 C Q1 E T1 1615 T2 2 3 4 +5VD 18H6G–1D1YLARLER1097 CR810kΩBQ1 E C1510pFQM4 C10–15V10Fμ 20VC110.1Fμ 12AD815ARB–24–VSC+VSC12130.1Fμ C1310Fμ 20V+15V – 3 2 U5 4 J9J8 T10T11 8H6G–YALER97 Ω467.2RR1 ,5R C19 J7 T9 ARB Ω421 ,4R R10 J6 T8 A D815 R115kΩ Ωk42.1 ,3R 7 8 – A 1 1 J5 T7 U5 Ωk4.21 ,2R C C J4 T6 R125kΩ C14 V V J3 T5 Ωk421 ,1R K1 +15 20V 20V –15 L C210Fμ 20VC10.1Fμ 3 DVDDJ2T4 58MEASOUT60MEASIOUT61MEASVOUT62FIN63CLH64CLL1CPH2CPL T12 59REFGND57REFGND 49FOH 47MEASI5H46MEASI4H45FOH344MEASI3H43FOH242MEASI2H41FOH140MEASI1H39FOH038MEASIOH37MEASIL 36MEASVH35NC34MEASVL32GAURDIN31NC30GUARD DAGND28 C23C2210Fμ0.1Fμ C24C250.1Fμ10Fμ N 1 2 3 +5VD 18 DVDD AVCCAVCC_G STANDBYSTBCPCKMOEBCSB AM0AM1AM2FSELCPSELMSELAC0AC1 CPOHCPOLCHL-DETCLL-DETQM4QM5 COMPIN2COMPOUT2 COMPIN1COMPOUT1 COMPIN0COMPOUT0 AVEEAVEE_GAVEE_B DGDGND717 +5VD J11– 20V J11– J11– 273350 221461213 2120192325241516 45891011 5653 5552 5451 262948 +15VC30.1Fμ C410Fμ 20V C7, 100pF C8, 1nF C9, 3.3nF C50.1Fμ C610Fμ 20V C21C2010Fμ1Fμ 0. 1 2 – – 0 0 1 1 J J 1918171615141312 1918171615141312 234567 89 111 74HCT573 Q0D0Q1D1Q2D2Q3D3Q4D4Q5D5Q6D6Q7D7 U2COE 74HCT573 Q0D0Q1D1Q2D2Q3D3Q4D4Q5D5Q6D6Q7D7 CU3OE D0Q0Q1D1Q2D2Q3D3D4Q4D5Q5D6Q6Q7D7 CU4OE 74HCT573 1–191–201–211–221–231–241–251–261–271–281–291–30 23456789 111 23456789 111 1918171615141312 JJJJJJJJJJJJ 01234567 01234567 01234567 DDDDDDDD DDDDDDDD DDDDDDDD S R ]7:0[D CITO 5VD D0D1D2D3D4D5D6D7 SS CAPA + C280.1Fμ J1–14 J1–1 J1–31 J1–36 J1–2J1–3J1–4J1–5J1–6J1–7J1–8J1–9 YPA C271Fμ B 0. 4 U U2, U3, C260.1Fμ 03701-028 Figure 28. Evaluation Board Schematic Rev. B | Page 23 of 24

AD5520 Preliminary Technical Data OUTLINE DIMENSIONS 0.75 12.00 0.60 1.60 BSC SQ 0.45 MAX 64 49 1 48 PIN 1 TOP VIEW 10.00 (PINS DOWN) BSC SQ 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° 16 33 0.05 SEATING 0.08 MAX 17 32 PLANE COPLANARITY VIEW A 0.27 0.50 BSC 0.22 VIEW A LEAD PITCH 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 29. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD5520JST 0°C to 70°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD5520JST-REEL 0°C to 70°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 AD5520JSTZ-REEL1 0°C to 70°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2 EVAL-AD5520EB Evaluation Board and Software 1 Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03701-0-9/05(B) Rev. B | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5520JSTZ EVAL-AD5520EBZ