a Precision, Low Power BiFET Op Amp AD548 FEATURES CONNECTION DIAGRAMS Enhanced Replacement for LF441 and TL061 Plastic Mini-DIP (N) Package DC Performance: and 200 (cid:1)A max Quiescent Current SOIC (R)Package 10 pA max Bias Current, Warmed Up (AD548C) 250 (cid:1)V max Offset Voltage (AD548C) 2 (cid:1)V/(cid:2)C max Drift (AD548C) OFFSET NULL 1 8 NC 2 (cid:1)V p-p Noise, 0.1 Hz to 10 Hz INVERTING 2 7 V+ INPUT AC Performance: NONINVERTING 3 6 OUTPUT 1.8 V/(cid:1)s Slew Rate INPUT 1 MHz Unity Gain Bandwidth V– 4 AD548 5 OFFSET TOP VIEW NULL Available in Plastic and Hermetic Metal Can Packages and in Chip Form Available in Tape and Reel in Accordance with NOTE: PIN 4 CONNECTED TO CASE NC = NO CONNECT EIA-481A Standard MIL-STD-883B Parts Available Dual Version Available: AD648 10k(cid:3) Surface-Mount (SOIC) Package Available 1 5 PRODUCT DESCRIPTION 4 –15V The AD548 is a low power, precision monolithic operational VOS TRIM TOP VIEW amplifier. It offers both low bias current (10 pA max, warmed up) and low quiescent current (200 µA max) and is fabricated with ion-implanted FET and laser wafer trimming technologies. Input bias current is guaranteed over the AD548’s entire common-mode voltage range. PRODUCT HIGHLIGHTS The economical J grade has a maximum guaranteed input offset 1. A combination of low supply current, excellent dc and ac voltage of less than 2 mV and an input offset voltage drift of less performance and low drift makes the AD548 the ideal op than 20 µV/°C. This level of dc precision is achieved utilizing amp for high performance, low power applications. Analog’s laser wafer drift trimming process. The combination of 2. The AD548 is pin compatible with industry standard op low quiescent current and low offset voltage drift minimizes amps such as the LF441, TL061, and AD542, enabling changes in input offset voltage due to self-heating effects. designers to improve performance while achieving a reduction The AD548 is recommended for any dual supply op amp applica- in power dissipation of up to 85%. tion requiring low power and excellent dc and ac performance. 3. Guaranteed low input offset voltage (2 mV max) and drift In applications such as battery-powered, precision instrument (20 µV/°C max) for the AD548J are achieved utilizing front ends and CMOS DAC buffers, the AD548’s excellent com- Analog Devices’ laser drift trimming technology, eliminating bination of low input offset voltage and drift, low bias current, the need for external trimming. and low 1/f noise reduces output errors. High common-mode 4. Analog Devices specifies each device in the warmed-up rejection (82 dB, min on the “B” grade) and high open-loop condition, insuring that the device will meet its published gain ensures better than 12-bit linearity in high impedance, specifications in actual use. buffer applications. 5. A dual version, the AD648, is also available. The AD548 is pinned out in a standard op amp configuration and is available in three performance grades. The AD548J and 6. Enhanced replacement for LF441 and TL061. AD548K are rated over the commercial temperature range of 0°C to 70°C. The AD548B is rated over the industrial tempera- ture range of –40°C to +85°C. The AD548 is available in an 8-lead plastic mini-DIP and surface-mount (SOIC) packages. REV.D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD548–SPECIFICATIONS (@ 25(cid:2)C and V = (cid:4)15V dc unless otherwise noted.) S AD548J AD548K/B Parameter Min Typ Max Min Typ Max Unit INPUT OFFSET VOLTAGE1 Initial Offset 0.75 2.0 0.3 0.5 mV T to T 3.0/3.0/3.0 0.7/0.8 mV MIN MAX vs. Temperature 20 5 µV/°C vs. Supply 80 86 dB vs. Supply, T to T 76/76/76 80 dB MIN MAX Long-Term Offset Stability 15 15 µV/Month INPUT BIAS CURRENT Either Input2, V = 0 5 20 3 10 pA CM Either Input2 at T , V = 0 0.45/1.3/20 0.25/0.65 nA MAX CM Max Input Bias Current Over Common-Mode Voltage Range 30 15 pA Offset Current, V = 0 5 10 2 5 pA CM Offset Current at T 0.25/0.65/10 0.15/0.35 nA MAX INPUT IMPEDANCE Differential 1 × 1012(cid:1)3 1 × 1012(cid:1)3 Ω(cid:1)pF Common Mode 3 × 1012(cid:1)3 3 × 1012(cid:1)3 Ω(cid:1)pF INPUT VOLTAGE RANGE Differential3 ±20 ±20 V Common Mode ±11 ±12 ±11 ±12 V Common-Mode Rejection V = ±10 V 76 90 82 92 dB CM T to T 76/76/76 90 82 92 dB MIN MAX V = ±11 V 70 84 76 86 dB CM T to T 70/70/70 84 76 86 dB MIN MAX INPUT VOLTAGE NOISE Voltage 0.1 Hz to 10 Hz 2 2 µV p-p f = 10 Hz 80 80 nV/√Hz f = 100 Hz 40 40 nV/√Hz f = 1 kHz 30 30 nV/√Hz f = 10 kHz 30 30 nV/√Hz INPUT CURRENT NOISE f = 1 kHz 1.8 1.8 fA/√Hz FREQUENCY RESPONSE Unity Gain, Small Signal 0.8 1.0 0.8 1.0 MHz Full Power Response 30 30 kHz Slew Rate, Unity Gain 1.0 1.8 1.0 1.8 V/µs Settling Time to ±0.01% 8 8 µs OPEN LOOP GAIN V = ±10 V, R ≥ 10 kΩ 300 1000 300 1000 3V/mV O L T to T , R ≥ 10 kΩ 300/300/300 700 300 700 V/mV MIN MAX L V = ±10 V, R ≥ 5 kΩ 150 500 150 500 V/mV O L T to T , R ≥ 5 kΩ 150/150/150 300 150 300 V/mV MIN MAX L OUTPUT CHARACTERISTICS Voltage @ R ≥ 10 kΩ, ±12 ±13 ±12 ±13 V L T to T ±12/±12/±12 ±12 MIN MAX Voltage @ R ≥ 5 kΩ, ±11 ±12.3 ±11 ±12.3 V L T to T ±11/±11/±11 ±11 MIN MAX Short Circuit Current 15 15 mA –2– REV. D

AD548 SPECIFICATIONS (continued) AD548J AD548K/B Min Typ Max Min Typ Max Unit POWER SUPPLY Rated Performance ±15 ±15 V Operating Range ±4.5 ±18 ±4.5 ±18 V Quiescent Current 170 200 170 200 µA TEMPERATURE RANGE Operating, Rated Performance Commercial (0°C to 70°C) AD548J AD548K Industrial (–40°C to +85°C) AD548A AD548B Military (–55°C to +125°C) AD548S PACKAGE OPTIONS SOIC (R-8) AD548JR AD548KR4 Plastic (N-8) AD548JN4 AD548KN Tape and Reel AD548JR-REEL AD548KR-REEL4 NOTES 1Input Offset Voltage specifications are guaranteed after five minutes of operation at TA = 25°C. 2Bias Current specifications are guaranteed maximum at either input after five minutes of operation at TA = 25°C. For higher temperature, the current doubles every 10°C. 3Defined as voltages between inputs, such that neither exceeds ±10 V from ground. 4Not recommended for new designs; obsolete April 2002. Specifications subject to change without notice. REV. D –3–

AD548 ABSOLUTE MAXIMUM RATINGSl NOTES Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V 1Stresses above those listed under Absolute Maximum Ratings may cause Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . .500 mW permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the Input Voltage3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±18 V operational sections of this specification is not implied. Exposure to absolute Output Short Circuit Duration . . . . . . . . . . . . . . . . .Indefinite maximum rating conditions for extended periods may affect device reliability. DStioffreargeen Ttiaelm Inpepruatt uVroel tRaagneg e. .( Q. ., .H . ). . .. .. .. .. .. .. .. –. 6. 5.°C+V tSo a+n1d5 –0V°CS 2T8-hLeremada lP Clahstairca Pctaecrkisatgices: : θ8JA- P=i n9 0S°OCI/CW .Package: θJA = 160°C/W, θJC = 42°C/W; (N, R) . . . . . . . .–65°C to +125°C 3For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. Operating Temperature Range AD548J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0°C to 70°C AD548B . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD548 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –4– REV. D

Typical Performance Characteristics–AD548 20 20 30 +VOUT p ±LTAGE – V 1150 +VIN ±AGE SWING – V 1150 –VOUT GE SWING – V p- 221505 O T A INPUT V 5 –VIN TPUT VOL 5 2R5L° =C 10k(cid:3) PUT VOLT 10 U T O U 5 O 0 0 0 0 5 10 15 20 0 5 10 15 20 10 100 1k 10k SUPPLY VOLTAGE – (cid:4)V SUPPLY VOLTAGE – (cid:4)V LOAD RESISTANCE – TPC 1.Input Voltage Range TPC 2.Output Voltage Swing TPC 3.Output Voltage Swing vs. Supply Voltage vs. Supply Voltage vs. Load Resistance 200 10 100nA 10nA A A 8 ESCENT CURRENT – µ118600 UT BIAS CURRENT – p 64 NPUT BIAS CURRENT1011001npppAAAA QUI 140 INP 2 I 100fA 120 0 10fA 0 5 10 15 20 0 4 8 12 16 20 –55 –25 5 35 65 95 125 SUPPLY VOLTAGE – (cid:4)V SUPPLY VOLTAGE – (cid:4)V TEMPERATURE – °C TPC 4.Quiescent Current vs. TPC 5.Input Bias Current TPC 6.Input Bias Current vs. Supply Voltage vs. Supply Voltage Temperature 10 30 1500 RL = 10k(cid:3) 25 1250 A 8 V p m S CURRENT – 6 (cid:1)VI – VOS2105 OP GAIN – V/1705000 T BIA 4 ∆I 10 N LO 500 U E P P IN 2 5 O 250 0 0 0 –10 –6 –2 2 6 10 0 10 20 30 40 50 60 70 –55 –25 5 35 65 95 125 COMMON-MODE VOLTAGE – V WARM-UP TIME – Sec TEMPERATURE – °C TPC 7.Input Bias Current vs. TPC 8.Change in Offset Voltage TPC 9.Open-Loop Gain vs. Common-Mode Voltage vs. Warm-Up Time Temperature REV. D –5–

AD548 100 100 120 120 OP GAIN – dB 864000 PGHAAINSE 486000 N DEGREES OLTAGE GAIN – dB11901000 Y REJECTION – dB1086000 +SUPPLY OPEN LO–22000 2–0020PHASE I OPEN LOOP V 8700 OWER SUPPL 24000 –SUPPLY P –40 –40 60 –20 1k 10k 100k 1M 10M 0 2 4 6 8 10 12 14 16 18 100 1k 10k 100k 1M FREQUENCY – Hz SUPPLY VOLTAGE – (cid:4)V FREQUENCY – Hz TPC 10.Open-Loop Frequency TPC 11.Open-Loop Voltage Gain TPC 12.PSRR vs. Frequency Response vs. Supply Voltage 90 22 10 10mV 20 80 70 V p-p 1186 NG – V 5 1mV CMRR – dB 6500 VOLTAGE – 111042 OLTAGE SWI 0 UT 8 T V 4300 OUTP 64 OUTPU –5 1mV 2 10mV 201k 10k 100k 1M 010 100 1k 10k 100k 1M –100 2 4 6 8 FREQUENCY – Hz FREQUENCY – Hz SETTLING TIME – µs TPC 13.CMRR vs. Frequency TPC 14.Large Signal Frequency TPC 15.Output Swing and Error Response Voltage vs. Output Settling Time 4 160 WHENEVER JOHNSON NOISE IS GREATER THAN AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE ON – % 1 √nV/Hz112400 V p-p10,000 CONSIDERED NEGLIG1IBkLHEz F BOARN ADPPWLIIDCATTHION C DISTORTI 0.1 WFITOHL GLOAWINE =R 10 OLTAGE – 18000 LTAGE – µ 1,010000 RESISTNOORI SJOEHNSON TOTAL HARMONI0.01 UNITY GAIN INPUT NOISE V 246000 NPUT NOISE VO 101 BAN1D0WHzIDTH FOLLOWER I AMPLIFIER GENERATED NOISE 0.001 0 0 100 1k 10k 100k 10 100 1k 10k 100k 100k 1M 10M 100M 1G 10G 100G FREQUENCY – Hz FREQUENCY – Hz SOURCE IMPEDANCE – (cid:3) TPC 16.Total Harmonic TPC 17.Input Noise Voltage TPC 18.Total Noise vs. Source Distortion vs. Frequency Spectral Density Impedance –6– REV. D

AD548 TPC 19a.Unity Gain Follower TPC 19b.Unity Gain Follower TPC 19c.Unity Gain Follower Pulse Response (Large Signal) Pulse Response (Small Signal) TPC 20a. Utility Gain Inverter TPC 20b. Utility Gain Inverter TPC 20c.Unity Gain Inverter Pulse Response (Large Signal) Pulse Response (Small Signal) APPLICATION NOTES The AD548 is a JFET-input op amp with a guaranteed maxi- mum I of less than 10 pA, and offset and drift laser-trimmed to B 0.5 mV and 5 µV/°C, respectively (AD548B). AC specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and 8 µs settling time for a 20 V step to ±0.01%—all at a supply current less than 200 µA. To capitalize on the device’s performance, a number of error sources should be considered. The minimal power drain and low offset drift of the AD548 reduce self-heating or “warm-up” effects on input offset voltage, making the AD548 ideal for on/off battery-powered applica- Figure 1.Offset Null Configuration tions. The power dissipation due to the AD548’s 200 µA supply current has a negligible effect on input current, but heavy out- LAYOUT put loading will raise the chip temperature. Since a JFET’s To take full advantage of the AD548’s 10 pA max input current, input current doubles for every 10°C rise in chip temperature, parasitic leakages must be kept below an acceptable level. The this can be a noticeable effect. practical limit of the resistance of epoxy or phenolic circuit board material is between 1 × 1012 Ω and 3 × 1012 Ω. This can The amplifier is designed to be functional with power supply voltages as low as ±4.5 V. It will exhibit a higher input offset result in an additional leakage of 5 pA between an input of 0 V voltage than at the rated supply voltage of ±15 V, due to power and a –15 V supply line. Teflon® or a similar low leakage mate- rial (with a resistance exceeding 1017 Ω) should be used to supply rejection effects. The common-mode range of the AD548 isolate high impedance input lines from adjacent lines carrying extends from 3 V more positive than the negative supply to 1 V high voltages. The insulator should be kept clean, since con- more negative than the positive supply. Designed to cleanly drive up to 10 kΩ and 100 pF loads, the AD548 will drive a 2 taminants will degrade the surface resistance. kΩ load with reduced open-loop gain. A metal guard completely surrounding the high impedance nodes and driven by a voltage near the common-mode input potential OFFSET NULLING can also be used to reduce some parasitic leakages. The guarding Unlike bipolar input amplifiers, zeroing the input offset voltage pattern in Figure 2 will reduce parasitic leakage due to finite of a BiFET op amp will not minimize offset drift. Using balance board surface resistance; but it will not compensate for a low Pins 1 and 5 to adjust the input offset voltage as shown in volume resistivity board. Figure 1 will induce an added drift of 0.24 µV/°C per 100 µV of nulled offset. The low initial offset (0.5 mV) of the AD548B results in only 0.6 µV/°C of additional drift. Teflon is a registered trademark of DuPont. REV. D –7–

AD548 Figure 2.Board Layout for Guarding Inputs INPUT PROTECTION The AD548 is guaranteed to withstand input voltages equal to Figure 4.AD548 Used as DAC Output Amplifier the power supply potential. Exceeding the negative supply volt- That is: age on either input will forward bias the substrate junction of tehxec ecshsi ph.e aTt.he induced current may destroy the amplifier due to VOSOutput=VOS Input1+RRFB O Input protection is required in applications such as a flame R is the feedback resistor for the op amp, which is internal to detector in a gas chromatograph, where a very high potential FB the DAC. R is the DAC’s R-2R ladder output resistance. The may be applied to the input terminals during a sensor fault O value of R is code dependent. This has the effect of changing condition. Figure 3 shows a simple current limiting scheme that O the offset error voltage at the amplifier’s output. An output can be used. R should be chosen such that the maxi- PROTECT amplifier with a sub millivolt input offset voltage is needed to mum overload current is 1.0 mA (l00 kΩ for a 100 V overload, preserve the linearity of the DAC’s transfer function. for example). The AD548 in this configuration provides a 700 kHz small Exceeding the negative common-mode range on either input signal bandwidth and 1.8 V/µs typical slew rate. The 33 pF terminal causes a phase reversal at the output, forcing the capacitor across the feedback resistor optimizes the circuit’s amplifier output to the corresponding high or low state. Exceed- response. The oscilloscope charts in Figures 5 and 6 show small ing the negative common-mode on both inputs simultaneously and large signal outputs of the circuit in Figure 4. Upper traces forces the output high. Exceeding the positive common-mode show the input signal V . Lower traces are the resulting output range on a single input does not cause a phase reversal, but if IN voltage with the DAC’s digital input set to all 1s. The AD548 both inputs exceed the limit the output will be forced high. In settles to ±0.01% for a 20 V input step in 14 µs. all cases, normal amplifier operation is resumed when input voltages are brought back within the common-mode range. 5V 20V 5µS 100 90 10 0% Figure 5.Response to ±20 V p-p Reference Square Wave Figure 3.Input Protection of IV Converter 50mV 200mV 2µS D/A CONVERTER OUTPUT BUFFER 10900 The circuit in Figure 4 shows the AD548 and AD7545 12-bit CMOS D/A converter in a unipolar binary configuration. V OUT will be equal to V attenuated by a factor depending on the REF digital word. V sets the full scale. Overall gain is trimmed by REF adjusting R . The AD548’s low input offset voltage, low drift, IN 10 and clean dynamics make it an attractive low power output buffer. 0% The input offset voltage of the AD548 output amplifier results in an output error voltage. This error voltage equals the input Figure 6.Response to ±100 mV p-p Reference Square Wave offset voltage of the op amp times the noise gain of the amplifier. –8– REV. D

Application Hints–AD548 PHOTODIODE PREAMP The performance of the photodiode preamp shown in Figure 7 is enhanced by the AD548’s low input current, input voltage offset, and offset voltage drift. The photodiode sources a current proportional to the incident light power on its surface. R converts F the photodiode current to an output voltage equal to R × I . F S Figure 7. An error budget illustrating the importance of low amplifier Figure 9.Low Power Instrumentation Amplifier input current, voltage offset, and offset voltage drift to minimize Gains of 1 to 100 can be accommodated with gain nonlinearities output voltage errors can be developed by considering the equi- of less than 0.01%. Input errors, which contribute an output valent circuit for the small (0.2 mm2 area) photodiode shown in error proportional to in amp gain, include a maximum untrimmed Figure 7. The input current results in an error proportional to input offset voltage of 0.5 mV and an input offset voltage drift the feedback resistance used. The amplifier’s offset will produce over temperature of 4 µV/°C. Output errors, which are indepen- an error proportional to the preamp’s noise gain (I + R /R ), F SH dent of gain, will contribute an additional 0.5 mV offset and where R is the photodiode shunt resistance. The amplifier’s input cuSrHrent will double with every 10°C rise in temperature, 4 µV/°C drift. The maximum input current is 15 pA over the and the photodiode’s shunt resistance halves with every 10°C common-mode range, with a common-mode impedance of over 1 × 1012 Ω. Resistor pairs R3/R5 and R4/R6 should be ratio rise. The error budget in Figure 8 assumes a room temperature photodiode R of 500 MΩ, and the maximum input current matched to 0.01% to take full advantage of the AD548’s high SH common-mode rejection. Capacitors C1 and C1′ compensate for and input offset voltage specs of an AD548C. peaking in the gain over frequency caused by input capacitance when gains of 1 to 3 are used. TEMP (cid:2)C RSH (M(cid:3)) VOS ((cid:1)V) (1+ RF/RSH) VOS IB (pA) IBRF TOTAL The –3 dB small signal bandwidth for this low power instrumenta- –25 15,970 150 151 µV 0.30 30 µV 181 µV tion amplifier is 700 kHz for a gain of 1 and 10 kHz for a gain of 0 2,830 200 207 µV 2.26 262 µV 469 µV 100. The typical output slew rate is 1.8 V/µs. 25 500 250 300 µV 10.00 1.0 mV 1.30 mV 50 88.5 300 640 µV 56.6 5.6 mV 6.24 mV LOG RATIO AMPLIFIER 75 15.6 350 2.6 mV 320 32 mV 34.6 mV Log ratio amplifiers are useful for a variety of signal conditioning 85 7.8 370 5.1 mV 640 64 mV 69.1 mV applications, such as linearizing exponential transducer outputs Figure 8. Photodiode Preamp Errors Over Temperature and compressing analog signals having a wide dynamic range. The AD548’s picoamp level input current and low input offset The capacitance at the amplifier’s negative input (the sum of the voltage make it a good choice for the front-end amplifier of the photodiode’s shunt capacitance, the op amp’s differential input log ratio circuit shown in Figure 10. This circuit produces an capacitance, stray capacitance due to wiring, etc.) will cause a output voltage equal to the log base 10 of the ratio of the input rise in the preamp’s noise gain over frequency. This can result in currents I and I . Resistive inputs R1 and R2 are provided for excess noise over the bandwidth of interest. C reduces the 1 2 F voltage inputs. noise gain “peaking” at the expense of bandwidth. Input currents I and I set the collector currents of Q1 and Q2, 1 2 INSTRUMENTATION AMPLIFIER a matched pair of logging transistors. Voltages at points A and The AD548C’s maximum input current of 10 pA makes it an B are developed according to the following familiar diode excellent building block for the high input impedance instru- equation: mentation amplifier shown in Figure 9. Total current drain for V =(kT/q)ln(I /I ) this circuit is under 600 µA. This configuration is optimal for BE C ES In this equation, k is Boltzmann’s constant, T is absolute tem- conditioning differential voltages from high impedance sources. perature, q is an electron charge, and I is the reverse saturation ES The overall gain of the circuit is controlled by R , resulting in G current of the logging transistors. The difference of these two the following transfer function: voltages is taken by the subtractor section and scaled by a factor V (R +R ) of approximately 16 by resistors R9, R10, and R8. Temperature OUT =1+ 1 2 V R IN G REV. D –9–

AD548 compensation is provided by resistors R8 and R15 that have a positive 3500 ppm/°C temperature coefficient. The transfer function for the output voltage is: V =1V log (I /I ) OUT 10 2 1 Frequency compensation is provided by R11, R12, C1, and C2. Small signal bandwidth is approximately 300 kHz at input cur- rents above 100 µA and will proportionally decrease with lower signal levels. D1, D2, R13, and R14 compensate for the effects of the two logging transistors’ ohmic emitter resistance. To trim this circuit, set the two input currents to 10 µA and adjust V to zero by adjusting the potentiometer on A3. Then set I OUT 2 to 1 µA and adjust the scale factor such that the output voltage is 1 V by trimming potentiometer R10. Offset adjustment for A1 and A2 is provided to increase the accuracy of the voltage inputs. This circuit ensures a 1% log conformance error over an input current range of 300 pA to 1 mA, with low level accuracy limited by the AD548’s input current. The low level input voltage accuracy of this circuit is limited by the input offset voltage and drift of the AD548. Figure 10. Log Ratio Amplifier –10– REV. D

AD548 OUTLINE DIMENSIONS Plastic Mini-DIP (N) Package SOIC (R) Package Dimensions shown in inches and (millimeters) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 0.1574 (4.00) 6.20 (0.2440) 0.1497 (3.80) 1 4 5.80 (0.2284) PIN 1 1.27 (0.0500) 0.50 (0.0196)(cid:5) 45(cid:2) BSC 0.25 (0.0099) COPLANARITY 1.75 (0.0688) 0.25 (0.0098) 1.35 (0.0532) 0.10 (0.0040) 8(cid:2) SEATING 0.51 (0.0201) 0.25 (0.0098)0(cid:2) 1.27 (0.0500) PLANE 0.33 (0.0130) 0.19 (0.0075) 0.41 (0.0160) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012 AA Revision History Location Page Data Sheet changed from REV. C to REV. D. Change to SOIC (R-8) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Deleted TO-99 CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Deleted AD548C from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Deleted Metal Can from Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Deleted TO-99 (H) and Cerdip (Q) Packages from OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 REV. D –11–

D) 2( 0 5/ – 0 – 0 1 5 0 0 C A. S. U. N D I E T N RI P –12–

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD548KNZ AD548JRZ-REEL7 AD548JRZ