8-/10-/12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5450/AD5451/AD5452/AD5453 FEATURES FUNCTIONAL BLOCK DIAGRAM 12 MHz multiplying bandwidth VDD VREF Integral nonlinearity (INL) of ±0.25 LSB at 8-bit 8-lead TSOT and MSOP packages AD5450/ R RFB 2.5 V to 5.5 V supply operation AD5451/ Pin-compatible 8-/10-/12-/14-bit current output DACs AADD55445523/ 8-/10-R/1-22-R/1 4D-ABCIT REF IOUT1 ±10 V reference input 50 MHz serial interface 2.7 MSPS update rate DAC REGISTER POWER-ON Extended temperature range: –40°C to +125°C RESET 4-quadrant multiplication INPUT LATCH Power-on reset with brownout detect <0.4 µA typical current consumption SYNC CONTROL LOGIC Guaranteed monotonic SCLK AND INPUT SHIFT Qualified for automotive applications SDIN REGISTER 04587-001 APPLICATIONS GND Figure 1. Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming Qualified for automotive applications GENERAL DESCRIPTION The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/12-/ The applied external reference input voltage (V ) determines REF 14-bit current output digital-to-analog converters (DACs), respect- the full-scale output current. These devices can handle ±10 V tively. These devices operate from a 2.5 V to 5.5 V power supply, inputs on the reference, despite operating from a single-supply making them suited to several applications including battery- power supply of 2.5 V to 5.5 V. An integrated feedback resistor powered applications. (R ) provides temperature tracking and full-scale voltage FB output when combined with an external current to voltage As a result of manufacture on a CMOS submicron process, these precision amplifier. DACs offer excellent 4-quadrant multiplication characteristics of up to 12 MHz. The AD5450/AD5451/AD5452/AD5453 DACs are available in small 8-lead TSOT, and the AD5452/AD5453 are also available These DACs use a double-buffered, 3-wire serial interface that in MSOP packages. The AD5453 also comes in 8-lead LFCSP. is compatible with SPI, QSPI™, MICROWIRE™, and most digital signal processor (DSP) interface standards. Upon power-up, the internal shift register and latches are filled with 0s, and the DAC output is at zero scale. 1 U.S. Patent Number 5,689,257. Rev. H Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5450/AD5451/AD5452/AD5453 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Section................................................................................ 16 Applications ....................................................................................... 1 Circuit Operation ....................................................................... 16 Functional Block Diagram .............................................................. 1 Single-Supply Applications ....................................................... 18 General Description ......................................................................... 1 Adding Gain ................................................................................ 18 Revision History ............................................................................... 2 Divider or Programmable Gain Element ................................ 19 Specifications ..................................................................................... 3 Reference Selection .................................................................... 19 Timing Characteristics ................................................................ 5 Amplifier Selection .................................................................... 19 Absolute Maximum Ratings ............................................................ 6 Serial Interface ............................................................................ 21 ESD Caution .................................................................................. 6 Microprocessor Interfacing ....................................................... 22 Pin Configurations and Function Descriptions ........................... 7 PCB Layout and Power Supply Decoupling ........................... 24 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 26 Terminology .................................................................................... 15 Ordering Guide .......................................................................... 27 General Description ....................................................................... 16 Automotive Products ................................................................. 27 REVISION HISTORY 12/15—Rev. G to Rev. H 3/11—Rev. D to Rev. E Changed LFCSP_WD to LFCSP .................................. Throughout Changes to SYNC Function Section ............................................ 21 Changes to Applications Section and General Added Figure 54 (Renumbered Sequentially) ............................ 21 Description Section .......................................................................... 1 Added Figure 55 and Table 11 ..................................................... 22 Deleted Positive Output Voltage Section and Figure 47............ 18 2/11—Rev. C to Rev. D Changes to Adding Gain Section ................................................. 19 Added 8-Lead LFCSP ......................................................... Universal Changes to ADSP-21xx Processors to AD5450/AD5451/AD5452/ Changes to Features Section ............................................................ 1 AD5453 Interface Section and Figure 56 ....................................... 23 Updated Outline Dimensions ....................................................... 27 Changes to ADSP-BF504 to ADSP-BF592 Device Family to Changes to Ordering Guide .......................................................... 28 AD5450/AD5451/AD5452/AD5453 Interface Section, MC68HC11 Added Automotive Products Section .......................................... 28 to AD5450/AD5451/AD5452/AD5453 Interface Section, 1/10—Rev. B to Rev. C Figure 57 Caption, and Figure 58 Caption .................................. 24 Changes to DAC Control Bits C1, C0 .......................................... 21 Changes to PIC16C6x/PIC16C7x to AD5450/AD5451/AD5452/ Updated Outline Dimensions ....................................................... 27 AD5453 Interface Section .............................................................. 25 Changes to Ordering Guide .......................................................... 28 Changes to Table 13 Title............................................................... 26 Changes to Ordering Guide .......................................................... 29 3/06—Rev. A to Rev. B Updated Format .................................................................. Universal 6/13—Rev. F to Rev. G Changes to Features .......................................................................... 1 Change to General Description Section ........................................ 1 Changes to General Description ..................................................... 1 Change to Figure 56 and Figure 57 .............................................. 22 Changes to Specifications ................................................................. 4 Updated Outline Dimensions ....................................................... 27 Changes to Figure 27 and Figure 28 ............................................ 11 Changes to Ordering Guide .......................................................... 27 Change to Table 9 ........................................................................... 20 4/12—Rev. E to Rev. F Changes to Table 12 ....................................................................... 26 Changes to General Description Section ...................................... 1 Updated Outline Dimensions ....................................................... 27 Deleted Evaluation Board for the DAC Section, Power Supplies Changes to Ordering Guide .......................................................... 28 for the Evaluation Board Section, and Figure 64; 7/05—Rev. 0 to Rev. A Renumbered Sequentially .............................................................. 25 Added AD5453 .................................................................... Universal Deleted Figure 65 and Figure 66 ................................................... 26 Changes to Specifications ................................................................. 4 Deleted Figure 67 ............................................................................ 27 Change to Figure 21 ....................................................................... 10 Changes to Ordering Guide .......................................................... 27 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 28 1/05—Revision 0: Initial Version Rev. H | Page 2 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 10 V. Temperature range for Y version: −40°C to +125°C. All specifications T to T , unless otherwise DD REF MIN MAX noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE AD5450 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic Total Unadjusted Error ±0.5 LSB Gain Error ±0.25 LSB AD5451 Resolution 10 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±0.5 LSB Guaranteed monotonic Total Unadjusted Error ±0.5 LSB Gain Error ±0.25 LSB AD5452 Resolution 12 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Total Unadjusted Error ±1 LSB Gain Error ±0.5 LSB AD5453 Resolution 14 Bits Relative Accuracy ±2 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Total Unadjusted Error ±4 LSB Gain Error ±2.5 LSB Gain Error Temperature Coefficient1 ±2 ppm FSR/°C Output Leakage Current ±1 nA Data = 0x0000, T = 25°C, I 1 A OUT ±10 nA Data = 0x0000, T = −40°C to +125°C, I 1 A OUT REFERENCE INPUT1 Reference Input Range ±10 V V Input Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C REF R Feedback Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C FB Input Capacitance Zero-Scale Code 18 22 pF Full-Scale Code 18 22 pF DIGITAL INPUTS/OUTPUTS1 Input High Voltage, V 2.0 V V = 3.6 V to 5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5 V, I = 200 µA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 µA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5 V, I = 200 µA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 µA DD SINK Input Leakage Current, I ±1 nA T = 25°C IL A ±10 nA T = −40°C to +125°C A Input Capacitance 10 pF Rev. H | Page 3 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Reference Multiplying BW 12 MHz V = ±3.5 V, DAC loaded with all 1s REF Multiplying Feedthrough Error V = ±3.5 V, DAC loaded with all 0s REF 72 dB 100 kHz 64 dB 1 MHz 44 dB 10 MHz Output Voltage Settling Time V = 10 V, R = 100 Ω; DAC latch alternately REF LOAD loaded with 0s and 1s Measured to ±1 mV of FS 100 110 ns Measured to ±4 mV of FS 24 40 ns Measured to ±16 mV of FS 16 33 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 10 30 ns Rise and fall times, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V = 0 V REF Output Capacitance I 1 13 pF DAC latches loaded with all 0s OUT 28 pF DAC latches loaded with all 1s I 2 18 pF DAC latches loaded with all 0s OUT 5 pF DAC latches loaded with all 1s Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 83 dB V = 3.5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 1 MHz, V = 3.5 V REF 50 kHz f 71 dB OUT 20 kHz f 77 dB OUT Output Noise Spectral Density 25 nV/√Hz At 1 kHz SFDR Performance (Wide Band) Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 78 dB 20 kHz fOUT 74 dB SFDR Performance (Narrow Band) Clock = 1 MHz, VREF = 3.5 V 50 kHz fOUT 87 dB 20 kHz fOUT 85 dB Intermodulation Distortion 79 dB f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, VREF = 3.5 V POWER REQUIREMENTS Power Supply Range 2.5 5.5 V IDD 0.4 10 µA TA = −40°C to +125°C, logic inputs = 0 V or VDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5% 1 Guaranteed by design and characterization, not subject to production test. Rev. H | Page 4 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. V = 2.5 V to 5.5 V, R F DD IL IH DD V = 10 V, temperature range for Y version: −40°C to +125°C. All specifications T to T , unless otherwise noted. REF MIN MAX Table 2. Parameter1 V = 2.5 V to 5.5 V Unit Description DD f 50 MHz max Maximum clock frequency SCLK t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t4 8 ns min SYNC falling edge to SCLK active edge setup time t 5 ns min Data setup time 5 t 4.5 ns min Data hold time 6 t7 5 ns min SYNC rising edge to SCLK active edge t8 30 ns min Minimum SYNC high time Update Rate 2.7 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. t1 SCLK t2 t3 t8 t4 t7 SYNC t6 DIN DB15 t5 DB0 04587-002 Figure 2. Timing Diagram Rev. H | Page 5 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses at or above those listed under Absolute Maximum T = 25°C, unless otherwise noted. A Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 3. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V DD the maximum operating conditions for extended periods may V , R to GND −12 V to +12 V REF FB affect product reliability. I 1 to GND −0.3 V to +7 V OUT Input Current to Any Pin Except Supplies ±10 mA ESD CAUTION Logic Inputs and Output1 −0.3 V to V + 0.3 V DD Operating Temperature Range, Extended −40°C to +125°C (Y Version) Storage Temperature Range −65°C to +150°C Junction Temperature 150°C θ Thermal Impedance JA 8-Lead MSOP 206°C/W 8-Lead TSOT 211°C/W Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. Rev. H | Page 6 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RFB 1 AD5450/ 8 IOUT1 VREF 2 AD5451/ 7 GND SYVNDCD 34 AADD55445523/ 65 SSCDLINK 04587-003 Figure 3. 8-Lead TSOT Pin Configuration IOUT1 1 8 RFB GND 2 AD5452/ 7 VREF SSCDLINK 34 AD5453 65 VSDYDNC 04587-004 Figure 4. 8-Lead MSOP Pin Configuration IOUT1 1 8 RFB AD5453 GND 2 7 VREF TOP VIEW SCLK 3 (Not to Scale) 6 VDD SDIN 4 5 SYNC N1 . O TCTHOEENS NEEXCPOTESDEDTOPA GDR MOUUSNTD .BE 04587-205 Figure 5. 8-Lead LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No1 TSOT MSOP LFCSP Mnemonic Description 1 8 8 R DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external FB amplifier output. 2 7 7 V DAC Reference Voltage Input. REF 3 6 6 V Positive Power Supply Input. These devices can operate from a supply of 2.5 V to 5.5 V. DD 4 5 5 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. Data is loaded to the shift register upon the active edge of the following clocks. 5 4 4 SDIN Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial clock input. By default, in power-up mode data is clocked into the shift register upon the falling edge of SCLK. The control bits allow the user to change the active edge to a rising edge. 6 3 3 SCLK Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register upon the rising edge of SCLK. 7 2 2 GND Ground Pin. 8 1 1 I 1 DAC Current Output. OUT N/A N/A EPAD EPAD Exposed pad must be connected to ground. 1 N/A = not applicable. Rev. H | Page 7 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.25 2.0 TA = 25°C TA = 25°C 0.20 VREF = 10V 1.6 VREF = 10V VDD = 5V VDD = 5V 0.15 1.2 0.10 0.8 0.05 0.4 B) B) S S L 0 L 0 L ( L ( N N I –0.05 I –0.4 –0.10 –0.8 –0.15 –1.2 ––00..2250 04587-020 ––21..06 04587-023 0 32 64 96 128 160 192 224 256 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 6. INL vs. Code (8-Bit DAC) Figure 9. INL vs. Code (14-Bit DAC) 0.25 0.5 TA = 25°C TA = 25°C 0.20 VREF = 10V 0.4 VREF = 10V VDD = 5V VDD = 5V 0.15 0.3 0.10 0.2 INL (LSB) –00..00550 DNL (LSB) –00..101 –0.10 –0.2 –0.15 –0.3 ––00..2250 04587-021 ––00..54 04587-024 0 128 256 384 512 640 768 896 1024 0 32 64 96 128 160 192 224 256 CODE CODE Figure 7. INL vs. Code (10-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC) 0.5 0.5 TA = 25°C TA = 25°C 0.4 VREF = 10V 0.4 VREF = 10V VDD = 5V VDD = 5V 0.3 0.3 0.2 0.2 INL (LSB) –00..101 DNL (LSB) –00..101 –0.2 –0.2 –0.3 –0.3 ––00..54 04587-022 ––00..54 04587-025 0 512 1024 1536 2048 2560 3072 2584 4096 0 128 256 384 512 640 768 896 1024 CODE CODE Figure 8. INL vs. Code (12-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC) Rev. H | Page 8 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 1.0 2.0 0.8 TVVARD ED=F = 2= 55 °1VC0V 1.5 TVAADD D5= 4 =25 552°VC 0.6 1.0 0.4 0.5 MAX DNL B) 0.2 B) S S L (L 0 L (L 0 N N MIN DNL D –0.2 D –0.5 –0.4 –1.0 –0.6 ––10..08 04587-026 ––21..05 04587-071 0 512 1024 1536 2048 2560 3072 2584 4096 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 12. DNL vs. Code (12-Bit DAC) Figure 15. DNL vs. Reference Voltage 2.0 0.5 TA = 25°C TA = 25°C 1.6 VREF = 10V 0.4 VREF = 10V VDD = 5V VDD = 5V 1.2 0.3 AD5450 0.8 0.2 B) 0.4 B) 0.1 S S L (L 0 E (L 0 N U D –0.4 T –0.1 –0.8 –0.2 –1.2 –0.3 ––21..06 04587-027 ––00..54 04587-030 0 2048 4096 6144 8192 10240 12288 14336 16384 0 32 64 96 128 160 192 224 256 CODE CODE Figure 13. DNL vs. Code (14-Bit DAC) Figure 16. TUE vs. Code (8-Bit DAC) 1.00 0.25 0.75 TVAADD D5= 4 =25 552°VC 0.20 TVVARD ED=F = 2= 55 °1VC0V 0.15 AD5451 0.50 MAX INL 0.10 0.25 B) B) 0.05 S S L (L 0 E (L 0 N U I–0.25 MIN INL T –0.05 –0.10 –0.50 –0.15 ––10..0705 04587-070 ––00..2250 04587-031 2 3 4 5 6 7 8 9 10 0 128 256 384 512 640 768 896 1024 REFERENCE VOLTAGE (V) CODE Figure 14. INL vs. Reference Voltage Figure 17. TUE vs. Code (10-Bit DAC) Rev. H | Page 9 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet 1.0 0.3 TA = 25°C 0.8 VREF = 10V VDD = 5V 0.2 0.6 0.4 B)0.1 E (LSB) 0.02 RROR (LS 0 VVDDDD == 35VV U E T –0.2 N AI –0.4 G–0.1 –0.6 –0.2 ––10..08 04587-032 –0.3 04587-073 0 512 1024 1536 2048 2560 3072 2584 4096 –60 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 18. TUE vs. Code (12-Bit DAC) Figure 21. Gain Error (LSB) vs. Temperature 2.0 2.0 TA = 25°C TA = 25°C 1.6 VVRDEDF = = 5 1V0V 1.5 VADDD5 4=5 52V 1.2 1.0 0.8 B) 0.4 LS0.5 B) R ( S O NL (L 0 ERR 0 I –0.4 N AI–0.5 –0.8 G –1.0 –1.2 ––21..06 04587-033 ––21..05 04587-074 0 2048 4096 6144 8192 10240 12288 14336 16384 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 19. TUE vs. Code (14-Bit DAC) Figure 22. Gain Error (LSB) vs. Reference Voltage 2.0 2.0 TA = 25°C 1.5 VADDD5 4=5 52V IOUT1 VDD = 5V 1.6 1.0 MAX TUE A) IOUT1VDD = 3V 0.5 n B) E ( 1.2 S G TUE (L–0.05 MIN TUE 1 LEAKA 0.8 T U O –1.0 I 0.4 ––21..05 04587-072 0 04587-039 2 3 4 5 6 7 8 9 10 –40 –20 0 20 40 60 80 100 120 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 20. TUE vs. Reference Voltage Figure 23. IOUT1 Leakage Current vs. Temperature Rev. H | Page 10 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 2.5 1.8 TA = 25°C TA = 25°C 1.6 2.0 1.4 VIH VIL V) E ( G 1.2 ENT (mA) 1.5 D VOLTA 1.0 R L 0.8 UR 1.0 HO C VDD = 5V ES 0.6 R H T 0.4 0.5 0 VDD = 3V 04587-038 0.02 04587-076 0 1 2 3 4 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) VOLTAGE (V) Figure 24. Supply Current vs. Logic Input Voltage Figure 27. Threshold Voltage vs. Supply Voltage 0.7 10 ALL 1s TA = 25°C ALL 0s 0 ALL ON LOADING 0.6 ZS TO FS DB13 –10 DB12 0.5 DB11 A) VDD = 5V –20 DB10 µRRENT ( 00..34 GAIN (dB) ––4300 DDDBBB987 U C DB6 –50 0.2 DB5 VDD = 3V –60 DDBB43 VDD = 5V 0.01 04587-037 ––8700 DB2 VCARDCEO8F0M 3=P8 ±= A3 1M.5.8PVpLFIFIER 04587-108 –40 –20 0 20 40 60 80 100 120 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 25. Supply Current vs. Temperature Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code 6 0.6 TA = 25°C AD5452 LOADING 010101010101 0.4 5 0.2 4 0 A) RENT(m3 VDD = 5V AIN (dB) ––00..24 R G U C2 –0.6 –0.8 TA = 25°C 1 VDD = 5V 0 VDD = 3V 04587-075 ––11..20 VCARDCEO8F0M 3=P8 ±= A3 1M.5.8PVpLFIFIER 04587-109 1 10 100 1k 10k 100k 1M 10M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 26. Supply Current vs. Update Rate Figure 29. Reference Multiplying Bandwidth—All 1s Loaded Rev. H | Page 11 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet 3 10 TA = 25°C TA = 25°C VDD = 5V 0 VDD = 3V AD8038AMPLIFIER –10 0 –20 –30 dB) dB)–40 GAIN( –3 PSRR (–50 FULL SCALE –60 ZERO SCALE –6 VREF =±2V, AD8038 CCOMP = 1pF –70 VREF =±2V, AD8038 CCOMP = 1.5pF –80 –9 VVVRRREEEFFF ===±±±111555VVV,,, AAADDD888000333888 CCCCCCOOOMMMPPP === 111p..58FppFF 04587-079 –1–0900 04587-082 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 30. Reference Multiplying Bandwidth vs. Frequency and Figure 33. Power Supply Rejection Ratio vs. Frequency Compensation Capacitor 0.08 –60 V0xD7DF =F 5TVO 0x800 VTAD D= =2 50°VC VTAD D= =2 55°VC 0.06 NRG = 2.154nVs AD8038AMPLIFIER –65 VREF =±3.5V CCOMP = 1.8pF E (V) 0.04 0NVxDR7DGF = F= 3 T1VO.7 904xn8V00s –70 VOLTAG 0.02 +N(dB)–75 PUT 0 THD OUT–0.02 V0xD8D0 =0 5TVO 0x7FF –80 NRG = 0.694nVs –85 ––00..0046 V0NxDR8DG0 = 0= 5T 0VO.6 09x47nFVFs 04587-080 –90 04587-083 50 75 100 125 150 175 200 225 250 100 1k 10k 100k TIME (ns) FREQUENCY (Hz) Figure 31. Midscale Transition, VREF = 0 V Figure 34. THD + Noise vs. Frequency –1.66 100 VDD =5V TA = 25°C –1.68 0NxR7GF F= T2O.1 504xn8V00s VADDD8 0=3 38.5AVMPLIFIER MCLK = 500kHz MCLK = 200kHz CCOMP = 1.8pF 80 V)–1.70 V0xD7DF =F 3TVO 0x800 MCLK = 1MHz E ( NRG = 1.794nVs G 60 A–1.72 B) OLT R(d V D UT –1.74 SF 40 P T U O–1.76 VDD =5V 0x800 TO 0x7FF 20 NRG = 0.694nVs ––11..8708 V0NxDR8DG0 = 0= 5T 0VO.6 09x47nFVFs 04587-081 0 TVAARD E8=F0 23=58±° AC3.M5VPLIFIER 04587-084 50 75 100 125 150 175 200 225 250 0 10 20 30 40 50 TIME (ns) fOUT (kHz) Figure 32. Midscale Transition, VREF = 3.5 V Figure 35. Wideband SFDR vs. fOUT Frequency Rev. H | Page 12 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 0 0 TA = 25°C TA = 25°C VDD = 5V VDD = 5V –20 VREF = 3.5V –20 VREF = 3.5V AD8038AMPLIFIER AD8038AMPLIFIER –40 –40 B) B) d d R (–60 R (–60 D D F F S S –80 –80 –100 –100 –120 04587-085 –120 04587-088 0 100k 200k 300k 400k 500k 30k 40k 50k 60k 70k FREQUENCY (Hz) FREQUENCY (Hz) Figure 36. Wideband SFDR, fOUT = 20 kHz, Clock = 1 MHz Figure 39. Narrow-Band SFDR , fOUT = 50 kHz, Clock = 1 MHz 0 0 –20 TVVADR DE=F = 2= 55 °3VC.5V –10 TVAARD E8=F0 23=58 °3CA.5MVPLIFIER AD8038AMPLIFIER –20 –30 –40 dB) B)–40 DR (–60 D (d–50 F M S I–60 –80 –70 –80 –100 –120 04587-086 –1–0900 04587-089 0 100k 200k 300k 400k 500k 10k 15k 20k 25k 30k 35k FREQUENCY (Hz) FREQUENCY (Hz) Figure 37. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz Figure 40. Narrow-Band IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz 0 0 TA = 25°C TA = 25°C VDD = 5V –10 VREF = 3.5V –20 VREF = 3.5V AD8038AMPLIFIER AD8038AMPLIFIER –20 –30 –40 dB) B)–40 DR (–60 D (d–50 F M S I–60 –80 –70 –100 –80 –120 04587-087 –1–0900 04587-090 10k 15k 20k 25k 30k 0 100k 200k 300k 400k 500k FREQUENCY (Hz) FREQUENCY (Hz) Figure 38. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz Figure 41. Wideband IMD, fOUT = 20 kHz, 25 kHz, Clock = 1 MHz | Rev. H | Page 13 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet 80 TA = 25°C 70 AD8038AMPLIFIER Hz) 60 FLUOLALD SECDA TLOE DAC V/ 50 n E ( OIS 40 N MIDSCALE UT 30 LOADED TO DAC TP U O 20 ZERO SCALE 100 LOADED TO DAC 04587-091 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 42. Output Noise Spectral Density Rev. H | Page 14 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Feedthrough A measure of the maximum deviation from a straight line passing When the device is not selected, high frequency logic activity through the endpoints of the DAC transfer function. It is mea- on the device’s digital inputs may be capacitively coupled sured after adjusting for zero and full scale and is normally through the device and produce noise on the I pins. This OUT expressed in LSBs or as a percentage of the full-scale reading. noise is coupled from the outputs of the device onto follow on circuitry. This noise is digital feedthrough. Differential Nonlinearity The difference between the measured change and the ideal 1 LSB Multiplying Feedthrough Error change between any two adjacent codes. A specified differential The error due to capacitive feedthrough from the DAC nonlinearity of −1 LSB maximum over the operating temperature reference input to the DAC I 1 terminal when all 0s are OUT range ensures monotonicity. loaded to the DAC. Gain Error (Full-Scale Error) Total Harmonic Distortion (THD) A measure of the output error between an ideal DAC and the The DAC is driven by an ac reference. The ratio of the rms sum actual device output. For these DACs, ideal maximum output is of the harmonics of the DAC output to the fundamental value is V − 1 LSB. Gain error of the DACs is adjustable to zero with the THD. Usually only the lower-order harmonics, such as REF external resistance. second to fifth, are included. Output Leakage Current V 2 +V 2 +V 2 +V 2 The current that flows into the DAC ladder switches when it is THD=20log 2 3 4 5 V turned off. For the I 1 terminal, it can be measured by loading 1 OUT all 0s to the DAC and measuring the IOUT1 current. Digital Intermodulation Distortion (IMD) Second-order intermodulation measurements are the relative Output Capacitance magnitudes of the fa and fb tones generated digitally by the Capacitance from I 1 to AGND. OUT DAC and the second-order products at 2fa − fb and 2fb − fa. Output Current Settling Time Compliance Voltage Range The amount of time it takes for the output to settle to a specified The maximum range of (output) terminal voltage for which the level for a full-scale input change. For these devices, it is specified device provides the specified characteristics. with a 100 Ω resistor to ground. The settling time specification includes the digital delay from the SYNC rising edge to the full- Spurious-Free Dynamic Range (SFDR) scale output change. The usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the Digital-to-Analog Glitch Impulse measure of difference in amplitude between the fundamental The amount of charge injected from the digital inputs to the and the largest harmonically or nonharmonically related spur analog output when the inputs change state. This is normally from dc to full Nyquist bandwidth (half the DAC sampling rate specified as the area of the glitch in either pA-s or nV-s, depending or f/2). Narrow band SFDR is a measure of SFDR over an on whether the glitch is measured as a current or voltage signal. S arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave. Rev. H | Page 15 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet GENERAL DESCRIPTION DAC SECTION VDD R2 The AD5450/AD5451/AD5452/AD5453 are 8-/10-/12-/14-bit current output DACs, respectively, consisting of a segmented VDD AD5450/ RFB C1 (4-bit) inverting R-2R ladder configuration. A simplified AD5451/ IOUT1 VREF VREF AD5452/ A1 diagram for the 12-bit AD5452 is shown in Figure 43. R1 AD5453 GND VOUT = 0 TO –VREF R R R SYNC SCLK SDIN VREF AGND 2R 2R 2R 2R 2R S1 S2 S3 S12 R µCONTROLLER RFB NOTES IOUT1 12..RCIF11 A AP1HN IADSS RAE2 H CUIOGSMHE DPS EPONENSELADYT AIIOFM NGP AL(1IIpFNFI EA TRDO.J U2SpTFM) MENATY IBSE R REEQQUUIRIREEDD. 04587-009 DACA NDDA TDAR ILVAETRCSHES AGND 04587-060 Figure 44. Unipolar Mode Operation These DACs are designed to operate with either negative or Figure 43. AD5452 Simplified Ladder positive reference voltages. The V power pin is only used by DD The feedback resistor, R , has a value of R. The value of R is FB the internal digital logic to drive the on and off states of the typically 9 kΩ (with a minimum value of 7 kΩ and a maximum DAC switches. value of 11 kΩ). If I 1 is kept at the same potential as GND, a OUT These DACs are designed to accommodate ac reference input constant current flows in each ladder leg, regardless of digital signals in the range of −10 V to +10 V. input code. Therefore, the input resistance presented at V is REF always constant and nominally of value R. The DAC output With a fixed 10 V reference, the circuit shown in Figure 44 gives (IOUT1) is code dependent, producing various resistances and a unipolar 0 V to −10 V output voltage swing. When VIN is an ac capacitances. When choosing the external amplifier, take into signal, the circuit performs 2-quadrant multiplication. account the variation in impedance generated by the DAC on Table 5 shows the relationship between the digital code and the amplifier’s inverting input node. the expected output voltage for a unipolar operation using the Access is provided to the V , R , and I 1 terminals of the 8-bit AD5450. REF FB OUT DAC, making the device extremely versatile and allowing it to be Table 5. Unipolar Code Table for the AD5450 configured in several operating modes; for example, it can provide Digital Input Analog Output (V) a unipolar output or can provide 4-quadrant multiplication in 1111 1111 −V (255/256) bipolar mode. Note that a matching switch is used in series with REF 1000 0000 −V (128/256) = −V /2 the internal R feedback resistor. If users attempt to measure REF REF FB 0000 0001 −V (1/256) R , power must be applied to V to achieve continuity. REF FB DD 0000 0000 −V (0/256) = 0 REF CIRCUIT OPERATION Unipolar Mode Using a single operational amplifier, these devices can easily be configured to provide a 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 44. When an output amplifier is connected in unipolar mode, the output voltage is given by D V =− ×V OUT 2n REF where: D is the fractional representation of the digital word loaded to the DAC. D = 0 to 255 (8-bit AD5450). = 0 to 1023 (10-bit AD5451). = 0 to 4095 (12-bit AD5452). = 0 to 16,383 (14-bit AD5453). n is the number of bits. Note that the output voltage polarity is opposite to the V REF polarity for dc reference voltages. Rev. H | Page 16 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 Bipolar Mode When VIN is an ac signal, the circuit performs 4-quadrant multiplication. Table 6 shows the relationship between the In some applications, it may be necessary to generate a full digital code and the expected output voltage for a bipolar 4-quadrant multiplying operation or a bipolar output swing. operation using the 8-bit AD5450. This can be easily accomplished by using another external amplifier and some external resistors, as shown in Figure 45. In Table 6. Bipolar Code Table for the AD5450 this circuit, the second amplifier, A2, provides a gain of 2. Biasing Digital Input Analog Output (V) the external amplifier with an offset from the reference voltage 1111 1111 +V (127/128) REF results in full 4-quadrant multiplying operation. The transfer 1000 0000 0 function of this circuit shows that both negative and positive 0000 0001 −V (127/128) REF output voltages are created as the input data (D) is incremented 0000 0000 −V (128/128) REF from Code 0 (V = − V ) to midscale (V − 0 V ) to full OUT REF OUT Stability scale (V = +V ). OUT REF In the I-to-V configuration, the I of the DAC and the OUT  D  V =V × −V inverting node of the operational amplifier must be connected OUT  REF 2n−1 REF as close as possible, and proper printed circuit board (PCB) where: layout techniques must be employed. Because every code change D is the fractional representation of the digital word loaded to corresponds to a step function, gain peaking may occur if the the DAC. operational amplifier has limited gain bandwidth product (GBP) D = 0 to 255 (8-bit AD5450). and there is excessive parasitic capacitance at the inverting node. = 0 to 1023 (10-bit AD5451). This parasitic capacitance introduces a pole into the open-loop = 0 to 4095 (12-bit AD5452). response, which can cause ringing or instability in the closed- n is the resolution of the DAC. loop applications circuit. An optional compensation capacitor, C1, can be added in parallel with R for stability, as shown in Figure 44 and Figure 45. Too FB small a value of C1 can produce ringing at the output, and too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation. R3 20kΩ VDD R2 R5 20kΩ VDD RFB C1 AD5450/ R4 V±1R0EVF VREF AADD55445512// IOUT1 A1 10kΩ R1 AD5453 GND A2 VOUT = –VREF TO +VREF SYNC SCLK SDIN AGND µCONTROLLER NOTES 1.R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2.MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS 3.RCIF13 A AP1HN/AAD2S R EIS4 .C AO HMIGPEHN SSPAETEIODN A (M1PpFL ITFOIE R2p.F) MAY BE REQUIRED 04587-010 Figure 45. Bipolar Mode Operation (4-Quadrant Multiplication) Rev. H | Page 17 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet SINGLE-SUPPLY APPLICATIONS ADDING GAIN Voltage Switching Mode In applications in which the output voltage is required to be Figure 46 shows these DACs operating in the voltage switching greater than VIN, gain can be added with an additional external mode. The reference voltage, V , is applied to the I 1 pin, and amplifier, or it can be achieved in a single stage. It is important IN OUT the output voltage is available at the V terminal. In this to consider the effect of the temperature coefficients of the DAC REF configuration, a positive reference voltage results in a positive thin film resistors. Simply placing a resistor in series with the RFB output voltage, making single-supply operation possible. The resistor causes mismatches in the temperature coefficients and output from the DAC is voltage at a constant impedance (the results in larger gain temperature coefficient errors. Instead, DAC ladder resistance); therefore, an operational amplifier is increase the gain of the circuit by using the recommended con- necessary to buffer the output voltage. The reference input no figuration shown in Figure 47. R1, R2, and R3 must have similar longer sees constant input impedance, but one that varies with temperature coefficients, but they need not match the temperature code; therefore, drive the voltage input from a low impedance coefficients of the DAC. This approach is recommended in circuits source. where gains greater than 1 are required. Note that RFB R2//R3 and a gain error percentage of 100 × (R2//R3)/R must be taken VDD R1 R2 into consideration. FB ≫ VDD RFB VDD VOUT VIN IOUT1 VREF GND VDD RFB C1 R1 IOUT1 VIN VREF VOUT NOTES R3 12..ACIFD1 A DP1IHT IASIOS ANE AH CLIGO PHMIN PSSEP NOESEMADITT ATIOMENDP L(F1IOFpIRFE RTCO.L A2RpFIT)Y M.AY BE REQUIRED 04587-011 GND R2 GAIN =R2R +2 R3 Figure 46. Single-Supply Voltage Switching Mode R2R3 NOTES R1 = R2 + R3 Itto ilso iwm vpoolrttaagnets tboe ncaoutes et hthate wswitihtc thheiss cino nthfieg uDrAatCio lna dVdINe ri sd loim noitte d 12..ACIFD1 A DP1IHT IASIOS ANE AH CLIGO PHMIN PSSEP NOESEMADITT ATIOMENDP L(F1IOFpIRFE RTCO.L A2RpFIT)Y M.AY BE REQUIRED 04587-013 have the same source-drain drive voltage. As a result, the on Figure 47. Increasing Gain of Current-Output DAC resistance of the switches differs, which degrades the integral linearity of the DAC. Also, V must not go negative by more IN than 0.3 V, or an internal diode turns on, causing the device to exceed the maximum ratings. In this type of application, the full range of multiplying capability of the DAC is lost. Rev. H | Page 18 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 DIVIDER OR PROGRAMMABLE GAIN ELEMENT The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system Current-steering DACs are very flexible and lend themselves to is required to hold its overall specification to within 1 LSB over many different applications. If this type of DAC is connected as the temperature range 0°C to 50°C, and the system’s maximum the feedback element of an operational amplifier and R is used FB temperature drift should be less than 78 ppm/°C. as the input resistor as shown in Figure 48, the output voltage is inversely proportional to the digital input fraction, D. A 12-bit system within 2 LSB accuracy requires a maximum drift of 10 ppm/°C. Choosing a precision reference with a low For D = 1 − 2−n, the output voltage is output temperature coefficient minimizes this error source. Table 7 −V −V V = IN = IN lists some dc references available from Analog Devices, Inc., that OUT D (1−2−n) are suitable for use with this range of current output DACs. As D is reduced, the output voltage increases. For small values AMPLIFIER SELECTION of the digital fraction, D, it is important to ensure that the The primary requirement for the current steering mode is an amplifier does not saturate and that the required accuracy is amplifier with low input bias currents and low input offset voltage. met. For example, an 8-bit DAC driven with the binary code The input offset voltage of an operational amplifier is multiplied 0x10 (00010000), that is, 16 decimal, in the circuit of Figure 48 by the variable gain of the circuit due to the code dependent output causes the output voltage to be 16 times V . IN resistance of the DAC. A change in this noise gain between two VDD adjacent digital fractions produces a step change in the output VIN voltage due to the offset voltage of the amplifier’s input. This RFB VDD output voltage change is superimposed on the desired change in IOUT1 VREF output between the two codes and gives rise to a differential GND linearity error, which if large enough, could cause the DAC to be nonmonotonic. The input bias current of an operational amplifier generates an VOUT offset at the voltage output as a result of the bias current flowing in the feedback resistor, R . Most operational amplifiers have NAODDTEITIONAL PINS OMITTED FOR CLARITY 04587-014 input bias currents low enFoBugh to prevent significant errors in 12-bit applications. However, for 14-bit applications, some Figure 48. Current Steering DAC Used as a Divider or Programmable Gain Element consideration should be given to selecting an appropriate amplifier. However, if the DAC has a linearity specification of ±0.5 LSB, D can have weight anywhere in the range of 15.5/256 to 16.5/256. Common-mode rejection of the operational amplifier is Therefore, the possible output voltage is in the range of 15.5 V important in voltage switching circuits because it produces a IN to 16.5 V —an error of 3%, even though the DAC itself has a code-dependent error at the voltage output of the circuit. Most IN maximum error of 0.2%. operational amplifiers have adequate common-mode rejection for use at 8-, 10-, and 12-bit resolutions. DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an Provided that the DAC switches are driven from true wideband low opposite current supplied from the operational amplifier impedance sources (VIN and AGND), they settle quickly. Con- through the DAC. Because only a fraction, D, of the current in sequently, the slew rate and settling time of a voltage switching the V terminal is routed to the I 1 terminal, the output DAC circuit is determined largely by the output operational REF OUT voltage changes as follows: amplifier. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the V node (the voltage Output Error Voltage Dueto Leakage = (Leakage × R)/D REF output node in this application) of the DAC. This is done by using where R is the DAC resistance at the VREF terminal. low input capacitance buffer amplifiers and careful board design. For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain Most single-supply circuits include ground as part of the analog (that is, 1/D) of 16, the error voltage is 1.6 mV. signal range, which in turn requires an amplifier that can handle REFERENCE SELECTION rail-to-rail signals. There is a large range of single-supply amplifiers available from Analog Devices. When selecting a reference for use with this series of current output DACs, pay attention to the reference’s output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but also may affect the linearity (INL and DNL) performance. Rev. H | Page 19 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet Table 7. Suitable Analog Devices Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable Analog Devices Precision Operational Amplifier 0.1 Hz to 10 Hz Part No. Supply Voltage (V) V (Max) (μV) I (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable Analog Devices High Speed Operational Amplifier Part No. Supply Voltage (V) BW at ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) I (Max) (nA) Package B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8 Rev. H | Page 20 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 SERIAL INTERFACE SYNC Function The AD5450/AD5451/AD5452/AD5453 have an easy to use SYNC is an edge triggered input that acts as a frame synchron- 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, ization signal and chip enable. Data can only be transferred to and most DSP interface standards. Data is written to the device in the device while SYNC is low. To start the serial data transfer, 16-bit words. This 16-bit word consists of two control bits and 8, SYNC should be taken low, observing the minimum SYNC 10, 12, or 14 data bits, as shown in Figure 49, Figure 50, Figure 51, falling to SCLK falling edge setup time, t. To minimize the and Figure 52. The AD5453 uses all 14 bits of DAC data, the 4 power consumption of the device, the interface powers up fully AD5452 uses 12 bits and ignores the two LSBs, the AD5451 uses only when the device is being written to, that is, upon the falling 10 bits and ignores the four LSBs, and the AD5450 uses 8 bits edge of SYNC. The SCLK and SDIN input buffers are powered and ignores the six LSBs. down upon the rising edge of SYNC. DAC Control Bits C1, C0 After the falling edge of the 16th SCLK pulse, bring SYNC high Control Bits C1 and C0 allow the user to load and update the to transfer data from the input shift register to the DAC register. new DAC code and to change the active clock edge. By default, the shift register clocks data upon the falling edge; this can be The serial interface to the AD5450 uses a 16-bit shift register. changed via the control bits. If changed, the DAC core is inop- Take care to avoid incomplete data sequences as these will be erative until the next data frame, and a power recycle is required to latched to update the DAC output. return it to active on the falling edge. A power cycle resets the For example, core to default condition. On-chip power-on reset circuitry • Loading 0x3FFF (a complete data sequence) will update ensures that the device powers on with zero scale loaded to the the output to 10 V (full scale). DAC register and I line. OUT • User intends to write 0x3200 but after 12 active edges Table 10. DAC Control Bits SYNC goes high (incomplete write sequence). This will C1 C0 Function Implemented update the following code: 0xF200. 0 0 Load and update (power-on default) • The user expects an output of 5.6 V. However, if SYNC 0 1 Reserved goes high after 12 valid clock edges then an incomplete 1 0 Reserved data sequence of 12 bits is loaded. To complete the shift 1 1 Clock data to shift register upon rising edge register the 4 LSBs from the previous sequence are taken and used as the 4 MSBs missing. The addition of these 4 bits will put the device in rising edge mode and the output will show no change. Figure 53, Figure 54, and Table 11 show the data frames for this example. Also note that if more then 16-bits are loaded to the device before SYNC goes high the last 16-bits will be latched. DB15 (MSB) DB0 (LSB) C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X CONTROL BITS DATA BITS 04587-005 Figure 49. AD5450 8-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X CONTROL BITS DATA BITS 04587-006 Figure 50. AD5451 10-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C1 C0 DB11DB10DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X CONTROL BITS DATA BITS 04587-007 Figure 51. AD5452 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C1 C0 DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS DATA BITS 04587-008 Figure 52. AD5453 14-Bit Input Shift Register Contents Rev. H | Page 21 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CONTROL BITS DATA BITS 04587-054 Figure 53. AD5453 First Write, Complete Data Sequence (0x3FFF) 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 DATA BITS DATA BITS CONTROL BITS INTENDED DATA FRAME CONTROL BITS ACTUAL DATA FRAME 04587-055 Figure 54. AD5453 Second Write, Incomplete Data Sequence (0x3200) and Subsequent Additional Bits (0xF200) Table 11. Writing Data Write in Data Transfer to Sequence Shift Register Action Expected the Device Action Carried Out 1 0x3FFF Load and update 0x3FFF 0x3FFF Load and update 0x3FFF 2 0x3200 Load and update 0x3200 0xF200 Clock data to shift register upon rising edge (0xF200) MICROPROCESSOR INTERFACING ADSP-2191M* AD5450/AD5451/ Microprocessor interfacing to a AD5450/AD5451/AD5452/ AD5452/AD5453* AD5453 DAC is through a serial bus that uses standard protocol TFS SYNC and is compatible with microcontrollers and DSP processors. DT SDIN The communication channel is a 3-wire interface consisting of SCLK SCLK aA cDlo54ck5 0s/iAgnDa5l,4 a5 1d/aAtaD s5i4g5n2a/lA, aDn5d4 5a 3s yrneqcuhirroen aiz 1a6ti-obnit swigonradl,. wTihthe *ADDITIONAL PINS OMITTED FOR CLARITY 04587-051 the default being data valid upon the falling edge of SCLK, but Figure 56. ADSP-2191M to AD5450/AD5451/AD5452/AD5453 Interface this is changeable using the control bits in the data-word. Communication between two devices at a given clock speed is ADSP-21xx Processors to AD5450/AD5451/AD5452/ possible when the following specifications are compatible: frame AD5453 Interface SYNC delay and frame SYNC setup and hold, data delay and The ADSP-21xx device family of DSPs is easily interfaced to a data setup and hold, and SCLK width. The DAC interface expects a AD5450/AD5451/AD5452/AD5453 DAC without the need for t (SYNC falling edge to SCLK falling edge setup time) of 13 ns 4 extra glue logic. Figure 55 is an example of an SPI interface minimum. See the ADSP-21xx device family for information on between the DAC and the ADSP-2191M. SCK of the DSP drives clock and frame SYNC frequencies for the SPORT register. Table 12 the serial data line, SDIN. SYNC is driven from one of the port shows the setup for the SPORT control register. lines, in this case SPIxSEL. Table 12. SPORT Control Register Setup AD5450/AD5451/ Name Setting Description ADSP-2191M* AD5452/AD5453* TFSW 1 Alternate framing SPIxSEL SYNC INVTFS 1 Active low frame signal MOSI SDIN DTYPE 00 Right justify data SCK SCLK ISCLK 1 Internal serial clock *ADDITIONAL PINS OMITTED FOR CLARITY 04587-100 TITFFSSR 11 IFnratemrnea el vfrearmy winogr dsi gnal Figure 55. ADSP-2191M SPI to AD5450/AD5451/AD5452/AD5453 Interface SLEN 1111 16-bit data-word A serial interface between the DAC and DSP SPORT is shown in Figure 56. In this example, SPORT0 is used to transfer data to the DAC shift register. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out upon each rising edge of the DSP’s serial clock and clocked into the DAC input shift register upon the falling edge of its SCLK. The update of the DAC output takes place upon the rising edge of the SYNC signal. Rev. H | Page 22 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 ADSP-BF504 to ADSP-BF592 Device Family to To load data correctly to the DAC, P1.1 is left low after the first AD5450/AD5451/AD5452/AD5453 Interface eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. Data on RxD is clocked out of The ADSP-BF504 to ADSP-BF592 device family of processors the microcontroller upon the rising edge of TxD and is valid upon has an SPI-compatible port that enables the processor to comm- the falling edge. As a result, no glue logic is required between the unicate with SPI-compatible devices. A serial interface between the DAC and microcontroller interface. P1.1 is taken high following BlackFin® processor and the AD5450/AD5451/AD5452/AD5453 the completion of this cycle. The 80C51/80L51 provide the LSB DAC is shown in Figure 57. In this configuration, data is trans- of its SBUF register as the first bit in the data stream. The DAC ferred through the MOSI (master output, slave input) pin. input register acquires its data with the MSB as the first bit received. SYNC is driven by the SPIxSEL pin, which is a reconfigured The transmit routine should take this into account. programmable flag pin. AD5450/AD5451/ 8051* ADSP-BF5xx* AD5450/AD5451/ AD5452/AD5453* AD5452/AD5453* TxD SCLK SPIxSEL SYNC RxD SDIN MOSI SDIN P1.1 SYNC *ADDITIONAL PINS SOCMKITTED FOR CLARITY SCLK 04587-102 *ADFDiIgTuIOrNe A5L9 .P 8IN0SC 5O1M/I8T0TEL5D1 F tOoR A CDL5A4R5I0TY/AD5451/AD5452/AD5453 Interface 04587-104 MC68HC11 to AD5450/AD5451/AD5452/AD5453 Interface Figure 57. ADSP-BF504 to ADSP-BF592 Device Family to AD5450/AD5451/AD5452/AD5453 Interface Figure 60 is an example of a serial interface between the DAC (ADSP-BFxx Denotes the ADSP-BF504 to ADSP-BF592) and the MC68HC11 microcontroller (Motorola). The serial The ADSP-BF504 to ADSP-BF592 processors incorporate peripheral interface (SPI) on the MC68HC11 is configured for channel synchronous serial ports (SPORT). A serial interface master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and between the DAC and the DSP SPORT is shown in Figure 58. clock phase bit (CPHA) = 1. The SPI is configured by writing to When the SPORT is enabled, initiate transmission by writing a the SPI control register (SPCR). SCK of the 68HC11 drives the word to the Tx register. The data is clocked out upon each rising SCLK of the DAC interface; the MOSI output drives the serial edge of the DSP’s serial clock and clocked into the DAC’s input data line (SDIN) of the DAC. shift register upon the falling edge its SCLK. The DAC output is The SYNC signal is derived from a port line (PC7). When data updated by using the transmit frame synchronization (TFS) line is being transmitted to the AD5450/AD5451/AD5452/AD5453, to provide a SYNC signal. the SYNC line is taken low (PC7). Data appearing on the MOSI ADSP-BF5xx* AD5450/AD5451/ output is valid upon the falling edge of SCK. Serial data from the AD5452/AD5453* 68HC11 is transmitted in 8-bit bytes with only eight falling clock TFS SYNC edges occurring in the transmit cycle. Data is transmitted MSB DT SDIN first. To load data to the DAC, PC7 is left low after the first eight SCLK SCLK bits are transferred, and a second serial write operation is performed *ADDITIONAL PINS OMITTED FOR CLARITY 04587-103 toM tCh6e8 DHCA1C1*. PC7 is taken high at the end of tAhiDs5 p4r5o0c/AedDu5r4e5. 1/ Figure 58. ADSP-BF504 to ADSP-BF592 Device Family SPORT to AD5452/AD5453* AD5450/AD5451/AD5452/AD5453 Interface PC7 SYNC (ADSP-BFxx Denotes the ADSP-BF504 to ADSP-BF592) SCK SCLK 80C51/80L51 to AD5450/AD5451/AD5452/AD5453 MOSI SDIN Interface *ADDITIONAL PINS OMITTED FOR CLARITY 04587-105 A serial interface between the DAC and the 80C51/80L51 is Figure 60. MC68HC11 to AD5450/AD5451/AD5452/AD5453 Interface shown in Figure 59. TxD of the 80C51/80L51 drives SCLK of the DAC serial interface, and RxD drives the serial data line, SDIN. If the user wants to verify the data previously written to the P1.1 is a bit-programmable pin on the serial port and is used to input shift register, the SDO line can be connected to MISO of drive SYNC. As data is transmitted to the switch, P1.1 is taken low. the MC68HC11. In this configuration with SYNC low, the shift The 80C51/80L51 transmit data only in 8-bit bytes; therefore, register clocks data out upon the rising edges of SCLK. only eight falling clock edges occur in the transmit cycle. Rev. H | Page 23 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet MICROWIRE to AD5450/AD5451/AD5452/AD5453 PCB LAYOUT AND POWER SUPPLY DECOUPLING Interface In any circuit where accuracy is important, careful consideration Figure 61 shows an interface between the DAC and any of the power supply and ground return layout helps to ensure MICROWIRE-compatible device. Serial data is shifted out the rated performance. The PCB on which a AD5450/AD5451/ upon the falling edge of the serial clock, SK, and is clocked into AD5452/AD5453 DAC is mounted should be designed so the the DAC input shift register upon the rising edge of SK, which analog and digital sections are separated and confined to certain corresponds to the falling edge of the DAC’s SCLK. areas of the board. If the DAC is in a system where multiple devices require an AGND to DGND connection, the connection MICROWIRE* AD5450/AD5451/ AD5452/AD5453* should be made at one point only. The star ground point should be established as close as possible to the device. SK SCLK SO SDIN These DACs should have ample supply bypassing of 10 μF in CS SYNC parallel with 0.1 μF on the supply located as close to the package *ADDITIONAL PINS OMITTED FOR CLARITY 04587-106 as possible, ideally right up against the device. The 0.1 μF capacitor should have low effective series resistance (ESR) and Figure 61. MICROWIRE to AD5450/AD5451/AD5452/AD5453 Interface low effective series inductance (ESI), like the common ceramic PIC16C6x/PIC16C7x to AD5450/AD5451/AD5452/ types that provide a low impedance path to ground at high AD5453 Interface frequencies, to handle transient currents due to internal logic The PIC16C6x/PIC16C7x (Microchip) synchronous serial port switching. Low ESR 1 μF to 10 μF tantalum or electrolytic (SSP) is configured as an SPI master with the clock polarity bit capacitors should also be applied at the supplies to minimize (CKP) = 0. This is done by writing to the synchronous serial transient disturbance and filter out low frequency ripple. port control register (SSPCON). Components, such as clocks, that produce fast switching signals In this example, input/output Port RA1 is used to provide a should be shielded with a digital ground to avoid radiating noise SYNC signal and enable the serial port of the DAC. This micro- to other devices of the board and should never be run near the controller transfers only eight bits of data during each serial reference inputs. transfer operation; therefore, two consecutive write operations Avoid crossover of digital and analog signals. Traces on opposite are required. Figure 62 shows the connection diagram. sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip PIC16C6x/PIC16C7x* AD5450/AD5451/ AD5452/AD5453* technique is the best solution, but its use is not always possible SCK/RC3 SCLK with a double-sided board. In this technique, the component SDI/RC4 SDIN side of the board is dedicated to the ground plane and signal RA1 SYNC traces are placed on the solder side. *ADDITIONAL PINS OMITTED FOR CLARITY 04587-107 It is good practice to employ compact, minimum lead length Figure 62. PIC16C6x/PIC16C7x to AD5450/AD5451/AD5452/AD5453 Interface PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance. The PCB metal traces between V and R should also be REF FB matched to minimize gain error. To optimize high frequency performance, the I-to-V amplifier should be located as close to the device as possible. Rev. H | Page 24 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 Table 13. Overview of the AD5405 to AD5453 Device Family and the AD5543 to AD5557 Device Family Part No. Resolution No. DACs INL (LSB) Interface Package1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 12 MHZ BW, 50 MHz serial interface AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial interface AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial interface AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 n WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. H | Page 25 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 1 2 3 4 PIN 1 INDICATOR 0.65 BSC 1.95 *0.90 BSC 0.87 0.84 *1.00 MAX 0.20 0.08 0.60 0.10 MAX 00..3282 SEATING 84°° 00..4350 PLANE 0° *COMPLIANT TO JEDEC STANDARDS MO-193-BAWITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 63. 8-Lead Thin Small Outline Transistor Package [TSOT] (UJ-8) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0.T25OJEDECSTA0°NDARDS0M.0O9-187-AA 0.40 09-B10-07-20 Figure 64. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. H | Page 26 of 28

Data Sheet AD5450/AD5451/AD5452/AD5453 3.10 0.35 3.00 SQ 0.30 0.65 BSC 2.90 0.25 5 8 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 4 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR 0.80 MAX 2.48 (R 0.2) 0.80 0.55 NOM 2.38 0.75 0.05 MAX 2.23 0.70 0.02 NOM FOR PROPER CONNECTION OF SEPALTAINNGE 0.20 REF TTFSHHUEENEC CTPEITIOXNIPON CON OOS DFNEE DFTSIH GPCISAUR DRIDP,AA TRTTIOEIAOFN NSES HRAE NTEODT. 02-05-2013-C Figure 65. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height, Dual Lead (CP-8-3) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Resolution INL Temperature Range Package Description Package Option Branding AD5450YUJZ-REEL7 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y AD5451YUJZ-REEL7 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z AD5452YUJZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70 AD5452YRM 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z AD5452YRM-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z AD5452YRMZ 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70 AD5452YRMZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70 AD5452YRMZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70 AD5453WBCPZ-RL 14 ±2 −40°C to +125°C 8-Lead LFCSP CP-8-3 DG3 AD5453YUJZ-REEL7 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH AD5453YRM 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26 AD5453YRM-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26 AD5453YRM-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26 AD5453YRMZ 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH AD5453YRMZ-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH AD5453YRMZ-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5453WBCPZ-RL model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. H | Page 27 of 28

AD5450/AD5451/AD5452/AD5453 Data Sheet NOTES ©2005-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04587-0-11/15(H) Rev. H | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5452YRM AD5452YRMZ-REEL AD5451YUJZ-REEL7 AD5453YUJZ-REEL7 AD5452YUJZ-REEL7 AD5453YRM-REEL AD5453YRM-REEL7 AD5450YUJZ-REEL7 AD5453YRMZ-REEL7 AD5452YRM-REEL AD5452YRMZ-REEL7 AD5453WBCPZ-RL AD5452YRMZ AD5453YRMZ AD5453YRM