Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface Data Sheet AD5428/AD5440/AD5447 FEATURES GENERAL DESCRIPTION 10 MHz multiplying bandwidth The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit, INL of ±0.25 LSB at 8 bits dual-channel, current output digital-to-analog converters (DACs), 20-lead and 24-lead TSSOP packages respectively. These devices operate from a 2.5 V to 5.5 V power 2.5 V to 5.5 V supply operation supply, making them suited to battery-powered and other ±10 V reference input applications. 21.3 MSPS update rate As a result of being manufactured on a CMOS submicron process, Extended temperature range: −40°C to +125°C they offer excellent 4-quadrant multiplication characteristics, 4-quadrant multiplication with large signal multiplying bandwidths of up to 10 MHz. Power-on reset 0.5 μA typical current consumption The DACs use data readback, allowing the user to read the Guaranteed monotonic contents of the DAC register via the DB pins. On power-up, the Readback function internal register and latches are filled with 0s, and the DAC AD7528 upgrade (AD5428) outputs are at zero scale. AD7547 upgrade (AD5447) ㈀he applied external reference input voltage (V ) determines REF APPLICATIONS the full-scale output current. An integrated feedback resistor (R ) FB provides temperature tracking and full-scale voltage output when Portable battery-powered applications combined with an external I-to-V precision amplifier. Waveform generators Analog processing The AD5428 is available in a small 20-lead TSSOP package, and Instrumentation applications the AD5440/AD5447 DACs are available in small 24-lead TSSOP Programmable amplifiers and attenuators packages. Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming FUNCTIONAL BLOCK DIAGRAM VREFA AD5428/AD5440/AD5447 R VDD RFBA INDPAUTTAS DB0 BIUNFPFUETR LATCH 8R--/21R0- /D1A2-CB IAT IOUTA DB7 DB9 DB11 AGND DAC A/B R CONTROL RFBB CS LOGIC R/W IOUTB LATCH 8-/10-/12-BIT R-2R DAC B DGND POWER-ON RESET VREFB 04462-001 Figure 1. 1 U.S. Patent Number 5,689,257. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5428/AD5440/AD5447 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Single-Supply Applications ....................................................... 19  Applications ....................................................................................... 1  Adding Gain ................................................................................ 19  General Description ......................................................................... 1  Divider or Programmable Gain Element ................................ 20  Functional Block Diagram .............................................................. 1  Reference Selection .................................................................... 20  Revision History ............................................................................... 2  Amplifier Selection .................................................................... 20  Specifications ..................................................................................... 3  Parallel Interface ......................................................................... 22  Timing Characteristics ................................................................ 5  Microprocessor Interfacing ....................................................... 22  Absolute Maximum Ratings ............................................................ 6  PCB Layout and Power Supply Decoupling ........................... 23  ESD Caution .................................................................................. 6  Evaluation Board for the AD5447 ............................................ 23  Pin Configurations and Function Descriptions ........................... 7  Power Supplies for the Evaluation Board ................................ 23  Typical Performance Characteristics ........................................... 10  Bill of Materials ............................................................................... 27  Terminology .................................................................................... 15  Overview of Multiplying DAC Devices ....................................... 28  General Description ....................................................................... 16  Outline Dimensions ....................................................................... 29  DAC Section ................................................................................ 16  Ordering Guide .......................................................................... 30  Circuit Operation ....................................................................... 16  REVISION HISTORY 1/16—Rev. C. to Rev. D Change to Absolute Maximum Ratings Section ........................... 6 Changed ADSP-21xx to ADSP-2191M ......................... Throughout Change to Figure 13, Figure 14, and Figure 18 ........................... 11 Changed ADSP-BF5xx to ADSP-BF534 ..................... Throughout Change to Figure 32 Through Figure 34 ..................................... 14 Deleted Positive Output Voltage Section and Figure 41 ............ 19 Changes to General Description Section .................................... 16 Changes to Adding Gain Section ................................................. 19 Changes to Figure 37 ...................................................................... 16 Changes to Ordering Guide .......................................................... 30 Changes to Single-Supply Applications Section ......................... 19 Changes to Figure 40 Through Figure 42.................................... 19 8/11—Rev. B to Rev. C Changes to Divider or Programmable Gain Element Section .... 20 Changes to CS Pin Description, Table 6 ........................................ 9 Changes to Figure 43 ...................................................................... 20 Changes to Table 9 Through Table 11 ......................................... 21 3/11—Rev. A to Rev. B Changes to Microprocessor Interfacing Section ........................ 22 Changes to Evaluation Board For the AD5447 Section ............ 23 Added Figure 44 Through Figure 46 ........................................... 22 Changes to Figure 47 Caption ....................................................... 24 Added 8xC51-to-AD5428/AD5440/AD5447 Changes to Figure 49 ...................................................................... 25 Interface Section ........................................................................ 22 Change to U1 Description in Table 12......................................... 27 Added ADSP-BF5xx-to-AD5428/AD5440/AD5447 Change to Ordering Guide ............................................................ 29 Interface Section ........................................................................ 22 Changes to Power Supplies for the Evaluation Board Section .... 23 7/05—Rev. 0 to Rev. A Changes to Table 13 ....................................................................... 28 Changed Pin DAC A/B to DAC A/B ................................ Universal Updated Outline Dimensions ....................................................... 29 Changes to Features List .................................................................. 1 Changes to Ordering Guide .......................................................... 29 Changes to Specifications ................................................................ 3 Changes to Timing Characteristics ................................................ 5 7/04—Revision 0: Initial Version Change to Figure 2 ........................................................................... 5 Rev. D | Page 2 of 32

Data Sheet AD5428/AD5440/AD5447 SPECIFICATIONS1 V = 2.5 V to 5.5 V, V = 10 V, I 2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T to T , unless DD REF OUT MIN MAX otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5428 Resolution 8 Bits Relative Accuracy ±0.25 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5440 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5447 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity –1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Output Leakage Current ±5 nA Data = 0x0000, T = 25°C A ±15 nA Data = 0x0000 REFERENCE INPUT Reference Input Range ±10 V V A, V B Input Resistance 8 10 13 kΩ Input resistance TC = –50 ppm/°C REF REF V A-to-V B Input 1.6 2.5 % Typ = 25°C, max = 125°C REF REF Resistance Mismatch Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, V 1.7 V V = 3.6 V to 5.5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5.5 V, I = 200 μA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 μA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5.5 V, I = 200 μA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 μA DD SINK Input Leakage Current, I 1 μA IL Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying BW 10 MHz V = ±3.5 V p-p, DAC loaded all 1s REF Output Voltage Settling Time R = 100 Ω, C = 15 pF, V = 10 V LOAD LOAD REF DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 15 30 ns Rise and fall times, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, V = 0 V REF Rev. D | Page 3 of 32

AD5428/AD5440/AD5447 Data Sheet Parameter Min Typ Max Unit Conditions Multiplying Feedthrough Error DAC latches loaded with all 0s, V = ±3.5 V REF 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Digital Feedthrough 1 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB V = 3.5 V p-p, all 1s loaded, f = 100 kHz REF Digital THD Clock = 10 MHz, V = 3.5 V REF 100 kHz f 61 dB OUT 50 kHz f 66 dB OUT SFDR Performance (Wide Band) AD5447, 65k codes, V = 3.5 V REF Clock = 10 MHz 500 kHz f 55 dB OUT 100 kHz f 63 dB OUT 50 kHz f 65 dB OUT Clock = 25 MHz 500 kHz f 50 dB OUT 100 kHz f 60 dB OUT 50 kHz f 62 dB OUT SFDR Performance (Narrow Band) AD5447, 65k codes, V = 3.5 V REF Clock = 10 MHz 500 kHz f 73 dB OUT 100 kHz f 80 dB OUT 50k Hz f 87 dB OUT Clock = 25 MHz 500 kHz f 70 dB OUT 100 kHz f 75 dB OUT 50 kHz f 80 dB OUT Intermodulation Distortion AD5447, 65k codes, V = 3.5 V REF f = 40 kHz, f = 50 kHz 72 dB Clock = 10 MHz 1 2 f = 40 kHz, f = 50 kHz 65 dB Clock = 25 MHz 1 2 POWER REQUIREMENTS Power Supply Range 2.5 5.5 V I 0.7 μA T = 25°C, logic inputs = 0 V or V DD A DD 0.5 10 μA T = −40°C to +125°C, logic inputs = 0 V or V A DD Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design, not subject to production test. Rev. D | Page 4 of 32

Data Sheet AD5428/AD5440/AD5447 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. V = 2.5 V to 5.5 V, DD IL IH DD V = 10 V, I 2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T to T , unless otherwise noted. REF OUT MIN MAX Table 2. Parameter1 Limit at T , T Unit Conditions/Comments MIN MAX Write Mode t 0 ns min R/W to CS setup time 1 t 0 ns min R/W to CS hold time 2 t 10 ns min CS low time 3 t 10 ns min Address setup time 4 t 0 ns min Address hold time 5 t 6 ns min Data setup time 6 t 0 ns min Data hold time 7 t 5 ns min R/W high to CS low 8 t 7 ns min CS min high time 9 Data Readback Mode t 0 ns typ Address setup time 10 t 0 ns typ Address hold time 11 t 5 ns typ Data access time 12 25 ns max t 5 ns typ Bus relinquish time 13 10 ns max Update Rate 21.3 MSPS Consists of CS min high time, CS low time, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. R/W t1 t2 t8 t2 t9 CS t3 t5 t4 t10 t11 DACA/DACB DATA DATtA8 VALID t7 t12 DATA VALID t13 04462-002 Figure 2. Timing Diagram 200A IOL TO OUTPUT VOH (MIN) + VOL (MAX) PIN 2 CL 50pF 200A IOH 04462-003 Figure 3. Load Circuit for Data Output Timing Specifications Rev. D | Page 5 of 32

AD5428/AD5440/AD5447 Data Sheet ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses at or above those listed under Absolute Maximum T = 25°C, unless otherwise noted. Ratings may cause permanent damage to the product. This is a A stress rating only; functional operation of the product at these Table 3. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond VDD to GND –0.3 V to +7 V the maximum operating conditions for extended periods may VREFA, VREFB, RFBA, RFBB to DGND –12 V to +12 V affect product reliability. I 1, I 2 to DGND –0.3 V to +7 V OUT OUT ESD CAUTION Logic Inputs and Output1 –0.3 V to V + 0.3 V DD Operating Temperature Range Automotive (Y Version) –40°C to +125°C Storage Temperature Range –65°C to +150°C Junction Temperature 150°C 20-lead TSSOP θ Thermal Impedance 143°C/W JA 24-lead TSSOP θ Thermal Impedance 128°C/W JA Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at DBx, CS, and R/W are clamped by internal diodes. Rev. D | Page 6 of 32

Data Sheet AD5428/AD5440/AD5447 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AGND 1 20 IOUTB IOUTA 2 19 RFBB RFBA 3 AD5428 18 VREFB VREFA 4 TOP VIEW 17 VDD (Not to Scale) DGND 5 16 R/W DAC A/B 6 15 CS DB7 7 14 DB0 (LSB) DB6 8 13 DB1 DDBB45 190 1121 DDBB32 04462-004 Figure 4. Pin Configuration 20-Lead TSSOP (RU-20) Table 4. AD5428 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 2, 20 I A, I B DAC Current Outputs. OUT OUT 3, 19 R A, R B DAC Feedback Resistor Pins. These pins establish voltage output for the DAC by connecting to an external FB FB amplifier output. 4, 18 V A, V B DAC Reference Voltage Input Terminals. REF REF 5 DGND Digital Ground Pin. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to14 DB7 to DB0 Parallel Data Bits 7 Through 0. 15 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. 16 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of the DAC register. 17 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD Rev. D | Page 7 of 32

AD5428/AD5440/AD5447 Data Sheet AGND 1 24 IOUTB IOUTA 2 23 RFBB RFBA 3 22 VREFB VREFA 4 AD5440 21 VDD DGND 5 TOP VIEW 20 R/W (Not to Scale) DAC A/B 6 19 CS DB9 7 18 NC DB8 8 17 NC DB7 9 16 DB0 (LSB) DB6 10 15 DB1 DDBB45 1121 1143 DDBB32 04462-005 NC = NO CONNECT Figure 5. Pin Configuration 24-Lead TSSOP (RU-24) Table 5. AD5440 Pin Function Descriptions Pin No. Mnemonic Function 1 AGND DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 2, 24 I A, I B DAC Current Outputs. OUT OUT 3, 23 R A, R B DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier output. FB FB 4, 22 V A, V B DAC Reference Voltage Input Terminals. REF REF 5 DGND Digital Ground Pin. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to16 DB9 to DB0 Parallel Data Bits 9 Through 0. 19 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. 20 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back contents of the DAC register. 21 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD Rev. D | Page 8 of 32

Data Sheet AD5428/AD5440/AD5447 AGND 1 24 IOUTB IOUTA 2 23 RFBB RFBA 3 22 VREFB VREFA 4 AD5447 21 VDD DGND 5 TOP VIEW 20 R/W (Not to Scale) DAC A/B 6 19 CS DB11 7 18 DB0 (LSB) DB10 8 17 DB1 DB9 9 16 DB2 DB8 10 15 DB3 DDBB67 1121 1143 DDBB54 04462-006 Figure 6. Pin Configuration 24-Lead TSSOP (RU-24) Table 6. AD5447 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to achieve single-supply operation. 2, 24 I A, I B DAC Current Outputs. OUT OUT 3, 23 R A, R B DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier FB FB output. 4, 22 V A, V B DAC Reference Voltage Input Terminals. REF REF 5 DGND Digital Ground Pin. 6 DAC A/B Selects DAC A or DAC B. Low selects DAC A; high selects DAC B. 7 to 18 DB11 to DB0 Parallel Data Bits 11 Through 0. 19 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read data from the DAC register. 20 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with CS to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent. Any changes on the data lines are reflected in the relevant DAC output. 21 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD Rev. D | Page 9 of 32

AD5428/AD5440/AD5447 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 TA = 25°C TA = 25°C 0.15 VREF = 10V 0.15 VREF = 10V VDD = 5V VDD = 5V 0.10 0.10 0.05 0.05 B) B) S S L L L ( 0 L ( 0 N N I D –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 50 100 CODE 150 200 250 04462-007 0 50 100 CODE 150 200 250 04462-010 Figure 7. INL vs. Code (8-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC) 0.5 0.5 0.4 TVAR E=F 2=5 °1C0V 0.4 TVAR E=F 2=5 °1C0V 0.3 VDD = 5V 0.3 VDD = 5V 0.2 0.2 B) 0.1 B) 0.1 NL (LS 0 NL (LS 0 I –0.1 D –0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 200 400 CODE 600 800 1000 04462-008 0 200 400 CODE 600 800 1000 04462-011 Figure 8. INL vs. Code (10-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC) 1.0 1.0 0.8 TVAR E=F 2=5 °1C0V 0.8 TVAR E=F 2=5 °1C0V 0.6 VDD = 5V 0.6 VDD = 5V 0.4 0.4 B) 0.2 B) 0.2 NL (LS 0 NL (LS 0 I –0.2 D –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 C2O00D0E 2500 3000 3500 4000 04462-009 0 500 1000 1500 C2O00D0E 2500 3000 3500 4000 04462-012 Figure 9. INL vs. Code (12-Bit DAC) Figure 12. DNL vs. Code (12-Bit DAC) Rev. D | Page 10 of 32

Data Sheet AD5428/AD5440/AD5447 0.6 8 0.5 TA = 25°C 7 0.4 MAX INL 6 0.3 NL (LSB) 00..12 TVAD D= =2 55°VC ENT (mA) 54 VDD = 5V I R R 0 CU 3 MIN INL –0.1 2 –0.2 VDD = 3V 1 –0.3 VDD = 2.5V 2 3 4 REF5ERENC6E VOLTA7GE 8 9 10 04462-013 00 0.5 1.0 1.5INP2U.0T VO2L.5TAG3E. 0(V) 3.5 4.0 4.5 5.0 04462-022 Figure 13. INL vs. Reference Voltage Figure 16. Supply Current vs. Logic Input Voltage –0.40 1.6 TA = 25°C VDD = 5V 1.4 –0.45 1.2 –0.50 IOUT1 VDD = 5V 1.0 B) A) L (LS–0.55 GE (n 0.8 DN KA IOUT1 VDD = 3V A 0.6 –0.60 LE MIN DNL 1 UT 0.4 O I –0.65 0.2 –0.70 0 2 3 4 REF5ERENC6E VOLTA7GE 8 9 10 04462-014 –40 –20 0 TE20MPERA4T0URE (6°C0) 80 100 120 04462-023 Figure 14. DNL vs. Reference Voltage Figure 17. IOUT1 Leakage Current vs. Temperature 5 0.50 4 0.45 VDD = 5V VDD = 5V 3 0.40 2 0.35 V) 1 A) 0.30 ALL 0s ERROR (m –10 VDD = 2.5V CURRENT ( 00..2205 VDD = 2.5V ALL 1s –2 0.15 ALL 1s ALL 0s –3 0.10 –4 VREF = 10V 0.05 –5 0 –60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 04462-015 –60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 04462-024 Figure 15. Gain Error vs. Temperature Figure 18. Supply Current vs. Temperature Rev. D | Page 11 of 32

AD5428/AD5440/AD5447 Data Sheet 14 3 TA = 25°C TA = 25°C 12 LOADING ZS TO FS VDD = 5V VDD = 5V 10 0 I (mA)DD 68 VDD = 3V GAIN (dB) –3 4 VDD = 2.5V –6 VVRREEFF ==22VV,, AADD88003388 CCCC 11.p4F7pF 2 VREF =0.15V, AD8038 CC 1pF VREF =0.15V, AD8038 CC 1.47pF VREF =3.51V, AD8038 CC 1.8pF 0 1 10 100 F1kREQU1E0NkCY (H10z0)k 1M 10M 100M 04462-025 –910k 100k FREQUE1MNCY (Hz) 10M 100M 04462-028 Figure 19. Supply Current vs. Update Rate Figure 22. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor 0.045 –1–2606 TLZAOS A=T DO2I5 NFGSC ADDDLBBBL119 10ON 00..003450 0x7FF TO 0x8V0D0D = 5V ACVTARMC EO=PFM 2==P5 A°0=CVD 18.80p3F8 –18 –24 DB8 V) 0.030 AIN (dB) –––433206 DDDDBBBB7654 OLTAGE ( 00..002250 VDD = 3V G –––––6564764082 DDDDBBBB3201 OUTPUT V 000...000011550 0VxD8D0 =0 3TVO 0x7FF –––879480 ALL OFF CCVORMETPFVA D== =D1 2=3.85. 55pCVVF –0.0005 –96 AMP = AD8038 VDD = 5V –1021 10 100 1FkREQU1E0NkCY (H10z0)k 1M 10M 100M 04462-026 –0.0100 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 04462-041 Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code Figure 23. Midscale Transition, VREF = 0 V 0.2 –1.68 –1.69 0x7FF TO 0x800 VTAR E=F 2=5 °3C.5V AMP = AD8038 0 –1.70 VDD = 5V CCOMP = 1.8pF V) E ( –1.71 G B) –0.2 TA –1.72 d L AIN ( T VO –1.73 VDD = 3V G –0.4 UTPU –1.74 VDD = 5V O VDD = 3V TA = 25°C –1.75 –0.6 VDD = 5V VREF =3.5V –1.76 ACMCOPM =P A= D18.80p3F8 0x800 TO 0x7FF –0.81 10 100 F1kREQU1E0NkCY (H10z0)k 1M 10M 100M 04462-027 –1.770 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 04462-042 Figure 21. Reference Multiplying Bandwidth—All 1s Loaded Figure 24. Midscale Transition, VREF = 3.5 V Rev. D | Page 12 of 32

Data Sheet AD5428/AD5440/AD5447 90 20 TA = 25C 80 VDD = 3V MCLK = 5MHz 0 AMP = AD8038 70 MCLK = 10MHz –20 60 B) dB) –40 R (d 50 R ( FULL SCALE FD 40 MCLK = 25MHz R S PS –60 ZERO SCALE 30 –80 20 –100 10 VTAR E=F 2=5 °3C.5V AMP = AD8038 0 –1201 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M04462-043 0 100 200 300 400fOU5T 0(0kHz)600 700 800 900 1000 04462-046 Figure 25. Power Supply Rejection Ratio vs. Frequency Figure 28. Wideband SFDR vs. fOUT Frequency –60 0 TA = 25°C TA = 25C –65 VVDRDEF = = 3 3V.5V p-p –10 VA65DMkDP C= =O 5 ADVDE8S038 –20 –70 –30 D + N (dB) –75 FDR (dB)––5400 H S T –80 –60 –70 –85 –80 –901 10 100FREQUE1kNCY (Hz)10k 100k 1M 04462-044 –900 2 4FREQUEN6CY (MHz)8 10 12 04462-047 Figure 26. THD + Noise vs. Frequency Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz 100 0 MCLK = 1MHz TA = 25C –10 VDD = 5V AMP = AD8038 80 65k CODES –20 –30 dB) 60 MCLK = 200kHz B)–40 DR ( MCLK = 0.5MHz R (d–50 F D S 40 SF–60 –70 20 –80 TA = 25°C VREF = 3.5V –90 AMP = AD8038 00 20 40 60 80fOU1T 0(0kHz)120 140 160 180 200 04462-045 –1000 0.5 1.0 1.5 FR2E.0QUE2N.5CY (M3.H0z) 3.5 4.0 4.5 5.0 04462048 Figure 27. Wideband SFDR vs. fOUT Frequency Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz Rev. D | Page 13 of 32

AD5428/AD5440/AD5447 Data Sheet 0 0 TA = 25C TA = 25C –10 AVDMDP = = 5 AVD8038 –10 VADMDP = = 3 AVD8038 65k CODES –20 65k CODES –20 –30 –30 FDR (dB)––5400 IMD (dB)––4500 S –60 –60 –70 –70 –80 –80 –90 –900 0.5 1.0 1.5 FR2E.0QUE2N.5CY (M3.H0z) 3.5 4.0 4.5 5.0 04462-049 –10070 75 80 85 FR9E0QUE9N5CY (1k0H0z) 105 110 115 120 04462-052 Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz 0 0 TA = 25C TA = 25C –10 VDD = 3V –10 VDD = 5V AMP = AD8038 AMP = AD8038 –20 65k CODES –20 65k CODES –30 –30 –40 B)–40 d R (dB)–50 IMD (–50 D–60 –60 F S –70 –70 –80 –80 –90 –90 –100250 300 350 400 FR45E0QUE5N00CY (5k5H0z) 600 650 700 750 04462-050 –1000 50 100 1F5R0EQUE2N00CY (kH25z0) 300 350 400 04462-53 Figure 32. Narrow-Band SFDR, fOUT = 500 kHz, Clock = 25 MHz Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz 20 TA = 25C 300 TA = 25C VDD = 3V ZERO SCALE LOADED TO DAC AMP = AD8038 0 A65MkP C =O ADDE8S038 250 MIDSCALE LOADED TO DAC FULL SCALE LOADED TO DAC –20 Hz) V/ 200 dB)–40 E (n SFDR (–60 T NOIS 150 U P T 100 –80 OU –100 50 –12050 60 70 80 FR9E0QUE1N00CY (1k1H0z) 120 130 140 150 04462-051 0100 1kFREQUENCY (Hz)10k 100k04462-054 Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 36. Output Noise Spectral Density Rev. D | Page 14 of 32

Data Sheet AD5428/AD5440/AD5447 TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Feedthrough A measure of the maximum deviation from a straight line When the device is not selected, high frequency logic activity passing through the endpoints of the DAC transfer function. It on the device’s digital inputs is capacitively coupled through the is measured after adjusting for zero and full scale and is device and produces noise on the I pins and, subsequently, OUT typically expressed in LSBs or as a percentage of the full-scale on the following circuitry. This noise is digital feedthrough. reading. Multiplying Feedthrough Error Differential Nonlinearity The error due to capacitive feedthrough from the DAC The difference in the measured change and the ideal 1 LSB reference input to the DAC I 1 terminal when all 0s are OUT change between two adjacent codes. A specified differential loaded to the DAC. nonlinearity of −1 LSB maximum over the operating Total Harmonic Distortion (THD) temperature range ensures monotonicity. The DAC is driven by an ac reference. The ratio of the rms sum Gain Error (Full-Scale Error) of the harmonics of the DAC output to the fundamental value is A measure of the output error between an ideal DAC and the the THD. Usually only the lower-order harmonics are included, actual device output. For these DACs, ideal maximum output is such as second to fifth harmonics. V – 1 LSB. The gain error of the DACs is adjustable to zero REF V 2 V 2 V 2 V 2 with an external resistance. THD20log 2 3 4 5 V Output Leakage Current 1 The current that flows into the DAC ladder switches when they Digital Intermodulation Distortion are turned off. For the I 1 terminal, it can be measured by Second-order intermodulation distortion (IMD) measurements OUT loading all 0s to the DAC and measuring the I 1 current. are the relative magnitude of the fa and fb tones digitally generated OUT Minimum current flows into the I 2 line when the DAC is by the DAC and the second-order products at 2fa − fb and OUT loaded with all 1s. 2fb − fa. Output Capacitance Spurious-Free Dynamic Range (SFDR) Capacitance from I 1 or I 2 to AGND. SFDR is the usable dynamic range of a DAC before spurious OUT OUT noise interferes or distorts the fundamental signal. SFDR is the Output Current Settling Time measure of difference in amplitude between the fundamental The amount of time for the output to settle to a specified level and the largest harmonic or nonharmonic spur from dc to full for a full-scale input change. For these devices, it is specified Nyquist bandwidth (half the DAC sampling rate, or fs/2). with a 100 Ω resistor to ground. Narrow-band SFDR is a measure of SFDR over an arbitrary Digital-to-Analog Glitch Impulse window size, in this case 50%, of the fundamental. Digital SFDR The amount of charge injected from the digital inputs to the is a measure of the usable dynamic range of the DAC when the analog output when the inputs change state. This is normally signal is a digitally generated sine wave. specified as the area of the glitch in either pA-sec or nV-sec, depending on whether the glitch is measured as a current or voltage signal. Rev. D | Page 15 of 32

AD5428/AD5440/AD5447 Data Sheet GENERAL DESCRIPTION DAC SECTION CIRCUIT OPERATION Unipolar Mode The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit, dual-channel, current output DACs consisting of a standard Using a single op amp, these devices can easily be configured to inverting R-2R ladder configuration. Figure 37 shows a simplified provide 2-quadrant multiplying operation or a unipolar output diagram for a single channel of the 8-bit AD5428. The feedback voltage swing, as shown in Figure 38. When an output amplifier resistor R A has a value of R. The value of R is typically 10 kΩ is connected in unipolar mode, the output voltage is given by FB (with a minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1 V = −V × D/2n OUT REF and AGND are kept at the same potential, a constant current where: flows into each ladder leg, regardless of digital input code. D is the fractional representation of the digital word loaded to Therefore, the input resistance presented at V A is always REF the DAC. constant and nominally of value R. The DAC output (I ) is OUT D = 0 to 255 (8-bit AD5428) code-dependent, producing various resistances and = 0 to 1023 (10-bit AD5440) capacitances. When choosing an external amplifier, take into = 0 to 4095 (12-bit AD5447) account the variation in impedance generated by the DAC on n is the resolution of the DAC. the amplifier’s inverting input node. Note that the output voltage polarity is opposite to the V R R R REF VREF polarity for dc reference voltages. These DACs are designed to 2R 2R 2R 2R 2R operate with either negative or positive reference voltages. The S1 S2 S3 S8 R RFBA VDD power pin is only used by the internal digital logic to drive IOUTA the on and off states of the DAC switches. DACA NDDA TDAR LIVAETRCSHES AGND 04462-029 Tinhpeuste sDigAnCalss ainre t hales ora dnegseig onfe –d1 t0o V ac tcoo +m1m0 oVd. ate ac reference Figure 37. Simplified Ladder With a fixed 10 V reference, the circuit in Figure 38 gives a Access is provided to the VREF, RFB, and IOUT terminals of DAC A unipolar 0 V to –10 V output voltage swing. When VIN is an ac and DAC B, making the devices extremely versatile and signal, the circuit performs 2-quadrant multiplication. allowing them to be configured in several operating modes, Table 7 shows the relationship between digital code and the such as unipolar output mode, 4-quadrant multiplication expected output voltage for unipolar operation using the 8-bit bipolar mode, or single-supply mode. Note that a matching AD5428. switch is used in series with the internal R A feedback resistor. FB If users attempt to measure RFBA, power must be applied to VDD Table 7. Unipolar Code to achieve continuity. Digital Input Analog Output (V) 1111 1111 –V (255/256) REF 1000 0000 –V (128/256) = –V /2 REF REF 0000 0001 –V (1/256) REF 0000 0000 –V (0/256) = 0 REF Rev. D | Page 16 of 32

Data Sheet AD5428/AD5440/AD5447 VINA (±10V) R11 AD5428/AD5440/AD5447 VREFA R RFBA R21 VDD C12 DATA DB0 IOUTA INPUTS BIUNFPFUETR LATCH 8R--/21R0- /D1A2-CB IAT VOUTA DB7 DB9 DB11 AGND AGND DAC A/B R RFBB R41 CS COLNOTGRICOL C22 IOUTB R/W LATCH 8-/10-/12-BIT VOUTB R-2R DAC B DGND AGND POWER-ON RESET VREFB R31 VINB (±10V) 12 RCH11IG,, RCH22 S APPHNEADESD RE A3 ,CM ROP4ML UIPFSEIEENRDSS AO TTNOILO YPN R I(F1E pGVFEA NTINOT A R2DpINJFGU) SIISNT GRM EOEQNRUT O IIRSSEC RDILE WLQAHUTEIRINOE NUD.S.ING 04462-030 Figure 38. Unipolar Operation Rev. D | Page 17 of 32

AD5428/AD5440/AD5447 Data Sheet Bipolar Operation Table 8. Bipolar Code In some applications, it may be necessary to generate full 4-quad- Digital Input Analog Output (V) rant multiplying operation or a bipolar output swing. This can 1111 1111 +VREF (127/128) easily be accomplished by using another external amplifier and 1000 0000 0 some external resistors, as shown in Figure 39. In this circuit, the 0000 0001 –VREF (127/128) second amplifier, A2, provides a gain of 2. Biasing the external 0000 0000 –VREF (128/128) amplifier with an offset from the reference voltage results in full Stability 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are In the I-to-V configuration, the I of the DAC and the inverting OUT created as the input data (D) is incremented from Code 0 (V = node of the op amp must be connected as close as possible, and OUT −V ) to midscale (V = 0 V) to full scale (V = +V ). proper PCB layout techniques must be used. Because every code REF OUT OUT REF When connected in bipolar mode, the output voltage is given by change corresponds to a step function, gain peaking may occur V  V D/2n1 V if the op amp has limited gain bandwidth product (GBP) and OUT REF REF there is excessive parasitic capacitance at the inverting node. where: This parasitic capacitance introduces a pole into the open-loop D is the fractional representation of the digital word loaded to response, which can cause ringing or instability in the closed- the DAC. loop applications circuit. D = 0 to 255 (AD5428) An optional compensation capacitor, C1, can be added in parallel = 0 to 1023 (AD5440) with R A for stability, as shown in Figure 38 and Figure 39. Too FB = 0 to 4095 (AD5447) small a value of C1 can produce ringing at the output, whereas n is the number of bits. too large a value can adversely affect the settling time. C1 should When V is an ac signal, the circuit performs 4-quadrant be found empirically, but 1 pF to 2 pF is generally adequate for IN multiplication. Table 8 shows the relationship between digital the compensation. code and the expected output voltage for bipolar operation using the 8-bit AD5428. VINA (±10V) R11 20Rk5 R62 AD5428/AD5440/AD5447 VREFA 20k R72 A2 R RFBA R21 10k VOUTA VDD C13 R11 DATA DB0 IOUTA 5k INPUTS BIUNFPFUETR LATCH 8R--/21R0- /D1A2-CB IAT A1 AGND DB7 DB9 DB11 AGND AGND DAC A/B R RFBB R41 CONTROL CS LOGIC C23 IOUTB R/W LATCH 8R--/21R0- /D1A2-CB IBT A3 R8 20k DGND 1R09k2 AGND PORWEESRE-TON 2R01k02 A4 VOUTB VREFB R12 5k R31 AGND 04462-031 VINB (±10V) 1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUTA = 0V WITH CODE 10000000 IN DAC A LATCH. ADJUST R3 FOR VOUTB = 0V WITH CODE 10000000 IN DAC B LATCH. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER. Figure 39. Bipolar Operation (4-Quadrant Multiplication) Rev. D | Page 18 of 32

Data Sheet AD5428/AD5440/AD5447 SINGLE-SUPPLY APPLICATIONS ADDING GAIN Voltage-Switching Mode In applications where the output voltage must be greater than Figure 40 shows the DACs operating in voltage switching mode. VIN, gain can be added with an additional external amplifier, or The reference voltage, V , is applied to the I A pin, and the it can be achieved in a single stage. Consider the effect of temper- IN OUT output voltage is available at the V A terminal. In this config- ature coefficients of the thin film resistors of the DAC. Simply REF uration, a positive reference voltage results in a positive output placing a resistor in series with the RFB resistor causes mismatches voltage, making single-supply operation possible. The output in the temperature coefficients, resulting in larger gain temper- from the DAC is voltage at constant impedance (the DAC ladder ature coefficient errors. Instead, the circuit in Figure 41 shows resistance). Therefore, an op amp is necessary to buffer the the recommended method for increasing the gain of the circuit. output voltage. The reference input no longer sees constant R1, R2, and R3 must have similar temperature coefficients, but input impedance, but one that varies with code. Therefore, the they need not match the temperature coefficients of the DAC. voltage input should be driven from a low impedance source. This approach is recommended in circuits where gains of greater than 1 are required. Note that R >> R2||R3 and a gain Note that V is limited to low voltages because the switches in FB IN error percentage of 100 × (R2||R3)/R must be taken into the DAC ladder no longer have the same source-drain drive FB consideration. voltage. As a result, their on resistance differs and degrades the integral linearity of the DAC. Also, VIN must not go negative by VDD more than 0.3 V, or an internal diode turns on, causing the device to exceed the maximum ratings. In this type of application, the full C1 VDD RFBA range of multiplying capability of the DAC is lost. VDD R1 R2 VIN R1 VREF8A-/10D-/A1C2-BIT IAOGUNTAD R3 VOUT GND R2 + R3 GAIN = R2 R2 RFBA VDD R2R3 VIN IAOGUNTAD VREFA VOUT N12 .. O ACIFTD1 EA DPS1IHT IASIOS ANE AH CLIGO PHMIN PSSEP NOESEMADITT ATIOMENDP L(F1IOFpIRFE RTCO.L A2RpFIT)Y M.AY BE REQUIREDR1=R2 +R3 04462-035 GND Figure 41. Increasing Gain of Current Output DAC NOTES 12 .. ACIFD1 A DP1IHT IASIOS ANE AH CLIGO PHMIN PSSEP NOESEMADITT ATIOMENDP L(F1IOFpIRFE RTCO.L A2RpFIT)Y M.AY BE REQUIRED 04462-033 Figure 40. Single-Supply Voltage-Switching Mode Rev. D | Page 19 of 32

AD5428/AD5440/AD5447 Data Sheet DIVIDER OR PROGRAMMABLE GAIN ELEMENT REFERENCE SELECTION Current-steering DACs are very flexible and lend themselves to When selecting a reference for use with the many applications. If this type of DAC is connected as the AD5428/AD5440/AD5447 series of current output DACs, pay feedback element of an op amp and R A is used as the input attention to the reference’s output voltage temperature coefficient FB resistor, as shown in Figure 42, the output voltage is inversely specification. This parameter not only affects the full-scale error, proportional to the digital input fraction, D. but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the For D = 1 − 2−n, the output voltage is system accuracy specifications. For example, an 8-bit system V V /DV /12n required to hold its overall specification to within 1 LSB over the OUT IN IN temperature range 0° to 50°C dictates that the maximum system VDD drift with temp-erature should be less than 78 ppm/°C. A 12-bit VIN system with the same temperature range to overall specification RFBA VDD within 2 LSBs requires a maximum drift of 10 ppm/°C. Choosing IOUTA a precision reference with low output temperature coefficient AGND VREFA minimizes this error source. Table 9 lists some references GND available from Analog Devices that are suitable for use with these current output DACs. AMPLIFIER SELECTION VOUT The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset N1.O ATDEDSITIONAL PINS OMITTED FOR CLARITY. 04462-040 vDoAltCag, eth. Be eincapuuste o offfs teht ev cooltdaeg-ed oefp aenn doepn at moupt pisu mt ruelstiisptlaiendc eb oyf t thhee Figure 42. Current-Steering DAC Used as a Divider or variable gain of the circuit. A change in the noise gain between Programmable Gain Element two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This As D is reduced, the output voltage increases. For small values output voltage change is superimposed on the desired change in of the digital fraction D, it is important to ensure that the output between the two codes and gives rise to a differential amplifier does not saturate and that the required accuracy is linearity error, which, if large enough, could cause the DAC to met. For example, an 8-bit DAC driven with the binary code be nonmonotonic. The input offset voltage should be <1/4 LSB 0x10 (0001 0000)—that is, 16 decimal—in the circuit of to ensure monotonic behavior when stepping through codes. Figure 42 should cause the output voltage to be 16 times V . IN However, if the DAC has a linearity specification of ±0.5 LSB, D The input bias current of an op amp also generates an offset at can have a weight in the range of 15.5/256 to 16.5/256 so that the the voltage output as a result of the bias current flowing in the possible output voltage is in the range of 15.5 VIN to 16.5 VIN— feedback resistor, RFB. Most op amps have input bias currents an error of 3%, even though the DAC itself has a maximum low enough to prevent significant errors in 12-bit applications. error of 0.2%. Common-mode rejection of the op amp is important in voltage- DAC leakage current is also a potential error source in divider switching circuits, because it produces a code-dependent error circuits. The leakage current must be counterbalanced by an at the voltage output of the circuit. Most op amps have adequate opposite current supplied from the op amp through the DAC. common-mode rejection for use at 8-, 10-, and 12-bit resolution. Because only a fraction, D, of the current into the V terminal REF Provided that the DAC switches are driven from true wideband, is routed to the I 1 terminal, the output voltage changes as OUT low impedance sources (V and AGND), they settle quickly. IN follows: Consequently, the slew rate and settling time of a voltage-   Output Error Voltage Due to DAC Leakage Leakage R /D switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, where R is the DAC resistance at the V terminal. REF minimize capacitance at the V node (the voltage output node REF For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that in this application) of the DAC by using low input capacitance is, 1/D) of 16, the error voltage is 1.6 mV. buffer amplifiers and careful board design. Most single-supply circuits include ground as part of the analog signal range, which in turns requires an amplifier that can handle rail-to-rail signals. Analog Devices offers a wide variety of single- supply amplifiers (see Table 10 and Table 11). Rev. D | Page 20 of 32

Data Sheet AD5428/AD5440/AD5447 Table 9. Suitable ADI Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 10. Suitable ADI Precision Op Amps 0.1 Hz to 10 Hz Part No. Supply Voltage (V) V (Max) (μV) I (Max) (nA) Noise (μV p-p) Supply Current (μA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 11. Suitable ADI High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) I (Max) (nA) Package B AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1,000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1,300 10,000 7,000 SOIC-8 Rev. D | Page 21 of 32

AD5428/AD5440/AD5447 Data Sheet PARALLEL INTERFACE 8xC51-to-AD5428/AD5440/AD5447 Interface Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or Figure 44 shows the interface between the AD5428/AD5440/ 12-bit parallel word format. Control lines CS and R/W allow AD5447 and the 8xC51 family of DSPs. To facilitate external data to be written to or read from the DAC register. A write data memory access, the address latch enable (ALE) mode is event takes place when CS and R/W are brought low, data enabled. The low byte of the address is latched with this output pulse during access to the external memory. AD0 to AD7 are available on the data lines fills the shift register, and the rising the multiplexed low order addresses and data bus, and they edge of CS latches the data and transfers the latched data-word require strong internal pull-ups when emitting 1s. During to the DAC register. The DAC latches are not transparent; access to external memory, A8 to A15 are the high order therefore, a write sequence must consist of a falling and rising address bytes. Because these ports are open drain, they also edge on CS to ensure that data is loaded into the DAC register require strong internal pull-ups when emitting 1s. and its analog equivalent is reflected on the DAC output. A read event takes place when R/W is held high and CS is A8TO A15 ADDRESS BUS brought low. Data is loaded from the DAC register, goes back into the input register, and is output onto the data line, where it AD5428/ can be read back to the controller for verification or diagnostic 80511 AD5440/ AD54471 purposes. The input and DAC registers of these devices are not DAEDCDORDEESRS CS transparent; therefore, a falling and rising edge of CS is required to load each data-word. WR R/W MICROPROCESSOR INTERFACING DB0 TO DB11 ALE 8-BIT LATCH ADSP-2191M and Family to AD5428/AD5440/AD5447 Interface Fthigeu AreD 4S3P -s2h1o9w1sM th see rAieDs 5o4f2 D8/SAPDs a5s4 a4 0m/AemDo5r4y4-7m inapteprefadc dedev tioc e. 1AADDD0 ITTOIO ANDA7L PINS OMITTED FOR CLADRAITTYA. BUS 04462-057 A single wait state may be necessary to interface the AD5428/ Figure 44. 8xC51-to-AD5428/AD5440/AD5447 Interface AD5440/AD5447 to the ADSP-2191M, depending on the clock ADSP-BF534 to AD5428/AD5440/AD5447 Interface speed of the DSP. The wait state can be programmed via the Figure 45 shows a typical interface between the AD5428/ data memory wait state control register of the ADSP-2191M AD5440/AD5447 and the ADSP-BF534 family of DSPs. The (see the ADSP-2191M family user manual for details). asynchronous memory write cycle of the processor drives the ADDR0TO ADDRESS BUS digital inputs of the DAC. The AMSx line is actually four ADRR13 memory select lines. Internal ADDR lines are decoded into AMS , and then these lines are inserted as chip selects. The AD5428/ 3–0 ADSP-2191M1 AD5440/ rest of the interface is a standard handshaking operation. DMS DAEDCDORDESESR CS AD54471 ADDR1TO ADDRESS BUS ADRR19 WR R/W AD5428/ DB0 TO DB11 ADSP-BF5341 AD5440/ AMSx DAEDCDORDESESR CS AD54471 DATA 0 TO 1ADDDITAITOAN A23L PINS OMITTED FOR CLADRAITTYA. BUS 04462-055 AWE DRB/W0TO DB11 Figure 43. ADSP-2191M-to-AD5428/AD5440/AD5447 Interface DATA 0TO 1ADDITIDOANTAAL 2 P3INS OMITTED FOR CLARIDTYA.TA BUS 04462-056 Figure 45. ADSP-BF534-to-AD5428/AD5440/AD5447 Interface Rev. D | Page 22 of 32

Data Sheet AD5428/AD5440/AD5447 PCB LAYOUT AND POWER SUPPLY DECOUPLING microstrip technique is by far the best method, but its use is not always possible with a double-sided board. In this technique, In any circuit where accuracy is important, careful the component side of the board is dedicated to the ground consideration of the power supply and ground return layout plane, and signal traces are placed on the soldered side. helps to ensure the rated performance. The printed circuit board on which the AD5428/AD5440/AD5447 is mounted It is good practice to use compact, minimum lead length PCB should be designed so that the analog and digital sections are layout design. Leads to the input should be as short as possible separate and confined to certain areas of the board. If the DAC to minimize IR drops and stray inductance. is in a system where multiple devices require an AGND-to- The PCB metal traces between V and R should also be REF FB DGND connection, the connection should be made at one matched to minimize gain error. To maximize high frequency point only. The star ground point should be established as close performance, the I-to-V amplifier should be located as close as as possible to the device. possible to the device. These DACs should have ample supply bypassing of 10 μF in EVALUATION BOARD FOR THE AD5447 parallel with 0.1 μF on the supply located as close as possible to The evaluation board consists of an AD5447 DAC and a the package, ideally right up against the device. The 0.1 μF current-to-voltage amplifier, the AD8065. Included on the capacitor should have low effective series resistance (ESR) and evaluation board is a 10 V reference, the ADR01. An external low effective series inductance (ESI), like the common ceramic reference may also be applied via an SMB input. types of capacitors that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal The evaluation kit consists of a CD-ROM with self-installing logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic PC software to control the DAC. The software simply allows the capacitors should also be applied at the supplies to minimize user to write a code to the device. transient disturbance and filter out low frequency ripple. POWER SUPPLIES FOR THE EVALUATION BOARD Components, such as clocks, that produce fast-switching signals The board requires ±12 V and +5 V supplies. The +12 V V DD should be shielded with digital ground to avoid radiating noise and −12 V V are used to power the output amplifier; the +5 V SS to other parts of the board, and they should never be run near is used to power the DAC (V ) and transceivers (V ). DD1 CC the reference inputs. Both supplies are decoupled to their respective ground plane Avoid crossover of digital and analog signals. Traces on with 10 μF tantalum and 0.1 μF ceramic capacitors. opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough on the board. A Rev. D | Page 23 of 32

AD5428/AD5440/AD5447 Data Sheet B A P P O/ O/ J6 J1 P4 P1 T T C2310F + C240.1F6 C2510F + C260.1F C910F + C100.1F6 C1110F + C120.1F 4V–V+7 4V–V+7 VSS 2 3U7 VDD VSS 2 3U3 VDD C221.8pF C71.8pF J5 EXTREF B B F V1DDC510F + C60.1F TP3TP2 J2 EXTREF A ALK1 4VOUT C80.11 U1 AD54472118V0DBDD17D1B61DB251DB341D4B23RBFB31D5B24BI21D6BOUT117DB018DB3RA9DB9FB280DB1AIOUT71D1B6_DACA/B2291CSVAREF02/RW4VBREF5DGNDAGND 1DGND DD 3+VIN U2 +C45TRIM0.1FGND2 V C310F 0DB1DB2DB3DB4DBDB56DB7DBDB89DB01DBDB11 CSRW J3 D 1DD CC N V V G VDD A VSS J4 C1410F C1610F C1810F C2010F + + + + F C130.1F C150.1F C170.1F C190.1F C10.1 CC CC V U442VCCLEBA32CEBAOEBA517BA0616B1A175B2A184B3A913BA4022B5A12B16A22B07A41LEABCEAB13OEABGND74ABT543 C2V0.1F U542VCCLEBA32CEBAOEBA517B0A61B61A175B2A814B3A913B4A02B2A5121B6A220B7A41LEABCEAB31OEABGND 74ABT543 3–2P 2–2P –12P 4–P2 6–2P 5–P2 123456789011121 123456789011121 12 11 01 9 B 0Y Y1 2Y 3Y 6- U 0A 1A E 41 31 15 GND D 4 5 6 7 7–1P–61P5–1P4–1P3–P12–1P U6-A 0Y0A1YA12Y 3EY 13–P1 11–P 41–1P P1–19P1–20P1–21P1–22P1–23P1–24P1–25P1–26P1–27P1–28P1–29P1–30 VCC C170.1F DGND 281–P391–P 1631–P 04464-037 Figure 46. Schematic of AD5447 Evaluation Board Rev. D | Page 24 of 32

Data Sheet AD5428/AD5440/AD5447 04462-036 Figure 47. Component-Side Artwork 04462-038 Figure 48. Silkscreen—Component-Side View (Top Layer) Rev. D | Page 25 of 32

AD5428/AD5440/AD5447 Data Sheet 04462-039 Figure 49. Solder-Side Artwork Rev. D | Page 26 of 32

Data Sheet AD5428/AD5440/AD5447 BILL OF MATERIALS Table 12. Bill of Materials Name/Position Part Description Value Tolerance (%) Stock Code C1 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C2 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C3 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C4 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C5 Tantalum capacitor—Taj series 10 μF, 10 V 10 FEC 197-130 C6 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C7 NPO ceramic capacitor 1.8 pF 10 FEC 721-876 C8 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C9 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C10 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C11 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C12 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C13 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C14 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C15 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C16 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C17 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C18 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C19 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C20 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C21 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C22 NPO ceramic capacitor 1.8 pF 10 FEC 721-876 C23 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C24 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 C25 Tantalum capacitor—Taj series 10 μF, 20 V 10 FEC 197-427 C26 X7R ceramic capacitor 0.1 μF 10 FEC 499-675 CS, DB0 to DB11 Red testpoint FEC 240-345 (Pack) J1 to J6 SMB socket FEC 310-682 J2 SMB socket FEC 310-682 J3 SMB socket FEC 310-682 J4 SMB socket FEC 310-682 J5 SMB socket FEC 310-682 J6 SMB socket FEC 310-682 LK1 3-pin header (2 × 2) FEC 511-791 and FEC 528-456 P1 36-pin Centronics connector FEC 147-753 P2 6-pin terminal block FEC 151-792 RW Red testpoint FEC 240-345 (Pack) TP1 to TP4 Red testpoint FEC 240-345 (Pack) U1 AD5447 AD5447YRU U2 ADR01 ADR01AR U3 AD8065 AD8065AR U4, U5 74ABT543 Fairchild 74ABT543CMTC U6 74139 CD74HCT139M U7 AD8065 AD8065AR Each Corner Rubber stick-on feet FEC 148-922 Rev. D | Page 27 of 32

AD5428/AD5440/AD5447 Data Sheet OVERVIEW OF MULTIPLYING DAC DEVICES Table 13. Part No. Resolution No. DACs INL (LSB) Interface Package1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. D | Page 28 of 32

Data Sheet AD5428/AD5440/AD5447 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 50. 20-Lead Thin Shrink Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 51. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters Rev. D | Page 29 of 32

AD5428/AD5440/AD5447 Data Sheet ORDERING GUIDE Model1 Resolution INL (LSB) Temperature Range Package Description Package Option AD5428YRU 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRU-REEL7 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ-REEL 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5428YRUZ-REEL7 8 ±0.5 –40°C to +125°C 20-Lead TSSOP RU-20 AD5440YRU 10 ±0.5 –40°C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ 10 ±0.5 –40°C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ-REEL 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5440YRUZ-REEL7 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRU 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ-REEL 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 AD5447YRUZ-REEL7 12 ±1 –40°C to +125°C 24-Lead TSSOP RU-24 EVAL-AD5447EBZ Evaluation Kit 1 Z = RoHS Compliant Part. Rev. D | Page 30 of 32

Data Sheet AD5428/AD5440/AD5447 NOTES Rev. D | Page 31 of 32

AD5428/AD5440/AD5447 Data Sheet NOTES ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04462-0-1/16(D) Rev. D | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5447EBZ AD5440YRUZ AD5428YRUZ-REEL AD5447YRUZ AD5428YRUZ AD5447YRU AD5440YRUZ- REEL AD5447YRUZ-REEL7 AD5428YRUZ-REEL7 AD5440YRU AD5428YRU AD5447YRUZ-REEL AD5440YRUZ- REEL7 AD5428YRU-REEL7