12-/14-Bit High Bandwidth Multiplying DACs with Serial Interface Data Sheet AD5444/AD5446 FEATURES FUNCTIONAL BLOCK DIAGRAM 12 MHz multiplying bandwidth VDD VREF INL of ±0.5 LSB at 12 bits RFB Pin-compatible 12-/14-bit current output DAC R AD5444/ 2.5 V to 5.5 V supply operation AD5446 12-BIT IOUT1 R-2R DAC 10-lead MSOP package IOUT2 ±10 V reference input 50 MHz serial interface DAC REGISTER 2.7 MSPS update rate POWER-ON Extended temperature range: −40°C to +125°C RESET INPUT LATCH 4-quadrant multiplication Power-on reset with brownout detection SYNC 0.4 µA typical current consumption SCLK INCPOUNTT RSOHILF TL ORGEIGCISATNEDR SDO SDIN GAuPaPraLnICteAeTd ImOoNnSo tonic GND 04588-001 Figure 1. Portable, battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming GENERAL DESCRIPTION The AD5444/AD54461 are CMOS 12-bit and 14-bit, current The applied external reference input voltage (V ) determines REF output, digital-to-analog converters (DACs). Operating from a the full-scale output current. These parts can handle ±10 V single 2.5 V to 5.5 V power supply, these devices are suited for inputs on the reference, despite operating from a single-supply battery-powered and other applications. power supply of 2.5 V to 5.5 V. An integrated feedback resistor (R ) provides temperature tracking and full-scale voltage output As a result of the CMOS submicron manufacturing process, FB when combined with an external current-to-voltage precision these parts offer excellent 4-quadrant multiplication char- amplifier. The AD5444/AD5446 DACs are available in small acteristics of up to 12 MHz. 10-lead MSOP packages, which are pin-compatible with the These DACs use a double-buffered, 3-wire serial interface that AD5425/AD5426/AD5432/AD5443 family of DACs. is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP The EV-AD5443/46/53SDZ board is available for evaluating interface standards. On power-up, the internal shift register and DAC performance. For more information, see the UG-327 latches are filled with 0s, and the DAC output is at zero scale. evaluation board user guide. 1 US Patent Number 5,689,257. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5444/AD5446 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DAC Section................................................................................ 15 Applications ....................................................................................... 1 Circuit Operation ....................................................................... 15 General Description ......................................................................... 1 Single-Supply Applications ....................................................... 17 Functional Block Diagram .............................................................. 1 Adding Gain ................................................................................ 17 Revision History ............................................................................... 2 Divider or Programmable Gain Element ................................ 17 Specifications ..................................................................................... 3 Amplifier Selection .................................................................... 18 Timing Characteristics ................................................................ 5 Reference Selection .................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Serial Interface ................................................................................ 20 ESD Caution .................................................................................. 6 Microprocessor Interfacing ....................................................... 21 Pin Configuration and Function Descriptions ............................. 7 PCB Layout and Power Supply Decoupling ................................ 23 Typical Performance Characteristics ............................................. 8 Overview of Current Output Devices .......................................... 24 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 25 General Description ....................................................................... 15 Ordering Guide .......................................................................... 25 REVISION HISTORY 2/16—Rev. E to Rev. F Changes to Ordering Guide .......................................................... 28 Changes to Applications Section .................................................... 1 Changes to Features .......................................................................... 1 Deleted Positive Output Voltage Section and Figure 41; Changes to General Description ..................................................... 1 Renumbered Sequentially .............................................................. 17 Changes to Table 1 ............................................................................. 3 Changes to Adding Gain Section ................................................. 17 Changes to Figure 22 ...................................................................... 10 Changes to ADSP-2191M to AD5444/AD5446 Interface Changes to Figure 23 ...................................................................... 10 Section, Blackfin to AD5444/AD5446 Interface Section, Changes to Table 9 .......................................................................... 19 Figure 46, Figure 47, and Figure 48 .............................................. 21 Changes to Table 12 ....................................................................... 27 Changes to Overview of Current Output Devices Section Updated Outline Dimensions ....................................................... 28 Heading ............................................................................................ 24 Changes to Ordering Guide .......................................................... 28 Changes to Ordering Guide .......................................................... 25 4/05—Rev. 0 to Rev. A 6/13—Rev. D to Rev. E Added AD5446 ................................................................... Universal Changes to General Description Section ...................................... 1 Changes to Features .......................................................................... 1 Change to Figure 46 and Figure 47 .............................................. 21 Changes to General Description ..................................................... 1 Changes to Ordering Guide .......................................................... 25 Changes to Specifications ................................................................. 3 Inserted Figure 7; Renumbered Sequentially................................. 9 4/12—Rev. C to Rev. D Inserted Figure 9; Renumbered Sequentially................................. 9 Changes to General Description Section ...................................... 1 Inserted Figure 13; Renumbered Sequentially ........................... 10 Deleted Evaluation Board for the DAC Section ......................... 23 Changes to Figure 22 ...................................................................... 11 Deleted Power Supplies for the Evaluation Board Section ....... 23 Changes to Figure 23 ...................................................................... 11 Deleted Figure 54; Renumbered Sequentially............................. 24 Changes to Serial Interface ............................................................ 20 Deleted Figure 55 and Figure 56 ................................................... 25 Changes to Figure 44 ...................................................................... 20 Updated Outline Dimensions ....................................................... 25 Changes to Figure 45 ...................................................................... 20 Changes to Ordering Guide .......................................................... 25 Updated Outline Dimensions ....................................................... 28 Deleted Figure 57 ............................................................................ 26 Changes to Ordering Guide .......................................................... 28 4/07—Rev. B to Rev. C 10/04—Revision 0: Initial Version Changes to Table 9 .......................................................................... 19 Rev. F | Page 2 of 28

Data Sheet AD5444/AD5446 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 10 V, I 2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T to T , DD REF OUT MIN MAX unless otherwise noted. DC performance measured with OP177, and ac performance measured with AD8038, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Conditions STATIC PERFORMANCE AD5444 Resolution 12 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±1 LSB Gain Error ±0.5 LSB AD5446 Resolution 14 Bits Relative Accuracy ±2 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±4 LSB Gain Error ±2.5 LSB Gain Error Temperature Coefficient1 ±2 ppm FSR/°C Output Leakage Current ±1 nA Data = 0x0000, T = 25°C, I 1 A OUT ±10 nA Data = 0x0000, T = −40°C to +125°C, I 1 A OUT REFERENCE INPUT1 Reference Input Range ±10 V V Input Resistance 7 9 11 kΩ Input resistance T = −50 ppm/°C REF C R Feedback Resistance 7 9 11 kΩ Input resistance T = −50 ppm/°C FB C Input Capacitance Zero-Scale Code 18 22 pF Full-Scale Code 18 22 pF DIGITAL INPUTS/OUTPUTS1 Input High Voltage, V 2.0 V V = 3.6 V to 5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5 V, I = 200 µA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 µA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5 V, I = 200 µA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 µA DD SINK Input Leakage Current, I ±1 nA T = 25°C IL A ±10 nA T = −40°C to +125°C A Input Capacitance 10 pF Rev. F | Page 3 of 28

AD5444/AD5446 Data Sheet Parameter Min Typ Max Unit Conditions DYNAMIC PERFORMANCE1 Reference Multiplying Bandwidth 12 MHz V = ±3.5 V, DAC loaded with all 1s REF Multiplying Feedthrough Error V = ±3.5 V, DAC loaded with all 0s REF 72 dB 100 kHz 64 dB 1 MHz 44 dB 10 MHz Output Voltage Settling Time V = 10 V, R = 100 Ω, DAC latch alternately REF LOAD loaded with 0s and 1s Measured to ±1 mV of FS 100 110 ns Measured to ±4 mV of FS 24 40 ns Measured to ±16 mV of FS 16 33 ns Digital Delay 20 40 ns Interface delay time 10%-to-90% Settling Time 10 30 ns Rise and fall time, V = 10 V, R = 100 Ω REF LOAD Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V = 0 V REF Output Capacitance I 1 13 pF DAC latches loaded with all 0s OUT 28 pF DAC latches loaded with all 1s I 2 18 pF DAC latches loaded with all 0s OUT 5 pF DAC latches loaded with all 1s Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Analog THD 83 dB V = 3.5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 1 MHz, V = 3.5 V REF 50 kHz f 71 dB OUT 20 kHz f 77 dB OUT Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wide Band) Clock = 10 MHz, V = 3.5 V REF 50 kHz f 78 dB OUT 20 kHz f 74 dB OUT SFDR Performance (Narrow Band) Clock = 1 MHz, V = 3.5 V REF 50 kHz f 87 dB OUT 20 kHz f 85 dB OUT Intermodulation Distortion 79 dB f = 20 kHz, f = 25 kHz, clock = 1 MHz, V = 3.5 V 1 2 REF POWER REQUIREMENTS Power Supply Range, V 2.5 5.5 V DD Supply Current, I 0.4 10 µA T = −40°C to +125°C, logic inputs = 0 V or V DD A DD 0.6 µA T = 25°C, logic inputs = 0 V or V A DD Power Supply Sensitivity1 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design and characterization; not subject to production test. Rev. F | Page 4 of 28

Data Sheet AD5444/AD5446 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. V = 2.5 V to 5.5 V, DD IL IH DD V = 10 V, I 2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications T to T , unless otherwise noted. REF OUT MIN MAX Table 2. V = 4.5 V to V = 2.5 V to DD DD Parameter1 5.5 V 5.5 V Unit Conditions/Comments f 50 50 MHz max Maximum clock frequency. SCLK t 20 20 ns min SCLK cycle time. 1 t 8 8 ns min SCLK high time. 2 t 8 8 ns min SCLK low time. 3 t 8 8 ns min SYNC falling edge to SCLK active edge setup time. 4 t 5 5 ns min Data setup time. 5 t 4.5 4.5 ns min Data hold time. 6 t 5 5 ns min SYNC rising edge to SCLK active edge setup time 7 t 30 30 ns min Minimum SYNC high time. 8 t 23 30 ns min SCLK active edge to SDO valid. 9 Update Rate 2.7 2.7 MSPS Consists of cycle time, SYNC high time, data setup time and output voltage settling time. 1 Guaranteed by design and characterization; not subject to production test. t1 SCLK t4 t2 t3 t7 SYNC t8 t6 t5 SDIN DB15 DB0 04588-002 Figure 2. Standalone Timing Diagram t1 SCLK t2 t3 t7 t4 t8 SYNC t6 t5 DB15 DB0 SDIN DB15 (N) DB0 (N) (N + 1) (N + 1) t9 SDO DB15 (N) DB0 (N) NADEDLOETTGTEEEERRS ONMFAIN TSEICVDLE KBL.YY T ,C IDMOAINNTTGAR CAOASLN AB BBITEOS VC. EILN,O WTCHIKTIESHD CS IACNSLTEKO, IDINNAVPTEUART T ISSEH DCI.FLTO CRKEEGDIS OTEURT OOFN SRDISOIN OGN E FDAGLEL IONFG SCLK AS 04588-003 Figure 3. Daisy-Chain Timing Diagram Rev. F | Page 5 of 28

AD5444/AD5446 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 100 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 3. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V DD the maximum operating conditions for extended periods may V , R to GND −12 V to +12 V REF FB affect product reliability. I 1, I 2 to GND −0.3 V to +7 V OUT OUT Logic Inputs and Outputs1 −0.3 V to V + 0.3 V Only one absolute maximum rating can be applied at any one DD Input Current (All Pins Except Supplies) ±10 mA time. Operating Temperature Range −40°C to +125°C Extended (Y Version) 200µA IOL Storage Temperature Range −65°C to +150°C TO VOH (MIN) +VOL (MAX) Junction Temperature 150°C OUTPPUINT CL 2 10-lead MSOP θ Thermal Impedance 206°C/W 20pF LIRe aRde fTloewm,p Peeraaktu TJreAem, Spoelrdaetruinreg ( (<1200 s seecc) ) 320305°°CC 200µA IOH 04588-004 Figure 4. Load Circuit for SDO Timing Specifications 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. ESD CAUTION Rev. F | Page 6 of 28

Data Sheet AD5444/AD5446 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IOUT1 1 10 RFB IOUT2 2 AADD55444446/ 9 VREF GND 3 8 VDD TOP VIEW SCLK 4 (Not to Scale) 7 SDO SDIN 5 6 SYNC04588-005 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 I 1 DAC Current Output. OUT 2 I 2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system. OUT 3 GND Ground Pin. 4 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. 5 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. 6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low, data is loaded to the shift register on the active edge of the following clocks. The output updates on the rising edge of SYNC. 7 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to data loaded to the shift register. 8 V Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. DD 9 V DAC Reference Voltage Input. REF 10 R DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output. FB Rev. F | Page 7 of 28

AD5444/AD5446 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 2.0 0.4 TVAR E=F 2=5 °1C0V 1.6 TVVARD ED=F = 2= 55 °1VC0V 0.3 VDD = 5V 1.2 0.2 0.8 B) 0.1 B) 0.4 S S L (L 0 L (L 0 N N I–0.1 D –0.4 –0.2 –0.8 –0.3 –1.2 ––00..54 04588-006 ––21..06 04588-077 0 512 1024 1536 2048 2560 3072 3584 4096 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE CODE Figure 6. INL vs. Code (12-Bit DAC) Figure 9. DNL vs. Code (14-Bit DAC) 2.0 1.00 TA = 25°C 1.6 VREF = 10V TA = 25°C VDD = 5V 0.75 VDD = 5V 1.2 AD5444 0.50 MAX INL 0.8 0.4 0.25 B) B) INL (LS –0.40 INL (LS–0.250 MIN INL –0.8 –0.50 –1.2 ––21..06 04588-076 ––10..0705 04588-047 0 2048 4096 6144 8192 10240 12288 14336 16384 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 7. INL vs. Code (14-Bit DAC) Figure 10. INL vs. Reference Voltage 1.0 2.0 0.8 VTAR E=F 2=5 °1C0V 1.5 TVAD D= =2 55°VC 0.6 VDD = 5V AD5444 1.0 0.4 0.5 MAX DNL B) 0.2 B) S S L (L 0 L (L 0 N N MIN DNL D–0.2 D –0.5 –0.4 –1.0 –0.6 ––10..08 04588-008 ––21..05 04588-048 0 512 1024 1536 2048 2560 3072 3584 4096 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 8. DNL vs. Code (12-Bit DAC) Figure 11. DNL vs. Reference Voltage Rev. F | Page 8 of 28

Data Sheet AD5444/AD5446 1.0 0.3 0.8 TA = 25°C VREF = 10V VREF = 10V 0.6 VDD = 5V 0.2 0.4 B)0.1 E (LSB) 0.20 RROR (LS 0 VVDDDD == 35VV U E T–0.2 N –0.4 GAI–0.1 –0.6 –0.2 ––10..08 04588-013 –0.3 04588-049 0 512 1024 1536 2048 2560 3072 3584 4096 –60 –40 –20 0 20 40 60 80 100 120 140 CODE TEMPERATURE (°C) Figure 12. TUE vs. Code (12-Bit DAC) Figure 15. Gain Error vs. Temperature 2.0 1.6 TVVARD ED=F = 2= 55 °1VC0V 12..50 TVAADD D5= 4 =24 554°VC 1.2 1.0 0.8 B) SB) 0.4 R (LS0.5 L 0 O INL ( –0.4 N ERR 0 AI–0.5 –0.8 G –1.0 –1.2 ––21..060 2048 4096 6144 8192 10240 12288 14336 1638404588-078 ––21..05 04588-051 2 3 4 5 6 7 8 9 10 CODE REFERENCE VOLTAGE (V) Figure 13. TUE vs. Code (14-Bit DAC) Figure 16. Gain Error vs. Reference Voltage 2.0 2.0 TA = 25°C 1.5 VDD = 5V AD5444 IOUT1, VDD = 5V 1.6 1.0 MAX TUE A) B)0.5 E (n1.2 IOUT1, VDD = 3V S G TUE (L–0.50 MIN TUE 1 LEAKA0.8 UT O –1.0 I 0.4 ––21..052 3 4 5 6 7 8 9 1004588-052 0 04588-017 –40 –20 0 20 40 60 80 100 120 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 14. TUE vs. Reference Voltage Figure 17. I 1 Leakage Current vs. Temperature OUT Rev. F | Page 9 of 28

AD5444/AD5446 Data Sheet 2.5 1.8 TA = 25°C TA = 25°C 1.6 2.0 1.4 VIH VIL URRENT (mA)1.5 VDD = 5V D VOLTAGE (V) 11..20 C L 0.8 SUPPLY 1.0 THRESHO 0.6 0.4 0.5 0 VDD = 3V 04588-018 0.20 04588-053 0 1 2 3 4 5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 18. Supply Current vs. Logic Input Voltage Figure 21. Threshold Voltage vs. Supply Voltage 0.7 10 ALL 1s TLAO A= D2I5N°GC 0.6 ALL 0s 0 ALL ON ZS TO FS DB13 –10 DB12 T (µA)0.5 –20 DDBB1110 REN0.4 VDD = 5V dB) –30 DB9 UR N ( DB8 Y C0.3 GAI –40 DB7 L P DB6 P –50 SU0.2 DB5 –60 DB4 VDD = 3V DB3 VDD = 5V 0.10 04588-019 ––8700 DB2 VCARDCEO8F0M 3=P8 ±= A3 1M.5.8PVpLFIFIER 04588-083 –40 –20 0 20 40 60 80 100 120 10k 100k 1M 10M 100M TEMPERATURE (°C) FREQUENCY (Hz) Figure 19. Supply Current vs. Temperature Figure 22. Reference Multiplying Bandwidth vs. Frequency and Code 6 0.6 TA = 25°C AD5444 0.4 LOADING 0101 0101 0101 5 0.2 A) m4 0 ( T RREN3 N (dB) –0.2 CU VDD = 5V GAI –0.4 Y L PP2 –0.6 U S –0.8 TA = 25°C 1 VDD = 5V 0 VDD = 3V 04588-055 ––11..20 VCARDCEO8F0M 3=P8 ±= A3 1M.5.8PVpLFIFIER 04588-084 1 10 100 1k 10k 100k 1M 10M 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 20. Supply Current vs. Update Rate Figure 23. Reference Multiplying Bandwidth vs. Frequency—All 1s Loaded Rev. F | Page 10 of 28

Data Sheet AD5444/AD5446 3 10 TA = 25°C TA = 25°C VDD = 5V 0 VDD = 3V AD8038AMPLIFIER –10 0 –20 –30 AIN(dB) –3 SRR(dB)––4500 FULL SCALE G P –60 ZERO SCALE –70 –6 VREF =±2V,AD8038 CCOMP = 1pF VREF =±2V,AD8038 CCOMP = 1.5pF –80 –9 VVVRRREEEFFF ===±±±111555VVV,,,AAADDD888000333888 CCCCCCOOOMMMPPP === 111p..58FppFF 04588-057 –1–0900 04588-060 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Reference Multiplying Bandwidth vs. Frequency Figure 27. Power Supply Rejection Ratio vs. Frequency and Compensation Capacitor 0.08 –60 V0xD7DF =F5TVO 0x800 TA = 25°C TVAD D= =2 55°VC 0.06 NRG = 2.154nV-s VARDE8F0 3=8 0AVMP –65 VREF =±3.5V E(V) 0.04 V0NxDR7DGF = F= 3 T1VO.7 904xn80V0-s CCOMP = 1.8pF –70 G B) OLTA 0.02 N(d–75 V + UT 0 HD P T OUT–0.02 V0xD8D0 =05TVO 0x7FF –80 NRG = 0.694nV-s –85 ––00..0064 V0NxDR8DG0 =0 =5T 0VO.6 09x47nFVF-s 04588-058 –90 04588-061 50 75 100 125 150 175 200 225 250 100 1k 10k 100k TIME (ns) FREQUENCY (Hz) Figure 25. Midscale Transition, V = 0 V Figure 28. THD + Noise vs. Frequency REF –1.66 100 V0xD7DF =F5TVO 0x800 TA = 25°C MCLK = 200kHz –1.68 NRG = 2.154nV-s VREF = 3.5V MCLK = 500kHz AD8038AMP 80 V)–1.70 0VxD7DF =F 3TVO 0x800 CCOMP = 1.8pF MCLK = 1MHz E( NRG = 1.794nV-s OLTAG–1.72 R(dB) 60 V D UT–1.74 SF 40 P T U O–1.76 VDD =5V 0x800TO 0x7FF 20 NRG = 0.694nV-s ––11..8708 V0NxDR8DG0 =0 =5T 0VO.6 09x47nFVF-s 04588-059 0 TVAARD E8=F0 23=58 °3CA.5MVP 04588-062 50 75 100 125 150 175 200 225 250 0 10 20 30 40 50 TIME (ns) fOUT (kHz) Figure 26. Midscale Transition, V = 3.5 V Figure 29. Wideband SFDR vs. f Frequency REF OUT Rev. F | Page 11 of 28

AD5444/AD5446 Data Sheet 0 0 TA = 25°C TA = 25°C VDD = 5V VDD = 5V –20 VARDE8F0 3=8 3A.5MVP –20 AVRDE8F0 3=8 3A.5MVP –40 –40 B) B) R(d–60 R(d–60 D D SF SF –80 –80 –100 –100 –120 04588-063 –120 04588-065 0 100k 200k 300k 400k 500k 10k 15k 20k 25k 30k FREQUENCY(Hz) FREQUENCY(Hz) Figure 30. Wideband SFDR , fOUT = 20 kHz, Clock = 1 MHz Figure 32. Narrow-Band SFDR, fOUT = 20 kHz, Clock = 1 MHz 0 0 TA = 25°C TA = 25°C VDD = 5V VDD = 5V –20 VARDE8F0 3=8 3A.5MVP –20 VARDE8F0 3=8 3A.5MVP –40 –40 B) B) d d ( ( R–60 R–60 D D F F S S –80 –80 –100 –100 –120 04588-064 –120 04588-066 0 100k 200k 300k 400k 500k 30k 40k 50k 60k 70k FREQUENCY(Hz) FREQUENCY(Hz) Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 1 MHz Figure 33. Narrow-Band SFDR, fOUT = 50 kHz, Clock = 1 MHz Rev. F | Page 12 of 28

Data Sheet AD5444/AD5446 0 80 –10 TVAR E=F 2=5 °3C.5V TAAD 8=0 2358°CAMP AD8038AMP 70 –20 –30 Hz) 60 FLUOLALD SECDATLOE DAC V/ 50 –40 n B) E( d S D(–50 OI 40 M N MIDSCALE I–60 PUT 30 LOADEDTO DAC T –70 U O 20 –80 ZERO SCALE –1–0900 04588-067 100 LOADEDTO DAC 04588-069 10k 15k 20k 25k 30k 35k 100 1k 10k 100k 1M FREQUENCY(Hz) FREQUENCY (Hz) Figure 34. Narrow-Band IMD, f = 20 kHz and 25 kHz, Clock = 1 MHz Figure 36. Output Noise Spectral Density OUT 0 TA = 25°C –10 VREF = 3.5V AD8038AMP –20 –30 –40 B) d (–50 D M I–60 –70 –80 –1–0900 04588-068 0 100k 200k 300k 400k 500k FREQUENCY(Hz) Figure 35. Wideband IMD, f = 20 kHz and 25 kHz, Clock = 1 MHz OUT Rev. F | Page 13 of 28

AD5444/AD5446 Data Sheet TERMINOLOGY Relative Accuracy or Integral Nonlinearity Digital Feedthrough Relative accuracy or integral nonlinearity is a measure of the When the device is not selected, high frequency logic activ- maximum deviation from a straight line passing through the ity on the device’s digital inputs can be capacitively coupled endpoints of the DAC transfer function. It is measured after through the device to show up as noise on the I 1 and I 2 OUT OUT adjusting for zero scale and full scale and is normally expressed pins and, subsequently, into the following circuitry. This noise is in LSBs or as a percentage of full-scale reading. digital feedthrough. Differential Nonlinearity Multiplying Feedthrough Error Differential nonlinearity is the difference between the measured Multiplying feedthrough error is due to capacitive feedthrough change and the ideal 1 LSB change between any two adjacent from the DAC reference input to the DAC I 1 line, when all OUT codes. A specified differential nonlinearity of −1 LSB maximum 0s are loaded to the DAC. over the operating temperature range ensures monotonicity. Total Harmonic Distortion (THD) Gain Error The DAC is driven by an ac reference. The ratio of the rms sum Gain error or full-scale error is a measure of the output error of the harmonics of the DAC output to the fundamental value is between an ideal DAC and the actual device output. For this the THD. Usually only the lower-order harmonics, such as second DAC, ideal maximum output is V − 1 LSB. Gain error of the to fifth, are included. REF DAC is adjustable to zero with external resistance. V 2+V 2+V 2+V 2 Output Leakage Current THD=20log 2 3 4 5 V Output leakage current is current that flows in the DAC ladder 1 switches when the ladder is turned off. For the I 1 line, it can Digital Intermodulation Distortion OUT be measured by loading all 0s to the DAC and measuring the Second-order intermodulation (IMD) measurements are the I 1 current. Minimum current flows in the I 2 line when relative magnitudes of the fa and fb tones digitally generated by OUT OUT the DAC is loaded with all 1s. the DAC and the second-order products at 2fa − fb and 2fb − fa. Output Capacitance Compliance Voltage Range Capacitance from I 1 or I 2 to AGND. The maximum range of (output) terminal voltage for which OUT OUT the device provides the specified characteristics. Output Current Settling Time The amount of time it takes for the output to settle to a speci- Spurious-Free Dynamic Range (SFDR) fied level for a full-scale input change. For this device, it is The usable dynamic range of a DAC before spurious noise specified with a 100 Ω resistor to ground. The settling time interferes or distorts the fundamental signal. SFDR is the specification includes the digital delay from the SYNC rising measure of difference in amplitude between the fundamental edge to the full-scale output change. and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling Digital-to-Analog Glitch Impulse rate or f/2). Narrow-band SFDR is a measure of SFDR over The amount of charge injected from the digital inputs to the S an arbitrary window size, in this case 50% of the fundamental. analog output when the inputs change state. This is normally Digital SFDR is a measure of the usable dynamic range of the specified as the area of the glitch in either picoamps per second DAC when the signal is a digitally generated sine wave. or nanovolts per second, depending upon whether the glitch is measured as a current or voltage signal. Rev. F | Page 14 of 28

Data Sheet AD5444/AD5446 GENERAL DESCRIPTION DAC SECTION CIRCUIT OPERATION Unipolar Mode The AD5444/AD5446 are 12-bit and 14-bit current output DACs consisting of segmented (4 bits), inverting R– 2R ladder Using a single op amp, the AD5444/AD5446 can easily be configurations. A simplified diagram for the 12-bit AD5444 configured to provide 2-quadrant multiplying operation or is shown in Figure 37. a unipolar output voltage swing, as shown in Figure 38. R R R When an output amplifier is connected in unipolar mode, the VREF output voltage is given by 2R 2R 2R 2R 2R S1 S2 S3 S12 R RFB VOUT 2Dn VREF IOUT1 IOUT2 where: DACA NDDA TDAR LIVAETRCSHES 04464-029 tDh eis D thAeC f:r actional representation of the digital word loaded to Figure 37. Simplified Ladder D = 0 to 4095 (12-bit AD5444) The feedback resistor (R ) has a value of R. The value of R is FB D = 0 to 16383 (14-bit AD5446) typically 9 kΩ (7 kΩ minimum, 11 kΩ maximum). If I 1 is OUT kept at the same potential as GND, a constant current flows in n is the number of bits. each ladder leg, regardless of digital input code. Therefore, the Note that the output voltage polarity is opposite to the V REF input resistance presented at VREF is always constant and nomi- polarity for dc reference voltages. nally of value R. The DAC output (I 1) is code-dependent, OUT This DAC is designed to operate with either negative or positive producing various resistances and capacitances. The external reference voltages. The V power pin is used by the internal amplifier choice should take into account the variation in DD digital logic only to drive the on and off states of the DAC impedance generated by the DAC on the amplifiers inverting switches. The DAC is also designed to accommodate ac refer- input node. ence input signals in the range of −10 V to +10 V. With a fixed Access is provided to the VREF, RFB, and both IOUT terminals of +10 V reference, the circuit shown in Figure 38 provides a the DAC, making the device extremely versatile and allowing it unipolar 0 V to −10 V output voltage swing. When V is an IN to be configured in several different operating modes. For ac signal, the circuit performs 2-quadrant multiplication. example, the device provides unipolar output mode, 4-quadrant Table 5 shows the relationship between digital code and multiplication in bipolar mode, and single-supply mode of expected output voltage for unipolar operation. operation. Note that a matching switch is used in series with the internal RFB. Power must be applied to VDD to achieve continuity Table 5. Unipolar Code when measuring RFB. Digital Input Analog Output (V) 1111 1111 1111 −VREF (4095/4096) 1000 0000 0000 −VREF (2048/4096) = −VREF/2 0000 0000 0001 −VREF (1/4096) 0000 0000 0000 −VREF (0/4096) = 0 VDD R2 C1 VDD RFB AD5444/ IOUT1 VREF VREF AD5446 A1 R1 IOUT2 VOUT = 0VTO –VREF SYNCSCLKSDIN AGND MICROCONTROLLER NOTES 12 .. RCIF11A AP1HN IADS SARE 2H CUIGOSHME DPS EPONENSELDAYT AIIFOM NGP LA(1IIFNpIFEARTDO.JU 2SpTFM) MENAYT BISE R REEQQUUIRIREEDD., 04588-030 Figure 38. Unipolar Operation Rev. F | Page 15 of 28

AD5444/AD5446 Data Sheet Bipolar Operation Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation. In some applications, it may be necessary to generate a full 4-quadrant multiplying operation, or a bipolar output swing. Table 6. Bipolar Code This can easily be accomplished by using another external Digital Input Analog Output (V) amplifier and some external resistors, as shown in Figure 39. 1111 1111 1111 +V (2047/2048) In this circuit, the second amplifier (A2) provides a gain of 2. REF 1000 0000 0000 0 Biasing the external amplifier with an offset from the reference 0000 0000 0001 −V (2047/2048) voltage results in a full 4-quadrant multiplying operation. The REF 0000 0000 0000 −V (0/2048) transfer function of this circuit shows that both negative and REF positive output voltages are created as the input data (D) is Stability incremented from code zero (V = −V ) to midscale OUT REF In the current-to-voltage (I-to-V) configuration, the I 1of the OUT (V − 0 V) to full scale (V = +V ) OUT OUT REF DAC and the inverting node of the op amp must be connected  D  as closely as possible, and proper PCB layout techniques must V =V × −V OUT  REF 2n−1 REF be employed. Because every code change corresponds to a step function, gain peaking can occur if the op amp has limited GBP where: and excessive parasitic capacitance exists at the inverting node. D is the fractional representation of the digital word loaded This parasitic capacitance introduces a pole into the open-loop to the DAC: response that can cause ringing or instability in the closed-loop D = 0 to 4095 (12-bit AD5444) applications circuit. D = 0 to 16383 (14-bit AD5446) An optional compensation capacitor (C1) can be added in n is the resolution of the DAC. parallel with RFB for stability, as shown in Figure 38 and Figure 39. Too small a value for C1 can produce ringing at When V is an ac signal, the circuit performs 4-quadrant IN the output, while too large a value can adversely affect the multiplication. settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation. R3 20kΩ VDD R2 R5 C1 20kΩ VDD RFB R1 AD5444/ IOUT1 10Rk4Ω VREF ±10V VREF AD5446 A1 IOUT2 A2 SYNCSCLKSDIN VOUT = –VREFTO +VREF AGND MICROCONTROLLER NOTES 1. R1AND R2 USED ONLY IF GAINADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADEDTO DAC. 2. MATCHINGAND TRACKING IS ESSENTIAL FOR RESISTORPAIRS 3 . RCIF31A AP1NH/ADA2 SR IES4 . CAO HMIGPHE NSSPAETEIDONA M(1PpLFIFTIOE R2.pF) MAY BE REQUIRED, 04588-031 Figure 39. Bipolar Operation (4-Quadrant Multiplication) Rev. F | Page 16 of 28

Data Sheet AD5444/AD5446 SINGLE-SUPPLY APPLICATIONS VDD Voltage Switching Mode of Operation C1 Figure 40 shows the AD5444/AD5446 DACs operating in the VDD RFB voltage switching mode. The reference voltage (V ) is applied R1 IOUT1 IN VIN VREF VOUT to the IOUT1 pin, IOUT2 is connected to AGND, and the output IOUT2 R3 voltage is available at the V terminal. In this configuration, GND REF R2 + R3 a positive reference voltage results in a positive output voltage, R2 GAIN = R2 making single-supply operation possible. The output from R2R3 NOTES R1 =R2 + R3 trhesei sDtaAnCce i)s. vTohlteargeefo arte a, acno nospt aanmt pim isp needcaenscsea r(yth teo DbuAfCfe rla tdhdee r 12 .. CAIF1DA DP1IH TIASIOS ANE AH CILGO PHMI NPSSEP NEOSEMDAITTATIOMENPD L (F1IFOpIFERR TCO.L A2pRFIT) YM.AY BE REQUIRED, 04588-034 output voltage. The reference input no longer sees a constant Figure 41. Increasing Gain of Current Output DAC input impedance but rather one that varies with code, so the DIVIDER OR PROGRAMMABLE GAIN ELEMENT voltage input should be driven from a low impedance source. Current-steering DACs are very flexible and lend themselves to VDD R1 R2 many different applications. If this type of DAC is connected as the feedback element of an op amp and R is used as the input FB RFB VDD resistor, as shown in Figure 42, then the output voltage is VIN IOUT1 VREF VOUT inversely proportional to the digital input fraction, D. For D = 1 − 2−n, the output voltage is GND V = −V /D = −V /(1 − 2−n) OUT IN IN NOTES 12 .. CAIF1DA DP1IH TIASIO SANE AH CILGO PHMI NPSSEP NEOSEMDAITTATIOMENPD L (F1IFOpIFERR TCO.L A2pRFIT) YM.AY BE REQUIRED, 04588-032 VIN VDD Figure 40. Single-Supply Voltage Switching Mode Operation RFB VDD It is important to note that, with this configuration, VIN is lim- IOUT1 VREF ited to low voltages, because the switches in the DAC ladder do GND not have the same source-drain drive voltage. As a result, their on resistance differs, which degrades the integral linearity of the DAC. In addition, V must not go negative by more than 0.3 V, IN VOUT or an internal diode turns on, exceeding the maximum ratings omf uthlteip dlyeivnigce c. aIpna tbhiliist yty opfe t ohfe aDpAplCic aist iloonst, .t he full range of the N1.O ATDEDSI:TIONAL PINS OMITTED FOR CLARITY. 04588-035 Figure 42. Current-Steering DAC Used as a Divider ADDING GAIN or Programmable Gain Element In applications in which the output voltage is required to be As D is reduced, the output voltage increases. For small values greater than V , gain can be added with an additional external IN of the digital fraction (D), it is important to ensure that the amplifier, or it can be achieved in a single stage. It is important amplifier does not saturate and the required accuracy is met. to take into consideration the effect of the temperature coeffi- For example, an 8-bit DAC driven with the binary code 0x10 cients of the thin film resistors of the DAC. Simply placing a (0001 0000), that is, 16 decimal, in the circuit of Figure 42, resistor in series with the R resistor can cause mismatches in FB should cause the output voltage to be 16 × V . However, if the IN the temperature coefficients and result in larger gain tempera- DAC has a linearity specification of ±0.5 LSB, then D can, in ture coefficient errors. Instead, increase the gain of the circuit fact, have a weight in the range of 15.5/256 to 16.5/256, so the by using the recommended configuration shown in Figure 41. possible output voltage is in the range 15.5 V to 16.5 V . This IN IN R1, R2, and R3 must all have similar temperature coefficients, is an error of 3%, even though the DAC itself has a maximum but they need not match the temperature coefficients of the error of 0.2%. DAC. This approach is recommended in circuits where gains of greater than 1 are required. Note that R >> R2||R3 and a gain FB error percentage of 100 × (R2||R3)/R must be taken into FB consideration. Rev. F | Page 17 of 28

AD5444/AD5446 Data Sheet DAC leakage current is also a potential error source in divider Provided that the DAC switches are driven from true wideband circuits. The leakage current must be counterbalanced by an low impedance sources (V and AGND), they settle quickly. IN opposite current supplied from the op amp through the DAC. Consequently, the slew rate and settling time of a voltage switching Because only a fraction (D) of the current into the V terminal DAC circuit is determined largely by the output op amp. To REF is routed to the I 1 terminal, the output voltage has to change, obtain minimum settling time in this configuration, it is impor- OUT as follows: tant to minimize capacitance at the V node (voltage output REF node in this application) of the DAC. This is done by using low Output Error Voltage due to DAC Leakage = (Leakage × R)/D input, capacitance buffer amplifiers and careful board design. where R is the DAC resistance at the V terminal. REF Most single-supply circuits include ground as part of the analog For a DAC leakage current of 10 nA, R equal to 10 kΩ, and a gain signal range, which, in turn, requires an amplifier that can handle (1/D) of 16, the error voltage is 1.6 mV. rail-to-rail signals. A large range of single-supply amplifiers is AMPLIFIER SELECTION available from Analog Devices, Inc. (see Table 8 and Table 9 for suitable suggestions). The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset REFERENCE SELECTION voltage. The input offset voltage of an op amp is multiplied by When selecting a reference for use with the AD5444/AD5446 the variable gain (due to the code-dependent output resistance current output DAC, pay attention to the output voltage tem- of the DAC) of the circuit. A change in this noise gain between perature coefficient specification. This parameter affects not two adjacent digital fractions produces a step change in the only the full-scale error but can also affect the linearity (INL output voltage due to the amplifier’s input offset voltage. This and DNL) performance. The reference temperature coefficient output voltage change is superimposed upon the desired change should be consistent with the system accuracy specifications. in output between the two codes and gives rise to a differential For example, an 8-bit system required to hold its overall speci- linearity error, which, if large enough, can cause the DAC to be fication to within 1 LSB over the temperature range 0°C to 50°C nonmonotonic. dictates that the maximum system drift with temperature The input bias current of an op amp also generates an offset should be less than 78 ppm/°C. at the voltage output as a result of the bias current flowing A 12-bit system with the same temperature range to overall in the feedback resistor, R . Most op amps have input bias FB specification within 2 LSBs requires a maximum drift of currents low enough to prevent any significant errors in 10 ppm/°C. By choosing a precision reference with low output 12-bit applications. temperature coefficient, this error source can be minimized. Common-mode rejection of the op amp is important in voltage Table 7 suggests some of the dc references available from switching circuits because it produces a code-dependent error Analog Devices that are suitable for use with this range of at the voltage output of the circuit. Most op amps have adequate current output DACs. common-mode rejection for use at 8-bit, 10-bit, and 12-bit resolutions. Rev. F | Page 18 of 28

Data Sheet AD5444/AD5446 Table 7. Suitable Analog Devices Precision References Initial Tolerance Temperature Drift Part No. Output Voltage (V) Accuracy (%) Coefficient (ppm/°C) I (mA) Output Noise (µV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable Analog Devices Precision Op Amps Part No. Supply Voltage (V) V (Max) (µV) I (Max) (nA) 0.1 Hz to 10 Hz Noise (µV p-p) Supply Current (µA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable Analog Devices High Speed Op Amps BW @ ACL Slew Rate Part No. Supply Voltage (V) (Typ) (MHz) (Typ) (V/µs) V (Max) (µV) I (Max) (nA) Package OS B AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23, MSOP AD8021 ±2.25 to ±12 490 120 1000 10500 SOIC-8, MSOP AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC-8 Rev. F | Page 19 of 28

AD5444/AD5446 Data Sheet SERIAL INTERFACE The AD5444/AD5446 have an easy-to-use, 3-wire interface that After the falling edge of the 16th SCLK pulse, bring SYNC high is compatible with SPI, QSPI, MICROWIRE, and DSP inter- to transfer data from the input shift register to the DAC register. face standards. Data is written to the device in 16-bit words. Daisy-Chain Mode This 16-bit word consists of two control bits, 12 data bits or Daisy-chain mode is the default power-on mode. To disable 14 data bits, as shown in Figure 43 and Figure 44. The AD5446 the daisy-chain function, write 01 to the control word. In daisy- uses all 14 bits of DAC data while AD5444 uses 12 bits and chain mode, the internal gating on the SCLK is disabled. The ignores the 2 LSBs. SCLK is continuously applied to the input shift register when Control Bit C1 and Control Bit C0 allow the user to load and SYNC is low. If more than 16 clock pulses are applied, the data update the new DAC code and to change the active clock edge. ripples out of the shift register and appears on the SDO line. By default, the shift register clocks data on the falling edge, but This data is clocked out on the rising edge of the SCLK (this this can be changed via the control bits. If changed, the DAC is the default; use the control word to change the active edge) core is inoperative until the next data frame. A power cycle and is valid for the next device on the falling edge (default). resets this back to the default condition. On-chip, power-on By connecting this line to the SDIN input on the next device in reset circuitry ensures the device powers on with zero scale the chain, a multidevice interface is constructed. Sixteen clock loaded to the DAC register and the I line. OUT pulses are required for each device in the system. Therefore, the Table 10. DAC Control Bits total number of clock cycles must equal 16 N, where N is the C1 C0 Function Implemented number of devices in the chain. 0 0 Load and update (power-on default) When the serial transfer to all devices is complete, SYNC 0 1 Disable SDO should be taken high. This prevents any further data from 1 0 No operation being clocked into the shift register. A burst clock containing 1 1 Clock data to shift register on rising edge the exact number of clock cycles can be used, and SYNC can be SYNC Function taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device’s input register to SYNC is an edge-triggered input that acts as a frame synchroni- the addressed DAC. zation signal. Data can be transferred into the device only while When the control bits = 10, the device is in no operation mode. SYNC is low. To start the serial data transfer, SYNC should be This can be useful in daisy-chain applications where the user taken low, observing the minimum SYNC falling to the SCLK does not want to change the settings of a particular DAC in the falling edge setup time, t. To minimize the power consumption 4 chain. Simply write 10 to the control bits for that DAC and the of the device, the interface powers up fully only when the device following data bits are ignored. is being written to, that is, on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC. DB15 (MSB) DB0 (LSB) C1 C0 DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X CONTROL BITS DATA BITS 04588-037 Figure 43. AD5444 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C1 C0 DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS DATA BITS 04588-038 Figure 44. AD5446 14-Bit Input Shift Register Contents Rev. F | Page 20 of 28

Data Sheet AD5444/AD5446 MICROPROCESSOR INTERFACING Table 11 shows the setup for the SPORT control register. Microprocessor interfacing to the AD5444/AD5446 DAC is Table 11. SPORT Control Register Setup through a serial bus that uses standard protocol compatible Name Setting Description with microcontrollers and DSP processors. The communica- TFSW 1 Alternate framing tions channel is a 3-wire interface consisting of a clock signal, a INVTFS 1 Active low frame signal data signal, and a synchronization signal. The AD5444/AD5446 DTYPE 00 Right-justify data requires a 16-bit word, with the default being data valid on the ISCLK 1 Internal serial clock falling edge of SCLK, but this can be changed using the control TFSR 1 Frame every word bits in the data-word. ITFS 1 Internal framing signal ADSP-2191M to AD5444/AD5446 Interface SLEN 1111 16-bit data-word The ADSP-2191M DSP is easily interfaced to the AD5444/AD5446 Blackfin to AD5444/AD5446 Interface DAC without the need for extra glue logic. Figure 45 is an example The ADSP-BF504 to ADSP-BF592 family of processors has an SPI- of an SPI interface between the DAC and the ADSP-2191M. compatible port that enables the processor to communicate with SCK of the DSP drives the serial clock line, SCLK. SYNC is SPI-compatible devices. Figure 47 shows a serial interface between driven from one of the port lines, in this case SPIxSEL. the ADSP-BF504 to ADSP-BF592 family (the ADSP-BF534 shown as an example) and the AD5444/AD5446 DAC. In this ADSP-2191M* AD5444/ AD5446* configuration, data is transferred through the MOSI (master SPIxSEL SYNC output/slave input) pin. SYNC is driven by the SPI chip select MOSI SDIN pin, which is a reconfigured programmable flag pin. SCK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY. 04588-074 ADSP-BSFP5I3S4E*Lx ASYDN5C444/AD5446* Figure 45. ADSP-2191M SPI to AD5444/AD5446 Interface MOSI SDIN A serial interface between the DAC and DSP SPORT is shown SCK SCLK ifner F digatuar eto 4 t6h. eI nD tAhCis sinhtieftr fraecgei setxera.m Tpralen,s SmPiOssRioTn0 i iss i unsiteidat teod tbrayn s- *ADDITIONAL PINS OMITTED FOR CLARITY. 04588-039 writing a word to the Tx register after the SPORT has been Figure 47. ADSP-BF534 to AD5444/AD5446 Interface enabled. In a write sequence, data is clocked out on each rising The ADSP-BF534 processor incorporates channel synchronous edge of the DSP serial clock and clocked into the DAC input serial ports (SPORT). A serial interface between the DAC and shift register on the falling edge of its SCLK. The update of the the DSP SPORT is shown in Figure 48. When the SPORT is DAC output takes place on the rising edge of the SYNC signal. enabled, initiate transmission by writing a word to the Tx register. The data is clocked out on each rising edge of the DSPs serial ADSP-2191M* AD5444/AD5446* clock and clocked into the DAC input shift register on the TFS SYNC falling edge of its SCLK. The DAC output is updated by using DT SDIN the transmit frame synchronization (TFS) line to provide a SCLK SCLK SYNC signal. *ADDITIONAL PINS OMITTED FOR CLARITY. 04588-082 ADSP-BF534* AD5444/AD5446* Figure 46. ADSP-2191M to AD5444/AD5446 Interface TFSx SYNC Communication between two devices at a given clock speed is DTx SDIN possible when the following specifications are compatible: frame SCLK SCLK ssyetnucp d-aenlady- ahnodld f,r aanmde S sCynLcK s wetiudpth-a. nTdh-eh DolAd,C d iantate drfealcaey eaxnpde dctast aa *ADDITIONAL PINS OMITTED FOR CLARITY. 04588-040 t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns Figure 48. ADSP-BF534 to AD5444/AD5446 Interface minimum. See the user manuals at www.analog.com/adsp-21xx- processor-manuals for information on clock and frame sync frequencies for the SPORT register. Rev. F | Page 21 of 28

AD5444/AD5446 Data Sheet 80C51/80L51 to AD5444/AD5446 Interface MC68HC11* AD5444/AD5446* A serial interface between the DAC and the 80C51/80L51 is PC7 SYNC shown in Figure 49. TxD of the 80C51/80L51 drives SCLK of SCK SCLK the DAC serial interface, while RxD drives the serial data line, MOSI SDIN SisD uIsNed. P to1 .d1 riisv ae bSYit-NpCro. gWrahmemn dabatlea pisi nto o bne t threa nsesrmiailt tpeodr tto a tnhde *ADDITIONAL PINS OMITTED FOR CLARITY 04588-042 switch, P1.1 is taken low. The 80C51/80L51 transmits data only Figure 50. MC68HC11 to AD5444/AD5446 Interface in 8-bit bytes; therefore, only eight falling clock edges occur in If the user wants to verify the data previously written to the the transmit cycle. To load data correctly to the DAC, P1.1 is input shift register, the SDO line can be connected to MISO of left low after the first eight bits are transmitted, and a second the MC68HC11, and, with SYNC low, the shift register clocks write cycle is initiated to transmit the second byte of data. data out on the rising edges of SCLK. Data on RxD is clocked out of the microcontroller on the rising MICROWIRE to AD5444/AD5446 Interface edge of TxD and is valid on the falling edge. As a result, no glue logic is required between the DAC and microcontroller inter- Figure 51 shows an interface between the DAC and any face. P1.1 is taken high following the completion of this cycle. MICROWIRE-compatible device. Serial data is shifted out The 80C51/80L51 provides the LSB of its SBUF register as the on the falling edge of the serial clock, SK, and is clocked into first bit in the data stream. The DAC input register requires its the DAC input shift register on the rising edge of SK, which data with the MSB as the first bit received. The transmit routine corresponds to the falling edge of the DAC SCLK. should take this into account. MICROWIRE* AD5444/AD5446* 8051* AD5444/AD5446* SK SCLK TxD SCLK SO SDIN RxD SDIN CS SYNC *ADDITIONAL PINSP 1O.1MITTED FOR CLARITY SYNC 04588-041 *ADDITIONALF PigINuSr eO 5M1IT. MTEIDC RFOORW CIRLEA tRoIT AYD5444/AD5446 Interface 04588-043 Figure 49. 80C51/80L51 to AD5444/AD5446 Interface PIC16C6x/7x to AD5444/AD5446 Interface MC68HC11 Interface to AD5444/AD5446 Interface The PIC16C6x/7x synchronous serial port (SSP) is configured Figure 50 is an example of a serial interface between the DAC as an SPI master with the clock polarity bit (CKP) = 0. This is and the MC68HC11 microcontroller. The serial peripheral done by writing to the synchronous serial port control register interface (SPI) on the MC68HC11 is configured for master (SSPCON); see the PIC16/17 Microcontroller User Manual. mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock In this example, I/O port RA1 is used to provide a SYNC phase bit (CPHA) = 1. The SPI is configured by writing to the signal and enable the serial port of the DAC. This micro- SPI control register (SPCR); see the 68HC11 User Manual. SCK controller transfers only eight bits of data during each serial of the 68HC11 drives the SCLK of the DAC interface, the MOSI transfer operation; therefore, two consecutive write operations output drives the serial data line (SDIN) of the AD5444/AD5446. are required. Figure 52 shows the connection diagram. The SYNC signal is derived from a port line (PC7). When data PIC16C6x/7x* AD5444/AD5446* is being transmitted to the AD5444/AD5446, the SYNC line is SCK/RC3 SCLK taken low (PC7). Data appearing on the MOSI output is valid SDI/RC4 SDIN on the falling edge of SCK. Serial data from the 68HC11 is RA1 SYNC transmitted in 8-bit bytes with only eight falling clock edges oTcoc luorardin dga itna ttoh et htrea DnsAmCi,t PcCyc7le i.s Dleaftta l oisw t raaftnesrm thitete fdir sMt eSiBg hfitr bsti.t s *ADDITIONAL PINS OMITTED FOR CLARITY 04588-044 Figure 52. PIC16C6x/7x to AD5444/AD5446 Interface are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. F | Page 22 of 28

Data Sheet AD5444/AD5446 PCB LAYOUT AND POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful considera- A microstrip technique, by far the best, is not always possible tion of the power supply and ground return layout helps to with a double-sided board. In this technique, the component ensure the rated performance. The printed circuit boards on side of the board is dedicated to the ground plane, while signal which the AD5444/AD5446 are mounted should be designed traces are placed on the solder side. so the analog and digital sections are separated and confined to It is good practice to employ compact, minimum lead-length certain areas of the board. If the DACs are in systems in which PCB layout design. Leads to the input should be as short as multiple devices require a AGND-to-DGND connection, the possible to minimize IR drops and stray inductance. connection should be made at one point only. The star ground The PCB metal traces between V and R should also be point should be established as close as possible to the devices. REF FB matched to minimize gain error. To maximize high frequency The DAC should have ample supply bypassing of 10 µF in performance, the I-to-V amplifier should be located as close parallel with 0.1 µF on the supply located as close to the pack- to the device as possible. age as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on oppo- site sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. Rev. F | Page 23 of 28

AD5444/AD5446 Data Sheet OVERVIEW OF CURRENT OUTPUT DEVICES Table 12. Part Number Resolution (Bits) Number of DACs INL (LSB) Interface Package1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial interface AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. F | Page 24 of 28

Data Sheet AD5444/AD5446 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 53. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution (Bits) INL (LSB) Temperature Range Package Description Package Option Branding AD5444YRM 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D27 AD5444YRMZ 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D6X AD5444YRMZ-REEL7 12 ±0.5 −40°C to +125°C 10-Lead MSOP RM-10 D6X AD5446YRM 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D28 AD5446YRMZ 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D7Z AD5446YRMZ-RL7 14 ±2 −40°C to +125°C 10-Lead MSOP RM-10 D7Z EV-AD5443/46/53SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. F | Page 25 of 28

AD5444/AD5446 Data Sheet NOTES Rev. F | Page 26 of 28

Data Sheet AD5444/AD5446 NOTES Rev. F | Page 27 of 28

AD5444/AD5446 Data Sheet NOTES ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04588-0-2/16(F) Rev. F | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5444YRMZ AD5444YRM AD5446YRM AD5446YRMZ AD5446YRMZ-RL7 AD5444YRMZ-REEL7