Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Serial Interface Data Sheet AD5429/AD5439/AD5449 FEATURES GENERAL DESCRIPTION 10 MHz multiplying bandwidth The AD5429/AD5439/AD54491 are CMOS, 8-, 10-, and 12-bit, INL of ±0.25 LSB at 8 bits dual-channel, current output digital-to-analog converters (DAC), 16-lead TSSOP package respectively. These devices operate from a 2.5 V to 5.5 V power 2.5 V to 5.5 V supply operation supply, making them suited to battery-powered and other ±10 V reference input applications. 50 MHz serial interface 2.47 MSPS update rate As a result of being manufactured on a CMOS submicron process, Extended temperature range: −40°C to +125°C these parts offer excellent 4-quadrant multiplication character- 4-quadrant multiplication istics, with large signal multiplying bandwidths of 10 MHz. Power-on reset The applied external reference input voltage (V ) determines 0.5 μA typical current consumption REF the full-scale output current. An integrated feedback resistor Guaranteed monotonic (RFB) provides temperature tracking and full-scale voltage Daisy-chain mode output when combined with an external current-to-voltage Readback function precision amplifier. APPLICATIONS These DACs use a double-buffered, 3-wire serial interface that Portable battery-powered applications is compatible with SPI, QSPI™, MICROWIRE™, and most DSP Waveform generators interface standards. In addition, a serial data out (SDO) pin allows Analog processing daisy-chaining when multiple packages are used. Data readback Instrumentation applications allows the user to read the contents of the DAC register via the Programmable amplifiers and attenuators SDO pin. On power-up, the internal shift register and latches Digitally controlled calibration Programmable filters and oscillators are filled with 0s, and the DAC outputs are at zero scale. Composite video The AD5429/AD5439/AD5449 DACs are available in 16-lead Ultrasound TSSOP packages. The EV-AD5415/49SDZ evaluation board is Gain, offset, and voltage trimming available for evaluating DAC performance. For more information, see the UG-297 evaluation board user guide. FUNCTIONAL BLOCK DIAGRAM VREFA AD5429/AD5439/AD5449 RFB VDD R RFBA SYNC SCLK RESGHISIFTTER REINGPISUTTER REGDIASCTER 8R--/21R0- /D1A2-CB IAT IOUT1A SDIN IOUT2A SDO CLR LDAC INPUT DAC 8-/10-/12-BIT IOUT1B POWER-ON REGISTER REGISTER R-2R DAC B RESET IOUT2B RFBB RFB LDAC VREFB R 04464-001 Figure 1. 1 U.S. Patent Number 5,689,257. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5429/AD5439/AD5449 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Digital-to-Analog Converter .................................................... 15  Applications ....................................................................................... 1  Circuit Operation ....................................................................... 15  General Description ......................................................................... 1  Single-Supply Applications ....................................................... 17  Functional Block Diagram .............................................................. 1  Adding Gain ................................................................................ 18  Revision History ............................................................................... 2  Divider or Programmable Gain Element ................................ 18  Specifications ..................................................................................... 3  Reference Selection .................................................................... 19  Timing Characteristics ................................................................ 5  Amplifier Selection .................................................................... 19  Timing Diagrams .......................................................................... 5  Serial Interface ............................................................................ 20  Absolute Maximum Ratings ............................................................ 7  Microprocessor Interfacing ....................................................... 22  ESD Caution .................................................................................. 7  PCB Layout and Power Supply Decoupling ........................... 24  Pin Configuration and Function Descriptions ............................. 8  Overview of Multiplying DAC Devices ....................................... 25  Typical Performance Characteristics ............................................. 9  Outline Dimensions ....................................................................... 26  Terminology .................................................................................... 14  Ordering Guide .......................................................................... 26  Theory of Operation ...................................................................... 15  REVISION HISTORY 1/16—Rev. E to Rev. F 7/05—Rev. 0 to Rev. A Changed AD54xx to AD5429/AD5439/AD5449 ........... Throughout Changes to Features List ................................................................... 1 Changed ADSP-21xx to ADSP-2191M and Family ........ Throughout Changes to Specifications ................................................................. 3 Changed ADSP-2101/ADSP-2103/ADSP-2191 to Changes to Timing Characteristics ................................................. 5 ADSP-2191M ................................................................. Throughout Changes to Absolute Maximum Ratings Section .......................... 7 Changed ADSP-BF5xx to ADSP-BF534 ........................... Throughout Changes to General Description Section .................................... 15 Deleted Positive Output Voltage Section and Figure 41; Changes to Table 5 .......................................................................... 15 Renumbered Sequentially .............................................................. 17 Changes to Table 6 .......................................................................... 16 Changes to Adding Gain Section ................................................. 18 Changes to Single-Supply Applications Section ......................... 17 Changed Overview of AD54xx Devices Section to Overview Changes to Divider or Programmable Gain Element Section .... 18 of Multiplying DAC Devices Section ........................................... 26 Changes to Table 7 Through Table 10 ......................................... 20 Added ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface 5/13—Rev. D to Rev. E Section .............................................................................................. 23 Changes to General Description .................................................... 1 Change to PCB Layout and Power Supply Decoupling Section ..... 25 Changes to Ordering Guide .......................................................... 26 Changes to Power Supplies for the Evaluation Board Section .... 25 Changes to Table 13 ....................................................................... 29 6/11—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 30 Changes to General Description .................................................... 1 Changes to Ordering Guide .......................................................... 30 Deleted Evaluation Board for the DAC Section ......................... 24 Changes to Ordering Guide .......................................................... 30 7/04—Revision 0: Initial Version 4/10—Rev. B to Rev. C Added to Figure 4 ............................................................................. 6 3/08—Rev. A to Rev. B Added t and t Parameters to Table 2 ......................................... 5 13 14 Changes to Figure 2 .......................................................................... 5 Changes to Figure 3 .......................................................................... 6 Changes to Figure 38 ...................................................................... 16 Changes to Ordering Guide .......................................................... 30 Rev. F | Page 2 of 28

Data Sheet AD5429/AD5439/AD5449 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 10 V, I 2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T to T , unless DD REF OUT MIN MAX otherwise noted. DC performance is measured with the OP177, and ac performance is measured with the AD8038, unless otherwise noted. Table 1. Parameter1 Min Typ Max Unit Conditions STATIC PERFORMANCE AD5429 Resolution 8 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5439 Resolution 10 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic AD5449 Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature ±5 ppm FSR/°C Coefficient Output Leakage Current ±5 nA Data = 0x0000, T = 25°C, I 1 A OUT ±15 nA Data = 0x0000, I 1 OUT REFERENCE INPUT Reference Input Range ±10 V V A, V B Input Resistance 9 11 13 kΩ Input resistance temperature coefficient = −50 ppm/°C REF REF V A-to-V B Input Resistance 1.6 2.5 % Typical = 25°C, maximum = 125°C REF REF Mismatch Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, V 1.7 V V = 3.6 V to 5.5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5.5 V, I = 200 µA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 µA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5.5 V, I = 200 µA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 µA DD SINK Input Leakage Current, I 1 µA IL Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference-Multiplying Bandwidth 10 MHz V = ±3.5 V p-p, DAC loaded all 1s REF Output Voltage Settling Time R = 100 Ω, C = 15 pF, V = 10 V, LOAD LOAD REF DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of FS 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, V = 0 V REF Rev. F | Page 3 of 28

AD5429/AD5439/AD5449 Data Sheet Parameter1 Min Typ Max Unit Conditions Multiplying Feedthrough Error DAC latches loaded with all 0s, V = ±3.5 V REF 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Digital Feedthrough 3 5 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz @ 1 kHz Analog THD 81 dB V = 3. 5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 10 MHz, V = 3.5 V REF 100 kHz f 61 dB OUT 50 kHz f 66 dB OUT SFDR Performance (Wide Band) AD5449, 65k codes, V = 3.5 V REF Clock = 10 MHz 500 kHz f 55 dB OUT 100 kHz f 63 dB OUT 50 kHz f 65 dB OUT Clock = 25 MHz 500 kHz f 50 dB OUT 100 kHz f 60 dB OUT 50 kHz f 62 dB OUT SFDR Performance (Narrow Band) AD5449, 65k codes, V = 3.5 V REF Clock = 10 MHz 500 kHz f 73 dB OUT 100 kHz f 80 dB OUT 50 kHz f 87 dB OUT Clock = 25 MHz 500 kHz f 70 dB OUT 100 kHz f 75 dB OUT 50 kHz f 80 dB OUT Intermodulation Distortion AD5449, 65k codes, V = 3.5 V REF f = 40 kHz, f = 50 kHz 72 dB Clock = 10 MHz 1 2 f = 40 kHz, f = 50 kHz 65 dB Clock = 25 MHz 1 2 POWER REQUIREMENTS Power Supply Range 2.5 5.5 V I 0.7 µA T = 25°C, logic inputs = 0 V or V DD A DD 0.5 10 µA T = −40°C to +125°C, logic inputs = 0 V or V A DD Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design and characterization, not subject to production test. Rev. F | Page 4 of 28

Data Sheet AD5429/AD5439/AD5449 TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. V = 2.5 V to 5.5 V, R F DD IL IH DD V = 10 V, I 2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T to T , unless otherwise noted. REF OUT MIN MAX Table 2. Parameter1 Limit at T , T Unit Conditions/Comments2 MIN MAX f 50 MHz max Maximum clock frequency SCLK t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 13 ns min SYNC falling edge to SCLK falling edge setup time 4 t 5 ns min Data setup time 5 t 4 ns min Data hold time 6 t 5 ns min SYNC rising edge to SCLK falling edge 7 t 30 ns min Minimum SYNC high time 8 t 0 ns min SCLK falling edge to LDAC falling edge 9 t 12 ns min LDAC pulse width 10 t 10 ns min SCLK falling edge to LDAC rising edge 11 t 3 25 ns min SCLK active edge to SDO valid, strong SDO driver 12 60 ns min SCLK active edge to SDO valid, weak SDO driver t 12 ns min CLR pulse width 13 t 4.5 ns min SYNC rising edge to LDAC falling edge 14 Update Rate 2.47 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. 3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5. TIMING DIAGRAMS t 1 SCLK t8 t4 t2 t3 t7 SYNC t 6 t 5 SDIN DB15 DB0 t 10 t 9 LDAC1 t 11 LDAC2 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. N1 . O ADTLEETTSEERRNMAINTEIVDE BLYY ,T DHAET CAO CNATNR BOEL CBLITOSC. KTEIMDI NINGT OIS TAHSE A IBNOPUVTE ,S WHIITFHT RSECGLKIS ITNEVRE ROTNE TDH.E RISING EDGE OF SCLK AS 04464-002 Figure 2. Standalone Mode Timing Diagram Rev. F | Page 5 of 28

AD5429/AD5439/AD5449 Data Sheet t 1 SCLK t t2 t3 t7 4 SYNC t6 t8 t 5 DB15 DB0 DB15 DB0 SDIN (N) (N) (N + 1) (N + 1) t 12 DB15 DB0 SDO (N) (N) N1 . O ADETDLEETTGSEEERR ONMFAIN TSEICVDLE KBL.YY T ,T IDMHAEINT CAGO CISNA TANRS BO AELB CBOLITVOSEC., KIWNEI DTT HHIN ISSTC OCLA TKSH IENE, V IDNEAPRTUTATE DWS.HOIUFLTD R BEEG ICSLTOERC KOEND T OHUET R OISFI NSGD OE DOGNE T OHFE SFCALLKLI NAGS 04464-003 Figure 3. Daisy-Chain Timing Diagram SCLK 16 32 SYNC SDIN DB15 DB0 DB15 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB15 DB0 UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 04464-059 Figure 4. Readback Mode Timing Diagram 200A IOL TO OUTPUT VOH (MIN) + VOL (MAX) PIN CL 2 50pF 200A IOH 04464-004 Figure 5. Load Circuit for SDO Timing Specifications Rev. F | Page 6 of 28

Data Sheet AD5429/AD5439/AD5449 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses at or above those listed under Absolute Maximum T = 25°C, unless otherwise noted. A Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 3. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V DD the maximum operating conditions for extended periods may V x, R x to GND −12 V to +12 V REF FB affect product reliability. I 1, I 2 to GND −0.3 V to +7 V OUT OUT Input Current to Any Pin Except Supplies ±10 mA Logic Inputs and Output1 −0.3 V to V + 0.3 V DD ESD CAUTION Operating Temperature Range Extended (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 16-Lead TSSOP, θ Thermal Impedance 150°C/W JA Lead Temperature, Soldering (10 sec) 300°C IR Reflow, Peak Temperature (<20 sec) 235°C 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. Rev. F | Page 7 of 28

AD5429/AD5439/AD5449 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IOUT1A 1 16 IOUT1B IOUT2A 2 15 IOUT2B RFBA 3 AD5429/ 14 RFBB VREFA 4 AD5439/ 13 VREFB GND 5 AD5449 12 VDD TOP VIEW LDAC 6 (Not to Scale) 11 CLR SCLK 7 10 SYNC SDIN 8 9 SDO 04464-005 Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 IOUT1A DAC A Current Output. 2 IOUT2A DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but it can be biased to achieve single-supply operation. 3 RFBA DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier output. 4 VREFA DAC A Reference Voltage Input Pin. 5 GND Ground Pin. 6 LDAC Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode. 7 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. 8 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, data is clocked at power-on into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to a rising edge. 9 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, and they are clocked out on the next 16 opposite clock edges to the active clock edge. 10 SYNC Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded into the shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge. 11 CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user to enable the hardware CLR pin as a clear-to-zero scale or midscale, as required. 12 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V. 13 VREFB DAC B Reference Voltage Input Pin. 14 RFBB DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier output. 15 IOUT2B DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but it can be biased to achieve single-supply operation. 16 IOUT1B DAC B Current Output. Rev. F | Page 8 of 28

Data Sheet AD5429/AD5439/AD5449 TYPICAL PERFORMANCE CHARACTERISTICS 0.20 0.20 TA = 25°C TA = 25°C 0.15 VREF = 10V 0.15 VREF = 10V VDD = 5V VDD = 5V 0.10 0.10 0.05 0.05 B) B) S S L L L ( 0 L ( 0 N N I D –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 –0.20 –0.20 0 50 100 CODE 150 200 250 04464-017 0 50 100 CODE 150 200 250 04464-020 Figure 7. INL vs. Code (8-Bit DAC) Figure 10. DNL vs. Code (8-Bit DAC) 0.5 0.5 0.4 TVAR E=F 2=5 °1C0V 0.4 TVAR E=F 2=5 °1C0V 0.3 VDD = 5V 0.3 VDD = 5V 0.2 0.2 INL (LSB) –00..011 DNL (LSB) –00..101 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.5 –0.5 0 200 400 CODE 600 800 1000 04464-018 0 200 400 CODE 600 800 1000 04464-021 Figure 8. INL vs. Code (10-Bit DAC) Figure 11. DNL vs. Code (10-Bit DAC) 1.0 1.0 0.8 TVAR E=F 2=5 °1C0V 0.8 TVAR E=F 2=5 °1C0V 0.6 VDD = 5V 0.6 VDD = 5V 0.4 0.4 INL (LSB) –00..202 DNL (LSB) –00..202 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0 –1.0 0 500 1000 1500 C2O0D00E 2500 3000 3500 4000 04464-019 0 500 1000 1500 C2O0D00E 2500 3000 3500 4000 04464-022 Figure 9. INL vs. Code (12-Bit DAC) Figure 12. DNL vs. Code (12-Bit DAC) Rev. F | Page 9 of 28

AD5429/AD5439/AD5449 Data Sheet 0.6 8 TA = 25°C 0.5 7 A) 0.4 MAX INL T (m 6 N 0.3 E RR 5 VDD = 5V NL (LSB) 00..12 TVAD D= =2 55°VC PPLY CU 4 I SU 3 0 MIN INL 2 –0.1 VDD = 3V 1 –0.2 VDD = 2.5V –0.32 3 4 REF5ERENC6E VOLTA7GE 8 9 10 04464-035 00 0.5 1.0 1.5INP2U.0T VO2L.5TAG3E. 0(V) 3.5 4.0 4.5 5.0 04464-038 Figure 13. INL vs. Reference Voltage Figure 16. Supply Current vs. Logic Input Voltage –0.40 1.6 TA = 25°C VDD = 5V 1.4 –0.45 1.2 –0.50 IOUT1 VDD = 5V 1.0 DNL (LSB) –0.55 KAGE (nA) 0.8 IOUT1 VDD = 3V A 0.6 –0.60 LE MIN DNL 1 UT 0.4 O I –0.65 0.2 –0.70 0 2 3 4 REF5ERENC6E VOLTA7GE 8 9 10 04464-036 –40 –20 0 TE20MPERA4T0URE (6°C0) 80 100 120 04464-039 Figure 14. DNL vs. Reference Voltage Figure 17. IOUT1 Leakage Current vs. Temperature 5 0.50 4 0.45 VDD = 5V VDD = 5V 3 0.40 2 A) 0.35 R (mV) 1 ENT (µ 0.30 ALL 0s AIN ERRO –10 VDD = 2.5V PLY CURR 00..2205 VDD = 2.5V ALL 1s G P –2 SU 0.15 ALL 1s ALL 0s –3 0.10 –4 0.05 VREF = 10V –5 0 –60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 04464-037 –60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 04464-040 Figure 15. Gain Error vs. Temperature Figure 18. Supply Current vs. Temperature Rev. F | Page 10 of 28

Data Sheet AD5429/AD5439/AD5449 14 3 TLAO A= D2I5N°GC ZS TO FS TVAD D= =2 55°VC 12 VDD = 5V 0 10 I (mA)DD 68 VDD = 3V GAIN(dB) –3 4 –6 VREF =±2V,AD8038 CC 1.47pF VDD = 2.5V VREF =±2V,AD8038 CC 1pF VREF =±0.15V,AD8038 CC 1pF 2 VREF =±0.15V,AD8038 CC 1.47pF VREF =±3.51V,AD8038 CC 1.8pF 01 10 100 F1kREQU1E0NkCY (H10z0)k 1M 10M 100M 04464-041 –910k 100k FREQUE1MNCY (Hz) 10M 100M 04464-044 Figure 19. Supply Current vs. Update Rate Figure 22. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor –1–2660 TLZAOS A=T DO2I5 NF°GSC ADDBLBL11 10ON 00..004450 0x7FF TO 0x8V0D0D = 5V TVAARM E=PF 2==5 A°0CVD8038 –18 DB9 0.035 CCOMP = 1.8pF DB8 –24 0.030 GAIN(dB) ––––––543643420086 DDDDDDBBBBBB765432 UT VOLTAGE (V) 000...000212550 VDD = 3V 0x800 TO 0x7FF DB1 P 0.010 –66 T –72 DB0 OU 0.005 VDD = 3V –78 TA = 25°C –84 VDD = 5V 0 –90 VREF = ±3.5V –96 ALL OFF CCOMP = 1.8pF –0.005 –1021 10 100 1FkREQU1E0NkCY (H10z0)k 1MAMP =10AMD8031080M 04464-042 –0.0100 20 40 60 V8D0D T=I M51VE0 0(ns)120 140 160 180 200 04464-045 Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code Figure 23. Midscale Transition, VREF = 0 V 0.2 –1.68 0x7FF TO 0x800 TA = 25°C –1.69 VREF = 3.5V 0 –1.70 VDD = 5V ACCMOPM =P A= D18.80p3F8 V) E ( –1.71 –0.2 G GAIN (dB) –0.4 UT VOLTA ––11..7732 VDD = 3V UTP –1.74 VDD = 5V TA = 25°C O –1.75 VDD = 3V –0.6 VDD = 5V CVARCMEOPFM ==P A=3 D1.85.80Vp3F8 –1.76 0x800 TO 0x7FF –0.8 –1.77 1 10 100 F1kREQU1E0NkCY (H10z0)k 1M 10M 100M 04464-043 0 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 04464-046 Figure 21. Reference Multiplying Bandwidth—All 1s Loaded Figure 24. Midscale Transition, VREF = 3.5 V Rev. F | Page 11 of 28

AD5429/AD5439/AD5449 Data Sheet 20 TA = 25°C 90 0 VADMDP = = 3 AVD8038 80 MCLK = 5MHz 70 MCLK = 10MHz –20 60 R (dB) –40 FULL SCALE R (dB) 50 R D MCLK = 25MHz PS –60 ZERO SCALE SF 40 30 –80 20 –100 10 VTAR E=F 2=5 °3C.5V –1201 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M04464-047 00 100 200 300 400fOU5T 0(0kHz)600 700 A8M0P0 = A9D0080318000 04464-050 Figure 25. Power Supply Rejection Ratio vs. Frequency Figure 28. Wideband SFDR vs. fOUT Frequency –60 0 –65 TVVADR DE=F = 2= 53 °3VC.5V p-p –10 A6VT5ADMk D=P C = 2=O 55 AD°VCDE8S038 –20 –70 –30 D + N (dB) –75 FDR (dB)––5400 H S T –80 –60 –70 –85 –80 –901 10 100FREQUE1NkCY (Hz)10k 100k 1M 04464-048 –900 2 4FREQUEN6CY (MHz)8 10 12 04464-051 Figure 26. THD + Noise vs. Frequency Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz 100 0 TA� = 25°C MCLK = 1MHz –10 VDD = 5V AMP = AD8038 80 –20 65k CODES –30 B) 60 MCLK = 200kHz B)–40 R (d MCLK = 0.5MHz R (d–50 D D SF 40 SF–60 –70 20 –80 TVAR E=F 2=5 °3C.5V –90 00 20 40 60 80fOU1T 0(0kHz)120 140 A1M6P0 = A1D808038200 04464-049 –1000 0.5 1.0 1.5 FR2E.0QUE2N.5CY (M3.H0z) 3.5 4.0 4.5 5.0 04464-052 Figure 27. Wideband SFDR vs. fOUT Frequency Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz Rev. F | Page 12 of 28

Data Sheet AD5429/AD5439/AD5449 0 0 TA = 25°C TA� = 25°C –10 VADMDP = = 5 AVD8038 –10 VADMDP = = 3 AVD8038 65k CODES –20 65k CODES –20 –30 –30 FDR (dB)––5400 IMD (dB)––5400 S –60 –60 –70 –70 –80 –80 –90 –900 0.5 1.0 1.5 FR2E.0QUE2N.5CY (M3.H0z) 3.5 4.0 4.5 5.0 04464-053 –10070 75 80 85 FR9E0QUE9N5CY (1k0H0z) 105 110 115 120 04464-056 Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz 0 0 TA� = 25°C TA� = 25°C –10 VDD = 3V –10 VDD = 5V AMP = AD8038 AMP = AD8038 –20 65k CODES –20 65k CODES –30 –30 –40 B)–40 d dB)–50 MD (–50 R ( I D–60 –60 F S –70 –70 –80 –80 –90 –90 –100250 300 350 400 FR45E0QUE5N00CY (5k5H0z) 600 650 700 750 04464-054 –1000 50 100 1F5R0EQUE2N00CY (kH25z0) 300 350 400 04464-057 Figure 32. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz 20 300 TA� = 25°C TA = 25°C VDD = 3V ZERO SCALE LOADED TO DAC AMP = AD8038 0 A65MkP C =O ADDE8S038 250 MIDSCALE LOADED TO DAC FULL SCALE LOADED TO DAC –20 Hz) V/ 200 dB)–40 E (n SFDR (–60 T NOIS 150 U P T 100 –80 OU –100 50 –12050 60 70 80 FR9E0QUE1N00CY (1k1H0z) 120 130 140 150 04464-055 0100 1kFREQUENCY (Hz)10k 100k04464-058 Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 36. Output Noise Spectral Density Rev. F | Page 13 of 28

AD5429/AD5439/AD5449 Data Sheet TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Crosstalk A measure of the maximum deviation from a straight line The glitch impulse transferred to the outputs of one DAC in passing through the endpoints of the DAC transfer function. response to a full-scale code change (all 0s to all 1s, or vice versa) It is measured after adjusting for zero and full scale and is typically in the input register of the other DAC. It is expressed in nV-sec. expressed in LSBs or as a percentage of the full-scale reading. Analog Crosstalk Differential Nonlinearity The glitch impulse transferred to the output of one DAC due to The difference in the measured change and the ideal 1 LSB a change in the output of another DAC. It is measured by change between two adjacent codes. A specified differential loading one of the input registers with a full-scale code change nonlinearity of −1 LSB maximum over the operating temperature (all 0s to all 1s, or vice versa) while keeping LDAC high and range ensures monotonicity. then pulsing LDAC low and monitoring the output of the DAC Gain Error (Full-Scale Error) whose digital code has not changed. The area of the glitch is A measure of the output error between an ideal DAC and the expressed in nV-sec. actual device output. For these DACs, ideal maximum output is Channel-to-Channel Isolation VREF − 1 LSB. The gain error of the DACs is adjustable to zero The portion of input signal from the reference input of a DAC with an external resistance. that appears at the output of another DAC. It is expressed in dB. Output Leakage Current Total Harmonic Distortion (THD) The current that flows into the DAC ladder switches when they The DAC is driven by an ac reference. The ratio of the rms sum are turned off. For the IOUT1x terminal, it can be measured by of the harmonics of the DAC output to the fundamental value is loading all 0s to the DAC and measuring the IOUT1 current. the THD. Usually only the lower-order harmonics are included, Minimum current flows into the IOUT2x line when the DAC is such as the second to fifth harmonics. loaded with all 1s. V 2 +V 2 +V 2 +V 2 Output Capacitance THD=20log 2 3 4 5 V Capacitance from IOUT1 or IOUT2 to AGND. 1 Output Current Settling Time Intermodulation Distortion (IMD) The amount of time for the output to settle to a specified level The DAC is driven by two combined sine wave references of for a full-scale input change. For these devices, it is specified Frequency fa and Frequency fb. Distortion products are produced with a 100 Ω resistor to ground. at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 … Intermodulation terms are those for which m or n is not Digital-to-Analog Glitch Impulse equal to 0. The second-order terms include (fa + fb) and (fa − fb), The amount of charge injected from the digital inputs to the and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb), analog output when the inputs change state. This is normally and (fa − 2fb). IMD is defined as specified as the area of the glitch in either pA-sec or nV-sec, depending on whether the glitch is measured as a current or RMSSumof theSumandDiff DistortionProducts IMD=20log voltage signal. RMSAmplitudeof theFundamental Digital Feedthrough Compliance Voltage Range When the device is not selected, high frequency logic activity on the digital inputs of the device is capacitively coupled through The maximum range of (output) terminal voltage for which the the device and produces noise on the I pins and, subsequently, device provides the specified characteristics. OUT on the circuitry that follows. This noise is digital feedthrough. Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC reference input to the DAC I 1x terminal when all 0s are OUT loaded to the DAC. Rev. F | Page 14 of 28

Data Sheet AD5429/AD5439/AD5449 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER When an output amplifier is connected in unipolar mode, the output voltage is given by The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit, dual- channel, current output DACs consisting of a standard inverting V V D/2n OUT REF R-2R ladder configuration. Figure 37 shows a simplified diagram where: for a single channel of the AD5449. The feedback resistor, R A, FB D is the fractional representation of the digital word loaded to has a value of R. The value of R is typically 10 kΩ (with a the DAC. minimum of 8 kΩ and a maximum of 12 kΩ). If I 1A and OUT D = 0 to 255 (AD5429) I 2A are kept at the same potential, a constant current flows OUT = 0 to 1023 (AD5439) into each ladder leg, regardless of digital input code. Therefore, = 0 to 4095 (AD5449) the input resistance presented at V A is always constant. REF n is the number of bits. R R R VREFA With a fixed 10 V reference, the circuit shown in Figure 38 gives 2R 2R 2R 2R 2R a unipolar 0 V to −10 V output voltage swing. When V is an ac IN S1 S2 S3 S12 R signal, the circuit performs 2-quadrant multiplication. RFBA IOUT1A Table 5 shows the relationship between digital code and the IOUT2A expected output voltage for unipolar operation using the 8-bit DACA NDDA TDAR ILVAETRCSHES 04464-006 AD5429 DAC. Figure 37. Simplified Ladder Table 5. Unipolar Code Table Digital Input Analog Output (V) Access is provided to the V x, R x, I 1x, and I 2x termi- REF FB OUT OUT 1111 1111 −V (255/256) nals of the DACs, making the devices extremely versatile and REF 1000 0000 −V (128/256) = −V /2 allowing them to be configured in several operating modes, such REF REF 0000 0001 −V (1/256) as unipolar mode, bipolar output mode, or single-supply mode. REF 0000 0000 −V (0/256) = 0 REF CIRCUIT OPERATION Unipolar Mode Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 38. VDD R2 C1 VDD RFBA AD5429/ IOUT1A VREF VREFx AD5439/ A1 R1 AD5449 IOUT2A VOUT = 0V TO –VREF SYNCSCLKSDIN GND MICROCONTROLLER AGND NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 23.. CDIF1A A CP1 HB IAS OS AME HICTITOGEMHD PS FEPONESREA DCT LAIOAMRNPI LT(1IYpF.FIE TRO. 2pF) MAY BE REQUIRED 04464-007 Figure 38. Unipolar Operation Rev. F | Page 15 of 28

AD5429/AD5439/AD5449 Data Sheet Bipolar Operation Stability In some applications, it may be necessary to generate full In the I-to-V configuration, the I of the DAC and the inverting OUT 4-quadrant multiplying operation or a bipolar output swing. node of the op amp must be connected as closely as possible, and This can easily be accomplished by using another external proper PCB layout techniques must be used. Because every code amplifier and three external resistors, as shown in Figure 39. change corresponds to a step function, gain peaking may occur if the op amp has limited gain bandwidth product (GBP) and When V is an ac signal, the circuit performs 4-quadrant IN there is excessive parasitic capacitance at the inverting node. multiplication. When connected in bipolar mode, the output This parasitic capacitance introduces a pole into the open-loop voltage is response, which can cause ringing or instability in the closed- V  V D/2n1V loop applications circuit. OUT REF REF where: As shown in Figure 38 and Figure 39, an optional compensation D is the fractional representation of the digital word loaded to capacitor, C1, can be added in parallel with RFBx for stability. the DAC. Too small a value of C1 can produce ringing at the output, D = 0 to 255 (AD5429) whereas too large a value can adversely affect the settling time. = 0 to 1023 (AD5439) C1 should be found empirically, but 1 pF to 2 pF is generally = 0 to 4095 (AD5449) adequate for the compensation. n is the number of bits. Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation with the AD5429. Table 6. Bipolar Code Digital Input Analog Output (V) 1111 1111 +V (255/256) REF 1000 0000 0 0000 0001 −V (255/256) REF 0000 0000 −V (256/256) REF R3 20kΩ VDD R2 R5 C1 20kΩ VDD RFBA R4 R1 AD5429/ IOUT1A 10kΩ VREF ±10V VREFx AD5439/ A1 R1 AD5449 IOUT2A A2 SYNCSCLKSDIN GND VOUT = –VREFTO +VREF MICROCONTROLLER AGND NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 34.. CDIF1A A CP1 HB/AA A2S NEISD C AAO DHMDIPGITEHIN OSSNPAAETLEIO DPN IAN (MS1pP OFLM ITFIOITET R2Ep.DF )F MOARY C BLEA RRIETQY.UIRED 04464-008 Figure 39. Bipolar Operation Rev. F | Page 16 of 28

Data Sheet AD5429/AD5439/AD5449 SINGLE-SUPPLY APPLICATIONS Note that V is limited to low voltages because the switches IN Voltage-Switching Mode in the DAC ladder no longer have the same source-drain drive voltage. As a result, their on resistance differs and degrades the Figure 40 shows the DACs operating in voltage-switching mode. integral linearity of the DAC. Also, V must not go negative by IN The reference voltage, V , is applied to the I 1A pin; I 2A IN OUT OUT more than 0.3 V, or an internal diode turns on, causing the device is connected to AGND; and the output voltage is available at the to exceed the maximum ratings. In this type of application, the V A terminal. In this configuration, a positive reference voltage REF full range of multiplying capability of the DAC is lost. results in a positive output voltage, making single-supply operation possible. The output from the DAC is voltage at a constant VDD R1 R2 impedance (the DAC ladder resistance). Therefore, an op amp is necessary to buffer the output voltage. The reference input RFBA VDD nthoa tlo vnagreiers s weeisth a ccoodnes.t aTnhte irnepfourte i,m thpee dvoalntcaeg;e i innspteuatd s,h iot uselde sb oen e VIN IIOOUUTT21AA 8-/10D-/A12C-BITVREFA VOUT driven from a low impedance source. GND NOTES 21.. AICFD1A DP1IH TIASIO SANE AH CLIGO PHMI NPSSEP NEOESMDAITTATIOMENPD L (F1IFOpIFERR TCO.L A2pRFIT)Y M.AY BE REQUIRED 04464-009 Figure 40. Single-Supply Voltage-Switching Mode Rev. F | Page 17 of 28

AD5429/AD5439/AD5449 Data Sheet ADDING GAIN As D is reduced, the output voltage increases. For small values of the Digital Fraction D, it is important to ensure that the amplifier In applications in which the output voltage must be greater than does not saturate and the required accuracy is met. For example, V , gain can be added with an additional external amplifier, or IN an 8-bit DAC driven with binary code of 0x10 (0001 0000)—that it can be achieved in a single stage. Consider the effect of temper- is, 16 decimal—in the circuit of Figure 42 should cause the output ature coefficients of the thin film resistors of the DAC. Simply voltage to be 16 × V . However, if the DAC has a linearity speci- placing a resistor in series with the RFB resistor causes mismatches IN fication of ±0.5 LSB, D can have a weight in the range of 15.5/256 in the temperature coefficients, resulting in larger gain temper- to 16.5/256, so that the possible output voltage is in the range of ature coefficient errors. Instead, the circuit in Figure 41 shows 15.5 V to 16.5 V . This range represents an error of 3%, even the recommended method of increasing the gain of the circuit. IN IN though the DAC itself has a maximum error of 0.2%. R1, R2, and R3 should have similar temperature coefficients, but they need not match the temperature coefficients of the DAC leakage current is also a potential error source in divider DAC. This approach is recommended in circuits in which circuits. The leakage current must be counterbalanced by an gains of greater than 1 are required. Note that R >> R2||R3 opposite current supplied from the op amp through the DAC. FB and a gain error percentage of 100 × (R2||R3)/RFB must be taken Because only a fraction, D, of the current into the VREFx terminal into consideration. is routed to the IOUT1 terminal, the output voltage changes as follows: DIVIDER OR PROGRAMMABLE GAIN ELEMENT Output Error Voltage Due to DAC Leakage = (Leakage × R)/D Current-steering DACs are very flexible and lend themselves to many applications. If this type of DAC is connected as the where R is the DAC resistance at the VREFx terminal. feedback element of an op amp and RFBA is used as the input For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that resistor, as shown in Figure 42, the output voltage is inversely is, 1/D) of 16, the error voltage is 1.6 mV. proportional to the digital input fraction, D. For D = 1 − 2−n, the output voltage is V =−V /D=−V /(1−2−n) OUT IN IN VDD VDD RFBA C1 R1 IOUT1A VIN VREFA 8-/10D-A/1C2-BIT IOUT2A R3 VOUT GND R2 + R3 R2 GAIN = R2 R2R3 R1 = NOTES R2 + R3 12.. ACIFD1 A DP1IHT IASIOS ANE AH CLIGO PHMIN PSSEP NOESEMADITT ATIOMENDP L(F1IOFpIRFE RTCO.L A2RpFIT)Y M.AY BE REQUIRED 04464-011 Figure 41. Increasing Gain of Current Output DAC VDD VIN RFBA VDD IOUT1A 8-/10-/12-BITVREFA IOUT2A DAC GND VOUT N1.OATDEDSITIONAL PINS OMITTED FOR CLARITY. 04464-012 Figure 42. Current-Steering DAC Used as a Divider or Programmable Gain Element Rev. F | Page 18 of 28

Data Sheet AD5429/AD5439/AD5449 REFERENCE SELECTION the amplifier input offset voltage. This output voltage change is superimposed on the desired change in output between the two When selecting a reference for use with the AD5429/AD5439/ codes and gives rise to a differential linearity error, which, if AD5449 series of current output DACs, pay attention to the large enough, could cause the DAC to be nonmonotonic. The reference output voltage temperature coefficient specification. This input bias current of an op amp also generates an offset at the parameter affects not only the full-scale error, but it can also affect voltage output as a result of the bias current flowing in the feedback the linearity (INL and DNL) performance. The reference tempera- resistor, RFB. Most op amps have input bias currents low enough ture coefficient should be consistent with the system accuracy to prevent significant errors in 12-bit applications. specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range of Common-mode rejection of the op amp is important in voltage- 0°C to 50°C dictates that the maximum system drift with tempera- switching circuits because it produces a code-dependent error ture should be less than 78 ppm/°C. A 12-bit system with the same at the voltage output of the circuit. Most op amps have adequate temperature range to overall specification within 2 LSBs requires a common-mode rejection for use at 8-, 10-, and 12-bit resolution. maximum drift of 10 ppm/°C. By choosing a precision reference If the DAC switches are driven from true wideband low impedance with a low output temperature coefficient, this error source can be sources (V and AGND), they settle quickly. Consequently, the IN minimized. Table 7 lists some references available from Analog slew rate and settling time of a voltage-switching DAC circuit Devices, Inc., that are suitable for use with this range of current is determined largely by the output op amp. To obtain minimum output DACs. settling time in this configuration, minimize capacitance at the V REF AMPLIFIER SELECTION node (the voltage output node in this application) of the DAC by using low input capacitance buffer amplifiers and careful board The primary requirement for the current-steering mode is an design. amplifier with low input bias currents and low input offset voltage. Because of the code-dependent output resistance of the DAC, the Most single-supply circuits include ground as part of the analog input offset voltage of an op amp is multiplied by the variable gain signal range, which, in turn, requires an amplifier that can handle of the circuit. A change in this noise gain between two adjacent rail-to-rail signals. Analog Devices offers a wide range of single- digital fractions produces a step change in the output voltage due to supply amplifiers (see Table 8 and Table 9). Table 7. Suitable Analog Devices Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (µV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC ADR01 10 0.05 9 1 20 TSOT, SC70 ADR02 5 0.06 3 1 10 SOIC ADR02 5 0.06 9 1 10 TSOT, SC70 ADR03 2.5 0.10 3 1 6 SOIC ADR03 2.5 0.10 9 1 6 TSOT, SC70 ADR06 3 0.10 3 1 10 SOIC ADR06 3 0.10 9 1 10 TSOT, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC ADR435 5 0.04 3 0.8 8 SOIC ADR391 2.5 0.16 9 0.12 5 TSOT ADR395 5 0.10 9 0.12 8 TSOT Table 8. Suitable Analog Devices Precision Op Amps Part No. Supply Voltage (V) V (Max) (µV) I (Max) (nA) 0.1 Hz to 10 Hz Noise (µV p-p) Supply Current (µA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC Table 9. Suitable Analog Devices High Speed Op Amps Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) V (Max) (µV) I (Max) (nA) Package OS B AD8065 5 to 24 145 180 1500 6000 SOIC, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1000 10,500 SOIC, MSOP AD8038 3 to 12 350 425 3000 750 SOIC, SC70 AD9631 ±3 to ±6 320 1300 10,000 7000 SOIC Rev. F | Page 19 of 28

AD5429/AD5439/AD5449 Data Sheet SDO Control (SDO1 and SDO2) SERIAL INTERFACE The SDO bits enable the user to control the SDO output driver The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire strength, disable the SDO output, or configure it as an open-drain interface that is compatible with SPI, QSPI, MICROWIRE, and driver. The strength of the SDO driver affects the timing of t , most DSP interface standards. Data is written to the device in 12 and, when stronger, allows a faster clock cycle. 16-bit words. Each 16-bit word consists of four control bits and eight, 10, or 12 data bits, as shown in Figure 43 through Figure 45. Table 10. SDO Control Bits Low Power Serial Interface SDO2 SDO1 Function Implemented 0 0 Full SDO driver To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is, 0 1 Weak SDO driver on the falling edge of SYNC. The SCLK and SDIN input buffers 1 0 SDO configured as open drain 1 1 Disable SDO output are powered down on the rising edge of SYNC. DAC Control Bit C3 to Control Bit C0 Daisy-Chain Control (DSY) Control Bit C3 to Control Bit C0 allow control of various functions DSY allows the enabling or disabling of daisy-chain mode. of the DAC, as shown in Table 11. The default settings of the DAC A 1 enables daisy-chain mode; a 0 disables daisy-chain mode. at power-on are such that data is clocked into the shift register When disabled, a readback request is accepted; SDO is auto- on falling clock edges and daisy-chain mode is enabled. The device matically enabled; the DAC register contents of the relevant powers on with a zero-scale load to the DAC register and I lines. DAC are clocked out on SDO; and, when complete, SDO is OUT The DAC control bits allow the user to adjust certain features at disabled again. power-on. For example, daisy-chaining can be disabled if not in Hardware CLR Bit (HCLR) use, an active clock edge can be changed to a rising edge, and DAC The default setting for the hardware CLR bit is to clear the registers output can be cleared to either zero scale or midscale. The user and DAC output to zero code. A 1 in the HCLR bit allows the can also initiate a readback of the DAC register contents for veri- CLR pin to clear the DAC outputs to midscale, and a 0 clears to fication. zero scale. Control Register (Control Bits = 1101) Active Clock Edge (SCLK) While maintaining software compatibility with single-channel The default active clock edge is a falling edge. Write a 1 to this current output DACs (AD5426/AD5432/AD5443), these DACs bit to clock data in on the rising edge, or a 0 to clock it in on the also feature additional interface functionality. Set the control bits falling edge. to 1101 to enter control register mode. Figure 46 shows the contents of the control register, the functions of which are described in the following sections. DB15 (MSB) DB0 (LSB) C3 COCN2TROL CB1ITS C0 DB7 DB6 DB5 DB4 DB3 DDBA2TA BIDTBS1 DB0 0 0 0 0 04464-013 Figure 43. AD5429 8-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C3 COCN2TROL CB1ITS C0 DB9 DB8 DB7 DB6 DB5 DDBA4TA BIDTBS3 DB2 DB1 DB0 0 0 04464-014 Figure 44. AD5439 10-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) C3 COCN2TROL CB1ITS C0 DB11 DB10 DB9 DB8 DB7 DDBA6TA BIDTBS5 DB4 DB3 DB2 DB1 DB0 04464-015 Figure 45. AD5449 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) 1 CO1NTROL B0ITS 1 SDO2 SDO1 DSY HCLR SCLK X X X X X X X 04464-016 Figure 46. Control Register Loading Sequence Rev. F | Page 20 of 28

Data Sheet AD5429/AD5439/AD5449 SYNC Function When control bits = 0000, the device is in no operation mode. This may be useful in daisy-chain applications in which the user SYNC is an edge-triggered input that acts as a frame synchron- does not want to change the settings of a particular DAC in the ization signal and chip enable. Data can be transferred into the chain. Write 0000 to the control bits for that DAC; subsequent device only while SYNC is low. To start the serial data transfer, data bits are ignored. SYNC should be taken low, observing the minimum SYNC Standalone Mode falling edge to SCLK falling edge setup time, t. 4 Daisy-Chain Mode After power-on, write 1001 to the control word to disable daisy- chain mode. The first falling edge of SYNC resets the serial Daisy-chain mode is the default power-on mode. To disable the clock counter to ensure that the correct number of bits are daisy-chain function, write 1001 to the control word. In daisy- shifted in and out of the serial shift registers. A SYNC edge chain mode, the internal gating on SCLK is disabled. SCLK is during the 16-bit write cycle causes the device to abort the continuously applied to the input shift register when SYNC is current write cycle. low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data After the falling edge of the 16th SCLK pulse, data is automat- is clocked out on the rising edge of SCLK (this is the default; use ically transferred from the input shift register to the DAC. For the control word to change the active edge) and is valid for the another serial transfer to take place, the counter must be reset next device on the falling edge of SCLK (default). By connecting by the falling edge of SYNC. this line to the SDIN input on the next device in the chain, LDAC Function a multidevice interface is constructed. For each device in the The LDAC function allows asynchronous and synchronous system, 16 clock pulses are required. Therefore, the total number updates to the DAC output. The DAC is asynchronously updated of clock cycles must equal 16n, where n is the total number of when this signal goes low. Alternatively, if this line is held perma- devices in the chain. See Figure 4. nently low, an automatic or synchronous update mode is selected, When the serial transfer to all devices is complete, SYNC should whereby the DAC is updated on the 16th clock falling edge when be taken high. This prevents additional data from being clocked the device is in standalone mode, or on the rising edge of SYNC into the input shift register. A burst clock containing the exact when the device is in daisy-chain mode. number of clock cycles can be used, after which SYNC can be Software LDAC Function taken high. After the rising edge of SYNC, data is automatically transferred from the input shift register of each device to the Load-and-update mode can also serve as a software update func- addressed DAC. tion, irrespective of the voltage level on the LDAC pin. Table 11. DAC Control Bits C3 C2 C1 C0 DAC Function Implemented 0 0 0 0 A and B No operation (power-on default) 0 0 0 1 A Load and update 0 0 1 0 A Initiate readback 0 0 1 1 A Load input register 0 1 0 0 B Load and update 0 1 0 1 B Initiate readback 0 1 1 0 B Load input register 0 1 1 1 A and B Update DAC outputs 1 0 0 0 A and B Load input registers 1 0 0 1 N/A Disable daisy-chain 1 0 1 0 N/A Clock data to shift register on rising edge 1 0 1 1 N/A Clear DAC output to zero scale 1 1 0 0 N/A Clear DAC output to midscale 1 1 0 1 N/A Control word 1 1 1 0 N/A Reserved 1 1 1 1 N/A No operation Rev. F | Page 21 of 28

AD5429/AD5439/AD5449 Data Sheet MICROPROCESSOR INTERFACING See the ADSP-2191M user manual at www.analog.com for details on clock and frame SYNC frequencies for the SPORT Microprocessor interfacing to the AD5429/AD5439/AD5449 register. Table 12 shows the setup for the SPORT control register. DACs is through a serial bus that uses standard protocol and is compatible with microcontrollers and DSP processors. The Table 12. SPORT Control Register Setup communication channel is a 3-wire interface consisting of a Name Setting Description clock signal, a data signal, and a synchronization signal. The TFSW 1 Alternate framing AD5429/AD5439/AD5449 require a 16-bit word, with the INVTFS 1 Active low frame signal default being data valid on the falling edge of SCLK; however, DTYPE 00 Right-justify data this is changeable using the control bits in the data-word. ISCLK 1 Internal serial clock ADSP-2191M and Family-to-AD5429/AD5439/AD5449 TFSR 1 Frame every word Interface ITFS 1 Internal framing signal The ADSP-2191M family of DSPs is easily interfaced to an SLEN 1111 16-bit data-word AD5429/AD5439/AD5449 DAC without the need for extra glue ADSP-BF534-to-AD5429/AD5439/AD5449 Interface logic. Figure 47 is an example of a serial peripheral interface (SPI) between the DAC and the ADSP-2191M. The MOSI (master The ADSP-BF534 family of processors has an SPI-compatible port output, slave input) pin of the DSP drives the serial data line, that enables the processor to communicate with SPI-compatible SDIN. SYNC is driven from a port line, in this case SPIxSEL. devices. A serial interface between the BlackFin® processor and the AD5429/AD5439/AD5449 DAC is shown in Figure 49. In AD5429/AD5439/ ADSP-2191M* this configuration, data is transferred through the MOSI pin. AD5449* SYNC is driven by the SPIxSEL pin, which is a reconfigured SPIxSEL SYNC programmable flag pin. MOSI SDIN SCK SCLK AD5429/AD5439/ ADSP-BF534* AD5449* *ADDITIONAL PINS OMITTED FOR CLARITY. 04464-027 SPIxSEL SYNC Figure 47. ADSP-2191M SPI-to-AD5429/AD5439/AD5449 Interface MOSI SDIN SCK SCLK The ADSP-2191M processor incorporates channel synchronous sDeSriPa lS pPoOrtRs T(S iPs OshRoTw)n. A in s Ferigiaulr ien 4te8r.f Ianc eth bise tiwnteeernfa cthe ee xDaAmCp lae,n d *ADDITIONAL PINS OMITTED FOR CLARITY. 04464-033 SPORT0 is used to transfer data to the DAC shift register. Figure 49. ADSP-BF534-to-AD5429/AD5439/AD5449 Interface Transmission is initiated by writing a word to the Tx register after A serial interface between the DAC and the DSP SPORT is shown SPORT has been enabled. In a write sequence, data is clocked in Figure 50. When SPORT is enabled, initiate transmission by out on each rising edge of the DSP serial clock and clocked into writing a word to the Tx register. The data is clocked out on each the DAC input shift register on the falling edge of its SCLK. rising edge of the DSP serial clock and clocked into the DAC Updating of the DAC output takes place on the rising edge of input shift register on the falling edge of its SCLK. The DAC the SYNC signal. output is updated by using the transmit frame synchronization (TFS) line to provide a SYNC signal. ADSP-2191M* AD5429/AD5439/ AD5449* ADSP-BF534* AD5429/AD5439/ TFS SYNC AD5449* DT SDIN TFS SYNC SCLK SCLK DT SDIN *ADFDiIgTuIOreN A4L8 .P AINDSS OP-M2I1T9T1EMD FSOPRO CRLTA-tRoI-TAY.D5429/AD5439/AD5449 Interface 04464-028 *ADDITIONAL PINSS COLMKITTED FOR CLARITY. SCLK 04464-034 Communication between two devices at a given clock speed is Figure 50. ADSP-BF534 SPORT-to-AD5429/AD5439/AD5449 Interface possible when the following specifications are compatible: frame SYNC delay and frame SYNC setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC interface expects a t (SYNC falling edge to SCLK falling edge setup time) of 13 ns 4 minimum. Rev. F | Page 22 of 28

Data Sheet AD5429/AD5439/AD5449 80C51/80L51-to-AD5429/AD5439/AD5449 Interface valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges A serial interface between the DAC and the 80C51/80L51 is occurring in the transmit cycle. Data is transmitted MSB first. shown in Figure 51. TxD of the 80C51/80L51 drives SCLK of the DAC serial interface, and RxD drives the serial data line, SDIN. To load data to the DAC, leave PC7 low after the first eight bits P1.1 is a bit-programmable pin on the serial port and is used to are transferred and perform a second serial write operation to drive SYNC. When data is to be transmitted to the switch, P1.1 the DAC. PC7 is taken high at the end of this procedure. is taken low. The 80C51/80L51 transmit data in 8-bit bytes only; If the user wants to verify the data previously written to the input therefore, only eight falling clock edges occur in the transmit cycle. shift register, the SDO line can be connected to MISO of the To load data correctly to the DAC, P1.1 is left low after the first MC68HC11, and, with SYNC low, the shift register clocks data eight bits are transmitted, and then a second write cycle is initiated out on the rising edges of SCLK. to transmit the second byte of data. Data on RxD is clocked out MICROWIRE-to-AD5429/AD5439/AD5449 Interface of the microcontroller on the rising edge of TxD and is valid on Figure 53 shows an interface between the DAC and any the falling edge of TxD. As a result, no glue logic is required MICROWIRE-compatible device. Serial data is shifted out between the DAC and microcontroller interface. P1.1 is taken on the falling edge of the serial clock, SK, and is clocked into high following the completion of this cycle. The 80C51/80L51 the DAC input shift register on the rising edge of SK, which provide the LSB of the SBUF register as the first bit in the data corresponds to the falling edge of the DAC SCLK. stream. The DAC input register requires its data with the MSB as the first bit received. The transmit routine should take this MICROWIRE* AD5429/AD5439/ requirement into account. AD5449* SK SCLK 80C51* AD5429/AD5439/ SO SDIN AD5449* TxD SCLK CS SYNC PR1x.D1 SSYDNINC *ADDITIONAL PINS OMITTED FOR CLARITY. 04464-031 Figure 53. MICROWIRE-to-AD5429/AD5439/AD5449 Interface *ADDITIONAL PINS OMITTED FOR CLARITY. 04464-029 PIC16C6x/7x-to-AD5429/AD5439/AD5449 Interface Figure 51. 80C51/80L51-to-AD5429/AD5439/AD5449 Interface The PIC16C6x/7x synchronous serial port (SSP) is configured MC68HC11-to-AD5429/AD5439/AD5449 Interface as an SPI master with the clock polarity bit (CKP) = 0. This is done by writing to the synchronous serial port control register Figure 52 is an example of a serial interface between the DAC (SSPCON). See the PIC16/17 microcontroller user manual for and the MC68HC11 microcontroller. The SPI on the MC68HC11 more information. In this example, the I/O port, RA1, is used to is configured for master mode (MSTR) = 1, clock polarity bit provide a SYNC signal and enable the serial port of the DAC. This (CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured microcontroller transfers only eight bits of data during each serial by writing to the SPI control register (SPCR); see the MC68HC11 transfer operation; therefore, two consecutive write operations user manual. The SCK of the MC68HC11 drives the SCLK of are required. Figure 54 shows the connection diagram. the DAC interface; the MOSI output drives the serial data line (SDIN) of the AD5429/AD5439/AD5449. PIC16C6x/7x* AD5429/AD5439/ AD5449* MC68HC11* AD5429/AD5439/ SCK/RC3 SCLK AD5449* SDI/RC4 SDIN PC7 SYNC RA1 SYNC SCK SCLK *ADDITIONAL PINSM OOMSIITTED FOR CLARITY. SDIN 04464-030 *ADDITIOFiNgAuLr eP 5IN4S. POIMC1IT6TCE6Dx F/7OxR- tCoL-AARDI5TY4.29/AD5439/AD5449 Interface 04464-032 Figure 52. MCH68HC11/68L11-to-AD5429/AD5439/AD5449 Interface The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5429/AD5439/AD5449, the SYNC line is taken low (PC7). Data appearing on the MOSI output is Rev. F | Page 23 of 28

AD5429/AD5439/AD5449 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING Components, such as clocks, that produce fast-switching signals, should be shielded with digital ground to avoid radiating noise In any circuit where accuracy is important, careful considera- to other parts of the board, and they should never be run near tion of the power supply and ground return layout helps to the reference inputs. ensure the rated performance. The printed circuit board on which the AD5429/AD5439/AD5449 is mounted should be Avoid crossover of digital and analog signals. Traces on opposite designed so that the analog and digital sections are separate sides of the board should run at right angles to each other. This and confined to certain areas of the board. If the DAC is in a layout reduces the effects of feedthrough on the board. A micro- system where multiple devices require an AGND-to-DGND strip technique is by far the best method, but its use is not always connection, the connection should be made at one point only. possible with a double-sided board. In this technique, the compo- The star ground point should be established as close as possible nent side of the board is dedicated to the ground plane, and to the device. signal traces are placed on the soldered side. The DAC should have ample supply bypassing of 10 µF in parallel It is good practice to use compact, minimum lead-length PCB with 0.1 µF on the supply, located as close as possible to the layout design. Leads to the input should be as short as possible package, ideally right up against the device. The 0.1 µF capacitor to minimize IR drops and stray inductance. should have low effective series resistance (ESR) and low effective The PCB metal traces between V x and R x should also be REF FB series inductance (ESI), such as the common ceramic types of matched to minimize gain error. To maximize high frequency capacitors that provide a low impedance path to ground at high performance, the I-to-V amplifier should be located as close as frequencies, to handle transient currents due to internal logic possible to the device. switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Rev. F | Page 24 of 28

Data Sheet AD5429/AD5439/AD5449 OVERVIEW OF MULTIPLYING DAC DEVICES Table 13. Part No. Resolution No. DACs INL (LSB) Interface Package1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. F | Page 25 of 28

AD5429/AD5439/AD5449 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 55. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution INL (LSB) Temperature Range Package Description Package Option AD5429YRU-REEL7 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRUZ 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5429YRUZ-REEL7 8 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRU-REEL 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRU-REEL7 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRUZ 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5439YRUZ-REEL7 10 ±0.5 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRU 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRU-REEL 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRU-REEL7 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRUZ 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRUZ-REEL 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 AD5449YRUZ-REEL7 12 ±1 −40°C to +125°C 16-Lead TSSOP RU-16 EV-AD5415/49SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. F | Page 26 of 28

Data Sheet AD5429/AD5439/AD5449 NOTES Rev. F | Page 27 of 28

AD5429/AD5439/AD5449 Data Sheet NOTES ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04464-0-1/16(F) Rev. F | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5429YRUZ AD5449YRU AD5439YRUZ AD5429YRUZ-REEL7 AD5449YRU-REEL AD5449YRUZ AD5449YRU- REEL7 AD5439YRUZ-REEL7