Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs, HART Connectivity Data Sheet AD5412/AD5422 FEATURES GENERAL DESCRIPTION 12-/16-bit resolution and monotonicity The AD5412/AD5422 are low cost, precision, fully integrated Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 12-/16-bit digital-to-analog converters (DAC) offering a pro- 0 mA to 24 mA grammable current source and programmable voltage output ±0.01% FSR typical total unadjusted error (TUE) designed to meet the requirements of industrial process control ±3 ppm FSR/°C output drift applications. Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V The output current range is programmable at 4 mA to 20 mA, 10% overrange 0 mA to 20 mA, or an overrange function of 0 mA to 24 mA. ±0.01% FSR typical TUE ±2 ppm FSR/°C output drift The LFCSP version of this product has a CAP2 pin so that the Flexible serial digital interface HART signals can be coupled onto the current output of the On-chip output fault detection AD5412/AD5422. On-chip reference: 10 ppm/°C maximum Voltage output is provided from a separate pin that can be Optional regulated DVCC output configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V Asynchronous clear function output ranges; an overrange of 10% is available on all ranges. Power supply range Analog outputs are short and open-circuit protected and can AV : 10.8 V to 40 V DD drive capacitive loads of 1 µF. AV : −26.4 V to −3 V/0 V SS Current loop compliance voltage: AVDD – 2.5 V The device operates with an AVDD power supply range from 10.8 V Temperature range: −40°C to +105°C to 40 V. Current loop compliance voltage is 0 V to AVDD − 2.5 V. TSSOP and LFCSP packages The flexible serial interface is SPI- and MICROWIRE™-compatible APPLICATIONS and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. Process controls Actuator controls The device also includes a power-on-reset function, ensuring PLC that the device powers up in a known state. The part also includes HART network connectivity (LFCSP package only) an asynchronous clear pin (CLEAR) that sets the outputs to zero-scale/midscale voltage output or the low end of the selected current range. The total output error is typically ±0.01% in current mode and ±0.01% in voltage mode. Table 1. Pin-Compatible Devices Part No. Description AD5410 Single channel, 12-bit, serial input current source DAC AD5420 Single channel, 16-bit, serial input current source DAC COMPANION PRODUCTS HART Modem: AD5700, AD5700-1 Rev. O Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5412/AD5422 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Fault Alert .................................................................................... 35 Applications ....................................................................................... 1 Voltage Output Short Circuit Protection ................................ 35 General Description ......................................................................... 1 Voltage Output Overrange ........................................................ 35 Companion Products ....................................................................... 1 Voltage Output Force-Sense ..................................................... 35 Revision History ............................................................................... 3 Asynchronous Clear (CLEAR) ................................................. 35 Functional Block Diagram .............................................................. 4 Internal Reference ...................................................................... 35 Specifications ..................................................................................... 5 External Current Setting Resistor ............................................ 35 AC Performance Characteristics .............................................. 10 Digital Power Supply .................................................................. 36 Timing Characteristics .............................................................. 10 External Boost Function............................................................ 36 Absolute Maximum Ratings .......................................................... 13 External Compensation Capacitor........................................... 36 ESD Caution ................................................................................ 13 HART Communication ............................................................. 36 Pin Configurations and Function Descriptions ......................... 14 Digital Slew Rate Control .......................................................... 36 Typical Performance Characteristics ........................................... 16 I Filtering Capacitors (LFCSP Package) ............................. 37 OUT General ......................................................................................... 16 Applications Information .............................................................. 39 Voltage Output ............................................................................ 18 Voltage and Current Output Ranges on the Same Terminal 39 Current Output ........................................................................... 23 Driving Inductive Loads ............................................................ 39 Terminology .................................................................................... 27 Transient Voltage Protection .................................................... 39 Theory of Operation ...................................................................... 29 Galvanically Isolated Interface ................................................. 39 Architecture ................................................................................. 29 Microprocessor Interfacing ....................................................... 39 Serial Interface ............................................................................ 30 Layout Guidelines....................................................................... 40 Power-On State ........................................................................... 31 Thermal and Supply Considerations ....................................... 40 Data Register ............................................................................... 33 Industrial Analog Output Module ........................................... 41 Control Register .......................................................................... 33 Industrial HART Capable Analog Output Application ........ 41 Reset Register .............................................................................. 34 Outline Dimensions ....................................................................... 43 Status Register ............................................................................. 34 Ordering Guide .......................................................................... 44 AD5412/AD5422 Features ............................................................ 35 Rev. O | Page 2 of 44

Data Sheet AD5412/AD5422 REVISION HISTORY 10/2017—Rev. N to Rev. O Changes to Table 21 ........................................................................ 33 Changed CP-40-10 to CP-40-1 .................................... Throughout Changes to Thermal and Supply Considerations Section ......... 38 Updated Outline Dimensions ........................................................ 43 Changes to Table 25 ........................................................................ 39 Changes to Ordering Guide ........................................................... 44 7/2012—Rev. E to Rev. F 3/2017—Rev. M to Rev. N Updated Outline Dimensions........................................................ 40 Changed CP-40-9 to CP-40-10 .................................... Throughout Changes to Ordering Guide ........................................................... 40 Changes to Table 6 .......................................................................... 13 Changes to Figure 85 ...................................................................... 43 5/2012—Rev. D to Rev. E Updated Outline Dimensions ........................................................ 43 Reorganized Layout ........................................................... Universal Changes to Ordering Guide ........................................................... 44 Changes to Product Title.................................................................. 1 Changes to Features Section, Applications Section, and General 7/2016—Rev. L to Rev. M Description Section; Added Companion Products Section ............. 1 Changed −40°C to +85°C to −40°C to +105°C and CP-40-1 to Changes to Figure 1 .......................................................................... 3 CP-40-9 ........................................................................... Throughout Change to Offset Error Temperature Coefficient (TC) Changes to Table 2 ............................................................................ 5 Parameter, Table 1 ............................................................................. 4 Added Table 3; Renumbered Sequentially ..................................... 9 Changes to Table 6 .......................................................................... 12 Changes to Figure 6......................................................................... 14 Changes to Power-On State Section ............................................. 29 Changes to Thermal and Supply Conditions Section ................ 40 Added HART Communication Section and Figure 68, Updated Outline Dimensions ........................................................ 43 Renumbered Sequentially .............................................................. 33 Changes to Ordering Guide ........................................................... 44 Added Voltage and Current Output Ranges on the Same Terminal Section and Figure 74 .................................................... 36 7/2015—Rev. K to Rev. L Added Industrial HART Capable Analog Output Application Change to I to GND Parameter, Table 5 ................................. 11 Section .............................................................................................. 38 OUT Change to Voltage and Current Output Ranges on the Same Added Figure 79 .............................................................................. 39 Terminal Section ............................................................................. 37 11/2011—Rev. C to Rev. D 3/2015—Rev. J to Rev. K Changes to Table 15 ........................................................................ 29 Changes to Table 4 ............................................................................ 9 Changes to Table 6 .......................................................................... 13 3/2010—Rev. B to Rev. C Changes to Power-On State Section ............................................. 29 Changes to AVSS to GND Parameter in Table 5 ......................... 10 10/2014—Rev. I to Rev. J 2/2010—Rev. A to Rev. B Changes to Power-On State Section ............................................. 29 Changes to Thermal and Supply Considerations Section and Changes to Table 25 ........................................................................ 39 Table 25 ............................................................................................. 36 10/2013—Rev. H to Rev. I 8/2009—Rev. 0 to Rev. A Added Figure 34 and Figure 35; Renumbered Sequentially ...... 18 Changes to Table 2 ............................................................................ 4 Changes to Figure 78 ...................................................................... 37 Changes to Table 3 ............................................................................ 7 Changes to Industrial Analog Output Module Section ............. 39 Changes to Introduction to Table 4 ................................................ 8 Changes to Industrial HART Capable Analog Output Changes to Introduction to Table 5 and to Table 5 .................... 10 Application Section ......................................................................... 39 Changes to Pin Configurations and Function Descriptions Section, Added Figure 6, Renumbered Subsequent Figures ..... 11 6/2013—Rev. G to Rev. H Changes to Theory of Operation Section .................................... 26 Change to REFOUT Pin, Table 6 .................................................. 12 Changes to Architecture Section ................................................... 26 Changes to Voltage and Current Output Ranges on the Same Changes to AD5412/AD5422 Features Section .......................... 31 Terminal Section and Figure 75 .................................................... 36 Added I Filtering Capacitors (LFCSP Package) Section, OUT Including Figure 69 to Figure 72 and Table 24 ............................ 33 3/2013—Rev. F to Rev. G Changes to Thermal and Supply Considerations Section ......... 36 Changed TSSOP_EP θ from 42°C/W to 35°C/W, Changed Updated Outline Dimensions........................................................ 38 JA LFCSP θ from 28°C/W to 33°C/W, and Added Endnote 2 ..... 11 Changes to Ordering Guide ........................................................... 39 JA Added Figure 67 .............................................................................. 30 Changes to REXT Description; Table 15 ...................................... 31 5/2009—Revision 0: Initial Version Rev. O | Page 3 of 44

AD5412/AD5422 Data Sheet FUNCTIONAL BLOCK DIAGRAM DVCC SELECT DVCC *CAP1 *CAP2 AVSS AVDD CLEAR SELECT AD5412/AD5422 R2 R3 4.5V LDO BOOST CLEAR LATCH INPUT SHIFT 12/16 SSCDLINK ANRDE CGOISNTTERROL 12-D/1A6C-BIT IOUT LOGIC SDO FAULT RSET POWER-ON VREF RSET RESET +VSENSE SRCAANLGINEG VOUT –VSENSE REFOUT REFIN GND CCOMP 06996-001 *PINS ONLY ON LFCSP OPTION. Figure 1. Rev. O | Page 4 of 44

Data Sheet AD5412/AD5422 SPECIFICATIONS AV = 10.8 V to 26.4 V, AV = −26.4 V to −3 V/0 V, AV + |AV | < 52.8 V, GND = 0 V, REFIN = 5 V external; DV = 2.7 V to 5.5 V. DD SS DD SS CC V : R = 1 kΩ, C = 200 pF, I : R = 350 Ω; all specifications T to T , unless otherwise noted. OUT LOAD L OUT LOAD MIN MAX Table 2. Parameter1 Min Typ Max Unit Test Conditions/Comments VOLTAGE OUTPUT Output Voltage Ranges 0 5 V 0 10 V −5 +5 V −10 +10 V Accuracy Output unloaded Resolution 16 Bits AD5422 12 Bits AD5412 Total Unadjusted Error (TUE) B Version −0.1 +0.1 % FSR −0.05 ±0.01 +0.05 % FSR T = 25°C A A Version −0.3 +0.3 % FSR T = −40°C to +85°C A −0.1 ±0.05 +0.1 % FSR T = 25°C A Relative Accuracy (INL)2 −0.008 +0.008 % FSR AD5422 −0.032 +0.032 % FSR AD5412 Differential Nonlinearity (DNL) −1 +1 LSB T = −40°C to +85°C, guaranteed monotonic A −1 +1.3 LSB Guaranteed monotonic Bipolar Zero Error −6 +6 mV T = −40°C to +85°C, bipolar output range A −9 +9 mV Bipolar output range −1.5 ±0.2 +1.5 mV T = 25°C, bipolar output range A Bipolar Zero Error Temperature ±3 ppm FSR/°C Bipolar output range Coefficient (TC)3 Zero-Scale Error −5 +5 mV T = −40°C to +85°C A −8 +8 mV −3.5 ±0.3 +3.5 mV T = 25°C A Zero-Scale Error TC3 ±2 ppm FSR/°C Offset Error −4 +4 mV T = −40°C to +85°C, unipolar output range A −6 +6 mV Unipolar output range −1.5 ±0.2 +1.5 mV T = 25°C, unipolar output range A Offset Error TC3 ±2 ppm FSR/°C Unipolar output range Gain Error −0.07 +0.07 % FSR −0.05 ±0.004 +0.05 % FSR T = 25°C A Gain Error TC3 ±1 ppm FSR/°C T = −40°C to +85°C A ±3 ppm FSR/°C Full-Scale Error −0.07 +0.07 % FSR −0.05 ±0.001 +0.05 % FSR T = 25°C A Full-Scale Error TC3 ±1 ppm FSR/°C T = −40°C to +85°C A ±2 ppm FSR/°C Rev. O | Page 5 of 44

AD5412/AD5422 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments OUTPUT CHARACTERISTICS3 Headroom 0.5 0.8 V Output unloaded Output Voltage Drift vs. Time 90 ppm FSR Drift after 1000 hours, T = 125°C A Short-Circuit Current 20 mA Load 1 kΩ Capacitive Load Stability T = 25°C A R = ∞ 20 nF LOAD R = 1 kΩ 5 nF LOAD R = ∞ 1 µF External compensation capacitor of 4 nF LOAD connected DC Output Impedance 0.3 Ω Power-On Time 10 µs DC PSRR 90 130 µV/V 3 12 µV/V Output unloaded CURRENT OUTPUT Output Current Ranges 0 24 mA 0 20 mA 4 20 mA Accuracy (Internal R ) SET Resolution 16 Bits AD5422 12 Bits AD5412 TUE B Version −0.3 +0.3 % FSR −0.13 ±0.08 +0.13 % FSR T = 25°C A A Version −0.5 +0.5 % FSR T = −40°C to +85°C A −0.3 ±0.15 +0.3 % FSR T = 25°C A INL4 −0.024 +0.024 % FSR AD5422 −0.032 +0.032 % FSR AD5412 DNL −1 +1 LSB T = −40°C to +85°C, guaranteed monotonic A −1 +1.3 LSB Guaranteed monotonic Offset Error −0.27 +0.27 % FSR T = −40°C to +85°C A −0.40 +0.40 % FSR −0.12 ±0.08 +0.12 % FSR T = 25°C A Offset Error TC3 ±16 ppm FSR/°C T = −40°C to +85°C A ±28 ppm FSR/°C Gain Error −0.18 +0.18 % FSR T = −40°C to +85°C, AD5422 A −0.20 +0.20 % FSR AD5422 −0.03 ±0.006 +0.03 % FSR AD5422, T = 25°C A −0.22 +0.22 % FSR T = −40°C to +85°C, AD5412 A −0.24 +0.24 % FSR AD5412 −0.06 ±0.006 +0.06 % FSR AD5412, T = 25°C A Gain TC3 ±10 ppm FSR/°C T = −40°C to +85°C A ±21 ppm FSR/°C Full-Scale Error −0.2 +0.2 % FSR T = −40°C to +85°C A −0.40 +0.40 % FSR −0.1 ±0.08 +0.1 % FSR T = 25°C A Full-Scale TC3 ±6 ppm FSR/°C T = −40°C to +85°C A ±13 ppm FSR/°C Rev. O | Page 6 of 44

Data Sheet AD5412/AD5422 Parameter1 Min Typ Max Unit Test Conditions/Comments Accuracy (External R ) SET Resolution 16 Bits AD5422 12 Bits AD5412 TUE B Version −0.15 +0.15 % FSR −0.06 ±0.01 +0.06 % FSR T = 25°C A A Version −0.3 +0.3 % FSR T = −40°C to +85°C A −0.1 ±0.02 +0.1 % FSR T = 25°C A INL4 −0.012 +0.012 % FSR AD5422 −0.032 +0.032 % FSR AD5412 DNL −1 +1 LSB T = −40°C to +85°C, guaranteed monotonic A −1 +1.3 LSB Guaranteed monotonic Offset Error −0.1 +0.1 % FSR T = −40°C to +85°C A −0.12 +0.12 % FSR −0.03 ±0.006 +0.03 T = 25°C A Offset Error TC3 ±3 ppm FSR/°C T = −40°C to +85°C A ±5 ppm FSR/°C Gain Error −0.08 +0.08 % FSR T = −40°C to +85°C A −0.15 +0.15 % FSR −0.05 ±0.003 +0.05 % FSR T = 25°C A Gain TC3 ±4 ppm FSR/°C Full-Scale Error −0.15 +0.15 % FSR −0.06 ±0.01 +0.06 % FSR T = 25°C A Full-Scale Error TC3 ±7 ppm FSR/°C T = −40°C to +85°C A ±9 ppm FSR/°C OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage 0 AV − 2.5 V DD Output Current Drift vs. Time Drift after 1000 hours, T = 125°C A 50 ppm FSR Internal R SET 20 ppm FSR External R SET Resistive Load 1200 Ω Inductive Load 50 mH T = 25 °C A DC PSRR 1 µA/V Output Impedance 50 MΩ Output Current Leakage When Output 60 pA Disabled REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage 4.95 5 5.05 V For specified performance DC Input Impedance 27 40 kΩ Reference Output Output Voltage 4.995 5 5.005 T = 25°C A Reference TC3, 5 1.8 10 ppm/°C Output Noise (0.1 Hz to 10 Hz)3 10 µV p-p Noise Spectral Density3 100 nV/√Hz At 10 kHz Output Voltage Drift vs. Time3 50 ppm Drift after 1000 hours, T = 125°C A Capacitive Load3 600 nF Load Current3 5 mA Short-Circuit Current3 7 mA Load Regulation3 95 ppm/mA Rev. O | Page 7 of 44

AD5412/AD5422 Data Sheet Parameter1 Min Typ Max Unit Test Conditions/Comments DIGITAL INPUTS3 JEDEC compliant Input High Voltage, V 2 V IH Input Low Voltage, V 0.8 V IL Input Current −1 +1 µA Per pin Pin Capacitance 10 pF Per pin DIGITAL OUTPUTS3 SDO Output Low Voltage, V 0.4 V Sinking 200 µA OL Output High Voltage, V DV − 0.5 V Sourcing 200 µA OH CC High Impedance Leakage Current −1 +1 µA High Impedance Output Capacitance 5 pF FAULT Output Low Voltage, V 0.4 V 10 kΩ pull-up resistor to DV OL CC Output Low Voltage, V 0.6 V At 2.5 mA OL Output High Voltage, V 3.6 V 10 kΩ pull-up resistor to DV OH CC POWER REQUIREMENTS AV 10.8 40 V DD AV −26.4 0 V SS |AV | + AV 10.8 52.8 V SS DD DV CC Input Voltage 2.7 5.5 V Internal supply disabled Output Voltage 4.5 V DV , which can be overdriven up to 5.5 V CC Output Load Current3 5 mA Short-Circuit Current3 20 mA AI Outputs unloaded DD 2.5 3 mA Outputs disabled 3.4 4 mA Current output enabled 3.9 4.4 mA Voltage output enabled AI Outputs unloaded SS 0.24 0.3 mA Outputs disabled 0.5 0.6 mA Current output enabled 1.1 1.4 mA Voltage output enabled DI 1 mA V = DV , V = GND CC IH CC IL Power Dissipation 128 mW AV = 40 V, AV = 0 V, outputs unloaded DD SS 120 mW AV = +24 V, AV = −24 V, outputs unloaded DD SS 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5 V and 0 V to 10 V ranges is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 3 Guaranteed by design and characterization; not production tested. 4 For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 5 The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +105°C. Rev. O | Page 8 of 44

Data Sheet AD5412/AD5422 AV = 15 V to 26.4 V, AV = −26.4 V to −3 V/0 V, AV + |AV | < 52.8 V, GND = 0 V, REFIN = 5 V external; DV = 2.7 V to 5.5 V. DD SS DD SS CC V : R = 1 kΩ, C = 200 pF, I : R = 350 Ω; all specifications T to T , unless otherwise noted. Voltage over range enabled. OUT LOAD L OUT LOAD MIN MAX Table 3. Parameter1 Min Typ Max Unit Test Conditions/Comments VOLTAGE OUTPUT Output Voltage Ranges 0 5.5 V 0 11 V −5.5 +5.5 V −11 +11 V Accuracy Output unloaded Resolution 16 Bits AD5422 12 Bits AD5412 Total Unadjusted Error (TUE) B Version −0.13 +0.13 % FSR −0.10 ±0.01 +0.10 % FSR T = 25°C A Relative Accuracy (INL)2 −0.008 +0.008 % FSR AD5422 −0.032 +0.032 % FSR AD5412 Differential Nonlinearity (DNL) −1 +1.3 LSB Guaranteed monotonic Bipolar Zero Error −9 +9 mV Bipolar output range Bipolar Zero Error Temperature Coefficient (TC)3 ±3 ppm FSR/°C Bipolar output range Zero-Scale Error −18 +18 mV Zero-Scale Error TC3 ±2 ppm FSR/°C Offset Error −6 +6 mV Unipolar output range Offset Error TC3 ±2 ppm FSR/°C Unipolar output range Gain Error −0.13 +0.13 % FSR Gain Error TC3 ±3 ppm FSR/°C Full-Scale Error −0.13 +0.13 % FSR Full-Scale Error TC3 ±2 ppm FSR/°C 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 When the AD5412/AD5422 is powered with AVSS = 0 V, INL for the 0 V to 5.5 V and 0 V to 11 V ranges is measured beginning from Code 256 for the AD5422 and Code 16 for the AD5412. 3 Guaranteed by design and characterization; not production tested. Rev. O | Page 9 of 44

AD5412/AD5422 Data Sheet AC PERFORMANCE CHARACTERISTICS AV = 10.8 V to 26.4 V, AV = −26.4 V to −3 V/0 V, AV + |AV | < 52.8 V, GND = 0 V, REFIN = +5 V external; DV = 2.7 V to 5.5 V. DD SS DD SS CC V : R = 1 kΩ, C = 200 pF, I : R = 350 Ω; all specifications T to T , unless otherwise noted. OUT LOAD L OUT LOAD MIN MAX Table 4. Parameter1 Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Voltage Output Output Voltage Settling Time 25 µs 10 V step to ±0.03 % FSR 32 µs 20 V step to ±0.03 % FSR 18 µs 5 V step to ±0.03 % FSR 8 µs 512 LSB step to ±0.03 % FSR (16-Bit LSB) Slew Rate 0.8 V/µs Power-On Glitch Energy 10 nV-sec Digital-to-Analog Glitch Energy 10 nV-sec Glitch Impulse Peak Amplitude 20 mV Digital Feedthrough 1 nV-sec Output Noise (0.1 Hz to 10 Hz Bandwidth) 0.1 LSB p-p 16-bit LSB Output Noise (100 kHz Bandwidth) 200 µV rms 1/f Corner Frequency 1 kHz Output Noise Spectral Density 150 nV/√Hz Measured at 10 kHz, midscale output, 10 V range AC PSRR −75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage Current Output Output Current Settling Time 10 µs 16 mA step to 0.1% FSR 40 µs 16 mA step to 0.1% FSR, L = 1 mH AC PSRR −75 dB 200 mV 50 Hz/60 Hz sine wave superimposed on power supply voltage 1 Guaranteed by characterization, not production tested. TIMING CHARACTERISTICS AV = 10.8 V to 26.4 V, AV = −26.4 V to −3 V/0 V, AV + |AV | < 52.8V, GND = 0 V, REFIN = +5 V external; DV = 2.7 V to 5.5 V. DD SS DD SS CC V : R = 1 kΩ, C = 200 pF, I : R = 300 Ω; all specifications T to T , unless otherwise noted. OUT LOAD L OUT LOAD MIN MAX Table 5. Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX WRITE MODE t 33 ns min SCLK cycle time 1 t 13 ns min SCLK low time 2 t 13 ns min SCLK high time 3 t 13 ns min LATCH delay time 4 t 5 µs min LATCH high time 5 t 5 ns min Data setup time 6 t 5 ns min Data hold time 7 t 40 ns min LATCH low time 8 t 20 ns min CLEAR pulse width 9 t 5 µs max CLEAR activation time 10 Rev. O | Page 10 of 44

Data Sheet AD5412/AD5422 Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX READBACK MODE t 90 ns min SCLK cycle time 11 t 40 ns min SCLK low time 12 t 40 ns min SCLK high time 13 t 13 ns min LATCH delay time 14 t 40 ns min LATCH high time 15 t 5 ns min Data setup time 16 t 5 ns min Data hold time 17 t 40 ns min LATCH low time 18 t 35 ns max Serial output delay time (C 4 = 15 pF) 19 L SDO t 35 ns max LATCH rising edge to SDO tristate (C 4 = 15 pF) 20 L SDO DAISY-CHAIN MODE t 90 ns min SCLK cycle time 21 t 40 ns min SCLK low time 22 t 40 ns min SCLK high time 23 t 13 ns min LATCH delay time 24 t 40 ns min LATCH high time 25 t 5 ns min Data setup time 26 t 5 ns min Data hold time 27 t 40 ns min LATCH low time 28 t 35 ns max Serial output delay time (C 4 = 15 pF) 29 L SDO 1 Guaranteed by characterization; not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 2, Figure 3, and Figure 4. 4 CL SDO = capacitive load on SDO output. Timing Diagrams t1 SCLK 1 2 24 t2 t3 t4 t5 LATCH t7 t8 t6 SDIN DB23 DB0 t9 CLEAR t10 IOUT, VOUT 06996-002 Figure 2. Write Mode Timing Diagram Rev. O | Page 11 of 44

AD5412/AD5422 Data Sheet t11 SCLK 1 2 24 1 2 8 9 22 23 24 t12 t13 t14 t15 LATCH t17 t18 t16 SDIN DB23 DB0 DB23 DB0 NOPCONDITION IRNEPGUITS WTEORR TDO S BPEE CRIEFAIEDS t19 t20 SDO X X X X DB15 DB0 UNDEFINED DATA DFIORNS’TT 8C BAIRTES BAIRTES SDEALTEACCTLEODCRKEEGDI SOTUETR 06996-003 Figure 3. Readback Mode Timing Diagram t21 SCLK 1 2 24 25 26 48 t22 t23 t24 t25 LATCH t27 t28 t26 SDIN DB23 DB0 DB23 DB0 INPUT WORD FOR DAC N t29 INPUT WORD FOR DAC N – 1 t20 SDO DB23 UNDEFINED DB0 DB23 INPUT WORD FOR DAC N DB0 06996-004 Figure 4. Daisy-Chain Mode Timing Diagram Rev. O | Page 12 of 44

Data Sheet AD5412/AD5422 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses at or above those listed under Absolute Maximum 80 mA do not cause SCR latch-up. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 6. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond AV to GND −0.3 V to +48 V DD the maximum operating conditions for extended periods may AV to GND +0.3 V to −28 V SS affect product reliability. AV to AV −0.3 V to +60 V DD SS DV to GND −0.3 V to +7 V CC ESD CAUTION Digital Inputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) Digital Outputs to GND −0.3 V to DV + 0.3 V or 7 V CC (whichever is less) REFIN/REFOUT to GND −0.3 V to +7 V V to GND AV to AV OUT SS DD I to GND AV to AV OUT SS DD Operating Temperature Range (T) A Industrial1 −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 125°C J 24-Lead TSSOP_EP Package θ Thermal Impedance2 35°C/W JA 40-Lead LFCSP Package θ Thermal Impedance2 33°C/W JA Power Dissipation (T max – T )/θ J A JA Lead Temperature JEDEC industry standard Soldering J-STD-020 1 Power dissipated on chip must be derated to keep the junction temperature below 125°C, assuming that the maximum power dissipation condition is sourcing 24 mA into GND from IOUT with a 4 mA on-chip current. 2 Thermal impedance simulated values are based on JEDEC 2S2P thermal test board with thermal vias. See JEDEC JESD51. Rev. O | Page 13 of 44

AD5412/AD5422 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS EE SS DAVVCSCS 12 2243 A–VVSDEDNSE CN09VDCC8CN7VASS6VADD5CN4V–NES3V+NESV2TUO1CN 4333333333 FAULT 3 22 +VSENSE GND 4 AD5412/ 21 VOUT NC 1 30 NC AD5422 FAULT 2 29 CAP2 CLEAR SELECT 5 TOP VIEW 20 BOOST CLEAR SELGENCDT 43 AD5412/ 2278 BCOAPO1ST CLEAR 6 (Not to Scale) 19 IOUT CLEAR 5 AD5422 26 IOUT LATCH 6 TOP VIEW 25 NC LASTCCLHK 78 1187 NCCCOMP SSSCDDLIOKN 789 (Not to Scale) 222342 CDNVCCOCCM PSELECT NC 10 21 NC SDIN 9 16 DVCC SELECT SDO 10 15 REFIN 11213141516171819102 GGNNDD 1121 1143 RRESEFTOUT 06996-005 CNDNGDNGVASSDNGRTESTUOFERNIFERCNCN NOTES NOTES 1. NC = NO CONNECT 1. NC = NO CONNECT. 2. THEPADDLE CAN BE CONNECTEDTO 0V IF THE OUTPUT VOLTAGE RANGE 2. THE EXPOSED PADDLE CAN BE CONNECTED TO 0V IF THE OUTPUT IS UNIPOLAR. THEPADDLE CAN BE LEFT ELECTRICALLY UNCONNECTED VOLTAGE RANGE IS UNIPOLAR. THE EXPOSED PADDLE CAN BE LEFT PROVIDED THAT A SUPPLY CONNECTION IS MADEAT THEAVSS PIN. IT IS ELECTRICALLY UNCONNECTED PROVIDED THAT A SUPPLY CONNECTION RCEOCPOPEMRM PELNADNEED FTOHRAT E TNHHEANPACDEDDL TEH BEER MTAHEL RPMEARLFOLYR CMOANNNCEEC.TEDTO A TTISHH MEERRAMMDEAA LLAL TPY ET CRHOFEON ARNVMESCAST NPECINDE. . TITO IAS CROECPOPEMRM PELNADNEED FTOHRA TE NTHHEA NPCAEDDDLE BE 06996-006 Figure 5. TSSOP Pin Configuration Figure 6. LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. TSSOP LFCSP Mnemonic Description 1 14, 37 AV Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This pin can be SS connected to 0 V if the output voltage range is unipolar. 2 39 DV Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. This pin can also be configured as a CC 4.5 V LDO output by leaving the DV SELECT pin floating. CC 3 2 FAULT Fault Alert. This pin is asserted low when an open circuit is detected in current mode or an overtemperature is detected. Open drain output must be connected to a pull-up resistor. 4, 12 3, 15 GND These pins must be connected to 0 V. 18 1, 10, 11, 19, 20, NC No Connection. Do not connect to these pins. 21, 22, 25, 30, 31, 35, 38, 40 5 4 CLEAR Selects the voltage output clear value, either zero-scale or midscale code (see Table 22). SELECT 6 5 CLEAR Active High Input. Asserting this pin sets the current output to the bottom of the selected range or sets the voltage output to the user selected value (zero-scale or midscale). 7 6 LATCH Positive Edge Sensitive Latch. A rising LATCH edge parallel loads the input shift register data into the DAC register, also updating the output. 8 7 SCLK Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds of up to 30 MHz. 9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK. 10 9 SDO Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is valid on the rising edge of SCLK (see Figure 3 and Figure 4). 11 12, 13 GND Ground Reference Pin. 13 16 R An external, precision, low drift 15 kΩ current setting resistor can be connected to this SET pin to improve the I temperature drift performance. See the AD5412/AD5422 Features OUT section. 14 17 REFOUT Internal Reference Voltage Output. REFOUT = 5 V ± 5 mV. 15 18 REFIN External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for a specified performance. Rev. O | Page 14 of 44

Data Sheet AD5412/AD5422 Pin No. TSSOP LFCSP Mnemonic Description 16 23 DV When connected to GND, this pin disables the internal supply, and an external supply CC SELECT must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. In this case, it is recommended to connect a 0.1 μF capacitor between DV and CC GND. See the AD5412/AD5422 Features section. 17 24 C Optional compensation capacitor connection for the voltage output buffer. Connecting COMP a 4 nF capacitor between this pin and the V pin allows the voltage output to drive up OUT to 1 µF. It should be noted that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 19 26 I Current Output Pin. OUT 20 27 BOOST Optional External Transistor Connection. Connecting an external transistor reduces the power dissipated in the AD5412/AD5422. See the AD5412/AD5422 Features section. N/A 28, 29 CAP1, CAP2 Connection for Optional Output Filtering Capacitor. See the AD5412/AD5422 Features section. 21 32 V Buffered Analog Output Voltage. The output amplifier is capable of directly driving a OUT 1 kΩ, 2000 pF load. 22 33 +V Sense connection for the positive voltage output load connection. SENSE 23 34 −V Sense connection for the negative voltage output load connection. SENSE 24 36 AV Positive Analog Supply Pin. Voltage ranges from 10.8 V to 60 V. DD 25 (EPAD) 41 (EPAD) Exposed Negative Analog Supply Pin. Voltage ranges from –3 V to –24 V. This paddle can be connected paddle to 0 V if the output voltage range is unipolar. The paddle can be left electrically unconnected provided that a supply connection is made at the AV pin. It is recommended that the SS paddle be thermally connected to a copper plane for enhanced thermal performance. Rev. O | Page 15 of 44

AD5412/AD5422 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS GENERAL 900 9 TA = 25°C 800 TA = 25°C 8 700 V) 7 E ( 600 AG 6 DI(µA)CC450000 DVCC = 5V TPUT VOLT 45 U O 300 3 C C V 200 D 2 DVCC = 3V 100 1 00 0.5 1.0 1.5LO2G.0IC VO2.L5TAG3E.0 (V)3.5 4.0 4.5 5.0 06996-022 0–21 –19 –17 –15 L–O13AD –C1U1RR–E9NT (m–7A) –5 –3 –1 1 06996-024 Figure 7. DICC vs. Logic Input Voltage Figure 10. DVCC Output Voltage vs. Load Current 5 AIDD 4 3 AVDD (mA)SS 2 TVOAOU UT=T P2 =U5 °T0C VUNLOADED AI 3 /D 1 D AI REFERENCE OUTPUT 0 –1 AISS 1 –2 10 12 14 16 AVD1D8/|AVS2S0| (V) 22 24 26 28 06996-108 CCHH13 52..0000VV M200µs CH3 2.1V 06996-025 Figure 8. AIDD/AISS vs. AVDD/|AVSS| Figure 11. REFOUT Turn-on Transient 5.0 4.5 TIOAU =T =2 50°mCA 4.0 3.5 A)3.0 m (DD2.5 1 AI 2.0 1.5 1.0 0.5 010 15 20 AVD2D5 (V) 30 35 40 06996-023 CH1 2µV M2.00s LINE 1.8V 06996-026 Figure 9. AIDD vs. AVDD Figure 12. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth) Rev. O | Page 16 of 44

Data Sheet AD5412/AD5422 45 40 AVDD = 24V 35 %)30 ( N O25 TI 1 ULA20 P O P15 10 5 CH1 20µV M2.00s LINE 0V 06996-027 0 0 1 2TEMP3ERAT4URE C5OEFFI6CIENT7 (ppm/8°C) 9 10 06996-030 Figure 13. REFOUT Output Noise (100 kHz Bandwidth) Figure 15. Reference Temperature Coefficient Histogram 5.003 5.0005 V) 5.002 5A0V DDDE V=I C24EVS SHOWN V)5.0000 ATAV D=D 2 =5° 2C4V E ( E (4.9995 G G LTA 5.001 LTA4.9990 O O V V4.9985 T T U U P 5.000 P4.9980 T T U U E O E O4.9975 ENC 4.999 ENC4.9970 R R E E REF 4.998 REF4.9965 4.9960 4.997 4.9955 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-029 0 1 2 L3OAD C4URREN5T (mA6) 7 8 9 06996-031 Figure 14. Reference Voltage vs. Temperature Figure 16. Reference Voltage vs. Load Current Rev. O | Page 17 of 44

AD5412/AD5422 Data Sheet VOLTAGE OUTPUT 0.0025 1.0 AVDD = +24V 0.0020 AVSS = –24V 0.8 +5V RANGE AVDD = 24V TA = 25°C +10V RANGE AVSS = 0V 0.0015 0.6 TA = 25°C R) 0.0010 0.4 FS B) % 0.0005 LS 0.2 R ( R ( RO 0 RO 0 R R L E –0.0005 L E –0.2 N N I D –0.0010 –0.4 ±10V RANGE –0.0015 ±5V RANGE –0.6 +5V RANGE –0.0020 +10V RANGE –0.8 –0.0025 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06996-117 –1.00 10,000 20,000 C30O,0D0E0 40,000 50,000 60,000 06996-120 Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply Figure 20. Differential Nonlinearity Error vs. DAC Code, Single Supply 0.0025 0.005 AVDD = +24V 0.0020 +5V RANGE AVDD = 24V AVSS = –24V 0.0015 +10V RANGE ATAV S=S 2 =5 °0CV FSR) 0.003 TA = 25°C % % FSR) 00..00000150 ERROR ( –00..000011 ERROR (–0.00050 JSUTED –0.003 INL –0.0010 UNAD –0.005 –0.0015 AL ±10V RANGE OT –0.007 ±5V RANGE –0.0020 T +5V RANGE +10V RANGE –0.0025 –0.009 0 10,000 20,000 C30O,0D0E0 40,000 50,000 60,000 06996-118 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06996-221 Figure 18. Integral Nonlinearity Error vs. DAC Code, Single Supply Figure 21. Total Unadjusted Error vs. DAC Code, Dual Supply 1.0 0.030 AVDD = +24V 00..68 ATAV S=S 2 =5 °–C24V FSR) 0.025 ++51V0V R RAANNGGEE TAAAVV DS=SD 2 ==5 °02CV4V % 0.020 0.4 R ( R (LSB) 0.2 D ERRO 0.015 O 0 E 0.010 R T R S DNL E––00..42 NADJU 0.005 U –0.6 ±±150VV R RAANNGGEE TAL 0 O –0.8 +10V RANGE T –0.005 +5V RANGE –1.00 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06996-119 –0.0100 10,000 20,000 C30O,0D0E0 40,000 50,000 60,000 06996-122 Figure 19. Differential Nonlinearity Error vs. DAC Code, Dual Supply Figure 22. Total Unadjusted Error vs. DAC Code, Single Supply Rev. O | Page 18 of 44

Data Sheet AD5412/AD5422 0.0015 0.012 AVDD = +24V 0.0010 AVSS = –24V 0.010 AAVVDSSD== –+2244VV R) 0.008 OUTPUTUNLOADED S % FSR) 0.0005 OR (% F 00..000046 ROR ( 0 E ERR 0.002 R L INL E–0.0005 L-SCA–0.0020 L U –0.0010 +5V RANGE MAX INL +10V RANGE MAX INL F–0.004 ++±551VV0V RR RAAANNNGGGEEE ±+55VV RRAANNGGEE MMAINX I NINLL ±+1100VV RRAANNGGEE MMAINX I NINLL –0.006 ±10V RANGE ±5V RANGE MIN INL ±10V RANGE MIN INL –0.0015–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-121 –0.008–40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-100 Figure 23. Integral Nonlinearity Error vs. Temperature Figure 26. Full-Scale Error vs. Temperature 1.0 1.5 0.8 AAAVVLLDSS DR ==A N–+22G44EVVS 1.0 AAOVVUDSTSDP=U= T–+22U44NVVLOADED 0.6 B) 0.4 mV) 0.5 +10VRANGE LS 0.2 R ( RROR ( 0 ERRO 0 +5VRANGE NL E –0.2 FSET D F –0.5 –0.4 O –0.6 –1.0 –0.8 –1.0 –1.5 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-124 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-129 Figure 24. Differential Nonlinearity Error vs. Temperature Figure 27. Offset Error vs. Temperature 0.015 1.5 % FSR) 0.010 AAOVVUDSTSDP=U= T–+22U44NVVLOADED V) 1.0 AAOVVUDSTSDP=U= T–+22U44NVVLOADED ROR ( 0.005 OR (m 0.5 +10VRANGE D ER ERR DJSUTE 0 R ZERO 0 +5VRANGE NA–0.005 LA –0.5 U O AL +5V RANGE BIP OT–0.010 +10V RANGE –1.0 T ±5V RANGE ±10V RANGE –0.015 –1.5 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-101 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-130 Figure 25. Total Unadjusted Error vs. Temperature Figure 28. Bipolar Zero Error vs. Temperature Rev. O | Page 19 of 44

AD5412/AD5422 Data Sheet 0.014 1.0 AVDD = +24V 0.012 AVSS = –24V 0.8 TA = 25°C OUTPUT UNLOADED ±10V RANGE 0.010 0.6 0.008 R) 0.4 S % F 0.006 B) 0.2 N ERROR ( 00..0000024 ERROR (LS –0.20 AI L G N –0.4 –0.002 D –0.004 +5V RANGE –0.6 +10V RANGE –0.006 ±5V RANGE –0.8 ±10V RANGE –0.008 –1.0 –40 –20 0TEMPERA20TURE (°C4)0 60 80 06996-131 10 12 14 16AVDD/1|A8VSS| 2(V0) 22 24 26 28 06996-232 Figure 29. Gain Error vs. Temperature Figure 32. Differential Nonlinearity Error vs. AVDD/|AVSS| 1.3 0.0050 AAVVDSSD== –+2244VV R)0.0045 OUTPUTUNLOADED S 0.8 F0.0040 % V) R(0.0035 OR (m 0.3 ERRO0.0030 T±1A0 =V 2R5A°CNGE E ERR STED0.0025 L U A –0.2 J0.0020 C D S A RO- UN0.0015 ZE –0.7 ++51V0V R RAANNGGEE OTAL0.0010 ±5V RANGE T –1.2–40 –20 ±10V0 RTAENMGPEER2A0TURE (°4C0) 60 80 06996-102 0.0005010 12 14 16 AVD1D8/|AVS2S0|(V) 22 24 26 28 06996-033 Figure 30. Zero-Scale Error vs. Temperature Figure 33. Total Unadjusted Error vs. AVDD/|AVSS| 0.0015 2.5 TA=25°C TA = 25°C ±10V RANGE 0V TO 10V RANGE 0.0010 2.0 V) SR) 0.0005 GE ( % F LTA 1.5 ROR ( 0 M VO ER OO 1.0 NL –0.0005 DR I A E H 0.5 –0.0010 –0.0015 0 10 12 14 16 AVD1D8/|AVS2S0| (V) 22 24 26 28 06996-231 0 5 10 1R5LOAD (kΩ20) 25 30 35 06996-301 Figure 31. Integral Nonlinearity Error vs. AVDD/|AVSS| Figure 34.VOUT Headroom Rev. O | Page 20 of 44

Data Sheet AD5412/AD5422 0 12 AVDD = +24V –0.2 AVSS = –24V 8 ±10V RANGE M VOLTAGE (V) –––000...468 VOLTAGE (V) 04 TOAU T= P2U5°TC UNLOADED O –1.0 T O U R P OT –1.2 UT –4 O O F –1.4 –8 –1.6 TA = 25°C 0V TO 10V RANGE –1.80 5 10 1R5LOAD (kΩ20) 25 30 35 06996-302 –12–10 –5 0 5 TIM1E0 (µs) 15 20 25 30 06996-136 Figure 35.VOUT Footroom Figure 38. Full-Scale Positive Step 0.05 12 0.04 AVDD=+15V V) AVSS= –15V 8 E ( 0.03 TA=25°C N OUTPUT VOLTAG–000...0001012 ±10V RANGE PUT VOLTAGE (V) 04 OAA±T1AVVU0 SDT=VSD P 2 R U==5A ° T–+CN 22UG44NVVELOADED GE I–0.02 OUT –4 N A H–0.03 C –8 –0.04 –0.05–20 –15 –10SOUR–C5E/SINK 0CURREN5T (mA)10 15 20 06996-132 –12–10 –5 0 5 TIM1E0 (µs) 15 20 25 3006996-137 Figure 36. Source and Sink Capability of Output Amplifier, Figure 39. Full-Scale Negative Step Full-Scale Code Loaded 0.05 4 0.04 AVDD = +15V 2 E (V) 0.03 ATAV S=S 2 =5 °–C15V 0 G ±10V RANGE TA 0.02 mV) –2 T VOL 0.01 AGE ( –4 00xx870F0F0F TTOO 00xx78F0F0F0 U T TP 0 OL –6 U V N O–0.01 UT –8 GE I–0.02 UTP–10 CHAN–0.03 O–12 ATAAVV SD=SD 2 ==5 ° –+C2244VV –0.04 –14 ±10V RANGE –0.05–20 –15 –10SOUR–C5E/SINK 0CURREN5T (mA)10 15 20 06996-035 –16–1 1 3 5 TIME7 (µs) 9 11 13 15 06996-036 Figure 37. Source and Sink Capability of Output Amplifier, Figure 40. Digital-to-Analog Glitch Zero-Scale Loaded Rev. O | Page 21 of 44

AD5412/AD5422 Data Sheet 35 AVDD=+15V 30 AVSS= –15V TA=25°C 25 mV) 20 1 (UT VO15 10 AATAVV DS=SD 2 ==5 ° –+C2244VV 06996-037 05 CH1 5.0µV M 5.00ms LINE 1.8V 0 2 4 6 8 TIM1E0 (µs)12 14 16 18 20 06996-039 Figure 41. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) Figure 43. VOUT vs. Time on Power-Up 1 AATAVV DS=SD 2 ==5 ° –+C2244VV 06996-038 CH1 50.0µV M 5.00ms LINE 0V Figure 42. Peak-to-Peak Noise (100 kHz Bandwidth) Rev. O | Page 22 of 44

Data Sheet AD5412/AD5422 CURRENT OUTPUT 0.004 0.004 EINXTTEERRNNAALL R RSSEETT 0.002 A0AmVVDSASD T ==O –2 22444VmV/A0V RANGE EXTERNAL RSET, BOOST TRANSISTOR 0.002 INTERNAL RSET, BOOST TRANSISTOR 0 % FSR) 0 % FSR) –0.002 INL ERROR ( ––00..000042 INL ERROR ( ––00..000064 –0.006 AVDD = 24V –0.008 AVSS = –24V/0V –0.008 TA= 25°C RLOAD = 250Ω –0.0100 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 06996-106 –0.010–40 –20 0TEMPERA20TURE (°C4)0 60 80 06996-009 Figure 44. Integral Nonlinearity vs. Code Figure 47. Integral Nonlinearity vs. Temperature, Internal RSET 1.0 0.003 0.8 AATAVVDS=SD 2 =5= ° –2C244VV/0V 0.002 A0AmVVDSASD T ==O –2 22444VmV/A0V RANGE 0.6 RLOAD = 250Ω B) 0.4 SR) 0.001 ROR (LS 0.20 OR (% F 0 R R DNL E ––00..24 INL ER –0.001 EXTERNAL RSET –0.6 INTERNAL RSET –0.002 –0.8 EXTERNAL RSET, BOOST TRANSISTOR INTERNAL RSET, BOOST TRANSISTOR –1.0 –0.003 0 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 06996-007 –40 –20 0TEMPERA20TURE (°C4)0 60 80 06996-109 Figure 45. Differential Nonlinearity vs. Code Figure 48. Integral Nonlinearity vs. Temperature, External RSET 0.05 1.0 AVDD = 24V 0.03 0.8 AAVLLSS R =A –N2G4EVS/0V SR) INTERNAL AND EXTERNAL RSET F 0.01 0.6 % R ( –0.01 0.4 O B) R S R –0.03 L 0.2 TED E –0.05 AVDD = 24V ROR ( 0 UNADJUS ––00..0097 ARTAVLOS=AS 2D =5 =°–C 2245V0Ω/0V DNL ER ––00..42 OTAL –0.11 EINXTTEERRNNAALL R RSSEETT –0.6 T –0.13 EXTERNAL RSET, BOOST TRANSISTOR –0.8 INTERNAL RSET, BOOST TRANSISTOR –0.15 –1.0 0 10,000 20,000 30,0C0O0DE40,000 50,000 60,000 06996-008 –40 –20 0TEMPERA20TURE (°C4)0 60 80 06996-010 Figure 46. Total Unadjusted Error vs. Code Figure 49. Differential Nonlinearity vs. Temperature Rev. O | Page 23 of 44

AD5412/AD5422 Data Sheet 0.10 0.015 AAVVDSSD == –2244VV/0V T0mA A= 2T5O° C24mA RANGE SR) 0.05 0.010 AVSS = 0V F % ERROR ( –0.050 % FSR) 0.005 ADJUSTED –0.10 4mA TO 20mA INTERNAL RSET NL ERROR (–0.0050 UN –0.15 0mA TO 20mA INTERNAL RSET I AL 0mA TO 24mA INTERNAL RSET TOT –0.20 40mmAA TTOO 2200mmAA EEXXTTEERRNNAALL RRSSEETT –0.010 0mA TO 24mA EXTERNAL RSET –0.25 –0.015 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-013 10 15 20 AVD2D5 (V) 30 35 40 06996-011 Figure 50. Total Unadjusted Error vs. Temperature Figure 53. Integral Nonlinearity Error vs. AVDD, External RSET 0.10 0.020 0.05 AAVVDSSD == –2244VV/0V 0.015 TA = 25°C 0mA TO 24mA RANGE R) 0 0.010 AVSS = 0V FS R) R (% –0.05 % FS 0.005 RRO OR ( 0 FSET E –0.10 4mA TO 20mA INTERNAL RSET NL ERR–0.005 OF –0.15 00mmAA TTOO 2204mmAA IINNTTEERRNNAALL RRSSEETT I–0.010 –0.20 4mA TO 20mA EXTERNAL RSET 0mA TO 20mA EXTERNAL RSET –0.015 0mA TO 24mA EXTERNAL RSET –0.25 –0.020 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-017 10 15 20 AVD2D5 (V) 30 35 40 06996-014 Figure 51. Offset Error vs. Temperature Figure 54. Integral Nonlinearity Error vs. AVDD, Internal RSET 0.06 1.0 0.04 AAVVDSSD == –2244VV/0V 0.8 0TmA A= 2T5O° C24mA RANGE 0.6 AVSS = 0V 0.02 R) 0.4 S B) % F 0 LS 0.2 AIN ERROR ( ––00..0042 4mA TO 20mA INTERNAL RSET DNLERROR( –0.20 G 0mA TO 20mA INTERNAL RSET –0.4 –0.06 0mA TO 24mA INTERNAL RSET 4mA TO 20mA EXTERNAL RSET –0.6 –0.08 0mA TO 20mA EXTERNAL RSET –0.8 0mA TO 24mA EXTERNAL RSET –0.10 –1.0 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-018 10 15 20 AVD2D5(V) 30 35 40 06996-012 Figure 52. Gain Error vs. Temperature Figure 55. Differential Nonlinearity Error vs. AVDD, External RSET Rev. O | Page 24 of 44

Data Sheet AD5412/AD5422 1.0 2.5 AVDD = 15V 0.8 AVSS = 0V 0.6 0TmA A= 2T5O° C24mA RANGE 2.0 IROLUOTA =D 2=4 5m0A0Ω AVSS = 0V V) B) 0.4 GE( S A R (L 0.2 OLT1.5 RRO 0 M V E O NL –0.2 RO1.0 D D –0.4 A E H –0.6 0.5 –0.8 –1.0 0 10 15 20 AVD2D5 (V) 30 35 40 06996-015 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 06996-019 Figure 56. Differential Nonlinearity Error vs. AVDD, Internal RSET Figure 59. Compliance Voltage Headroom vs. Temperature 0.025 3.5 TA = 25°C AVDD = 24V R) 0.020 0mA TO 24mA RANGE 3.0 AVSS = 0V % FS 0.015 AVSS = 0V TRAL O=A 2D5 =°C 250Ω OR ( A) 2.5 D ERR 0.010 ENT(µ 2.0 JUSTE 0.005 CURR 1.5 D 0 T A U N P AL U–0.005 OUT 1.0 T TO–0.010 0.5 –0.01510 15 20 AVD2D5 (V) 30 35 40 06996-016 00 100 200 TIM3E0 0(µs) 400 500 600 06996-020 Figure 57. Total Unadjusted Error vs. AVDD, External RSET Figure 60. Output Current vs. Time on Power-Up 0.05 20 0.03 R) 10 S F 0.01 % TED ERROR(–––000...000531 T0mA A= T2O5° C24mA RANGE URRENT (µA) –100 AATRAVVL ODS=ASD 2D ==5 = ° 02C V245V0Ω L UNADJUS––00..0097 AVSS = 0V OUTPUT C ––3200 A T–0.11 O T –40 –0.13 –0.15 –50 10 15 20 AVD2D5(V) 30 35 40 06996-032 0 0.5 1.0 1.5 2.0TIM2E.5 (µs)3.0 3.5 4.0 4.5 5.0 06996-021 Figure 58. Total Unadjusted Error vs. AVDD, Internal RSET Figure 61. Output Current vs. Time on Output Enable Rev. O | Page 25 of 44

AD5412/AD5422 Data Sheet 70 25 60 TA = 25°C 20 AVDD = 24V ENT (pA) 4500 NT (mA) 15 ARVLOSASD = =0 V300Ω R E R R U 30 R C U LEAKAGE 1200 TAAV D=D 2 =5° 4C0V OUTPUT C 10 AVSS = 0V 5 OUTPUT DISABLED 0 –10 0 0 5 10 CO1M5PLIA2N0CE VO25LTAG3E0 (V) 35 40 45 06996-028 –1 0 1 2 T3IME (µ4s) 5 6 7 8 06996-134 Figure 62. Output Leakage Current vs. Compliance Voltage Figure 64. 4 mA to 20 mA Output Current Step 30 AAVVDSSD == 02V4V 00xx870F0F0F TTOO 00xx78F0F0F0 20 TA = 25°C RLOAD = 250Ω A) T (µ 10 N E R UR 0 C T U P T –10 U O –20 –30 06996-049 0 2 4 6 8 10 12 14 16 18 20 TIME (µs) Figure 63. Digital to Analog Glitch Rev. O | Page 26 of 44

Data Sheet AD5412/AD5422 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Gain Error For the DAC, relative accuracy, or INL, is a measure of the Gain error is a measure of the span error of the DAC. It is the maximum deviation, in LSBs, from a straight line passing deviation in slope of the DAC transfer characteristic from the through the endpoints of the DAC transfer function. A typical ideal expressed in % FSR. A plot of gain error vs. temperature INL vs. code plot can be seen in Figure 17. can be seen in Figure 29. Differential Nonlinearity (DNL) Gain Error Temperature Coefficient (TC) DNL is the difference between the measured change and the Gain error TC is a measure of the change in gain error with ideal 1 LSB change between any two adjacent codes. A specified changes in temperature. Gain error TC is expressed in ppm differential nonlinearity of ±1 LSB maximum ensures monoton- FSR/°C. icity. This DAC is guaranteed monotonic by design. A typical Total Unadjusted Error (TUE) DNL vs. code plot can be seen in Figure 19. TUE is a measure of the output error taking all the various Monotonicity errors into account, namely INL error, offset error, gain error, A DAC is monotonic if the output either increases or remains and output drift over supplies, temperature, and time. TUE is constant for increasing digital input code. The AD5412/AD5422 expressed in % FSR. are monotonic over their full operating temperature range. Current Loop Voltage Compliance Bipolar Zero Error The maximum voltage at the I pin for which the output OUT Bipolar zero error is the deviation of the analog output from the current is equal to the programmed value. ideal half-scale output of 0 V when the DAC register is loaded Power-On Glitch Energy with 0x8000 (straight binary coding) or 0x0000 (twos complement Power-on glitch energy is the impulse injected into the analog coding). A plot of bipolar zero error vs. temperature can be seen output when the AD5412/AD5422 is powered on. It is specified in Figure 28. as the area of the glitch in nV-sec. See Figure 43 and Figure 60. Bipolar Zero Temperature Coefficient (TC) Digital-to-Analog Glitch Impulse Bipolar zero TC is a measure of the change in the bipolar zero Digital-to-analog glitch impulse is the impulse injected into the error with a change in temperature. It is expressed in ppm FSR/°C. analog output when the input code in the DAC register changes Full-Scale Error state, but the output voltage remains constant. It is normally Full-scale error is a measure of the output error when full-scale specified as the area of the glitch in nV-sec and is measured code is loaded to the DAC register. Ideally, the output should be when the digital input code is changed by 1 LSB at the major full-scale − 1 LSB. Full-scale error is expressed in percent of carry transition (0x7FFF to 0x8000). See Figure 40 and full-scale range (% FSR). Figure 63. Negative Full-Scale Error/Zero-Scale Error Glitch Impulse Peak Amplitude Negative full-scale error is the error in the DAC output voltage Glitch impulse peak amplitude is the peak amplitude of the when 0x0000 (straight binary coding) or 0x8000 (twos complement impulse injected into the analog output when the input code in coding) is loaded to the DAC register. Ideally, the output voltage the DAC register changes state. It is specified as the amplitude should be negative full-scale − 1 LSB. A plot of zero-scale error of the glitch in millivolt and is measured when the digital input vs. temperature can be seen in Figure 30. code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 40 and Figure 63. Zero-Scale Temperature Coefficient (TC) Zero-scale TC is a measure of the change in zero-scale error Digital Feedthrough with a change in temperature. Zero-scale error TC is expressed Digital feedthrough is a measure of the impulse injected into in ppm FSR/°C. the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is Output Voltage Settling Time specified in nV-sec and measured with a full-scale code change Output voltage settling time is the amount of time it takes for the on the data bus. output to settle to a specified level for a full-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed of a voltage-output DAC is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is expressed in V/µs. Rev. O | Page 27 of 44

AD5412/AD5422 Data Sheet Power Supply Rejection Ratio (PSRR) where: PSRR indicates how the output of the DAC is affected by changes V is the maximum reference output measured over the REFmax in the power supply voltage. total temperature range. V is the minimum reference output measured over the total Voltage Reference TC REFmin temperature range. Voltage reference TC is a measure of the change in the reference V is the nominal reference output voltage, 5 V. output voltage with a change in temperature. The reference TC REFnom TempRange is the specified temperature range, −40°C to is calculated using the box method, which defines the TC as the +105°C. maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: Load Regulation Load regulation is the change in reference output voltage due to  V −V  TC= REFmax REFmin ×106 a specified change in load current. It is expressed in ppm/mA. V ×TempRange REFnom Rev. O | Page 28 of 44

Data Sheet AD5412/AD5422 THEORY OF OPERATION The AD5412/AD5422 are precision digital-to-current loop and voltage output converters designed to meet the requirements of AD5412/AD5422 +VSENSE industrial process control applications. They provide a high R1 precision, fully integrated, low cost single-chip solution for 12-/16-BIT RANGE VOUT DAC SCALING generating current loop and unipolar/bipolar voltage outputs. RLOAD –VSENSE Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA ttoo 2100 mV, Aan; tdh ±e 1v0o lVta; gae 1r0a%ng oevs earvraainlagbel eis a arvea 0il aVb lteo o5n V a, l±l v5o Vlt,a 0g eV REFIN –1VTO +3V VCM 06996-059 output ranges. The current and voltage outputs are available on Figure 67. Voltage Output separate pins, and only one is active at any time. The desired Voltage Output Amplifier output configuration is user selectable via the control register. The voltage output amplifier is capable of generating both unipolar ARCHITECTURE and bipolar output voltages. It is capable of driving a load of The DAC core architecture of the AD5412/AD5422 consists 1 kΩ in parallel with 1 µF (with an external compensation of two matched DAC sections. A simplified circuit diagram is capacitor) to GND. The source and sink capabilities of the shown in Figure 65. The four MSBs of the 12-/16-bit data-word output amplifier can be seen in Figure 37. The slew rate is are decoded to drive 15 switches, E1 to E15. Each of these switches 1 V/µs with a full-scale settling time of 25 µs maximum (10 V connects one of 15 matched resistors to either ground or the step). Figure 67 shows the voltage output driving a load, R , LOAD reference buffer output. The remaining 8/12 bits of the data- on top of a common-mode voltage (V ) of −1 V to +3 V. In CM word drive the S0 to S7/S11 switches of an 8-/12-bit voltage output module applications where a cable could possibly mode R-2R ladder network. become disconnected from +V , resulting in the amplifier SENSE VOUT loop being broken and possibly resulting in large destructive 2R 2R 2R 2R 2R 2R 2R voltages on VOUT, include an optional resistor (R1) between +V and V , as shown in Figure 67, of a value between S0 S1 S7/S11 E1 E2 E15 SENSE OUT 2 kΩ and 5 kΩ to ensure the amplifier loop is kept closed. If remote sensing of the load is not required, connect +V SENSE directly to V and connect −V directly to GND. When 8-12 BIT R-2R LADDER FOU15R EMQSUBAsL D SEECGOMDEENDT ISNTO 06996-057 cthhiasn rgeiansgo nra, niOtg UieTss r oenco tmhem veonltdaegde tohSuEaNttpS Etuhte, ao ugltiptucht bme adyi soacbcluedr. bFyo r Figure 65. DAC Ladder Structure setting the OUTEN bit of the control register to logic low before The voltage output from the DAC core is either converted to changing the output voltage range; this prevents a glitch from a current (see Figure 66) which is then mirrored to the supply occurring. rail so that the application simply sees a current source output Driving Large Capacitive Loads with respect to ground or it is buffered and scaled to output a The voltage output amplifier is capable of driving capacitive software selectable unipolar or bipolar voltage range (see loads of up to 1 µF with the addition of a nonpolarized 4 nF Figure 67). The current and voltage are output on separate compensation capacitor between the C and V pins. pins and cannot be output simultaneously. COMP OUT Without the compensation capacitor, up to 20 nF capacitive AVDD loads can be driven. R2 R3 T2 A2 12-/16-BIT T1 DAC A1 IOUT RSET 06996-058 Figure 66. Voltage-to-Current Conversion Circuitry Rev. O | Page 29 of 44

AD5412/AD5422 Data Sheet SERIAL INTERFACE CONTROLLER AD5412/ The AD5412/AD5422 are controlled over a versatile 3-wire AD54221 serial interface that operates at clock rates of up to 30 MHz. It is DATA OUT SDIN compatible with SPI, QSPI™, MICROWIRE, and DSP standards. SERIAL CLOCK SCLK Input Shift Register CONTROL OUT LATCH The input shift register is 24 bits wide. Data is loaded into the DATA IN SDO device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of SCLK. SDIN The input register consists of eight address bits and 16 data bits, AD5412/ as shown in Table 8. The 24-bit word is unconditionally latched AD54221 on the rising edge of the LATCH pin. Data continues to be clocked SCLK in irrespective of the state of LATCH. On the rising edge of LATCH LATCH, the data that is present in the input register is latched; in other words, the last 24 bits to be clocked in before the rising SDO edge of LATCH is the data that is latched. The timing diagram SDIN for this operation is shown in Figure 2. AD5412/ Table 8. Input Shift Register Format AD54221 MSB LSB SCLK D23 to D16 D15 to D0 LATCH Address byte Data-word SDO Table 9. Address Byte Functions A00d0d0r0e0s0s0 W ord FNuon ocptieornat ion (NOP) 1ADDITIONAL PINS OMITTED FOR CLARITY. 06996-060 00000001 Data register Figure 68. Daisy Chaining the AD5412/AD5422 00000010 Readback register value as per read address Daisy-Chain Operation (see Table 10) For systems that contain several devices, the SDO pin can be 01010101 Control register used to daisy-chain the devices together as shown in Figure 68. 01010110 Reset register This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Daisy-chain Standalone Operation mode is enabled by setting the DCEN bit of the control register The serial interface works with both a continuous and non- to 1. The first rising edge of SCLK that clocks in the MSB of the continuous serial clock. A continuous SCLK source can be used data-word marks the beginning of the write cycle. SCLK is only if LATCH is taken high after the correct number of data continuously applied to the input shift register. If more than bits have been clocked in. In gated clock mode, a burst clock 24 clock pulses are applied, the data ripples out of the shift containing the exact number of clock cycles must be used, and register and appears on the SDO line. This data is valid on the LATCH must be taken high after the final clock to latch the rising edge of SCLK, having been clocked out on the previous data. The rising edge of SCLK that clocks in the MSB of the falling SCLK edge. By connecting the SDO of the first device to data-word marks the beginning of the write cycle. Exactly 24 the SDIN input of the next device in the chain, a multidevice rising clock edges must be applied to SCLK before LATCH is interface is constructed. Each device in the system requires brought high. If LATCH is brought high before the 24th rising 24 clock pulses. Therefore, the total number of clock cycles SCLK edge, the data written is invalid. If more than 24 rising must equal 24 × n, where n is the total number of AD5412/ SCLK edges are applied before LATCH is brought high, the AD5422 devices in the chain. When the serial transfer to all input data is also invalid. devices is complete, LATCH is taken high. This latches the input data in each device in the daisy chain. The serial clock can be a continuous or a gated clock. A continuous SCLK source can be used only if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data (see Figure 4 for a timing diagram). Rev. O | Page 30 of 44

Data Sheet AD5412/AD5422 Readback Operation Voltage Output Readback mode is invoked by setting the address byte and read For a unipolar voltage output range, the output voltage can be address when writing to the input register (see Table 10 and expressed as Table 12). The next write to the AD5412/AD5422 should be a  D  NOP command, which clocks out the data from the previously VOUT =VREFIN×Gain2N addressed register as shown in Figure 3. For a bipolar voltage output range, the output voltage can be By default the SDO pin is disabled after having addressed the expressed as AD5412/AD5422 for a read operation; a rising edge on LATCH enables the SDO pin in anticipation of data being clocked out.  D  Gain×V V =V ×Gain − REFIN After the data has been clocked out on SDO, a rising edge on OUT REFIN 2N 2 LATCH disables (tristate) the SDO pin. To read back the data where: register, for example, implement the following sequence: D is the decimal equivalent of the code loaded to the DAC. 1. Write 0x020001 to the input register. This configures the N is the bit resolution of the DAC. part for read mode with the data register selected. V is the reference voltage applied at the REFIN pin. REFIN 2. Follow this with a second write: a NOP condition, which is Gain is an internal gain whose value depends on the output 0x000000. During this write, the data from the register is range selected by the user as shown in Table 11. clocked out on the SDO line. Table 11. Internal Gain Value Table 10. Read Address Decoding Output Range Gain Value Read Address Function +5 V 1 00 Read status register +10 V 2 01 Read data register ±5 V 2 10 Read control register ±10 V 4 POWER-ON STATE Current Output During power-on of the AD5412/AD5422, the power-on-reset For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA circuit ensures that all registers are loaded with zero-code. As current output ranges, the output current is respectively such, both outputs are disabled; that is, the V and I pins expressed as OUT OUT are in tristate. The +V pin is internally connected to ground SENSE 20mA through a 30 kΩ resistor. Therefore, if the VOUT and +VSENSE pins IOUT = 2N ×D are connected together, V is effectively clamped to ground OUT through a 30 kΩ resistor. Also upon power-on, internal calibration 24mA registers are read, and the data is applied to internal calibration IOUT = 2N ×D circuitry. For a reliable read operation, there must be sufficient 16mA tvhoelt DagVe on p tohwe eArV suDpD psluyp ppolyw werhineng tuhpe. rPeoawde ervineng tu ips ttrhieg gDeVred by IOUT = 2N ×D+4mA CC CC supply after the AVDD supply has reached at least 5 V ensures this. If where: DVCC and AVDD are powered up simultaneously, then the D is the decimal equivalent of the code loaded to the DAC. supplies should be powered up at a rate greater than, typically, N is the bit resolution of the DAC. 5000 V/sec. If the internal DV is enabled, the supplies should CC be powered up at a rate greater than, typically, 2000 V/sec. If this cannot be achieved, issue a reset command to the AD5412/ AD5422 after power-on; this performs a power-on-reset event, reading the calibration registers and ensures specified operation of the AD5412/AD5422. To ensure correct calibration and to allow the internal reference to settle to its correct trim value, 40 µs should be allowed after a successful power on reset. Table 12. Input Shift Register Contents for a Read Operation MSB LSB D23 D22 D21 D20 D19 D18 D17 D16 D15 to D2 D1 D0 0 0 0 0 0 0 1 0 X1 Read address 1 X = don’t care. Rev. O | Page 31 of 44

AD5412/AD5422 Data Sheet POWER-ON SOFTWARE RESET CONTROL REGISTER WRITE (ONE WRITE COMMAND) • SELECT RSET EXTERNAL/INTERNAL • SET THE REQUIRED RANGE • CONFIGURE THE SLEW RATE CONTROL (IF REQUIRED) • CONFIGURE DAISY CHAIN MODE (IF REQUIRED) • ENABLE THE OUTPUT CONTROL REGISTER WRITE • DISABLE OUTPUT DATA REGISTER WRITE • WRITE REQUIRED CODE TO DATA REGISTER RSET CONFIGURATION CHANGE RANGE CHANGE 06996-300 Figure 69. Programming Sequence to Write/Enable the Output Correctly Rev. O | Page 32 of 44

Data Sheet AD5412/AD5422 DATA REGISTER The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 13 and Table 14. Table 13. Programming the AD5412 Data Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 12-bit data-word X X X X Table 14. Programming the AD5422 Data Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16-bit data-word CONTROL REGISTER The control register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the control register is entered in the D15 to D0 positions, as shown in Table 15. The control register functions are shown in Table 16. Table 15. Programming the Control Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLRSEL OVRRNG REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0 Table 16. Control Register Functions Option Description CLRSEL See Table 22 for a description of the CLRSEL operation. OVRRNG Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section). REXT Setting this bit selects the external current setting resistor (see the AD5412/AD5422 Features section). When using an external current setting resistor, it is recommended to only set REXT when also setting the OUTEN bit. Alternately, REXT can be set before the OUTEN bit is set, but the range (see Table 17) must be changed on the write in which the output is enabled. See Figure 69 for best practice. OUTEN Output enable. This bit must be set to enable the outputs. The range bits select which output is functional. SR clock Digital slew rate control (see the AD5412/AD5422 Features section). SR step Digital slew rate control (see the AD5412/AD5422 Features section). SREN Digital slew rate control enable. DCEN Daisy chain enable. R2, R1, R0 Output range select (see Table 17). Table 17. Output Range Options R2 R1 R0 Output Range Selected 0 0 0 0 V to 5 V voltage range 0 0 1 0 V to 10 V voltage range 0 1 0 ±5 V voltage range 0 1 1 ±10 V voltage range 1 0 1 4 mA to 20 mA current range 1 1 0 0 mA to 20 mA current range 1 1 1 0 mA to 24 mA current range Rev. O | Page 33 of 44

AD5412/AD5422 Data Sheet RESET REGISTER The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is entered in the D0 position as shown in Table 18. The reset register options are shown in Table 18 and Table 19. Table 18. Programming the Reset Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reset Table 19. Reset Register Functions Option Description Reset Setting this bit performs a reset operation, restoring the AD5412/AD5422 to its power-on state. STATUS REGISTER The status register is a read-only register. The status register functionality is shown in Table 20 and Table 21. Table 20. Decoding the Status Register MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Reserved I fault Slew active Over temp OUT Table 21. Status Register Functions Option Description I Fault This bit is set if a fault is detected on the I pin. OUT OUT Slew Active This bit is set while the output value is slewing (slew rate control enabled). Over Temp This bit is set if the AD5412/AD5422 core temperature exceeds ~150°C. Rev. O | Page 34 of 44

Data Sheet AD5412/AD5422 AD5412/AD5422 FEATURES FAULT ALERT ASYNCHRONOUS CLEAR (CLEAR) The AD5412/AD5422 are equipped with a FAULT pin, which The CLEAR pin is an active high clear that allows the voltage is an open-drain output allowing several AD5412/AD5422 output to be cleared to either zero-scale code or midscale code, devices to be connected together to one pull-up resistor for user selectable via the CLEAR SELECT pin, or the CLRSEL bit global fault detection. The FAULT pin is forced active by one of of the control register, as described in Table 22. (The clear select the following fault scenarios: feature is a logical OR function of the CLEAR SELECT pin and the CLRSEL bit.) The current output clears to the bottom of its • The voltage at I attempts to rise above the compliance OUT programmed range. It is necessary for CLEAR to be high for a range, due to an open-loop circuit or insufficient power minimum amount of time to complete the operation (see Figure 2). supply voltage. The I current is controlled by a PMOS OUT When the CLEAR signal is returned low, the output remains at transistor and internal amplifier, as shown in Figure 66. the cleared value. The preclear value can be restored by pulsing The internal circuitry that develops the fault output avoids the LATCH signal low without clocking any data. A new value using a comparator with window limits because this would cannot be programmed until the CLEAR pin is returned low. require an actual output error before the FAULT output becomes active. Instead, the signal is generated when the Table 22. CLRSEL Options internal amplifier in the output stage has less than ~1 V Output Value of remaining drive capability (when the gate of the output CLRSEL Unipolar Output Range Bipolar Output Range PMOS transistor nearly reaches ground). Thus, the FAULT 0 0 V 0 V output activates slightly before the compliance limit is 1 Midscale Zero scale reached. Because the comparison is made within the In addition to defining the output value for a clear operation, feedback loop of the output amplifier, the output accuracy the CLRSEL bit and CLEAR SELECT pin also define the default is maintained by its open-loop gain, and an output error output value. During selection of a new voltage range, the does not occur before the FAULT output becomes active. output value is as defined in Table 22. To avoid glitches on the • If the core temperature of the AD5412/AD5422 exceeds output, it is recommended that, before changing voltage ranges, approximately 150°C. the user disable the output by setting the OUTEN bit of the The I fault and over temp bits of the status register are used control register to logic low. When OUTEN is set to logic high, OUT in conjunction with the FAULT pin to inform the user which the output goes to the default value as defined by CLRSEL and CLEAR SELECT. one of the fault conditions caused the FAULT pin to be asserted (see Table 20 and Table 21). INTERNAL REFERENCE VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION The AD5412/AD5422 contain an integrated 5 V voltage reference with initial accuracy of ±5 mV maximum and a Under normal operation, the voltage output sinks/sources temperature drift coefficient of ±10 ppm/°C maximum. The 10 mA. The maximum current that the voltage output delivers reference voltage is buffered and externally available for use is ~20 mA; this is the short-circuit current. elsewhere within the system. See Figure 16 for a load regulation VOLTAGE OUTPUT OVERRANGE graph of the integrated reference. An overrange facility is provided on the voltage output. When EXTERNAL CURRENT SETTING RESISTOR enabled via the control register, the selected output range is R is an internal sense resistor as part of the voltage-to-current overranged by, typically, 10%. SET conversion circuitry (see Figure 66). The stability of the output VOLTAGE OUTPUT FORCE-SENSE current over temperature is dependent on the stability of the The +VSENSE and −VSENSE pins are provided to facilitate remote value of RSET. As a method of improving the stability of the sensing of the load connected to the voltage output. If the load output current over temperature, an external precision 15 kΩ is connected at the end of a long or high impedance cable, low drift resistor can be connected to the RSET pin of the sensing the voltage at the load allows the output amplifier to AD5412/AD5422 to be used instead of the internal resistor compensate and ensure that the correct voltage is applied across (RSET). The external resistor is selected via the control register the load. This function is limited only by the available power (see Table 15). supply headroom. Rev. O | Page 35 of 44

AD5412/AD5422 Data Sheet DIGITAL POWER SUPPLY AVDD C2 By default, the DV pin accepts a power supply of 2.7 V to CC CAP2 p5.o5w Ve.r A sultperpnlya tciavnel yb,e v oiau tthpue tD oVnC tCh SeE DLVECCCT p pinin f,o ar nu sinet aesr naa dl i4g.i5t aVl HAORTU TMPOUDTEM C1 06996-051 power supply for other devices in the system or as a termination Figure 71. Coupling HART Signal for pull-up resistors. This facility offers the advantage of not In determining the absolute values of the capacitors, ensure that having to bring a digital supply across an isolation barrier. The the FSK output from the modem is passed undistorted. Thus, internal power supply is enabled by leaving the DV SELECT CC the bandwidth presented to the modem output signal must pass pin unconnected. To disable the internal supply, tie DV CC 1200 Hz and 2200 Hz frequencies. The recommended values SELECT to 0 V. DV is capable of supplying up to 5 mA of CC are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew current (for a load regulation graph, see Figure 10). rate of the output is necessary to meet the analog rate of change EXTERNAL BOOST FUNCTION requirements for HART. The addition of an external boost transistor, as shown in DIGITAL SLEW RATE CONTROL Figure 70, reduces the power dissipated in the AD5412/AD5422 The slew rate control feature of the AD5412/AD5422 allows the by reducing the current flowing in the on-chip output transistor user to control the rate at which the output voltage or current (dividing it by the current gain of the external circuit). A discrete changes. With the slew rate control feature disabled, the output NPN transistor with a breakdown voltage, BV , greater than CEO changes at a rate limited by the output drive circuitry and the 40 V can be used. The external boost capability has been developed attached load. See Figure 64 for current output step and for users who may wish to use the AD5412/AD5422 at the Figure 38 for voltage output step. To reduce the slew rate, enable extremes of the supply voltage, load current, and temperature the slew rate control feature. With the feature enabled via the range. The boost transistor can also be used to reduce the SREN bit of the control register (see Table 15), the output, instead amount of temperature-induced drift in the part. This minimizes of slewing directly between two values, steps digitally at a rate the temperature-induced drift of the on-chip voltage reference, defined by two parameters accessible via the control register, as which improves on drift and linearity. shown in Table 15. The parameters are set by the SR clock and SR step bits. SR clock defines the rate at which the digital slew is BOOST MJD31C updated; SR step defines by how much the output value changes AD5412/ OR AD5422 PBSS8110Z at each update. Both parameters together define the rate of IOUT change of the output voltage or current. Table 23 and Table 24 outline the range of values for both the SR clock and SR step 1kΩ 0.022µF RLOAD 06996-061 praamrapm teimteress. oFfi g1u0r me 7s,2 5 s0h mows,s atnhde o1u0t0p muts c. urrent changing for Figure 70. External Boost Configuration Table 23. Slew Rate Step Size Options EXTERNAL COMPENSATION CAPACITOR SR Step AD5412 Step Size (LSB) AD5422 Step Size (LSB) The voltage output can ordinarily drive capacitive loads of up to 000 1/16 1 20 nF; if there is a requirement to drive greater capacitive loads, 001 1/8 2 of up to 1 µF, an external compensation capacitor can be con- 010 1/4 4 nected between the CCOMP and VOUT pins. The addition of the 011 1/2 8 capacitor keeps the output voltage stable but also reduces the 100 1 16 bandwidth and increases the settling time of the voltage output. 101 2 32 HART COMMUNICATION 110 4 64 111 8 128 The AD5412/AD5422 (LFCSP version only) contain a CAP2 pin, into which a HART signal can be coupled. The HART signal appears on the current output if the output is enabled. To achieve a 1 mA peak-to-peak current, the signal amplitude at the CAP2 pin must be 48 mV peak-to-peak. Assuming that the modem output amplitude is 500 mV peak-to-peak, its output must be attenuated by 500/48 = 10.42. If this voltage is used, the current output should meet the HART amplitude specifications. Figure 71 shows the recommended circuit for attenuating and coupling in the HART signal. Rev. O | Page 36 of 44

Data Sheet AD5412/AD5422 25 Table 24. Slew Rate Update Clock Options TA = 25°C SR Clock Update Clock Frequency (Hz) AVDD = 24V RLOAD = 300Ω 0000 257,730 20 0001 198,410 mA) 0010 152,440 T ( N15 E 0011 131,580 R R U 0100 115,740 C 0101 69,440 PUT 10 T 0110 37,590 OU 0111 25,770 5 10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5 11000001 2106,,106300 0 5100m0ms sR RAAMMPP, ,S SRR C CLLOOCCKK = = 0 0xxA8, ,S SRR S STTEEPP = = 0 0xx75 06996-139 1010 10,290 –10 0 10 20 30 40 50 60 70 80 90 100 110 1011 8280 TIME (ms) Figure 72. Output Current Slewing Under Control of the Digital Slew Rate 1100 6900 Control Feature 1101 5530 I FILTERING CAPACITORS (LFCSP PACKAGE) 1110 4240 OUT 1111 3300 Capacitors can be placed between CAP1 and AV , and CAP2 DD and AV , as shown in Figure 73. DD The time it takes for the output to slew over a given output AVDD range can be expressed as follows: C1 C2 SlewTime= AVDD CAP1 OutputChange (1) AD5412/ AD5422 CAP2 StepSize×UpdateClockFrequency×LSBSize wSlhewer eT:i me is expressed in seconds. GND IOUT 06996-062 Output Change is expressed in amps for I or volts for V . Figure 73. IOUT Filtering Capacitors OUT OUT The CAP1 and CAP2 pins are available only on the LFCSP When the slew rate control feature is enabled, all output package. The capacitors form a filter on the current output changes change at the programmed slew rate; if the CLEAR circuitry, as shown in Figure 74, reducing the bandwidth and pin is asserted, the output slews to the zero-scale value at the the slew rate of the output current. Figure 75 shows the effect programmed slew rate. The output can be halted at its current the capacitors have on the slew rate of the output current. To value with a write to the control register. To avoid halting the achieve significant reductions in the rate of change, very large output slew, the slew active bit (see Table 20) can be read to capacitor values are required, which may not be suitable in check that the slew has completed before writing to any of the some applications. In this case, the digital slew rate control AD5410/AD5420 registers. The update clock frequency for any feature can be used. The capacitors can be used in conjunction given value is the same for all output ranges. The step size, with the digital slew rate control feature as a means of however, varies across output ranges for a given value of step smoothing out the steps caused by the digital code increments, size because the LSB size is different for each output range. as shown in Figure 76. Table 25 shows the range of programmable slew times for a full- scale change on any of the output ranges. The values in Table 25 were obtained using Equation 1. The digital slew rate control feature results in a staircase formation on the current output, as shown in Figure 76. This figure also shows how the staircase can be removed by connecting capacitors to the CAP1 and CAP2 pins, as described in the I Filtering Capacitors (LFCSP Package) section. OUT Rev. O | Page 37 of 44

AD5412/AD5422 Data Sheet C1 6.8 C2 6.7 TAAV D=D 2 =5° 2C4V RLOAD = 300Ω CAP1 CAP2 AVDD A)6.6 m T ( N E6.5 4kΩ 40Ω R R BOOST CU T 6.4 U P T OU6.3 DAC 12.5kΩ IOUT NO EXTERNAL CAPS R1 06996-063 66..12–1 0 1 2 T3IME (m4s)1100nnFF5 OONN CCAA6PP12 7 806996-043 Figure 76. Smoothing Out the Steps Caused by the Digital Slew Figure 74. IOUT Filter Circuitry Rate Control Feature 25 20 A) m T( TA=25°C EN15 AVDD=24V RR RLOAD=300Ω U C UT10 P UT NOCAPACITOR O 10nFONCAP1 5 10nFONCAP2 47nFONCAP1 0 47nFONCAP2 06996-142 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 TIME(ms) Figure 75. Slew Controlled 4 mA to 20 mA Output Current Step Using External Capacitors on the CAP1 and CAP2 Pins Table 25. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range Step Size (LSB) Update Clock Frequency (Hz) 1 2 4 8 16 32 64 128 257,730 0.25 0.13 0.06 0.03 0.016 0.008 0.004 0.0020 198,410 0.33 0.17 0.08 0.04 0.021 0.010 0.005 0.0026 152,440 0.43 0.21 0.11 0.05 0.027 0.013 0.007 0.0034 131,580 0.50 0.25 0.12 0.06 0.031 0.016 0.008 0.0039 115,740 0.57 0.28 0.14 0.07 0.035 0.018 0.009 0.0044 69,440 0.9 0.47 0.24 0.12 0.06 0.03 0.015 0.007 37,590 1.7 0.87 0.44 0.22 0.11 0.05 0.03 0.014 25,770 2.5 1.3 0.64 0.32 0.16 0.08 0.04 0.020 20,160 3.3 1.6 0.81 0.41 0.20 0.10 0.05 0.025 16,030 4.1 2.0 1.0 0.51 0.26 0.13 0.06 0.03 10,290 6.4 3.2 1.6 0.80 0.40 0.20 0.10 0.05 8280 7.9 4.0 2.0 1.0 0.49 0.25 0.12 0.06 6900 9.5 4.8 2.4 1.2 0.59 0.30 0.15 0.07 5530 12 5.9 3.0 1.5 0.74 0.37 0.19 0.09 4240 15 7.7 3.9 1.9 0.97 0.48 0.24 0.12 3300 20 9.9 5.0 2.5 1.24 0.62 0.31 0.16 Rev. O | Page 38 of 44

Data Sheet AD5412/AD5422 APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT RANGES ON AVDD THE SAME TERMINAL The current and voltage output pins can be connected together. AVDD A buffer amplifier is required, however, to prevent a current leakage path through an internal 30 kΩ resistor on the +VSENSE pin AADD55441222/ IOUT RP when the device is in current output mode. In current mode, tmhoe dVeO, UtTh ep iInO UiTs phiingh is i mhipgehd iamnpcee;d wanhceer eaansd i nd oveoslt nagoet aofufetpcut tt he GND AVSS RLOAD 06996-064 voltage output. It is important that the external R be used in SET AVSS this configuration, as depicted in Figure 77. Figure 78. Output Transient Voltage Protection GALVANICALLY ISOLATED INTERFACE IOUT AD5412/ AD5422 OP07/OP184 In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being +VSENSE controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The VOUT IOUT/VOUT iCoupler® products from Analog Devices, Inc., provide voltage isolation in excess of 2.5 kV. The serial loading structure of the –VSENSE RSET AD5412/AD5422 makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum. 06996-071 FAiDgu5r4e2 729 u sshinogw as na A4-DchuaMnn1e4l0 i0s.o Flaotre dfu irnttheerrfa icnef otorm thaeti AonD, 5v4is1it2 / Figure 77. IOUT and VOUT Connected Together www.analog.com/isolators. DRIVING INDUCTIVE LOADS CONTROLLER ADuM14001 When driving inductive or poorly defined loads, connect a SERIAL VIA VOA TO 0.01 µF capacitor between IOUT and GND. This ensures stability CLOCK IN ENCODE DECODE SCLK with loads above 50 mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower DASTAE ROIAUTL VIB ENCODE DECODE VOB TSODIN settling. The digital slew rate control feature may also prove useful in this situation. SYNC OUT VIC ENCODE DECODE VOC TLOATCH TRANSIENT VOLTAGE PROTECTION The AD5412/AD5422 contain ESD protection diodes that CONTOROUTL VID ENCODE DECODE VOD TCOLEAR prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher htriagnhs iveonlttsa.g Te ot rparnostieecntt st,h eex AteDrn5a4l1 p2o/AwDer5 d4i2o2d ferso amn de xac seussrigvee ly 1ADDITIONAL PINS OMITTED FOR CLARITY. 06996-065 current limiting resistor are required, as shown in Figure 78. Figure 79. Isolated Interface The constraint on the resistor value is that, during normal MICROPROCESSOR INTERFACING operation, the output level at I must remain within its voltage OUT compliance limit of AV – 2.5 V, and the two protection diodes Microprocessor interfacing to the AD5412/AD5422 is via a serial DD and resistor must have appropriate power ratings. Further bus that uses a protocol compatible with microcontrollers and protection can be provided with transient voltage suppressors or DSP processors. The communications channel is a 3-wire transorbs; these are available as both unidirectional suppressors minimum interface consisting of a clock signal, a data signal, (protect against positive high voltage transients) and bidirectional and a latch signal. The AD5412/AD5422 require a 24-bit data- suppressors (protect against both positive and negative high word with data valid on the rising edge of SCLK. voltage transients) and are available in a wide range of standoff For all interfaces, the DAC output update is initiated on the rising and breakdown voltage ratings. It is recommended that all field edge of LATCH. The contents of the registers can be read using connected nodes be protected. the readback function. Rev. O | Page 39 of 44

AD5412/AD5422 Data Sheet LAYOUT GUIDELINES maximum AV while driving the maximum current (24 mA) DD directly to ground. In this case, control the ambient temperature In any circuit where accuracy is important, careful consideration of or reduce AV . The conditions depend on the device package. the power supply and ground return layout helps to ensure the DD rated performance. Design the printed circuit board (PCB) on At the ambient temperature of 85°C, the 24-lead TSSOP package which the AD5412/AD5422 is mounted so that the analog and can dissipate 1.14 mW, and the 40-lead LFCSP package can digital sections are separated and confined to certain areas of the dissipate 1.21 W. board. If the AD5412/AD5422 is in a system where multiple To ensure that the junction temperature does not exceed 125°C devices require an analog ground-to-digital ground connection, while driving the maximum current of 24 mA directly into ground make the connection at one point only. Establish the star ground (also adding an on-chip current of 3 mA), reduce AV from the DD point as close as possible to the device. maximum rating to ensure that the package is not required to The AD5412/AD5422 should have ample supply bypassing of dissipate more power than previously stated (see Table 26, 10 µF in parallel with 0.1 µF on each supply located as close to Figure 80, and Figure 81). the package as possible, ideally right up against the device. The 2.5 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and low effective LFCSP 2.0 series inductance (ESI), such as the common ceramic types, W) which provide a low impedance path to ground at high frequencies N ( O to handle transient currents due to internal logic switching. TI1.5 A P TSSOP The power supply lines of the AD5412/AD5422 should use as SSI DI large a trace as possible to provide low impedance paths and reduce R 1.0 E W the effects of glitches on the power supply line. Fast switching O P signals such as clocks should be shielded with a digital ground 0.5 to avoid radiating noise to other parts of the board. Never run these naneadr SthCeL rKef elirneensc eh einlppsu rtse.d Au cger ocuronsds tlianlke rboeuttweede bne ttwheemen (tthhei sS Dis InNot 0 06996-066 40 45 50 55 60 65 70 75 80 85 required on a multilayer board that has a separate ground plane, AMBIENT TEMPERATURE (°C) but separating the lines helps). It is essential to minimize noise Figure 80. Maximum Power Dissipation vs. Ambient Temperature on the REFIN line because it couples through to the DAC output. 45 Avoid crossover of digital and analog signals. Traces on 43 LFCSP opposite sides of the PCB should run at right angles to each 41 other. This reduces the effects of feed through the board. A V)39 mwiitchr oas dtroipu btelec-hsnidiqedu eb iosa brdy .f Ianr tthheis b teescth bnuiqt uneo,t t ahlew caoyms ppoosnseibnlte AGE (37 TSSOP T L side of the board is dedicated to the ground plane, and signal O35 V Y traces are placed on the solder side. L33 P P THERMAL AND SUPPLY CONSIDERATIONS SU31 The AD5412/AD5422 are designed to operate at a maximum 29 jnuontc btieo onp teermatpeedr autnudree ro cf o1n2d5i°tCio. nIts itsh iamt cpaourstea ntht eth jautn tchteio dne vices 2257 06996-067 25 35 45 55 65 75 85 temperature to exceed this value. Excessive junction tempera- AMBIENT TEMPERATURE (°C) ture can occur if the AD5412/AD5422 are operated from the Figure 81. Maximum Supply Voltage vs. Ambient Temperature Rev. O | Page 40 of 44

Data Sheet AD5412/AD5422 Table 26. Thermal and Supply Considerations for Each Package Considerations TSSOP LFCSP Maximum Allowed Power Dissipation When Operating at an T max−T 125−85 T max−T 125−85 Ambient Temperature of 85°C J A = =1.14W J A = =1.21W θ 35 θ 33 JA JA Maximum Allowed Ambient Temperature When Operating from T max−P ×θ = T max−P ×θ = J D JA J D JA a Supply of 40 V and Driving 24 mA Directly to Ground 125−(40×0.028)×35=86°C 125−(40×0.028)×33=88°C MTeamxipmeuramtu Arlelo owf e8d5 °SCu panpdly DVorilvtaingge W24h menA O Dpiereracttilnyg t oat G arno Aunmdb ient TJ max−TA = 125−85 =40V TJ max−TA = 125−85 =43V AI ×θ 0.028×35 AI ×θ 0.028×33 DD JA DD JA INDUSTRIAL ANALOG OUTPUT MODULE which both the voltage output and current output are available— one at a time—on one pin, thus reducing the number of screw Many industrial control applications have requirements for connections required. There is no conflict with tying the two output accurately controlled current and voltage output signals. The pins together because only the voltage output or the current output AD5412/AD5422 are ideal for such applications. Figure 83 shows can be enabled at any one time. For further information on this the AD5412/AD5422 in a circuit design for an output module, circuit, see Circuit Note CN0278, Complete 4 mA to 20 mA specifically for use in an industrial control application. The design HART Solution with Additional Voltage Output Capability. provides for a current or voltage output. The module is powered from a field supply of 24 V. This supplies AV directly. An inverting The design provides for a HART-enabled current output, with DD buck regulator generates the negative supply for AV . For transient the HART capability provided by the AD5700/AD5700-1 HART SS overvoltage protection, transient voltage suppressors (TVS) are modem, the industry’s lowest power and smallest footprint HART- placed on all field accessible connections. A 24 V volt TVS is placed compliant IC modem. For additional space-savings, the AD5700-1 on each I , V , +V , and −V connection, and a 36 V TVS offers a 0.5% precision internal oscillator. The HART_OUT signal OUT OUT SENSE SENSE is placed on the field supply input. For added protection, clamping from the AD5700 is attenuated and ac-coupled into the RSET pin diodes are connected from the I , V , +V , and −V of the AD5412/AD5422. Because the RSET pin is used to couple OUT OUT SENSE SENSE pins to the AV and AV power supply pins. If remote voltage load the HART signal into the AD5412/AD5422, either the TSSOP or DD SS sensing is not required, the +V pin can be directly connected to LFCSP package option can be used for this configuration. It should SENSE the V pin and the –V pin can be connected to GND. be noted however, that since the TSSOP package does not have OUT SENSE a CAP1 pin, C1 (see Figure 82) cannot be inserted in this case. Isolation between the AD5412/AD5422 and the backplane While the TSSOP equivalent circuit (as in Figure 82 but without circuitry is provided with ADuM1400 and ADuM1200 iCoupler C1 in place) still passes the HART Communication Foundation digital isolators; further information on iCoupler products is physical layer specs, the results with C1 in place are superior to available at www.analog.com/isolators. The internally generated those without C1 in place. Further information on an alternative digital power supply of the AD5412/AD5422 powers the field configuration, whereby the HART signal is coupled into the CAP2 side of the digital isolaters, removing the need to generate a digital pin can be found in Application Note AN-1065. This is based power supply on the field side of the isolation barrier. The AD5412/ on the AD5410/AD5420 but can also be applied to the AD5412/ AD5422 digital supply output supplies up to 5 mA, which is more AD5422. Use of either configuration results in the AD5700 HART than enough to supply the 2.8 mA requirements of the ADuM1400 modem output modulating the 4 mA to 20 mA analog current and ADuM1200 operating at a logic signal frequency of up to without affecting the dc level of the current. This circuit adheres 1 MHz. To reduce the number of isolators required, nonessential to the HART physical layer specifications as defined by the signals such as CLEAR can be connected to GND. FAULT and HART Communication Foundation. SDO can be left unconnected, reducing the isolation requirements to just three signals. See Circuit Note CN0321 for an example of The module is powered from a field supply of ±10.8 V to ±26.4 V. a built and tested circuit of a fully isolated, single channel voltage This supplies AVDD/AVSS directly. For transient overvoltage and 4 mA to 20 mA output with HART. protection, transient voltage suppressors (TVS) are placed on both the I and field supply connections. A 24 V TVS is placed INDUSTRIAL HART CAPABLE ANALOG OUTPUT OUT on the I connection, and a 36 V TVS is placed on the field APPLICATION OUT supply input(s). For added protection, clamping diodes are Many industrial control applications have requirements for connected from the I pin to the AV and GND power OUT DD accurately controlled current output signals, and the AD5412/ supply pins. A 10 kΩ current limiting resistor is also placed in AD5422 are ideal for such applications. Figure 82 shows the series with the positive terminal of the +V buffer input. This is SENSE AD5412/AD5422 in a circuit design for a HART-enabled output to limit the current to an acceptable level during a transient event. module, specifically for use in an industrial control application in Rev. O | Page 41 of 44

AD5412/AD5422 Data Sheet 10µF 10µF 10.8V 2.7V D4 TO 5.T5OV 0.1µF C3 0.1µF 26.4V 10kΩ DVCC CAP1 AVDD FAULT REFIN 0.1µF CLEAR REFOUT D2 INDTIEGRITFAALCE LATCH IOUT RP 4mA TO 20mA SCLK CURRENTLOOP SDIN AD5412/ D1 D3 UART SDO AD5422 RL INTERFACE OP1177 500Ω 0V +VSENSE RP TO RSET 10kΩ –26.4V 10µF AVSS VOUT AVSS 0.1µF –VSENSE CAP2 GND 0.1µF C1 C2 VCC 2.2nF 22nF TXD HART_OUT RXD AVDD REF RTS 1µF AD5700 1.2MΩ 300pF 150kΩ CD ADC_IP AGND DGND 1.2MΩ 150pF 06996-079 Figure 82. AD5412/AD5422 in HART Configuration –15V INVERTING 24V FIELD SUPPLY BUCK + 10µF REGULATOR SMAJ36CA 36V FIELD GROUND BACKPLANE 0.1µF SUPPLY E 0.1µF ADuM1400 0.1µF 4nF BACKPLANE INTERFAC MICROCONTROLLER DIGITALDIGITALOUTPUTSINPUTS GVVVVGGVVVVNDOODIIIINNNCACDBDDABDDD21211GGGVVVVVVNNVNDDVVOOOODDDEDDIIACDB2222AB11 10kCCSFSLSΩLACALDDSEEULTIODENAAKCLVLRTRHEC CCSTELGEDNCVDTCCAADDA55V44S12S221/ARVEDFDOUTC+C–VVOSSMRVEEPIEOONNFSSUUIEETTN 184Ω.7k1Ω00Ω 2S4MVA+I+–OJVVVU2SSOT4EEUCNNTASSEE ADuM1200 0.1µF + 10µF –15V 0.1µF 06996-068 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 83. AD5412/AD5422 in an Industrial Analog Output Module Application Rev. O | Page 42 of 44

Data Sheet AD5412/AD5422 OUTLINE DIMENSIONS 7.90 5.02 7.80 5.00 7.70 4.95 24 13 4.50 EXPOSED 3.25 4.40 PAD 3.20 4.30 (Pins Up) 3.15 6.40 BSC 1 12 TOP VIEW BOTTOM VIEW FOR PROPER CONNECTION OF 1.05 THE EXPOSED PAD, REFER TO 1.20 MAX 1.00 THE PIN CONFIGURATION AND 8° FUNCTION DESCRIPTIONS 0.80 0° SECTION OF THIS DATA SHEET. 0.15 0.20 0.05 SPELAATNIENG B0.S6C5 00..3109 0.09 00..7650 0.10 COPLANARITY 0.45 COMPLIANTTO JEDEC STANDARDS MO-153-ADT 061708-A Figure 84. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters 6.10 0.60 MAX 6.00 SQ 5.90 0.60 MAX PIN 1 INDICATOR 3031 401 PIN 1 5.85 0.50 EXPOSED 4.25 INDICATOR 5.75 SQ BSC PAD 4.10 SQ 5.65 (BOTTOM VIEW) 3.95 21 10 20 11 TOP VIEW 00..5400 0.20 MIN 4.50 REF 0.30 12° MAX 0.80 MAX FOR PROPER CONNECTION OF 1.00 0.65 TYP THE EXPOSED PAD, REFER TO 0.85 0.05 MAX THE PIN CONFIGURATION AND 0.80 FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. SEATING 0.30 COPL0A.0N8ARITY PLANE 00C..21O38MPLIANTTO0 J.2E0D REECF STANDARDS MO-220-VJJD-2 06-01-2012-D Figure 85. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body and 0.85 mm Package Height (CP-40-1) Dimensions shown in millimeters Rev. O | Page 43 of 44

AD5412/AD5422 Data Sheet ORDERING GUIDE Resolution I TUE V TUE Package OUT OUT Model1 (Bits) (% FSR max) (% FSR max) Temperature Range Package Description Option AD5412AREZ 12 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24 AD5412AREZ-REEL7 12 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24 AD5412ACPZ-REEL 12 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1 AD5412ACPZ-REEL7 12 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1 AD5422AREZ 16 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24 AD5422AREZ-REEL 16 0.5 0.3 −40°C to +105°C 24-Lead TSSOP_EP RE-24 AD5422BREZ 16 0.3 0.1 −40°C to +105°C 24-Lead TSSOP_EP RE-24 AD5422BREZ-REEL 16 0.3 0.1 −40°C to +105°C 24-Lead TSSOP_EP RE-24 AD5422ACPZ-REEL 16 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1 AD5422ACPZ-REEL7 16 0.5 0.3 −40°C to +105°C 40-Lead LFCSP CP-40-1 AD5422BCPZ-REEL 16 0.3 0.1 −40°C to +105°C 40-Lead LFCSP CP-40-1 AD5422BCPZ-REEL7 16 0.3 0.1 −40°C to +105°C 40-Lead LFCSP CP-40-1 EVAL-AD5422EBZ AD5422 Evaluation Board EVAL-AD5422LFEBZ AD5422 LFCSP Evaluation Board 1 Z = RoHS Compliant Part. ©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06996-0-10/17(O) Rev. O | Page 44 of 44

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5422EBZ EVAL-AD5422LFEBZ AD5412ACPZ-REEL AD5412AREZ-REEL7 AD5412ACPZ-REEL7 AD5422ACPZ-REEL7 AD5412AREZ AD5422BCPZ-REEL7 AD5422AREZ AD5422BREZ-REEL AD5422ACPZ-REEL AD5422AREZ-REEL AD5422BCPZ-REEL AD5422BREZ