Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Serial Interface Data Sheet AD5415 FEATURES GENERAL DESCRIPTION 10 MHz multiplying bandwidth The AD54151 is a CMOS, 12-bit, dual-channel, current output On-chip 4-quadrant resistors allow flexible output ranges digital-to-analog converter (DAC). This device operates from a INL of ±1 LSB 2.5 V to 5.5 V power supply, making it suited to battery-powered 24-lead TSSOP package applications and other applications. As a result of being manufac- 2.5 V to 5.5 V supply operation tured on a CMOS submicron process, this device offers excellent ±10 V reference input 4-quadrant multiplication characteristics with large signal 50 MHz serial interface multiplying bandwidths of 10 MHz. 2.47 MSPS update rate Extended temperature range: −40°C to 125°C The applied external reference input voltage (V ) determines REF 4-quadrant multiplication the full-scale output current. An integrated feedback resistor (R ) FB Power-on reset provides temperature tracking and full-scale voltage output when 0.5 µA typical current consumption combined with an external current to voltage precision amplifier. Guaranteed monotonic In addition, this device contains the 4-quadrant resistors necessary Daisy-chain mode for bipolar operation and other configuration modes. Readback function APPLICATIONS This DAC uses a double-buffered, 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP Portable battery-powered applications interface standards. In addition, a serial data out pin (SDO) allows Waveform generators daisy-chaining when multiple packages are used. Data readback Analog processing Instrumentation applications allows the user to read the contents of the DAC register via the Programmable amplifiers and attenuators SDO pin. On power-up, the internal shift register and latches Digitally controlled calibration are filled with 0s, and the DAC outputs are at zero scale. Programmable filters and oscillators The AD5415 DAC is available in a 24-lead TSSOP package. The Composite video EV-AD5415/49SDZ evaluation board is available for evaluating Ultrasound DAC performance. For more information, see UG-296, Evaluating Gain, offset, and voltage trimming the AD5415 Serial Input, Dual-Channel Current Output DAC. FUNCTIONAL BLOCK DIAGRAM R3A R2_3A R2A VREFA R1A R3 R2 AD5415 2R 2R R1 RFB 2R 2R VDD RFBA SYNC SHIFT INPUT DAC 12-BIT IOUT1A SCLK REGISTER REGISTER REGISTER R-2R DAC A SDIN IOUT2A SDO LDAC INPUT DAC 12-BIT IOUT1B REGISTER REGISTER R-2R DAC B POWER-ON IOUT2B CLR RESET RFBB GND R1 RFB R3 R2 2R 2R R3B 2RR2_3B2RR2B VREFB R1B 04461-001 Figure 1. 1 U.S. Patent Number 5,689,257. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5415 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Circuit Operation ....................................................................... 15  Applications ....................................................................................... 1  Single-Supply Applications ....................................................... 16  General Description ......................................................................... 1  Adding Gain ................................................................................ 17  Functional Block Diagram .............................................................. 1  Divider or Programmable Gain Element ................................ 17  Revision History ............................................................................... 2  Reference Selection .................................................................... 18  Specifications ..................................................................................... 3  Amplifier Selection .................................................................... 18  Timing Characteristics ................................................................ 5  Serial Interface ............................................................................ 20  Absolute Maximum Ratings ............................................................ 7  Microprocessor Interfacing ....................................................... 22  ESD Caution .................................................................................. 7  PCB Layout and Power Supply Decoupling ........................... 24  Pin Configuration and Function Descriptions ............................. 8  Overview of the AD5424 to AD5547 Devices ............................ 25  Typical Performance Characteristics ............................................. 9  Outline Dimensions ....................................................................... 26  Terminology .................................................................................... 14  Ordering Guide .......................................................................... 26  General Description ....................................................................... 15  DAC Section ................................................................................ 15  REVISION HISTORY 12/15—Rev. E to Rev. F 7/05—Rev. 0 to Rev. A Deleted Positive Output Voltage Section ..................................... 17 Changes to Features List ................................................................... 1 Changes to Adding Gain Section ................................................. 17 Change to General Description ....................................................... 1 Changes to Reference Selection Section ...................................... 18 Changes to Specifications ................................................................. 3 Changes to ADSP21xx to AD5415 Interface Section, Changes to Timing Characteristics ................................................. 5 ADSP-BF504 to ADSP-BF592 Device Family to AD5415 Interface Change to Figure 8 and Figure 9 ..................................................... 9 Section, Figure 41, and Figure 42 .................................................. 22 Change to Figure 13 ....................................................................... 10 Changes to MC68HC11 to AD5415 Interface Section and Change to Figure 27 Through Figure 29 ..................................... 12 PIC16C6x/PIC16C7x to AD5415 Interface Section .................. 23 Change to Figure 32 ....................................................................... 15 Changes to Overview of the AD5424 to AD5547 Devices Changes to Table 5 and Table 6 .................................................... 15 Section Title ...................................................................................... 25 Change to Stability Section ........................................................... 16 Changes to Voltage-Switching Mode of Operation Section ..... 16 5/13—Rev. D to Rev. E Change to Figure 35 ....................................................................... 16 Changes to General Description .................................................... 1 Changes to Divider or Programmable Gain Element Section .... 17 Change to Ordering Guide ............................................................ 26 Changes to Figure 36 Through Figure 38.................................... 17 Changes to Table 7 Through Table 10 ......................................... 19 5/12—Rev. C to Rev. D Added ADSP-BF5xx-to-AD5415 Interface Section ................... 22 Changes SDO Control (SDO1 and SDO2) Section ................... 20 Change to 80C51/80L51-to-AD5415 Interface Section ............ 23 Change to MC68HC11-to-AD5415 Interface Section .............. 23 6/11—Rev. B to Rev. C Change to Power Supplies for the Evaluation Board Section ... 24 Changes to General Description ................................................... 1 Changes to Table 13 ....................................................................... 28 Deleted Evaluation Board for the DAC Section and Power Updated Outline Dimensions ....................................................... 29 Supplies for the Evaluation Board Section .................................. 24 Changes to Ordering Guide .......................................................... 29 Changes to Ordering Guide .......................................................... 26 7/04—Revision 0: Initial Version 4/10—Rev. A to Rev. B Added Figure 4 .................................................................................. 6 Rev. F | Page 2 of 27

Data Sheet AD5415 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 10 V, I 2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T to T , unless DD REF OUT MIN MAX otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted. Table 1.1 Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 12 Bits Relative Accuracy ±1 LSB Differential Nonlinearity −1/+2 LSB Guaranteed monotonic Gain Error ±25 mV Gain Error Temperature Coefficient ±5 ppm FSR/°C Bipolar Zero Code Error ±25 mV Output Leakage Current ±1 nA Data = 0x0000, T = 25°C, I 1 A OUT ±15 nA Data = 0x0000, T = −40°C to +125°C, I 1 A OUT REFERENCE INPUT Reference Input Range ±10 V V A, V B Input Resistance 8 10 13 kΩ Input resistance temperature coefficient (TC) = REF REF −50 ppm/°C V A to V B Input Resistance 1.6 2.5 % Typ = 25°C, max = 125°C REF REF Mismatch R1, R Resistance 17 20 25 kΩ Input resistance TC = −50 ppm/°C FB R2, R3 Resistance 17 20 25 kΩ Input resistance TC = −50 ppm/°C R2 to R3 Resistance Mismatch 0.06 0.18 % Typ = 25°C, max = 125°C Input Capacitance Code 0 3.5 pF Code 4095 3.5 pF DIGITAL INPUTS/OUTPUT Input High Voltage, V 1.7 V V = 3.6 V to 5.5 V IH DD 1.7 V V = 2.5 V to 3.6 V DD Input Low Voltage, V 0.8 V V = 2.7 V to 5.5 V IL DD 0.7 V V = 2.5 V to 2.7 V DD Output High Voltage, V V − 1 V V = 4.5 V to 5.5 V, I = 200 μA OH DD DD SOURCE V − 0.5 V V = 2.5 V to 3.6 V, I = 200 μA DD DD SOURCE Output Low Voltage, V 0.4 V V = 4.5 V to 5.5 V, I = 200 μA OL DD SINK 0.4 V V = 2.5 V to 3.6 V, I = 200 μA DD SINK Input Leakage Current, I 1 μA IL Input Capacitance 4 10 pF DYNAMIC PERFORMANCE Reference Multiplying Bandwidth (BW) 10 MHz V = ±3.5 V p-p, DAC loaded all 1s REF Output Voltage Settling Time R = 100 Ω, C = 15 pF, V = 10 V LOAD LOAD REF DAC latch alternately loaded with 0s and 1s Measured to ±1 mV of Full Scale (FS) 80 120 ns Measured to ±4 mV of FS 35 70 ns Measured to ±16 mV of FS 30 60 ns Digital Delay 20 40 ns 10% to 90% Settling Time 15 30 ns Rise and fall times Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry, V = 0 V REF Multiplying Feedthrough Error DAC latches loaded with all 0s, V = ±3.5 V REF 70 dB 1 MHz 48 dB 10 MHz Output Capacitance 12 17 pF DAC latches loaded with all 0s 25 30 pF DAC latches loaded with all 1s Rev. F | Page 3 of 27

AD5415 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments Digital Feedthrough 3 5 nV-sec Feedthrough to DAC output with CS high and alternate loading of all 0s and all 1s Output Noise Spectral Density 25 nV/√Hz At 1 kHz Analog THD 81 dB V =3. 5 V p-p, all 1s loaded, f = 1 kHz REF Digital THD Clock = 10 MHz, V = 3.5 V REF 100 kHz f 61 dB OUT 50 kHz f 66 dB OUT SFDR Performance (Wide Band) V = 3.5 V REF Clock = 10 MHz 500 kHz f 55 dB OUT 100 kHz f 63 dB OUT 50 kHz f 65 dB OUT Clock = 25 MHz 500 kHz f 50 dB OUT 100 kHz f 60 dB OUT 50 kHz f 62 dB OUT SFDR Performance (Narrow Band) V = 3.5 V REF Clock = 10 MHz 500 kHz f 73 dB OUT 100 kHz f 80 dB OUT 50 kHz f 87 dB OUT Clock = 25 MHz 500 kHz f 70 dB OUT 100 kHz f 75 dB OUT 50 kHz f 80 dB OUT Intermodulation Distortion V = 3.5 V REF f = 40 kHz, f = 50 kHz 72 dB Clock = 10 MHz 1 2 f = 40 kHz, f = 50 kHz 65 dB Clock = 25 MHz 1 2 POWER REQUIREMENTS Power Supply Range 2.5 5.5 V I 0.7 μA T = 25°C, logic inputs = 0 V or V DD A DD 0.5 10 μA T = −40°C to +125°C, logic inputs = 0 V or V A DD Power Supply Sensitivity 0.001 %/% ∆V = ±5% DD 1 Guaranteed by design and characterization, not subject to production test. Rev. F | Page 4 of 27

Data Sheet AD5415 TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. V = 2.5 V to 5.5 V, DD IL IH DD V = 10 V, I 2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T to T , unless otherwise noted. REF OUT MIN MAX Table 2. Parameter1 Limit at T , T Unit Test Conditions/Comments2 MIN MAX f 50 MHz max Maximum clock frequency SCLK t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t4 13 ns min SYNC falling edge to SCLK falling edge setup time t 5 ns min Data setup time 5 t 4 ns min Data hold time 6 t7 5 ns min SYNC rising edge to SCLK falling edge t8 30 ns min Minimum SYNC high time t9 0 ns min SCLK falling edge to LDAC falling edge t10 12 ns min LDAC pulse width t11 10 ns min SCLK falling edge to LDAC rising edge t 3 25 ns min SCLK active edge to SDO valid, strong SDO driver 12 60 ns min SCLK active edge to SDO valid, weak SDO driver Update Rate 2.47 MSPS Consists of cycle time, SYNC high time, data setup, and output voltage settling time 1 Guaranteed by design and characterization, not subject to production test. 2 Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register. 3 Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in Figure 5. t1 SCLK t8 t4 t2 t3 t7 SYNC t6 t5 DIN DB15 DB0 t10 t9 LDAC1 t11 LDAC2 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. NADOLETTTEEERRSNMAINTEIVDE BLYY, TDHAET CAO CNATNR BOEL CBLITOSC. KTIEMDIN INGT IOS TAHSE A IBNOPVUET, SWHIITFHT SRCELGKIS ITNEVRE ROTNE TDH.E RISING EDGE OF SCLK AS 04461-002 Figure 2. Standalone Mode Timing Diagram Rev. F | Page 5 of 27

AD5415 Data Sheet t1 SCLK t4 t2 t3 t7 SYNC t6 t8 t5 DB15 DB0 DB15 DB0 SDIN (N) (N) (N + 1) (N + 1) t12 DB15 DB0 SDO (N) (N) N1 . O ADTLEETTSEERRNMAINTEIVDE BLYY, TDHAET CAO CNATNR BOEL CBLITOSC. KINE TDH INIST COA TSHEE, DINAPTUAT I SS HCILFOT CRKEEGDIS OTEURT OOFN STDHOE ROINS ITNHGE E FDAGLEL IONGF SCLK AS 04461-003 EDGE OF SCLK. TIMING IS AS ABOVE, WITH SCLK INVERTED. Figure 3. Daisy-Chain Timing Diagram SCLK 16 32 SYNC SDIN DB15 DB0 DB15 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB15 DB0 UNDEFINED SELECCTLEOD CRKEEGDIS OTUETR DATA 04461-053 Figure 4. Readback Mode Timing Diagram 200µA IOL TO OUTPUT VOH (MIN) + VOL (MAX) PIN CL 2 50pF 200µA IOH 04461-004 Figure 5. Load Circuit for SDO Timing Specifications Rev. F | Page 6 of 27

Data Sheet AD5415 ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. Stresses at or above those listed under Absolute Maximum T = 25°C, unless otherwise noted. A Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Table 3. or any other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Operation beyond V to GND −0.3 V to +7 V DD the maximum operating conditions for extended periods may V , R to GND −12 V to +12 V REF FB affect product reliability. I 1, I 2 to GND −0.3 V to +7 V OUT OUT Input Current to Any Pin Except Supplies ±10 mA ESD CAUTION Logic Inputs and Output1 −0.3 V to V + 0.3 V DD Operating Temperature Range Extended (Y Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C 24-Lead TSSOP, θ Thermal Impedance 128°C/W JA Lead Temperature, Soldering (10 sec) 300°C Infrared (IR) Reflow, Peak Temperature 235°C (<20 sec) 1 Overvoltages at SCLK, SYNC, and SDIN are clamped by internal diodes. Rev. F | Page 7 of 27

AD5415 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IOUT1A 1 24 IOUT1B IOUT2A 2 23 IOUT2B RFBA 3 22 RFBB R1A 4 21 R1B R2A 5 20 R2B AD5415 R2_3A 6 TOP VIEW 19 R2_3B R3A 7 (Not to Scale) 18 R3B VREFA 8 17 VREFB GND 9 16 VDD LDAC 10 15 CLR SSCDLINK 1121 1143 SSDYNOC 04461-005 Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 I 1A DAC A Current Output. OUT 2 I 2A DAC A Analog Ground. This pin is normally tied to the analog ground of the system, but can be biased to achieve OUT single-supply operation. 3 R A DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external FB amplifier output. 4 to 7 R1A, R2A, DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with R2_3A, R3A minimum external components. 8 V A DAC A Reference Voltage Input Pin. REF 9 GND Ground Pin. 10 LDAC Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge when the device is in standalone mode, or on the rising edge of SYNC when in daisy-chain mode. 11 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK. 12 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power-up data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge. 13 SDO Serial Data Output. This pin allows a number of devices to be daisy-chained. By default, data is clocked into the shift register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes the DAC register contents available for readback on the SDO pin; they are clocked out on the next 16 opposite clock edges to the active clock edge. 14 SYNC Active Low Control Input. This pin provides the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and SDIN buffers, and the input shift register is enabled. Data is loaded into the shift register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks, and data is latched into the shift register on the 16th active clock edge. 15 CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user to enable the hardware CLR pin as a clear to zero scale or midscale as required. 16 V Positive Power Supply Input. This device can be operated from a supply of 2.5 V to 5.5 V. DD 17 V B DAC B Reference Voltage Input Pin. REF 18 to 21 R3B, R2_3B, DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with R2B, R1B a minimum of external components. 22 R B DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external FB amplifier output. 23 I 2B DAC B Analog Ground. This pin is normally tied to the analog ground of the system, but can be biased to achieve OUT single-supply operation. 24 I 1B DAC B Current Output. OUT Rev. F | Page 8 of 27

Data Sheet AD5415 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 –0.40 0.8 TVAR E=F 2=5 °1C0V VTAD D= =2 55°VC 0.6 VDD = 5V –0.45 0.4 –0.50 B) 0.2 B) NL (LS 0 NL (LS–0.55 I –0.2 D –0.60 –0.4 MIN DNL –0.6 –0.65 –0.8 –1.0 –0.70 0 500 1000 1500 C2O0D00E 2500 3000 3500 4000 04461-006 2 3 4 REF5ERENC6E VOLTA7GE 8 9 10 04461-009 Figure 7. Integral Nonlinearity (INL) vs. Code (12-Bit DAC) Figure 10. DNL vs. Reference Voltage 1.0 5 00..68 VVTARD ED=F = 2= 55 °1VC0V 34 VDD = 5V 0.4 2 B) 0.2 mV) 1 DNL (LS –0.20 ERROR ( –10 VDD = 2.5V –0.4 –2 –0.6 –3 –0.8 –4 VREF = 10V –1.00 500 1000 1500 C2O0D00E 2500 3000 3500 4000 04461-007 –5–60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 04461-010 Figure 8. Differential Nonlinearity (DNL) vs. Code (12-Bit DAC) Figure 11. Gain Error vs. Temperature 0.6 8 TA = 25°C 0.5 7 0.4 6 MAX INL 0.3 mA) 5 VDD = 5V NL (LSB) 00..12 TVAD D= =2 55°VC RRENT ( 4 I CU 3 0 MIN INL 2 –0.1 VDD = 3V 1 –0.2 VDD = 2.5V –0.32 3 4 REF5ERENC6E VOLTA7GE 8 9 10 04461-008 00 0.5 1.0 1.5INP2U.0T VO2L.5TAG3E. 0(V) 3.5 4.0 4.5 5.0 04461-011 Figure 9. INL vs. Reference Voltage Figure 12. Supply Current vs. Logic Input Voltage Rev. F | Page 9 of 27

AD5415 Data Sheet 1.6 06 TLAO A= D2I5NGC ADLBL1 1ON 1.4 –6 ZS TO FS DB10 –12 DB9 –18 1.2 DB8 –24 IOUT1 VDD = 5V –30 DB7 KAGE (nA) 01..80 IOUT1 VDD = 3V GAIN (dB) ––––54434286 DDDDDBBBBB65432 LEA 0.6 ––6660 DB1 1 OUT 0.4 ––7728 DB0 TA = 25C I –84 VDD = 5V 0.2 –90 VREF =3.5V 0–40 –20 0 TE20MPERA4T0URE (6°C0) 80 100 120 04461-012 ––190621 10 10A0LL O1FFkFREQU1E0NkCY (H10z0)k 1MACMCPOM =1P 0AM=D18.80p13F080M 04461-015 Figure 13. Iout1 Leakage Current vs. Temperature Figure 16. Reference Multiplying Bandwidth vs. Frequency and Code 0.50 0.2 0.45 VDD = 5V 0.40 0 0.35 A) ALL 0s ENT ( 00..2350 ALL 1s N (dB) –0.2 URR 0.20 VDD = 2.5V GAI –0.4 C 0.15 ALL 1s ALL 0s TA = 25°C 0.10 –0.6 VDD = 5V VREF =3.5V 0.05 CCOMP = 1.8pF AMP = AD8038 0 –0.8 –60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 04461-013 1 10 100 F1kREQU1E0NkCY (H10z0)k 1M 10M 100M 04461-016 Figure 14. Supply Current vs. Temperature Figure 17. Reference Multiplying Bandwidth—All 1s Loaded 14 3 TLAO A= D2I5N°GC ZS TO FS TVAD D= =2 55°VC 12 VDD = 5V 0 10 I (mA)DD 68 VDD = 3V GAIN (dB) –3 4 –6 VREF =2V, AD8038 CC 1.47pF VDD = 2.5V VREF =2V, AD8038 CC 1pF VREF =0.15V, AD8038 CC 1pF 2 VREF =0.15V, AD8038 CC 1.47pF VREF =3.51V, AD8038 CC 1.8pF 01 10 100 F1kREQU1E0NkCY (H10z0)k 1M 10M 100M 04461-014 –910k 100k FREQUE1MNCY (Hz) 10M 100M 04461-017 Figure 15. Supply Current vs. Update Rate Figure 18. Reference Multiplying Bandwidth vs. Frequency and Compensation Capacitor Rev. F | Page 10 of 27

Data Sheet AD5415 0.045 –60 0x7FF TO 0x800 TA = 25°C TA = 25°C 0.040 VREF = 0V VDD = 3V 0.035 VDD = 5V ACMCOPM =P A=D 18.80p3F8 –65 VREF = 3.5V p-p V) 0.030 OUTPUT VOLTAGE ( 00000.....000000212155500 VDD = 3V 0VxD8D0 =0 3TVO 0x7FF THD + N (dB) –––877050 0 –85 –0.005 VDD = 5V –0.010 –90 0 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 04461-018 1 10 100FREQUE1NkCY (Hz)10k 100k 1M 04461-021 Figure 19. Midscale Transition, VREF = 0 V Figure 22. THD and Noise vs. Frequency –1.68 100 –1.69 0x7FF TO 0x800 TVAR E=F 2=5 °3C.5V MCLK = 1MHz –1.70 VDD = 5V ACMCOPM =P A=D 18.80p3F8 80 V) E ( –1.71 AG B) 60 MCLK = 200kHz T –1.72 d VOL VDD = 3V DR ( MCLK = 0.5MHz UT –1.73 SF 40 UTP –1.74 VDD = 5V O VDD = 3V –1.75 20 –1.76 TVAR E=F 2=5 °3C.5V 0x800 TO 0x7FF AMP = AD8038 –1.770 20 40 60 80TIM1E0 0(ns)120 140 160 180 200 04461-019 00 20 40 60 80fOU1T 0(0kHz)120 140 160 180 200 04461-022 Figure 20. Midscale Tr ansition, VREF = 3.5 V Figure 23. Wideband Spurious-Free Dynamic Range (SFDR) vs. fOUT Frequency 20 TA = 25°C 90 VDD = 3V 0 AMP = AD8038 80 MCLK = 5MHz –20 70 MCLK = 10MHz 60 dB) –40 B) RR ( FULL SCALE R (d 50 PS –60 ZERO SCALE SFD 40 MCLK = 25MHz –80 30 20 –100 10 TVAR E=F 2=5 °3C.5V –1201 10 100 FRE1QkUENC1Y0 (kHz) 100k 1M 10M04461-020 00 100 200 300 400fOU5T 0(0kHz)600 700 A8M0P0 = A9D0800318000 04461-023 Figure 21. Power Supply Rejection Ratio vs. Frequency Figure 24. Wideband SFDR vs. fOUT Frequency Rev. F | Page 11 of 27

AD5415 Data Sheet 0 0 TA = 25°C TA� = 25°C –10 AVDMDP = = 5 AVD8038 –10 VADMDP = = 3 AVD8038 65k CODES –20 65k CODES –20 –30 –30 B) –40 d–40 SFDR (–50 DR (dB)––5600 F –60 S –70 –70 –80 –80 –90 –900 2 4FREQUEN6CY (MHz)8 10 12 04461-024 –100250 300 350 400 FR45E0QUE5N00CY (5k5H0z) 600 650 700 750 04461-027 Figure 25. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz Figure 28. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz 0 20 TA� = 25°C TA� = 25°C –10 VDD = 5V VDD = 3V AMP = AD8038 0 AMP = AD8038 –20 65k CODES 65k CODES –30 –20 dB)–40 dB)–40 R (–50 R ( D D SF–60 SF–60 –70 –80 –80 –100 –90 –1000 0.5 1.0 1.5 FR2E.0QUE2N.5CY (M3.H0z) 3.5 4.0 4.5 5.0 04461-025 –12050 60 70 80 FR9E0QUE1N00CY (1k1H0z) 120 130 140 150 04461-028 Figure 26. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz Figure 29. Narrow-Band SFDR, fOUT = 100 kHz, MCLK = 25 MHz 0 0 TA = 25°C TA� = 25°C –10 AVDMDP = = 5 AVD8038 –10 VADMDP = = 3 AVD8038 65k CODES –20 65k CODES –20 –30 –30 B) –40 d–40 R ( B)–50 FD–50 (d S –60 –60 –70 –70 –80 –80 –90 –900 0.5 1.0 1.5 FR2E.0QUE2N.5CY (M3.H0z) 3.5 4.0 4.5 5.0 04461-026 –10070 75 80 85 FR9E0QUE9N5CY (1k0H0z) 105 110 115 120 04461-029 Figure 27. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz Figure 30. Narrow-Band Intermodulation Distortion (IMD), fOUT = 90 kHz, 100 kHz, Clock = 10 MHz Rev. F | Page 12 of 27

Data Sheet AD5415 0 300 TA� = 25°C TA = 25°C –10 VDD = 5V ZERO SCALE LOADED TO DAC AMP = AD8038 AMP = AD8038 250 MIDSCALE LOADED TO DAC –20 65k CODES FULL SCALE LOADED TO DAC –30 Hz) V/ 200 –40 E (n dB)–50 OIS 150 ( N –60 UT P T 100 –70 U O –80 50 –90 –1000 50 100 1F5R0EQUE2N00CY (kH25z0) 300 350 400 04461-030 0100 1kFREQUENCY (Hz)10k 100k 04461-031 Figure 31. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz Figure 32. Output Noise Spectral Density Rev. F | Page 13 of 27

AD5415 Data Sheet TERMINOLOGY Relative Accuracy (Endpoint Nonlinearity) Digital Crosstalk A measure of the maximum deviation from a straight line The glitch impulse transferred to the outputs of one DAC in passing through the endpoints of the DAC transfer function. It response to a full-scale code change (all 0s to all 1s, or vice is measured after adjusting for zero scale and full scale and is versa) in the input register of the other DAC. It is expressed normally expressed in LSB or as a percentage of the full-scale in nV-sec. reading. Analog Crosstalk Differential Nonlinearity The glitch impulse transferred to the output of one DAC due to The difference in the measured change and the ideal 1 LSB a change in the output of another DAC. It is measured by change between two adjacent codes. A specified differential loading one of the input registers with a full-scale code change nonlinearity of −1 LSB maximum over the operating (all 0s to all 1s, or vice versa) while keeping LDAC high and temperature range ensures monotonicity. then pulsing LDAC low and monitoring the output of the DAC Gain Error (Full-Scale Error) whose digital code has not changed. The area of the glitch is A measure of the output error between an ideal DAC and the expressed in nV-sec. actual device output. For this DAC, ideal maximum output is Channel-to-Channel Isolation VREF − 1 LSB. The gain error of the DAC is adjustable to zero The portion of input signal from a DAC reference input that with an external resistance. appears at the output of another DAC. It is expressed in decibels. Output Leakage Current Total Harmonic Distortion (THD) The current that flows into the DAC ladder switches when they The DAC is driven by an ac reference. The ratio of the rms sum are turned off. For the IOUT1 terminal, it can be measured by of the harmonics of the DAC output to the fundamental value is loading all 0s to the DAC and measuring the IOUT1 current. the THD. Usually only the lower-order harmonics are included, Minimum current flows into the IOUT2 line when the DAC is such as the second to fifth harmonics. loaded with all 1s. V 2 +V 2 +V 2 +V 2 Output Capacitance THD=20log 2 3 4 5 V Capacitance from IOUT1 or IOUT2 to AGND. 1 Output Current Settling Time Intermodulation Distortion (IMD) The amount of time for the output to settle to a specified level The DAC is driven by two combined sine wave references of for a full-scale input change. For this device, it is specified with frequencies fa and fb. Distortion products are produced at sum a 100 Ω resistor to ground. and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 ... Intermodulation terms are those for which m or n is not equal Digital-to-Analog Glitch Impulse to 0. The second-order terms include (fa + fb) and (fa − fb), and The amount of charge injected from the digital inputs to the the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa + 2fb), and analog output when the inputs change state. This is normally (fa − 2fb). IMD is defined as specified as the area of the glitch in either pA-sec or nV-sec, depending on whether the glitch is measured as a current or (rmssumof thesumanddiff distortionproducts) IMD=20log voltage signal. rms amplitude of the fundamental Digital Feedthrough When the device is not selected, high frequency logic activity on Compliance Voltage Range the digital inputs of the device is capacitively coupled through the The maximum range of (output) terminal voltage for which the device and produces noise on the IOUT pins and, subsequently, on device provides the specified characteristics. the following circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error The error due to capacitive feedthrough from the DAC reference input to the DAC I 1 terminal when all 0s are OUT loaded to the DAC. Rev. F | Page 14 of 27

Data Sheet AD5415 GENERAL DESCRIPTION DAC SECTION When an output amplifier is connected in unipolar mode, the output voltage is given by The AD5415 is a 12-bit, dual-channel, current output DAC consisting of standard inverting R-2R ladder configuration. VOUT = −VREF × D/2n Figure 33 shows a simplified diagram of a single channel of the where: AD5415. The feedback resistor R has a value of 2R. The value FB D is the fractional representation, in the range of 0 to 4,095, of of R is typically 10 kΩ (with a minimum of 8 kΩ and a maximum the digital word loaded to the DAC. of 12 kΩ). If I 1 and I 2 are kept at the same potential, a OUT OUT n is the number of bits. constant current flows into each ladder leg, regardless of the Note that the output voltage polarity is opposite the V digital input code. Therefore, the input resistance presented at REF polarity for dc reference voltages. This DAC is designed to V is always constant. REF operate with either negative or positive reference voltages. The R R R VREFA VDD power pin is only used by the internal digital logic to drive 2R 2R 2R 2R 2R the on and off states of the DAC switches. S1 S2 S3 S12 R RFBA This DAC is also designed to accommodate ac reference input IOUT1A signals in the range of −10 V to +10 V. IOUT2A With a fixed 10 V reference, the circuit in Figure 34 gives a DACA NDDA TDAR ILVAETRCSHES 04461-032 aucn ispigonlaarl ,0 t hVe tcoir −cu1i0t Vpe orfuotrpmuts v2o-lqtuagaed rsawnitn mg. uWltihpelnic aVtiINo nis. an Figure 33. Simplified Ladder Table 5 shows the relationship between digital code and Access is provided to the V , R , I 1, and I 2 terminals of REF FB OUT OUT expected output voltage for unipolar operation. the DAC, making the device extremely versatile and allowing it to be configured in several operating modes, such as unipolar Table 5. Unipolar Code output, bipolar output, or single-supply mode. Digital Input Analog Output (V) CIRCUIT OPERATION 1111 1111 1111 −VREF (4,095/4,096) 1000 0000 0000 −V (2,048/4,096) = −V /2 Unipolar Mode REF REF 0000 0000 0001 −V (1/4,096) REF Using a single operational amplifier, this device can easily be 0000 0000 0000 −V (0/4,096) = 0 REF configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 34. VDD R1A R1 RFB 2R 2R RFBA R2A C1 R2 IOUT1A 2R AD5415 R2_3A 12-BIT DAC A A1 R3 R IOUT2A VOUT = 0V TO–VIN 2R R3A AGND AGND VREFA SYNC SCLK SDIN GND µCONTROLLER AGND NOTES 12 .. DCIFA1 A CP1 HB IAS OS AME H ICTITGOEHMD PS FEPONERSE ADCT LAIAOMRNPI LT(1IYFp.IFE RTO. 2pF) MAY BE REQUIRED 04461-033 Figure 34. Unipolar Operation Rev. F | Page 15 of 27

AD5415 Data Sheet Bipolar Operation VDDR1A In some applications, it may be necessary to generate full R2R1 R2FRB RFBA 4-quadrant multiplying operation or a bipolar output swing. VIN R2A C1 This can easily be accomplished by using another external R2R2 AD5415 IOUT1A R2_3A 12-BIT DAC A A1 amplifier and the on-chip 4-quadrant resistors, as shown in R3 R IOUT2A VOUT =–VIN TO +VIN Figure 35. 2R R3A A1 AGND When in bipolar mode, the output voltage is given by VREFA SYNC SCLK SDIN GND VOUT = (VREF × D/2n − 1) − VREF AGND µCONTROLLER AGND where: Dth eis d tihgeit farla wctoiordn alol aredperde stoen tthaet iDonA, Cin. the range of 0 to 4,095, of N12 .. O DCIFTA1 EA CPS1 HB IAS OS AME H ICTITGOEHMD PS FEPONERSE ADCT LAIAOMRNPI LT(1IYFp.IFE RTO. 2pF) MAY BE REQUIRED 04461-034 n is the number of bits. Figure 35. Bipolar Operation When VIN is an ac signal, the circuit performs 4-quadrant SINGLE-SUPPLY APPLICATIONS multiplication. Voltage Switching Mode of Operation Table 6 shows the relationship between digital code and the Figure 36 shows the DAC operating in the voltage switching expected output voltage for bipolar operation. mode. The reference voltage, V , is applied to the I 1A pin, IN OUT Table 6. Bipolar Code IOUT2A is connected to AGND, and the output voltage is available at the V A terminal. In this configuration, a positive Digital Input Analog Output (V) REF reference voltage results in a positive output voltage, making 1111 1111 1111 +V (4095/4096) REF single-supply operation possible. The output from the DAC is 1000 0000 0000 0 voltage at a constant impedance (the DAC ladder resistance). 0000 0000 0001 −V (4095/4096) REF Therefore, an operational amplifier is necessary to buffer the 0000 0000 0000 −V (4096/4096) REF output voltage. The reference input no longer sees a constant Stability input impedance, but one that varies with code. Therefore, the voltage input must be driven from a low impedance source. In the I-to-V configuration, the I of the DAC and the inverting OUT node of the operational amplifier must be connected as close as VDD R1 R2 possible, and proper printed circuit board (PCB) layout techniques must be used. Because every code change corresponds to a step RFBA VDD fliumnictetido nga, igna bina npdewakidinthg pmroadyu occtc (uGrB iPf )t haen do pthereartei oisn eaxl caemsspivliefi pera rh-as VIN IIOOUUTT21AA VREFA VOUT asitic capacitance at the inverting node. This parasitic capacitance GND introduces a pole into the open-loop response, which can cause ringing or instability in the closed-loop applications circuit. NOTES Awnit ho pRtFioBAna flo cro smtapbeinlistayt, iaosn schaopwacnit ionr, FCi1g,u craen 3 b4e a anddd Fedig iunr pe a3r5a.l lTelo o 12.. ISCFI1 MA PI1LH AIASR SA EC H OCINGOFHMI GPSUEPNRESEAADTIT OAIOMNN PF LO(1IFRpI FED RTAO.C B2pF) MAY BE REQUIRED 04461-035 small a value of C1 can produce ringing at the output, whereas Figure 36. Single-Supply Voltage Switching Mode too large a value can adversely affect the settling time. C1 must Note that V is limited to low voltages because the switches in be found empirically, but 1 pF to 2 pF is generally adequate for IN the DAC ladder no longer have the same source-drain drive the compensation. voltage. As a result, the on resistance differs and degrades the integral linearity of the DAC. Also, V must not go negative by IN more than 0.3 V or an internal diode turns on, causing the device to exceed the maximum ratings. In this type of application, the full range of multiplying capability of the DAC is lost. Rev. F | Page 16 of 27

Data Sheet AD5415 ADDING GAIN VDD VIN In applications where the output voltage must be greater than V , IN gain can be added with an additional external amplifier or it can RFBA VDD be achieved in a single stage. Consider the effect of temperature IOUT1A VREFA coefficients of the thin film resistors of the DAC. Simply placing IOUT2A a resistor in series with the R resistor causes mismatches in the GND FB temperature coefficients, resulting in larger gain temperature coefficient errors. Instead, the circuit in Figure 37 shows the VOUT recommended method for increasing the gain of the circuit. R1, Rne2e, da nndo tR m3 actacnh hthavee t esimmpielarra ttuerme pceoreaftfuicriee cnotse foffi ctiheen tDs,A bCu.t Tthheisy N1.O ATDEDSITIONAL PINS OMITTED FOR CLARITY. 04461-038 approach is recommended in circuits where gains greater than 1 Figure 38. Current Steering DAC Used as a Divider or are required. Note that R R2//R3 and a gain error percentage of FB Programmable Gain Element 100 × (R2//R3)/R must be taken into consideration. FB ≫ As D is reduced, the output voltage increases. For small values VDD of the digital fraction, D, it is important to ensure the amplifier does not saturate and the required accuracy is met. For example, an 8-bit VDD RFBA C1 DAC driven with the binary code 0x10 (0001 0000)—that is, R1 IOUT1A 16 decimal—in the circuit of Figure 38 must cause the output VIN VREFA 12-BIT DAC VOUT IOUT2A R3 voltage to be 16 times VIN. However, if the DAC has a linearity GND R2 + R3 specification of ±0.5 LSB, D can have a weight in the range of R2 GAIN = R2 15.5/256 to 16.5/256, so that the possible output voltage is in the R2R3 NOTES R1 =R2 + R3 range of 15.5 VIN to 16.5 VIN—an error of 3%, even though the 12 .. ACIFD1 A DP1IHT IASIOS ANE AH CLIGO PHMIN PSSEP NOESEMADITT ATIOMENDP L(F1IOFpIRFE RTCO.L A2RpFIT)Y M.AY BE REQUIRED 04461-037 DAC itself has a maximum error of 0.2%. DAC leakage current is also a potential source of errors in Figure 37. Increasing the Gain of the Current Output DAC divider circuits. The leakage current must be counterbalanced by DIVIDER OR PROGRAMMABLE GAIN ELEMENT an opposite current supplied from the operational amplifier through the DAC. Because only a fraction, D, of the current into Current steering DACs are very flexible and lend themselves to the V A terminal is routed to the I 1A terminal, the output REF OUT many applications. If this type of DAC is connected as the feedback voltage changes as follows: element of an operational amplifier and R is used as the input FB Output Error Voltage Due to DAC Leakage = (Leakage × R)/D resistor, as shown in Figure 38, the output voltage is inversely proportional to the digital input fraction, D. where R is the DAC resistance at the V A terminal. REF For D, which is equal to 1 − 2−n, the output voltage is For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that V = −V /D = −V /(1 − 2−n) is, 1/D) of 16, the error voltage is 1.6 mV. OUT IN IN Rev. F | Page 17 of 27

AD5415 Data Sheet REFERENCE SELECTION This output voltage change is superimposed on the desired change in output between the two codes and gives rise to a When selecting a reference for use with the AD5415 and other differential linearity error, which, if large enough, might cause devices in this series of current output DACs, pay attention to the DAC to be nonmonotonic. the reference output voltage temperature coefficient specification. This parameter not only affects the full-scale error, but also can The input bias current of an operational amplifier also generates affect the linearity (INL and DNL) performance. The reference an offset at the voltage output as a result of the bias current flowing temperature coefficient must be consistent with the system in the feedback resistor, RFB. Most operational amplifier s have accuracy specifications. For example, an 8-bit system required input bias currents low enough to prevent significant errors in to hold the overall specification within 1 LSB over the temp- 12-bit applications. erature range 0°C to 50°C dictates that the maximum system Common-mode rejection of the operational amplifier is drift with temperature must be less than 78 ppm/°C. A 12-bit important in voltage switching circuits, because it produces a system with the same temperature range to overall specification code dependent error at the voltage output of the circuit. Most within 2 LSB requires a maximum drift of 10 ppm/°C. Choosing operational amplifier s have adequate common-mode rejection a precision reference with a low output temperature coefficient for use at 12-bit resolution. minimizes this error source. Table 7 lists some of the references Provided that the DAC switches are driven from true wideband available from Analog Devices, Inc., that are suitable for use low impedance sources (V and AGND), they settle quickly. with this range of current output DACs. IN Consequently, the slew rate and settling time of a voltage switching AMPLIFIER SELECTION DAC circuit is largely determined by the output operational The primary requirement for the current steering mode is an amplifier. To obtain minimum settling time in this configuration, amplifier with low input bias currents and low input offset voltage. minimize capacitance at the VREF node (the voltage output node Because of the code dependent output resistance of the DAC, in this application) of the DAC. This is done by using low input the input offset voltage of an operational amplifier is multiplied capacitance buffer amplifiers and careful board design. by the variable gain of the circuit. A change in this noise gain Most single-supply circuits include ground as part of the analog between two adjacent digital fractions produces a step change in signal range, which in turn requires an amplifier that can handle the output voltage due to the amplifier input offset voltage. rail-to-rail signals. Analog Devices offers a wide range of single- supply amplifiers, as listed in Table 8 and Table 9. Rev. F | Page 18 of 27

Data Sheet AD5415 Table 7. Suitable Analog Devices Precision References Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) I (mA) Output Noise (μV p-p) Package SS ADR01 10 0.05 3 1 20 SOIC-8 ADR01 10 0.05 9 1 20 TSOT-23, SC70 ADR02 5 0.06 3 1 10 SOIC-8 ADR02 5 0.06 9 1 10 TSOT-23, SC70 ADR03 2.5 0.10 3 1 6 SOIC-8 ADR03 2.5 0.10 9 1 6 TSOT-23, SC70 ADR06 3 0.10 3 1 10 SOIC-8 ADR06 3 0.10 9 1 10 TSOT-23, SC70 ADR431 2.5 0.04 3 0.8 3.5 SOIC-8 ADR435 5 0.04 3 0.8 8 SOIC-8 ADR391 2.5 0.16 9 0.12 5 TSOT-23 ADR395 5 0.10 9 0.12 8 TSOT-23 Table 8. Suitable Analog Devices Precision Operational Amplifiers Part No. Supply Voltage (V) V (Max) (μV) I (Max) (nA) 0.1 Hz to 10 Hz Noise (μV p-p) Supply Current (μA) Package OS B OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8 OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8 AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8 AD8603 1.8 to 6 50 0.001 2.3 50 TSOT AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8 Table 9. Suitable Analog Devices High Speed Operational Amplifiers Part No. Supply Voltage (V) BW at ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) I (Max) (nA) Package B AD8065 5 to 24 145 180 1,500 6,000 SOIC-8, SOT-23, MSOP AD8021 ±2.5 to ±12 490 120 1,000 10,500 SOIC-8, MSOP AD8038 3 to 12 350 425 3,000 750 SOIC-8, SC70-5 AD9631 ±3 to ±6 320 1,300 10,000 7,000 SOIC-8 Rev. F | Page 19 of 27

AD5415 Data Sheet SERIAL INTERFACE SDO Control (SDO1 and SDO2) The AD5415 has an easy to use 3-wire interface that is The SDO bits enable the user to control the SDO output driver compatible with SPI, QSPI, MICROWIRE, and most DSP strength, disable the SDO output, or configure it as an open- interface standards. Data is written to the device in 16-bit drain driver. The strength of the SDO driver affects the timing words. Each 16-bit word consists of four control bits and of t12 and, when stronger, allows a faster clock cycle to be used. 12 data bits, as shown in Figure 39. Note that when the SDO output is disabled the daisy-chain mode is also disabled. Low Power Serial Interface To minimize the power consumption of the device, the interface Table 10. SDO Control Bits only powers up fully when the device is being written to, that is, SDO2 SDO1 Function on the falling edge of SYNC. The SCLK and DIN input buffers 0 0 Full SDO driver are powered down on the rising edge of SYNC. 0 1 Weak SDO driver 1 0 SDO configured as open drain DAC Control Bits C3 to C0 1 1 Disable SDO output Control Bits C3 to C0 allow control of various functions of the DAC, as shown in Table 11. Default settings of the DAC at power Daisy-Chain Control (DSY) on are as follows. Data is clocked into the shift register on falling DSY enables or disables daisy-chain mode. A 1 enables daisy- clock edges, and daisy-chain mode is enabled. The device powers chain mode; a 0 disables it. When disabled, a readback request on with a zero-scale load to the DAC register and I lines. The OUT is accepted, SDO is automatically enabled, the DAC register DAC control bits allow the user to adjust certain features at power contents of the relevant DAC are clocked out on SDO, and, on. For example, daisy-chaining can be disabled when not in use, when complete, SDO is disabled again. an active clock edge can be changed to a rising edge, and DAC output can be cleared to either zero scale or midscale. The user Hardware CLR Bit (HCLR) can also initiate a readback of the DAC register contents for The default setting for the hardware CLR pin is to clear the verification purposes. registers and DAC output to zero code. A 1 in the HCLR bit Control Register (Control Bits = 1101) clears the DAC outputs to midscale; a 0 clears them to zero scale. While maintaining software compatibility with single-channel Active Clock Edge (SCLK) current output DACs (AD5426/AD5433/AD5443), this DAC The default active clock edge is the falling edge. Write a 1 to this also features additional interface functionality. Simply set the bit to clock data in on the rising edge; write a 0 to clock it in on control bits to 1101 to enter control register mode. Figure 40 the falling edge. shows the contents of the control register, the functions of which are described in the following sections. DB15 (MSB) DB0 (LSB) C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CONTROL BITS DATA BITS 04461-039 Figure 39. 12-Bit Input Shift Register Contents DB15 (MSB) DB0 (LSB) 1 1 0 1 SDO1 SDO2 DSY HCLR SCLK X X X X X X X CONTROL BITS 04461-040 Figure 40. Control Register Loading Sequence Rev. F | Page 20 of 27

Data Sheet AD5415 Table 11. DAC Control Bits C3 C2 C1 C0 DAC Function 0 0 0 0 A and B No operation (power-on default) 0 0 0 1 A Load and update 0 0 1 0 A Initiate readback 0 0 1 1 A Load input register 0 1 0 0 B Load and update 0 1 0 1 B Initiate readback 0 1 1 0 B Load input register 0 1 1 1 A and B Update DAC outputs 1 0 0 0 A and B Load input registers 1 0 0 1 – Disable daisy-chain 1 0 1 0 – Clock data to shift register on rising edge 1 0 1 1 – Clear DAC output to zero scale 1 1 0 0 – Clear DAC output to midscale 1 1 0 1 – Control word 1 1 1 0 – Reserved 1 1 1 1 – No operation SYNC Function When control bits are 0000, the device is in no-operation mode. This might be useful in daisy-chain applications where the user SYNC is an edge triggered input that acts as a frame synchroni- does not want to change the settings of a particular DAC in the zation signal and chip enable. Data can only be transferred into chain. Write 0000 to the control bits for that DAC, and subsequent the device while SYNC is low. To start the serial data transfer, data bits are ignored. SYNC must be taken low, observing the minimum SYNC falling Standalone Mode to SCLK falling edge setup time, t. 4 Daisy-Chain Mode After power on, writing 1001 to the control word disables daisy- chain mode. The first falling edge of SYNC resets the serial clock Daisy-chain mode is the default mode at power on. To disable counter to ensure that the correct number of bits are shifted in and the daisy-chain function, write 1001 to the control word. In out of the serial shift registers. A SYNC edge during the 16-bit daisy-chain mode, the internal gating on SCLK is disabled. write cycle causes the device to abort the current write cycle. SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data After the falling edge of the 16th SCLK pulse, data is automati- ripples out of the shift register and appears on the SDO line. cally transferred from the input shift register to the DAC. For This data is clocked out on the rising edge of SCLK and is valid another serial transfer to take place, the counter must be reset for the next device on the falling edge of SCLK (default). By by the falling edge of SYNC. connecting this line to the SDIN input on the next device in the LDAC Function chain, a multidevice interface is constructed. For each device in The LDAC function allows asynchronous and synchronous the system, 16 clock pulses are required. Therefore, the total updates to the DAC output. The DAC is asynchronously updated number of clock cycles must equal 16N, where N is the total when this signal goes low. Alternatively, if this line is held per- number of devices in the chain. (See Figure 5.) manently low, an automatic or synchronous update mode is When the serial transfer to all devices is complete, SYNC must be selected, whereby the DAC is updated on the 16th clock falling taken high. This prevents additional data from being clocked edge when the device is in standalone mode, or on the rising into the input shift register. A burst clock containing the exact edge of SYNC when the device is in daisy-chain mode. number of clock cycles can be used, after which SYNC is taken Software LDAC Function high. After the rising edge of SYNC, data is automatically trans- ferred from each device input shift register to the addressed DAC. The load and update mode also functions as a software update function, irrespective of the voltage level on the LDAC pin. Rev. F | Page 21 of 27

AD5415 Data Sheet MICROPROCESSOR INTERFACING Table 12 shows the setup for the SPORT control register. Microprocessor interfacing to the AD5415 DAC is through a Table 12. SPORT Control Register Setup serial bus that uses standard protocol compatible with micro- Name Setting Description controllers and DSP processors. The communication channel is TFSW 1 Alternate framing a 3-wire interface consisting of a clock signal, a data signal, and INVTFS 1 Active low frame signal a synchronization signal. The AD5415 requires a 16-bit word, DTYPE 00 Right justify data with the default being data valid on the falling edge of SCLK; ISCLK 1 Internal serial clock however, this is changeable using the control bits in the data-word. TFSR 1 Frame every word ADSP-21xx to AD5415 Interface ITFS 1 Internal framing signal The ADSP-21xx family of DSPs is easily interfaced to the AD5415 SLEN 1111 16-bit data-word DAC without the need for extra glue logic. Figure 41 is an example ADSP-BF504 to ADSP-BF592 Device Family to AD5415 of an SPI interface between the DAC and the ADSP-2191M. SCK Interface of the DSP drives the serial data line, SDIN. SYNC is driven from a port line, in this case SPIxSEL. The ADSP-BF504 to ADSP-BF592 device family of processors has an SPI-compatible port that enables the processor to comm- AADDSSPP--22119911MM11 AD54151 unicate with SPI-compatible devices. A serial interface between the BlackFin® processor and the AD5415 DAC is shown in SPIxSEL SYNC Figure 43. In this configuration, data is transferred through the MOSI SDIN MOSI (master output, slave input) pin. SYNC is driven by the SCK SCLK SPIxSEL pin, which is a reconfigured programmable flag pin. 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-041 ADSP-BF5xx1 AD54151 Figure 41. ADSP-2191M SPI to AD5415 Interface SPIxSEL SYNC A serial interface between the DAC and DSP SPORT is shown MOSI SDIN in Figure 42. In this interface example, SPORT0 is used to transfer SCK SCLK data to the DAC shift register. Transmission is initiated by writing a wdaotrad i sto c tlohec kTexd r oeguits toenr aefatcehr SrPisOinRgT e idsg een oabf ltehde. IDnS aP w sreirteia sl ecqluoecnkc e, 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-052 and clocked into the DAC input shift register on the falling edge Figure 43. ADSP-BF504 to ADSP-BF592 Device Family to AD5415 Interface (ADSP-BFxx Denotes the ADSP-BF504 to ADSP-BF592) of the SCLK. The update of the DAC output takes place on the rising edge of the SYNC signal. The ADSP-BF504 to ADSP-BF592 device family processors incorporates channel synchronous serial ports (SPORT). A serial interface between the DAC and the DSP SPORT is shown in ADSP-2191M1 AD54151 Figure 44. When SPORT is enabled, initiate transmission by TFS SYNC writing a word to the Tx register. The data is clocked out on DT SDIN each rising edge of the DSP serial clock and clocked into the SCLK SCLK DAC input shift register on the falling edge of the SCLK. The 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-042 DroAnCiz aotuiotpnu (tT iFs Su)p ldinaete tdo bpyr ouvsiidneg at hSeY tNraCn ssmigint aflr.a me synch- Figure 42. ADSP-2191M SPORT to AD5415 Interface ADSP-BF5xx1 AD54151 Communication between two devices at a given clock speed is possible when the following specifications are compatible: frame TFS SYNC sync delay and frame sync setup and hold, data delay and data DT SDIN setup and hold, and SCLK width. The DAC interface expects a SCLK SCLK t (SYNC falling edge to SCLK falling edge setup time) of 13 ns m4inimum. See the ADSP-21xx device family for information on 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-051 clock and frame SYNC frequencies for the SPORT register. Figure 44. ADSP-BF504 to ADSP-BF592 Device Family SPORT to AD5415 Interface (ADSP-BFxx Denotes the ADSP-BF504 to ADSP-BF592) Rev. F | Page 22 of 27

Data Sheet AD5415 80C51/80L51 to AD5415 Interface MC68HC111 AD54151 A serial interface between the DAC and the 80C51 is shown in PC7 SYNC Figure 45. TxD of the 80C51 drives SCLK of the DAC serial SCK SCLK interface, and RxD drives the serial data line, SDIN. P1.1 is a MOSI SDIN bit-programmable pin on the serial port and is used to drive SYNC. When data is to be transmitted to the switch, P1.1 is 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-044 taken low. The 80C51/80L51 only transmits data in 8-bit bytes; Figure 46. MC68HC11 to AD5415 Interface therefore, only eight falling clock edges occur in the transmit If the user wants to verify the data previously written to the cycle. To load data correctly to the DAC, P1.1 is left low after input shift register, the SDO line can be connected to MISO of the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. Data on RxD is the MC68HC11, and, with SYNC low, the shift register clocks clocked out of the microcontroller on the rising edge of TxD data out on the rising edges of SCLK. and is valid on the falling edge of TxD. As a result, no glue logic MICROWIRE to AD5415 Interface is required between the DAC and microcontroller interface. Figure 47 shows an interface between the DAC and any P1.1 is taken high following the completion of this cycle. The MICROWIRE-compatible device. Serial data is shifted out on 80C51 provides the LSB of the SBUF register as the first bit in the falling edge of the serial clock, SK, and is clocked into the the data stream. The DAC input register requires the data with DAC input shift register on the rising edge of SK, which the MSB as the first bit received. The transmit routine must take corresponds to the falling edge of the DAC SCLK. this into account. MICROWIRE1 AD54151 80511 AD54151 SK SCLK TxD SCLK SO SDIN RxD SDIN CS SYNC P1.1 SYNC 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-043 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-045 Figure 47. MICROWIRE to AD5415 Interface Figure 45. 80C51/80L51 to AD5415 Interface PIC16C6x/PIC16C7x to AD5415 Interface MC68HC11 to AD5415 Interface The PIC16C6x/PIC16C7x (Microchip) synchronous serial port Figure 46 is an example of a serial interface between the DAC and (SSP) is configured as an SPI master with the clock polarity bit the MC68HC11 microcontroller (Motorola). The serial peripheral (CKP) = 0. This is done by writing to the synchronous serial interface (SPI) on the MC68HC11 is configured for master mode port control register (SSPCON). In this example, the input/output (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock phase port RA1 is used to provide a SYNC signal and enable the serial bit (CPHA) = 1. The SPI is configured by writing to the SPI control port of the DAC. This microcontroller transfers only eight bits register (SPCR); see the 68HC11 User Manual. SCK of the 68HC11 of data during each serial transfer operation; therefore, two drives the SCLK of the DAC interface; the MOSI output drives consecutive write operations are required. Figure 48 shows the the serial data line (SDIN) of the DAC. connection diagram. The SYNC signal is derived from a port line (PC7). When data is transmitted to the AD5415, the SYNC line is taken low (PC7). PIC16C6x/7x1 AD54151 Data appearing on the MOSI output is valid on the falling edge of SCK/RC3 SCLK SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with SDI/RC4 SDIN only eight falling clock edges occurring in the transmit cycle. Data RA1 SYNC iasf tterra tnhsem fiirtstet dei gMhSt Bbi tfsi rasrte. Ttroa nlosfaedr rdeadt aa ntod tpheer DfoArmC, ale saevceo PnCd7 s elorwia l 1ADDITIONAL PINS OMITTED FOR CLARITY. 04461-046 write operation to the DAC. PC7 is taken high at the end of this Figure 48. PIC16C6x/PIC16C7x to AD5415 Interface procedure. Rev. F | Page 23 of 27

AD5415 Data Sheet PCB LAYOUT AND POWER SUPPLY DECOUPLING Components, such as clocks, that produce fast switching signals must be shielded with digital ground to avoid radiating noise to In any circuit where accuracy is important, careful considera- other parts of the board, and they must never be run near the tion of the power supply and ground return layout ensures the reference inputs. rated performance. The PCB on which the AD5415 is mounted must be designed so that the analog and digital sections are Avoid crossover of digital and analog signals. Traces on opposite separated and confined to certain areas of the board. If the DAC sides of the board must run at right angles to each other. This is in a system where multiple devices require an AGND to DGND reduces the effects of feedthrough on the board. A microstrip connection, the connection must be made at one point only. The technique is by far the best, but the use of the technique is not star ground point must be established as close as possible always possible with a double-sided board. In this technique, to the device. the component side of the board is dedicated to the ground plane, and signal traces are placed on the soldered side. The DAC must have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close as possible to the It is good practice to use a compact, minimum lead length PCB package, ideally right up against the device. The 0.1 µF capacitor layout design. Leads to the input must be as short as possible to must have low effective series resistance (ESR) and low effective minimize IR drops and stray inductance. series inductance (ESI), like the common ceramic types of The PCB metal traces between V and R must also be REF FB capacitors that provide a low impedance path to ground at high matched to minimize gain error. To maximize high frequency frequencies, to handle transient currents due to internal logic performance, the I-to-V amplifier must be located as close as switching. Low ESR 1 µF to 10 µF tantalum or electrolytic possible to the device. capacitors must also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple. Rev. F | Page 24 of 27

Data Sheet AD5415 OVERVIEW OF THE AD5424 TO AD5547 DEVICES Table 13. Part No. Resolution No. DACs INL (LSB) Interface Package1 Features AD5424 8 1 ±0.25 Parallel RU-16, CP-20 10 MHz BW, 17 ns CS pulse width AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial AD5428 8 2 ±0.25 Parallel RU-20 10 MHz BW, 17 ns CS pulse width AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial AD5450 8 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial AD5440 10 2 ±0.5 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5451 10 1 ±0.25 Serial UJ-8 10 MHz BW, 50 MHz serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial AD5405 12 2 ±1 Parallel CP-40 10 MHz BW, 17 ns CS pulse width AD5445 12 2 ±1 Parallel RU-20, CP-20 10 MHz BW, 17 ns CS pulse width AD5447 12 2 ±1 Parallel RU-24 10 MHz BW, 17 ns CS pulse width AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial AD5452 12 1 ±0.5 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5556 14 1 ±1 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5557 14 2 ±1 Parallel RU-38 4 MHz BW, 20 ns WR pulse width AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock AD5546 16 1 ±2 Parallel RU-28 4 MHz BW, 20 ns WR pulse width AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock AD5547 16 2 ±2 Parallel RU-38 4 MHz BW, 20 ns WR pulse width 1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT. Rev. F | Page 25 of 27

AD5415 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution INL (LSB) Temperature Range Package Description Package Option AD5415YRUZ 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 AD5415YRUZ-REEL 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 AD5415YRUZ-REEL7 12 ±1 −40°C to +125°C 24-Lead TSSOP RU-24 EV-AD5415/49SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. F | Page 26 of 27

Data Sheet AD5415 NOTES ©2004–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04461-0-12/15(F) Rev. F | Page 27 of 27