Real-Time Analog Computational Unit (ACU) AD538 FEATURES FUNCTIONAL BLOCK DIAGRAM V = V (V /V )m transfer function O Y Z X IX D Wide dynamic range (denominator) −1000:1 25kΩ 100Ω VX Simultaneous multiplication and division Resistor-programmable powers and roots LOG B RATIO No external trims required Low input offsets <100 μV 25kΩ VZ A Low error ±0.25% of reading (100:1 range) 100Ω IZ Monolithic construction Real-time analog multiplication, division and +10V INTERNAL VOLTAGE exponentiation +2V REFERENCE High accuracy analog division with a wide input dynamic range VY 25kΩ On board +2 V or +10 V scaling reference IY AD538 LOG Voltage and current (summing) input modes Monolithic construction with lower cost and higher C ANTILOG reliability than hybrid and modular circuits I OUTPUT AOnPeP- LoIrC twATo-IqOuNadSr ant multiply/divide VO00959-001 Figure 1. Log ratio computation Squaring/square rooting Trigonometric function approximations Linearization via curve fitting Precision AGC Power functions GENERAL DESCRIPTION The AD538 is a monolithic real-time computational circuit multiplication and division can be set using the on-chip +2 V or that provides precision analog multiplication, division, and +10 V references, or controlled externally to provide simultaneous exponentiation. The combination of low input and output offset multiplication and division. Exponentiation with an m value voltages and excellent linearity results in accurate computation from 0.2 to 5 can be implemented with the addition of one or over an unusually wide input dynamic range. Laser wafer two external resistors. trimming makes multiplication and division with errors as low Direct log ratio computation is possible by using only the log as 0.25% of reading possible, while typical output offsets of ratio and output sections of the chip. Access to the multiple 100 μV or less add to the overall off-the-shelf performance level. summing junctions adds further to the flexibility of the AD538. Real-time analog signal processing is further enhanced by the Finally, a wide power supply range of ±4.5 V to ±18 V allows 400 kHz bandwidth of the device. operation from standard ±5 V, ±12 V and ±15 V supplies. The overall transfer function of the AD538 is V = V (V /V )m. O Y Z X The AD538 is available in two accuracy grades (A and B) over Programming a particular function is via pin strapping. No the industrial (−25°C to +85°C) temperature range and one external components are required for one-quadrant (positive grade (S) over the military (−55°C to +125°C) temperature input) multiplication and division. Two-quadrant (bipolar range. The device is packaged in an 18-lead TO-118 hermetic numerator) division is possible with the use of external level side-brazed ceramic DIP. A-grade chips are also available. shifting and scaling resistors. The desired scale factor for both Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

AD538 TABLE OF CONTENTS Features .............................................................................................. 1 Stability Precautions ................................................................... 10 Applications ....................................................................................... 1 Using The Voltage References .................................................. 10 Functional Block Diagram .............................................................. 1 One-Quadrant Multiplication/Division .................................. 11 General Description ......................................................................... 1 Two-Quadrant Division ............................................................ 12 Revision History ............................................................................... 2 Log Ratio Operation .................................................................. 12 Specifications ..................................................................................... 3 Analog Computation Of Powers And Roots .......................... 13 Absolute Maximum Ratings ............................................................ 5 Square Root Operation .............................................................. 13 ESD Caution .................................................................................. 5 Applications Information .............................................................. 15 Pin Configuration and Function Descriptions ............................. 6 Transducer Linearization .......................................................... 15 Typical Performance Characteristics ............................................. 7 ARC-Tangent Approximation .................................................. 15 Theory of Operation ........................................................................ 9 Outline Dimensions ....................................................................... 16 Re-Examination of Multiplier/Divider Accuracy .................... 9 Ordering Guide .......................................................................... 16 Functional Description .............................................................. 10 REVISION HISTORY 6/11—Rev. D to Rev. E Updated Format .................................................................. Universal Added Table 3 .................................................................................... 6 Changes to Ordering Guide .......................................................... 11 5/10—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 11 Rev. E | Page 2 of 16

AD538 SPECIFICATIONS V = ±15 V, T = 25°C, unless otherwise noted. S A Table 1. Test Conditions/ AD538AD AD538BD AD538SD Parameter Comments Min Typ Max Min Typ Max Min Typ Max Unit MULTIPLIER DIVIDER PERFORMANCE Nominal Transfer Function 10 V ≥ VX, VY, VZ ≥ 0 VO = VY(VZ/VX)m VO = VY(VZ/VX)m VO = VY(VZ/VX)m 400 µA ≥ IX, IY, IZ ≥ 0 VO = 25 kΩ × IY(IZ/IX)m VO = 25 kΩ × IY(IZ/IX)m VO = 25 kΩ × IY(IZ/IX)m Total Error Terms 100 mV ≤ V ≤ 10 V ±0.5 ±1 ±0.25 ±0.5 ±0.5 ±1 % of Reading + X 100:1 Input 100 mV ≤ V ≤ 10 V ±200 ±500 ±100 ±250 ±200 ±500 µV Y Range1 100 mV ≤ V ≤ 10 V Z V ≤ 10 V, m = 1.0 Z X T = T to T ±1 ±2 ±0.5 ±1 ±1.25 ±2.5 % of Reading + A MIN MAX ±450 ±750 ±350 ±500 ±750 ±1000 µV Wide Dynamic 100 mV ≤ V ≤ 10 V ±1 ±2 ±0.5 ±1 ±1 ±2 % of Reading + X Range2 100 mV ≤ V ≤ 10 V ±200 ±500 ±100 ±250 ±200 ±500 µV Y 100 mV ≤ V ≤ 10 V ±100 ±250 ±750 ±150 ±200 ±250 µV × (V + V)/V Z Y Z X V ≤ 10 V, m = 1.0 Z X T = T to T ±1 ±3 ±1 ±2 ±2 ±4 % of Reading + A MIN MAX ±450 ±750 ±350 ±500 ±750 ±1000 µV + ±450 ±750 ±350 ±500 ±750 ±1000 µV × (V + Y V)/V Z X Exponent (m) T = T to T 0.2 5 0.2 5 0.2 5 A MIN MAX Range OUTPUT CHARACTERISTICS Offset Voltage V = 0, V = ±200 ±500 ±100 ±250 ±200 ±500 µV Y C −600 mV T = T to T ±450 ±750 ±350 ±500 ±750 ±1000 µV A MIN MAX Output Voltage R = 2 kΩ −11 +11 −11 +11 −11 +11 V L Swing Output Current 5 10 5 10 5 10 mA FREQUENCY RESPONSE Slew Rate 1.4 1.4 1.4 V/µs Small Signal 100 mV ≤ 10 V, V, 400 400 400 kHz Y Z Bandwidth V ≤ 10 V X VOLTAGE REFERENCE Accuracy V = 10 V or 2 V ±25 ±50 ±15 ±25 ±25 ±50 mV REF Additional Error T = T or T ±20 ±30 ±20 ±30 ±30 ±50 mV A MIN MAX Output Current V = 10 V to 2 V 1 2.5 1 2.5 1 2.5 mA REF Power Supply Rejection +2 V = V ±4.5 V ≤ V ≤ ±18 V 300 600 300 600 300 600 µV/V REF S +10 V = V ±13 V ≤ V ≤ ±18 V 200 500 200 500 200 500 µV/V REF S POWER SUPPLY Rated R = 2 kΩ ±15 ±15 ±15 V L Operating Range3 ±4.5 ±18 ±4.5 ±18 ±4.5 ±18 V PSRR ±4.5 V<, V < ±18 V 0.5 0.1 0.5 0.1 0.5 0.1 %/V S V = V = V = 1 V X Y Z V = 1 V O Quiescent Current 4.5 7 4.5 7 4.5 7 mA Rev. E | Page 3 of 16

AD538 Test Conditions/ AD538AD AD538BD AD538SD Parameter Comments Min Typ Max Min Typ Max Min Typ Max Unit TEMPERATURE RANGE Rated −25 +85 −25 +85 −55 +125 °C Storage −65 +150 −65 +150 −65 +150 °C 1 Over the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error. 2 The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by the incremental gain (V + V) V. Y Z X 3 When using supplies below ±13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly. Rev. E | Page 4 of 16

AD538 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage ±18 V other conditions above those indicated in the operational Internal Power Dissipation 250 mW section of this specification is not implied. Exposure to absolute Output Short Circuit-to-Ground Indefinite maximum rating conditions for extended periods may affect Input Voltages V , V, V (+V − 1 V), −1 V X Y Z S device reliability. Input Currents I , I , I , I 1 mA X Y Z O Operating Temperature Range −25°C to +85°C Storage Temperature Range −65°C to +150°C ESD CAUTION Lead Temperature, Storage 60 sec, +300°C Thermal Resistance θ 35°C/W JC θ 120°C/W JA Rev. E | Page 5 of 16

AD538 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS IZ 1 18 A VZ 2 17 D B 3 16 IX AD538 +10V 4 15 VX TOP VIEW +2V 5 (Not to Scale) 14 SIGNAL GND +VS 6 13 PWR GND –VS 7 12 C VOI 89 1110 IVYY 00959-002 Figure 2. Pin Configuration Table 3. Pin No. Mnemonic Description 1 I Current Input for the Z Multiplicand. Z 2 V Voltage Input for the Z Multiplicand. Z 3 B Output of the Log Ratio Differential Amplifier. This amplifier subtracts the log of the Z input from the log of the X input, or performs the equivalent logarithmic equivalent of long division. 4 +10V +10 V Reference Voltage Output. 5 +2V +2 V Reference Voltage Output. 6 +V Positive Supply Rail. S 7 –V Negative Rail. S 8 V Output Voltage. O 9 I Current Input to the Output Amplifier. 10 V Voltage Input to the Y Multiplicand. Y 11 I Current Input to the Y Multiplicand. Y 12 C Current Input to the Base of the Antilog Log-to-Linear Converter. 13 PWR GND High level Power Return of the Chip. 14 SIGNAL GND Low Level Ground Return of the Device. 15 V Voltage Input of the X Multiplicand. X 16 I Current Input of the X Input Multiplicand. X 17 D Use for Log Ratio Function. 18 A Use for Log Ratio Function. Rev. E | Page 6 of 16

AD538 TYPICAL PERFORMANCE CHARACTERISTICS 5 1000 1M VY = 10V dc VZ = VX +0.05 VX SIN ωt DING ERROR 43 860000 OFFSET (µV) NDWIDTH (Hz)400k OF REA 2 400 STAGE NAL BA100k TOTAL % 1 OFFSET 200 OUTPUT MALL SIG 40k S % OF READING 0–55 –40 –20 0 TEM2P0ERAT4U0RE (°6C0) 80 100 1250 00959-003 10k0.01 DENOM0I.N1ATOR VOLTAGE, V1X – V dc 10 00959-006 Figure 3. Multiplier Error vs. Temperature (100 mV < V, V, V ≤ 10 V) Figure 6. Small Signal Bandwidth vs. Denominator Voltage (One-Quadrant X Y Z Mult/Div) 5 1000 6 1200 5 1000 OR 4 800 V) OR V) G ERR SET (µ G ERR 4 800 SET (µ DIN 3 600 OFF DIN OFF OF REA 2 400 STAGE OF REA 3 600 STAGE % T % T TOTAL 1 OFFSET 200 OUTPU TOTAL 2 % OF READING 400 OUTPU 1 200 % OF READING OFFSET 0–55 –40 –20 0 TEM2P0ERAT4U0RE (°6C0) 80 100 1250 00959-004 0–55 –40 –20 0 TEM2P0ERAT4U0RE (°6C0) 80 100 1250 00959-007 Figure 4. Divider Error vs. Temperature (100 mV < V, V, V ≤ 10 V) Figure 7. Multiplier Error vs. Temperature (10 mV < V, V, V ≤ 100 mV) X Y Z X Y Z 1000 5 1000 VX = 10V VY = 0V VZ = 5V +5V SIN ωt VOLTS OR 4 800 V) 100 G ERR SET (µ V (mV p-p)O OF READIN 32 640000 STAGE OFF 10 TOTAL % 1 % OF READING 200 OUTPUT OFFSET 1100 1k INPUT FRE1Q0UkENCY (Hz) 100k 1M 00959-005 0–55 –40 –20 0 TEM2P0ERAT4U0RE (°6C0) 80 100 1250 00959-008 Figure 5. V Feedthrough vs. Frequency Figure 8. Divider Error vs. Temperature (10 mV < V, V, V ≤ 100 mV) Z X Y Z Rev. E | Page 7 of 16

AD538 150 5 VX = 10V FOR THE FREQUENCY RANGE OF 10Hz VY = 5V +5V SIN ωt VOLTS TO 100kHz THE TOTAL rms OUTPUT VZ = 0V NOISE, eo, FOR A GIVEN BANDWIDTH 100 Hz) 4 Bw, IS CALCULATED eo = en Bw. V/ µ – V (mV p-p)O 10 E NOISE (e n 32 VX = 0.01V G A T 1 OL VX = 10V V 1 0.1100 1k INPUT FRE1Q0UkENCY (Hz) 100k 1M 00959-009 00.01 D0C.1 OUTPUT VOLTAGE 1(V) 1000959-010 Figure 9. V Feedthrough vs. Frequency Figure 10. 1 kHz Output Noise Spectral Density vs. DC Output Voltage Y Rev. E | Page 8 of 16

AD538 THEORY OF OPERATION RE-EXAMINATION OF MULTIPLIER/DIVIDER ACCURACY total error calculations for both grades over the 100:1 input Traditionally, the accuracy (actually the errors) of analog range are illustrated in Table 4. This error specification format multipliers and dividers has been specified in terms of percent is a familiar one to designers and users of digital voltmeters of full scale. Thus specified, a 1% multiplier error with a 10 V where error is specified as a percent of reading ± a certain full-scale output would mean a worst-case error of +100 mV at number of digits on the meter readout. any level within its designated output range. While this type of error specification is easy to test evaluate, and interpret, it can For operation as a multiplier or divider over a wider dynamic leave the user guessing as to how useful the multiplier actually range (>100:1), the AD538 has a more detailed error specification is at low output levels, those approaching the specified error that is the sum of three components: a percent of reading term, limit (in this case) 100 mV. an output offset term, and an input offset term for the V /V log Y X ratio section. A sample application of this specification, taken The error sources of the AD538 do not follow the percent of from Table 4, for the AD538AD with V = 1 V, V = 100 mV full-scale approach to specification, thus it more optimally Y Z and V = 10 mV would yield a maximum error of ±2.0% of fits the needs of the very wide dynamic range applications X reading ±500 μV ± (1 V + 100 mV)/10 mV × 250 μV or ±2.0% for which it is best suited. Rather than as a percent of full of reading ±500 μV ± 27.5 mV. This example illustrates that scale, the AD538’s error as a multiplier or divider for a 100:1 with very low level inputs the AD538’s incremental gain (V + (100 mV to 10 V) input range is specified as the sum of two Y V )/V has increased to make the input offset contribution to error components: a percent of reading (ideal output) term Z X error substantial. plus a fixed output offset. Following this format, the AD538AD, operating as a multiplier or divider with inputs down to 100 mV, has a maximum error of ±1% of reading ±500 μV. Some sample Table 4. Sample Error Calculation Chart (Worst Case) Total Error V V V Ideal % of Reading Total Error Summation as a Y Z X Input Input Input Output Total Offset Error Error Term Summation % of the Ideal (V) (V) (V) (V) Term (mV) (mV) (mV) Output 100:1 INPUT 10 10 10 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD) RANGE 0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD) Total Error = ±% rdg 10 0.1 0.1 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD) ±Output V OS 0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD) 1 1 1 1 0.5 (AD) 10 ) (AD 10.5 (AD) 1.05 (AD) 0.25 (BD) 5 (BD) 5.25 (BD) 0.5 (BD) 0.1 0.1 0.1 0.1 0.5 (AD) 1 (AD) 1.5 (AD) 1.5 (AD) 0.25 (BD) 0.5 (BD) 0.75 (BD) 0.75 (BD) WIDE 1 0.10 0.01 10 28 (AD) 200 (AD) 228 (AD) 2.28 (AD) DYNAMIC 16.75 (BD) 100 (BD) 116.75 (BD) 1.17 (BD) RANGE Total Error = 10 0.05 2 0.25 1.76 (AD) 5 (AD) 6.76 (AD) 2.7 (AD) ±% rdg ± Output V ± 1 (BD) 2.5 (BD) 3.5 (BD) 1.4 (BD) OS Input V × OS (VY + VZ)/VX 5 0.01 0.01 5 125.75 (AD) 100 (AD) 225.75 (AD) 4.52 (AD) 75.4 (BD) 50 (BD) 125.4 (BD) 2.51 (BD) 10 0.01 0.1 1 25.53 (AD) 20 (AD) 45.53 (AD) 4.55 (AD) 15.27 (BD) 10 (BD) 25.27 (BD) 2.53 (BD) Rev. E | Page 9 of 16

AD538 FUNCTIONAL DESCRIPTION STABILITY PRECAUTIONS As shown in Figure 1 and Figure 11, the V and V inputs At higher frequencies, the multistaged signal path of the AD538 Z X connect directly to the input log ratio amplifiers of the AD538. can result in large phase shifts (as illustrated in Figure 11). If a This subsection provides an output voltage proportional to the condition of high incremental gain exists along that path (for natural log of input voltage, V , minus the natural log of input example, V = V × V /V = 10 V × 10 mV/10 mV = 10 V so Z O Y Z X voltage, V . The output of the log ratio subsection at B can be that ΔV /ΔV = 1000), then small amounts of capacitive feedback X O X expressed by the transfer function from V to the current inputs I or I can result in instability. O Z X Appropriate care should be exercised in board layout to prevent kT V  VB = q lnVZ  capacitive feedback mechanisms under these conditions. X IX Ln X Ln Z – Ln X where: LOGe M(Ln Z – Ln X) k is 1.3806 × 10−23 J/K. VX M(Ln Z – Ln X) +Ln Y q is 1.60219 × 10−19 C. – T is in Kelvins. +Σ 0.2≤M≤5 + Σ+ ANTILOGe BUFFER Ttleehvmeep ll oe(srgea ertua ttrhieoe c Acoopmnppfliiegcnuastriaaotteniodsn Ia nnmfdoa rysmc baaelet uidos nteo ds teahcleoti nodene,s) ii.fr ecdo roruetcptluyt VIZZ LOGe Ln Z VIYY LOGe Ln Y VO = VY VVZXM 00959-012 Figure 11. Model Circuit Under normal operation, the log-ratio output will be directly USING THE VOLTAGE REFERENCES connected to a second functional block at Input C, the antilog subsection. This section performs the antilog according to the A stable band gap voltage reference for scaling is included in the transfer function: AD538. It is laser-trimmed to provide a selectable voltage output of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages  q  V =V eV  between +2 V and +10.2 V buffered as shown in Figure 12. The O Y  C kT output impedance at Pin 5 is approximately 5 kΩ. Note that any As with the log-ratio circuit included in the AD538, the user loading of this pin produces an error in the +10 V reference may use the antilog subsection by itself. When both subsections voltage. External loads on the +2 V output should be greater are combined, the output at B is tied to C, the transfer function than 500 kΩ to maintain errors less than 1%. of the AD538 computational unit is: V = V ekQTkqTlnVVXZ;VB =VC IZ 1 25kΩ LOG 18 A O Y +2V TO +10.2V VZ 2 RATIO 17 D BUFFERED which reduces to: B 3 16 IX VO =VYVVXZ  REF OUT 4 100Ω 100Ω 25kΩ 15 VX Finally, by increasing the gain, or attenuating the output of the 50kΩ +2V 5 14 SGINGDNAL INTERNAL log ratio subsection via resistor programming, it is possible to 11.5kΩ +VS 6 RVEOFELRTEANGCEE AD538 13 PGWNDR raise the quantity V /V to the mth power. Without external Z X programming, m is unity. Thus, the overall AD538 transfer –VS 7 OUTPUT 12 C function equals: 25kΩ VO 8 ANTILOG 11 IY V m VO =VYVXZ  I 9 LOG 25kΩ 10 VY 00959-013 Figure 12. +2 V to +10.2 V Adjustable Reference where 0.2 < m < 5. In situations not requiring both reference levels, the +2 V output When the AD538 is used as an analog divider, the V input can Y can be converted to a buffered output by tying Pin 4 and Pin 5 be used to multiply the ratio V /V by a convenient scale factor. Z X together. If both references are required simultaneously, the The actual multiplication by the V input signal is accomplished Y +10 V output should be used directly and the +2 V output by adding the log of the V input signal to the signal at C, which Y should be externally buffered. is already in the log domain. Rev. E | Page 10 of 16

AD538 ONE-QUADRANT MULTIPLICATION/DIVISION When the input V is tied to the +10 V reference terminal, the X multiplier transfer function becomes: Figure 13 shows how the AD538 may be easily configured as a precision one-quadrant multiplier/divider. The transfer  V  function VO = VY (VZ/VX) allows three independent input VO =VY 10ZV variables, a calculation not available with a conventional multiplier. In addition, the 1000:1 (that is, 10 mV to 10 V) As a multiplier, this circuit provides a typical bandwidth of 400 kHz input dynamic range of the AD538 greatly exceeds that of with values of V , V , or V varying over a 100:1 range (that is, X Y Z analog multipliers computing one-quadrant multiplication 100 mV to 10 V). The maximum error with a 100 mV to 10 V and division. range for the two input variables will typically be +0.5% of reading. Using the optional Z offset trim scheme, as shown in VO = VY VVZX Figure 14, this error can be reduced to +0.25% of reading. By using the 10 V reference as the V input, the circuit of Y IZ 1 18 A Figure 13 is configured as a one-quadrant divider with a fixed INPUVTZ VZ 2 25kΩ RLAOTGIO 17 D asccacleep fta ocntolyr. sAinsg wlei t(hp othseit iovnee) -pqoulaadrirtayn sti gmnualltsi.p Tlihere, othuetp iuntp uoft st he B 3 16 IX one-quadrant divider with a +10 V scale factor is: +10V 4 100Ω 100Ω 25kΩ 15 SVIXGNAL IVNXPUT VO =10V VVZ  GND X +2V 5 14 INTERNAL PWR The typical bandwidth of this circuit is 370 kHz with 1 V to VOLTAGE GND +15V 6 REFERENCE AD538 13 10 V denominator input levels. At lower amplitudes, the band- C width gradually decreases to approximately 200 kHz at the –15V 7 OUTPUT 12 2 mV input level. VO 8 25kΩ 11 IY IN4148 ANTILOG OUTPUT I 9 LOG 25kΩ 10 VY VINYPUT00959-014 Figure 13. One-Quadrant Combination Multiplier/Divider By simply connecting the input, V (Pin 15) to the 10 V X reference (Pin 4), and tying the log-ratio output at B to the antilog input at C, the AD538 can be configured as a one- quadrant analog multiplier with 10 V scaling. If 2 V scaling is desired, V can be tied to the 2 V reference. X Rev. E | Page 11 of 16

AD538 TWO-QUADRANT DIVISION LOG RATIO OPERATION The two-quadrant linear divider circuit illustrated in Figure 14 Figure 15 shows the AD538 configured for computing the log uses the same basic connections as the one-quadrant version. of the ratio of two input voltages (or currents). The output However, in this circuit the numerator has been offset in the signal from B is connected to the summing junction of the positive direction by adding the denominator input voltage output amplifier via two series resistors. The 90.9 Ω metal film to it. The offsetting scheme changes the divider’s transfer resistor effectively degrades the temperature coefficient of the function from ±3500 ppm/°C resistor to produce a 1.09 kΩ +3300 ppm/°C equivalent value. In this configuration, the V input must V  Y VO =10 VVXZ  breem tioevdi ntog stohmis ein vpoultta fgreo mles tsh teh tarna nzesfreor (f−u1n.c2t iVo nin. this case) to The 5 kΩ potentiometer controls the circuit’s scale factor ( ) adjustment providing a +1 V per decade adjustment. The V +AV  V  VO=10V ZV X =10V1A+VZ  output offset potentiometer should be set to provide a zero X X output with VX = VZ = 1 V. The input VZ adjustment should V  be set for an output of 3 V with V = l mV and V = 1 V. =10A+10V Z  Z X VX  –VS where: AD589 658%kΩ VO = 1V LOG10 VVZX –1.2V 35kΩ A=  25kΩ 1MΩ 10MΩ IZ 1 18 A 48.7Ω OPTIONAL VZ 25kΩ LOG D As long as the magnitude of the denominator input is equal INPUT VOS 2 RATIO 17 ADJUSTMENT to or greater than the magnitude of the numerator input, the B 3 16 IX circuit accepts bipolar numerator voltages. However, under 90.9Ω the conditions of a 0 V numerator input, the output would 1% +10V 4 25kΩ 15 VX VINXPUT 1k 100Ω 100Ω SIGNAL incorrectly equal +14 V. The offset can be removed by connecting +3500 +2V 5 14 GND ppm/°C the 10 V reference through Resistors R1 and R2 to the output IVNOTLETRANGAEL PGWNDR +15V 6 REFERENCE AD538 13 section’s summing Node I at Pin 9 thus providing a gain of 1.4 OUTPUT C at the center of the trimming potentiometer. The potentiometer, –15V 7 OUTPUT 12 5kΩ 2kΩ R2, adjusts out or corrects this offset, leaving the desired 1% VO 8 25kΩ 11 IY transfer function of 10 V (V /V ). SCALE ANTILOG IN4148 Z X FAADCJTUOSRT I 9 LOG 10 VY NUMERATOR DENOMINATOR 25kΩ OPTIONAL VZ VX Z OFFSET TRIM +VS –VS68kΩ 35kΩ VO = 10 VVZX FOR VX ≥ VZ 10MΩ –VS10kΩ OOADPUJTTUIPOSUNTTAM VLEONST 00959-016 AD589 Figure 15. Log Ratio Circuit –1.2V VOS 1AMDΩJ 10MΩ IZ 1 18 A The log ratio circuit shown achieves ±0.5% accuracy in the log 3.9MΩ VZ 2 25kΩ RLAOTGIO 17 D 35kΩ domain for input voltages within three decades of input range: 10 mV to 10 V. This error is not defined as a percent of full- B IX 3 16 scale output, but as a percent of input. For example, using a +10V 4 25kΩ 15 VX 1 V/decade scale factor, a 1% error in the positive direction 100Ω 100Ω SGINGDNAL at the input of the log ratio amplifier translates into a 4.3 mV +2V 5 14 INTERNAL PWR deviation from the ideal OUTPUT (that is, 1 V × log (1.01) = VOLTAGE GND 10 +15V 6 REFERENCE AD538 13 4.3214 mV). An input error 1% in the negative direction is IN4148 –15V 7 OUTPUT 12 C slightly different, giving an output deviation of 4.3648 mV. OUTPUT R2 R1 VO 8 25kΩ ANTILOG 11 IY 10kΩ 12.4kΩ I 9 LOG 10 VY 25kΩ ZAEDRJUOST 00959-015 Figure 14. Two-Quadrant Division with 10 V Scaling Rev. E | Page 12 of 16

AD538 ANALOG COMPUTATION OF POWERS AND ROOTS SQUARE ROOT OPERATION It is often necessary to raise the quotient of two input signals to The explicit square root circuit of Figure 17 illustrates a precise a power or take a root. This could be squaring, cubing, square method for performing a real-time square root computation. rooting or exponentiation to some noninteger power. Examples For added flexibility and accuracy, this circuit has a scale factor include power series generation. With the AD538, only one or adjustment. two external resistors are required to set any desired power, over The actual square rooting operation is performed in this circuit the range of 0.2 to 5. Raising the basic quantity V /V to a Z X by raising the quantity V /V to the one-half power via the Z X power greater than one requires that the gain of the AD538’s log resistor divider network consisting of resistors R and R . For B C ratio subtractor be increased, via an external resistor between maximum linearity, the two resistors should be 1% (or better) the A and D pins. Similarly, a voltage divider that attenuates the ratio-matched metal film types. log ratio output between Point B and Point C will program the 1 V scaling is achieved by dividing-down the 2 V reference power to a value less than one. and applying approximately 1 V to both the V and V inputs. RA Y X In this circuit, the V input is intentionally set low, to about X B C A D 0.95 V, so that the V input can be adjusted high, permitting POWERS Y 3 12 18 17 a ±5% scale factor trim. Using this trim scheme, the output VVZY 210 VY ( V VR ZE F )m 8 VO m234 R196974A6..69ΩΩΩ v1o0 lVta gtoe 1w millV b ein wpuitth riann ±ge3 (m80V d ±B )0. .F2o%r ao fd tehcere iadseeadl ivnapluute d oyvnearm ai c 15 5 48.7Ω VREF VX range of 10 mV to 10 V (60 dB) the error is even less; here the RA =M19 6– Ω1 output will be within ±2 mV ± 0.2% of the ideal value. The RB = RC ≤ 200Ω bandwidth of the AD538 square root circuit is approximately RB RC 280 kHz with a 1 V p-p sine wave with a +2 V dc offset. B C This basic circuit may also be used to compute the cube, fourth ROOTS 3 12 or fifth roots of an input waveform. All that is required for a VVZY 210 VY ( V VR ZE F )m 8 VO 111m///234 111R005B000ΩΩΩ R144099C0..99ΩΩΩ sgeivleecnt erdo ostu icsh t hthaat tt thhee ciro rsruemct irsa btieot wofe erens 1is5to0 rΩs, RanCd a n2d00 R ΩB, .b e 15 1/5 162Ω 40.2Ω VREF VX RRBC= M 1 –1 00959-017 Talhloew osp tthioen uasl ea bofs obliuptoel avra liunep ucitr vcoulitta sgheosw. On nplrye ocendei onpg athmep A iDs 538 Figure 16. Basic Configurations and Transfer Functions for the AD538 required for the absolute value function because the I input of Z the AD538 functions as a summing junction. If it is necessary to preserve the sign of the input voltage, the polarity of the op amp output may be sensed and used after the computation to switch the sign bit of a DVM chip. Rev. E | Page 13 of 16

AD538 OPTIONAL VO= 1V V1IVN ABSOLUTEVALUE SECTION 5kΩ 10kΩ IZ 1 18 A 20kΩ IN4148 IN4148 VZ 2 25kΩ RLAOTGIO 17 D +VS B 3 16 IX 100RΩB * 20kΩ VOS 20kΩ 271 +10V 4 15 VX VIN 8 6 100Ω 100Ω 25kΩ SIGNAL 3 +2V +2V GND 4 AD OP-07 5 14 ORAD811 INTERNAL PWR –VS (TVOO S–VTSA)P +15V 6 RVEOFELTRAEGNECE AD538 13 GND C –15V 7 OUTPUT 12 VO VO 8 25kΩ ANTILOG 11 IY D1 I 9 LOG 10 VY IN4148 1kΩ 25kΩ 100Ω SCALEFACTOR TRIM 1kΩ *RREATSIIOST MOARTSC FHO 1R% B MEESTTAALC FCILUMRACY 100RΩC * 00959-018 Figure 17. Square Root Circuit Rev. E | Page 14 of 16

AD538 APPLICATIONS INFORMATION TRANSDUCER LINEARIZATION The (V − V) function is implemented in this circuit by θREF θ adding together the output, V, and an externally applied Many electronic transducers used in scientific, commercial or θ reference voltage, V , via an external AD547 op amp. The industrial equipment monitor the physical properties of a device θREF 1 μF capacitor connected around the AD547’s 100 kΩ feedback and/or its environment. Sensing (and perhaps compensating for) resistor frequency compensates the loop (formed by the amplifier changes in pressure, temperature, moisture or other physical between V and V ). phenomenon can be an expensive undertaking, particularly θ Y where high accuracy and very low nonlinearity are important. Vθ = [VθREF –Vθ] × VVZX1.21 θ =TAN–1 ZX In conventional analog systems accuracy may be easily increased by offset and scale factor trims; however, nonlinearity is usually IZ 1 18 A the absolute limitation of the sensing device. RA VZ 25kΩ LOG D 931Ω, 1% With the ability to easily program a complex analog function, VZ 2 RATIO 17 the AD538 can effectively compensate for the nonlinearities B 3 16 IX of an inexpensive transducer. The AD538 can be connected +10V 4 15 VX VX between the transducer preamplifier output and the next stage 100Ω 100Ω 25kΩ SIGNAL GND of monitoring or transmitting circuitry. The recommended +2V 5 14 INTERNAL PWR procedure for linearizing a particular transducer is first to find +15V +VS 6 RVEOFELRTEANGCEE AD538 13 GND 1µF the closest function which best approximates the nonlinearity –15V –VS 7 OUTPUT 12 C of the device and then, to select the appropriate exponent 1µF resistor value(s). Vθ VO 8 25kΩ ANTILOG 11 IY IN4148 ARC-TANGENT APPROXIMATION I 9 LOG 10 VY 25kΩ The circuit of Figure 18 is typical of those AD538 applications 0.1µF where the quantity V /V is raised to powers greater than one. Z X In an approximate arc-tangent function, the AD538 will accurately R1* +15V 10R02k*Ω 100kΩ compute the angle that is defined by X and Y displacements 2 7 10kΩ represented by input voltages V and V . With accuracy to FULL-SCALE AD547JH 6 X Z ADJUST 118kΩ w10it Vhi)n, tohnee A dDeg5r3e8e a(rfoc-rt iannpguetn vt oclitracgueist ibse mtwoereen p 1re0c0i sμeV th aannd 1µF 100kΩ 3 –145V *RFAIACLTCMIUO RR EMASCAIYTSCTHO R1S% FMOERT ABLEST 00959-019 conventional analog circuits and is faster than most digital Figure 18. The Arc-Tangent Function techniques. The circuit shown is set up for the transfer The V /V quantity is calculated in the same manner as in the B A function: one-quadrant divider circuit, except that the resulting quotient Vθ=(VθREF −Vθ)((VVXZ))1.21 itsh era pisoewde tro o trh me 1 f.a2c1t opro. wer. Resistor RA (nominally 931 Ω) sets For the highest arc-tangent accuracy the R1 and R2 external where: resistors should be ratio matched; however, the offset trim scheme shown in other circuits is not required since nonlinearity effects  Z  θ=Tan−1  are the predominant source of error. Also note that instability X  will occur as the output approaches 90° because, by definition, the arc-tangent function is infinite and therefore, the gain of the AD538 will be extremely high. Rev. E | Page 15 of 16

AD538 OUTLINE DIMENSIONS 0.005 (0.13) MIN 0.098 (2.49) MAX 18 10 0.310 (7.87) PIN 1 0.220 (5.59) 1 9 0.320 (8.13) 0.290 (7.37) 0.200 (5.08) 0.960 (24.38) MAX 0.060 (1.52) MAX 0.015 (0.38) 0.150 (3.81) 0.200 (5.08) MIN 0.125 (3.18) 0.100 0.070 (1.78)SEATING 0.015 (0.38) 0.023 (0.58) (B2.S5C4) 0.030 (0.76)PLANE 0.008 (0.20) 0.014 (0.36) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 19. 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] (D-18) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD538ACHIPS −25°C to +85°C Chips AD538AD −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD538ADZ −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD538BD −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD538BDZ −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD538SD −55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 AD538SD/883B −55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18 1 Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00959-0-6/11(E) Rev. E | Page 16 of 16

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