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AD537–SPECIFICATIONS (typical @ +25(cid:2)C with V (total) = 5 V to 36 V, unless otherwise noted) S AD537KD AD537SD1 Model AD537JH AD537JD AD537KH AD537SH1 CURRENT-TO-FREQUENCY CONVERTER Frequency Range 0kHz to 150kHz * * * Nonlinearity1 f = 10kHz 0.15% max (0.1% typ) * 0.07% max ** MAX f = 100kHz 0.25% max (0.15% typ) * 0.1% max ** MAX Full-Scale Calibration Error C = 0.01µF, I = 1.000mA ±10% max ±7% max ±5% max * * IN vs. Supply (f < 100kHz) ±0.1%/V max (0.01% typ) * * * MAX vs. Temp (T to T ) ±150ppm/°C max (50ppm typ) * 50ppm/°C max (30ppm typ)2 250ppm/°C max MIN MAX ANALOG INPUT AMPLIFIER (Voltage-to-Current Converter) Voltage Input Range Single Supply 0 to (+V – 4) Volts (min) * * * S Dual Supply –V to (+V – 4) Volts (min) * * * S S Input Bias Current (Either Input) 100nA * * * Input Resistance (Noninverting) 250MΩ * * * Input Offset Voltage (Trimmable in “D” Package Only) 5mV max * 2 mV max ** vs. Supply 200µV/V max 100µV/V max 100µV/V max ** vs. Temp (T to T ) 5µV/°C * 1µV/°C 10µV/°C max MIN MAX Safe Input Voltage3 ±V * * * S REFERENCE OUTPUTS Voltage Reference Absolute Value 1.00 Volt ± 5% max * * * vs. Temp (T to T ) 50ppm/°C * 100 ppm/°C max ** MIN MAX vs. Supply ±0.03%/V max * * * Output Resistance4 380Ω * * * Absolute Temperature Reference5 Nominal Output Level 1.00mV/K * * * Initial Calibration @ +25°C 298mV (±5mV typ) * 298mV (±5mV max) ** Slope Error from 1.00mV/K ±0.02mV/K * * * Slope Nonlinearity ±0.1K * * * Output Resistance5 900Ω * * * OUTPUT INTERFACE (Open Collector Output) (Symmetrical Square Wave) Output Sink Current in Logic “0” V = 0.4V max (T to T ) 20mA min 20mA min 20mA min 10 mA min OUT MIN MAX Output Leakage Current in Logic “1” (T to T ) 200nA max * * 2µA max MIN MAX Logic Common Level Range –V to (+V – 4) Volts * * * S S Rise/Fall Times (C = 0.01µF) T I = lmA 0.2 µs * * * IN I = 1µA 1µs * * * IN POWER SUPPLY Voltage, Rated Performance Single Supply 4.5V to 36V * * * Dual Supply ±5V to ±18V * * * Quiescent Current 1.2 mA (2.5 mA max) * * * TEMPERATURE RANGE Rated Performance 0°C to +70°C * * –55°C to +125°C Storage –65°C to +150°C * * * PACKAGE OPTIONS6, 7 D-14 Ceramic DIP AD537JD AD537KD AD537SD H-10A Header AD537JH AD537KH AD537SH NOTES *Specifications same as AD537JH. **Specifications same as AD537K. 1Nonlinearity is specified for a current input level (I ) to the converter from 0.1µA to 1000µA. Converter has 100% overrange capability up to I = 2000µA with slightly IN IN reduced linearity. Nonlinearity is defined as deviation from a straight line from zero to full scale, expressed as a percentage of full scale. 2Guaranteed not tested. 3Maximum voltage input level is equal to the supply on either input terminal. However, large negative voltage levels can be applied to the negative terminal if the input is scaled to a nominal 1mA full scale through an appropriate value resistor (See Figure 2). 4Loading the 1.0 volt or 1mV/K outputs can cause a significant change in overall circuit performance, as indicated in the applications section. To maintain normal operation, these outputs should be operated into the external buffer or an external amplifier. 5Temperature reference output performance is specified from 0°C to +70°C for “J” and “K” devices, –55°C to +125°C for “S” model. 6D = Ceramic DIP; H = Hermetic Metal Can. For outline information see Package Information section. 7For AD537/883B specifications, refer to Analog Devices Military Products Databook. Specifications subject to change without notice. –2– REV. C

Applying the AD537 CIRCUIT OPERATION V-F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE Block diagrams of the AD537 are shown above. A versatile OR CURRENT operational amplifier (BUF) serves as the input stage; its pur- A wide range of negative input voltages can be accommodated pose is to convert and scale the input voltage signal to a drive with proper selection of the scaling resistor, as indicated in Fig- current in the NPN follower. Optimum performance is achieved ure 2. This connection, unlike the buffered positive connection, when, at the full-scale input voltage, a 1mA drive current is is not high impedance since the 1mA F.S. drive current must be delivered to the current-to-frequency converter. The drive cur- supplied by the signal source. However, very large negative volt- rent to the current-to-frequency converter (an astable ages beyond the supply can be handled easily; just modify the multivibrator) provides both the bias levels and the charging scaling resistors appropriately. Diode CR1 (HP50822811) is current to the externally connected timing capacitor. This necessary for overload and latchup protection for current or “adaptive” bias scheme allows the oscillator to provide low non- voltage inputs. linearity over the entire current input range of 0.1µA to If the input signal is a true current source, R1 and R2 are not 2000µA. The square wave oscillator output goes to the output used. Full-scale calibration can be accomplished by connecting a driver which provides a floating base drive to the NPN power 200kΩ pot in series with a fixed 27kΩ from Pin 7 to –V (see transistor. This floating drive allows the logic interface to be ref- S calibration section, below). erenced to a different level than –V . The “SYNC” input (“D” S package only) allows the oscillator to be slaved to an external master oscillator; this input can also be used to shut off the FOUT =1I0INC AD537 FO =10 (R1V I+N R2) C oscillator. 1 14 fOUT The reference generator uses a bandgap circuit (this allows 0 TIION –1mA 2 DRIVER 13 5kΩ (TYP) +VS single-supply operation to 4.5 volts which is not possible with 3 12 laomwp Tlif.iCer. aZnedn eorssc)i ltloa tporro svtiadgee st.h eT rheef erreefnerceen acne dg ebniaesr aletovre lasl sfoor p trhoe- R1 CR1 4 BUF TOCU-FRRRE-Q 11 C CONV vides the precision, low T.C. 1.00 volt output and the V R2 5 10 TEMP output which tracks absolute temperature at 1mV/K. 6 VT PRECISION 9 20kΩ V-F CONNECTION FOR POSITIVE INPUT VOLTAGES 0 TOV I–N10V 7 VR RVEOFELRTAEGNCEE 8 The positive voltage input range is from –V (ground in single S supply operation) to 4 volts below the positive supply. The con- Figure 2.V-F Connections for Negative Input Voltage or nection shown in Figure 1 provides a very high (250MΩ) input Current impedance. The input voltage is converted to the proper drive current at Pin 3 by selecting a scaling resistor. The full-scale CALIBRATION current is 1mA, so, for example a 10 volt range would require a There are two independent adjustments: scale and offset. The nominal 10kΩ resistor. The trim range required will depend on first is trimmed by adjustment of the scaling resistor R and the capacitor tolerance. Full-scale currents other than 1mA can be second by the (optional) potentiometer connected to +V and S chosen, but linearity will be reduced; 2mA is the maximum the V pins (“D” package only). Precise calibration requires the OS allowable drive. use of an accurate voltage standard set to the desired FS value and a frequency meter; a scope is useful for monitoring output As indicated by the scaling relationship in Figure 1, a 0.01µF waveshape. Verification of linearity requires the availability of a timing capacitor will give a 10kHz full-scale frequency, and switchable voltage source (or a DAC) having a linearity error 0.001µF will give 100kHz with a 1mA drive current. The below ±0.005%, and the use of long measurement intervals to maximum frequency is 150kHz. Polystyrene or NPO ceramic minimize count uncertainties. Every AD537 is automatically tested capacitors are preferred for T.C. and dielectric absorption; for linearity, and it will not usually be necessary to perform this polycarbonate or mica are acceptable; other types will degrade verification, which is both tedious and time-consuming. linearity. The capacitor should be wired very close to the AD537. Although drifts are small it is good practice to allow the operat- ing environment to attain stable temperature and to ensure that AD537 FO =10 (R1V I+N R2) C tthineg s tuhpep ilnyp, usot uvrocleta agned t olo 1a/d1 0c,o0n0d0i toiof nfus lal rsec aplreo. pAedr.j uBset gtihne b oyf fsseett- 1 14 fOUT pot until the output frequency is 1/10,000 of full scale (for ex- GUARD RING 2 DRIVER 13 ROUT +VS ample 1Hz for FS of 10kHz). This is most easily accomplished using a frequency meter connected to the output. Then apply 3 12 the FS input voltage and adjust the gain pot until the desired FS CURR- C R2 R1 4 BUF TO-FREQ 11 frequency is indicated. In applications where the FS input is CONV OPTIONAL 5 10 small, this adjustment will very slightly affect the offset voltage, INPUTVIN 10kΩ 10µF due to the input bias current of the buffer amplifier. A change of FILTER 6 VT PVROELCTIASIGOEN 9 R20Tk lkΩ in R will affect the input by approximately 100µV, which is 7 VR REFERENCE 8 as much as 0.1% of a 100mV FS range. Therefore, it may be necessary to repeat the offset and scale adjustments for the high- Figure 1.Standard V-F Connection for Positive Input est accuracy. The design of the input amplifier is such that the Voltages input voltage drift after offset nulling is typically below lµV/°C. REV. C –3–

AD537 In some cases the signal may be in the form of a negative cur- The –V , +V and I pins should not be driven more than IN IN IN rent source. This can be handled in a similar way to a negative 300mV below –V . This would cause internal junctions to con- S input voltage. However, the scaling resistor is no longer re- duct, possibly damaging the IC. The AD537 can be protected quired, eliminating the capability of trimming full scale in this from “below –V ” inputs by a Schottky diode, CR1 (HP5082- S fashion. Since it will usually be impractical to vary the capaci- 2811) as shown in Figure 3. It is also desirable not to drive tance, an alternative calibration scheme is needed. This is +V , –V and I above +V . In operation, the converter will IN IN IN S shown in Figure 3. A resistor-potentiometer connected from become very nonlinear for inputs above (+V – 3.5V). Control S the VR output to –VS will alter the internal operating conditions currents above 2mA will also cause nonlinearity. in a predictable way, providing the necessary adjustment range. The 80 dB dynamic range of the AD537 guarantees operation With the values shown, a range of ±4% is available; a larger from a control current of 1mA (nominal FS) down to 100nA range can be attained by reducing R1. This technique does not (equivalent to 1mV to 10V FS). Below 100nA improper op- degrade the temperature-coefficient of the converter, and the eration of the oscillator may result, causing a false indication of linearity will be as for negative input voltages. The minimum input amplitude. In many cases this might be due to short-lived supply voltage may be used. noise spikes which become added to the input. For example, Unless it is required to set the input node at exactly ground when scaled to accept a FS input of 1 V, the –80dB level is potential, no offset adjustment is needed. The capacitor C is se- only 100µV, so when the mean input is only 60dB below FS lected to be 5% below the nominal value; with R2 in its (1mV), noise spikes of 0.9mV are sufficient to cause momen- midposition the output frequency is given by: tary malfunction. I This effect can be minimized by using a simple low-pass filter f = 10.5×C ahead of the converter and a guard ring around the IIN or –VIN pins. For a FS of 10kHz a single-pole filter with a time-constant where f is in kHz, I is in mA and C is in µF. For example, for a of 100ms (Figure 2) will be suitable, but the optimum configu- FS frequency of 10kHz at a FS input of 1mA, C = 9500pF. ration will depend on the application and type of signal process- Calibration is effected by applying the full-scale input and ad- ing. Noise spikes are only likely to be a cause of error when the justing R2 for the correct reading. input current remains near its minimum value for long periods This alternative adjustment scheme may also be used when it is of time; above 100nA (1mV) full integration of additive input desired to present an exact input resistance in the negative volt- noise occurs. age mode. The scaling relationship is then The AD537 is somewhat susceptible to interference from other signals. The most sensitive nodes (besides the inputs) are the V 1 f = × capacitor terminals and the SYNC pin. The timing capacitor R 10.5C EXACT should be located as close as possible to the AD537 to minimize The calibration procedure is then similar to that used for posi- signal pickup in the leads. In some cases, guard rings or shield- tive input voltages, except that the scale adjustment is by means ing may be required. The SYNC pin should be decoupled of R2. through a 0.005µF (or larger) capacitor to Pin 13 (+VS). This minimizes the possibility that the AD537 will attempt to syn- VLOGIC chronize to a spurious signal. This precaution is unnecessary on the metal can package since the SYNC function is not brought AD537 out to a package pin and is thus not susceptible to pickup. OUTPUT LOGIC GND 1 14 f =IIN DEC/SYN 2 DRIVER 13 +VS 10C DECOUPLING It is good engineering practice to use bypass capacitors on the I 3 CURR- 12 CAP C supply-voltage pins and to insert small-valued resistors (10Ω to IIN 4 BUF TOC-OFNRVEQ 11 100Ω) in the supply lines to provide a measure of decoupling V 5 10 VOS between the various circuits in a system. Ceramic capacitors of VTEMP 6 VT PRECISION 9 VOS 0.1µF to 1.0µF should be applied between the supply-voltage R1VREF 7 VR RVEOFELRTAENGCEE 8 –VS pAiDns5 a3n7d. analog signal ground for proper bypassing on the 27k R2 ADJ. A decoupling capacitor may also be useful from +V to SYNC 200k SCALE S in those applications where very low cycle-to-cycle period varia- tion (jitter) is demanded. By placing a capacitor across +V and S Figure 3.Scale Adjustment for Current Inputs SYNC this noise is reduced. On the 10kHz FS range, a 6.8µF capacitor reduces the jitter to one in 20,000 which adequate for INPUT PROTECTION most applications. A tantalum capacitor should be used to avoid The AD537 was designed to be used with a minimum of addi- errors due to dc leakage. tional hardware. However, the successful application of a preci- sion IC involves a good understanding of possible pitfalls and the use of suitable precautions. –4– REV. C

AD537 NONLINEARITY SPECIFICATION Figure 5 shows the AD537 with a standard 0 to +10 volt input The preferred method for specifying linearity error is in terms of connection and the output stage connections. The values for the the maximum deviation from the ideal relationship after cali- logic common voltage, pull-up resistor, positive logic level, and brating the converter at full scale and “zero”. This error will –V supply are given in the accompanying chart for several logic S vary with the full-scale frequency and the mode of operation. forms. The AD537 operates best at a 10kHz full-scale frequency with a negative voltage input; the linearity is typically within ±0.05%. LOGIC COM VEE Operating at higher frequencies or with positive inputs will AD537 degrade the linearity as indicates in the Specification table. The 1 14 fOUT shape of a typical linearity plot is given in Figure 4. 2 DRIVER 13 RL +LVOSGIC VCC (+15V) 3 12 0.18 10k 4 BUF TOCU-FRRRE-Q 11 C TTL/DTL V+5CC VGENEDR5kL –GVNSD 0.16 TEST CONDITIONS: CONV ULL SCALE 000...111024 –+CRVVVFTTSS S== === 01 0±.0+0V1k110Ω5µVVF AD537J VIN 675 VVRT RPVEROFEELCRTIASEINGOCENE 1980 V2–0OVkSS 51HEV5CNV LICL CM1M0OkOSS/ ++0515 GG–8NNDD21500kkk GG––81NN 5TDDO % OF F 00..0068 PNOEGS IINNPPUUTT –– FFIIGG.. 34 EPCMLO2S.5k +01.3 ––215 51k0k ––515 – 0.04 RITY 0.02 Figure 5.Interfacing Standard Logic Families EA 0 LIN –0.02 APPLICATIONS N NO –0.04 AD537K, S The diagrams and descriptions of the following applications are provided to stimulate the discerning engineer with alternative –0.06 circuit design ideas. “Applications of the AD537 IC Voltage- –0.08 1 10 100 1k 10k to-Frequency Converter”, available from Analog Devices on OUTPUT FREQUENCY – Hz request, covers a wider range of topics and concepts in data conversion and data transmission using voltage-to-frequency Figure 4a. Typical Nonlinearity Error Envelopes with converters. 10kHz F.S. Output TRUE TWO-WIRE DATA TRANSMISSION 0.18 Figure 6 shows the AD537 in a true two-wire data transmission 0.16 TEST CONDITIONS: scheme. The twisted-pair transmission lines serves the dual pur- ULL SCALE 000...111024 –+CRVVVFTTSS S== === 01 0±.0+0V1k100Ω51VVµF AD537J pqatou stehen eco yrf esdcuaeptiavp ilinyngi n tehgn epd fo orwremperr eotsofe cnthutser r ade nefavt iimrcleyo adsniumdla patlileos onw .c aTayr hfroey riPn cgNo fnPrve ce-irrtcinugit F 0.08 POS INPUT – FIG. 3 % OF 0.06 NEG INPUT – FIG. 4 twhiell cdurrivreen dt imgitoadl ulolagtiico nd ibreacctkly i.n Ttoh ae v0o.6lt avgoelt ssqquuaarree wwaavvee wwhhicichh – 0.04 Y will appear on the supply line at the device terminals does not NEARIT 0.002 AD537K, S asuffpepctly t hreej epcetrifoonr.m Aalnscoe, noof tteh eth AatD t5h3e7 c ibreccuaitu osep eorfa ittess e axtc nelelaenrlty LI –0.02 NON –0.04 constant average power regardless of frequency. –0.06 –0.08 LOGIC GND 10 100 1k 10k 100k OUTPUT FREQUENCY – Hz RCAL RSCALE 10 1 9 RL VIN AD537 Figure 4b. Typical Nonlinearity Error with 100kHz F.S. DRIVER +VS 120 Output +VIN 2 8 +VS CURR- TO-FREQ OUTPUT INTERFACING CONSIDERATIONS BUF CONV The design of the output stage allows easy interfacing to all digi- VTEMP 3 VT PRECISION 7 RS ttvaroall ntlaosgigseitc ob rfea atmwreiel eibenos .t– hTV uhn eac ncodoml l4em cvitototlert sda ;bn tedhl oeew me mi+ttiVettre .o rT fc htahene ob opeue ttnipe ucdot tlNole PcatnNoyr VREF 4 VR RVEOFELRTAENGCEE 6 C TWLOI-NWKIRE 220Ω OUTPUT S S 5 can be pulled up to a voltage 36 volts above the emitter regard- –VS VS RS RL less of +VS. The high power output stage can supply up to (CONNECTED TO CASE) ++515 01k 13k.3k 20mA (10mA for “H” package) at a maximum saturation volt- age of 0.4 volts. The stage limits the output current at 25mA; it Figure 6.True Two-Wire Operation can handle this limit indefinitely without damaging the device. REV. C –5–

AD537 F-V CONVERTERS normally result in an accuracy of ±2°C from –55°C to +125°C The AD537 can be used as a high linearity VCO in a phase- (using an AD537S). An NPO ceramic capacitor is recom- locked loop to accomplish frequency-to-voltage conversion. By mended to minimize nonlinearity due to capacitance drift. operating the loop without a low-pass filter in the feedback path (first-order system), it can lock to any frequency from zero to an LOGIC upper limit determined by the design, responding in three or 2kΩ 9.1kΩ 10 GND four cycles to a step change of input frequency. In practice, the 1 9 f = 10Hz/K AD537 overall response time is determined by the characteristics of the 10kΩ DRIVER averaging filter which follows the PLL. +V 2 8 +VS Figure 7 shows a connection using a low power TTL quad CURR- TO-FREQ open-collector nand gate which serves as the phase comparator. BUF CONV The input signal should be a pulse train or square wave with 3 7 characteristics similar to TTL or 5-volt CMOS outputs. Any VTEMP VT PVROELCTIASIGOEN duty cycle is acceptable, but the minimum pulse width is 40µs. VR REFERENCE 1000pF The output voltage is one volt for a 10kHz input frequency. VREF 4 6 5 The output as shown here is at a fairly high impedance level; for many situations an additional buffer may be required. –VS (CONNECTED TO CASE) Trimming is similar to V-F application trimming. First set the Figure 8.Absolute Temperature to Frequency Converter V trimmer to mid-scale. Apply a 10kHz input frequency and OS trim the 2kΩ potentiometer for 1.00 volts out. Then apply a OFFSET TEMPERATURE SCALES 10Hz waveform and trim the V for 1mV out. Finally, retrim OS Many other temperature scales can be set up by offsetting the the full-scale output at 10kHz. Other frequency scales can be temperature output with the voltage reference output. Such a obtained by appropriate scaling of timing components. scheme is shown by the Celsius-to-frequency converter in +5V Figure 9. Corresponding component values for a Fahrenheit-to- frequency converter which give 10Hz/°F are given in parentheses. fIN (0-10kHz) 21 ADRDIV5E3R7 1143 10k 10k 74LO3 1 AD537 14 10k f1(1O00UHHTzz/°/°CF) 0.001µF 10k 2 DRIVER 13 +5V 3 12 4 BUF CCF-RUOTOERNQ-RV 11 10k (24095ΩΩ) 34 BUF TOCU-FRRRE-Q 1121 3(1950000 ppFF) 9.09k 5 10 500Ω CONV 2k 67 RPVEROFEELCRTIASEINGOCENE 89 2V0OkS 6.04k 56 VT PRECISION 190 (10k) 2k VOLTAGE 1N4148 7 VR REFERENCE 8 2.74k 0.005µF 3.9k 120k (4.02k) OUTPUT 1V F.S. 0.33µF Figure 9.Offset Temperature Scale Converters Centigrade and (Fahrenheit) to Frequency Figure 7. 10kHz F-V Converter A simple calibration procedure which will provide ±2°C accu- racy requires substitution of a 7.27k resistor for the series com- TEMPERATURE-TO-FREQUENCY CONVERSION bination of the 6.04k with the 2k trimmer; then simply set the The linear temperature-proportional output of the AD537 can 500Ω trimmer to give 250Hz at +25°C. be used as shown in these applications to perform various direct temperature-to-frequency conversion functions; it can also be High accuracy calibration procedure: used with other external connections in a temperature sensing 1. Measure room temperature in K. or compensation scheme. If the sensor output is used externally, 2. Measure temperature output at Pin 6 at that temperature. it should be buffered through an op amp since loading that 3. Calculate offset adjustment as follows: point will cause significant error in the sensor output as well as V (Pin 6) (mV) in the main V-F converter circuitry. Offset Voltage (mV) = TEMP ×273.2 Room temp (K) An absolute temperature (Kelvin)-to-frequency converter is very 4. Temporarily disconnect 49Ω resistor (or 500Ω pot) and easily accomplished, as shown in Figure 8. The 1mV per K out- trim 2kΩ pot to give the offset voltage at the indicated node. put serves as the input to the buffer amplifier, which then scales Reconnect 49Ω resistor. the oscillator drive current to a nominal 298µA at +25°C 5. Adjust slope trimmer to give proper frequency at room tem- (298K). Use of a 1000pF capacitor results in a corresponding perature (+25°C = 250Hz). frequency of 2.98kHz. Setting the single 2 kΩ trimmer for the Adjustment for °F or any other scale is analogous. correct frequency at a well-defined temperature near +25°C will –6– REV. C

AD537 SYNCHRONOUS OPERATION The SYNC terminal at pin 2 of the DIP package can be used to LOGIC GND AD537 OUTPUT RECOVERED synchronize a free running AD537 to a master oscillator, either 1 14 FREQUENCY at a multiple or a sub-multiple of the primary frequency. The DSEYCN/ 2 DRIVER 13 +VS 3.9V SIGNAL +15V preferred connection is shown in Figure 10. The diodes are used 3 12 1 14 12 tToh per SodYuNcCe ttheer mprinopale rc adnr iavles om baeg nuisteudd et of rsohmut h oigffh t hleev eols csiigllnataolsr.. CONIFTNRRPEOUQLT 10k 4 BUF CF-RUTOERQ-R 11 C0.A01PµF 2 11 P OCSOIMTE- Souhtoprutitn wg itlhl eg ote hrmighin (aol utotp +uVt SN wPiNll sotfof)p. the oscillator, and the 0 TO –10V VVTERMEFP 567 VT RPVEROFEELCRTCIASEOIGNONCENVE 1980 V–OVSS±S1II2GNVNP PAUKLT 67 8 10 ES±1RIGVRN POAKRL VR –15V AD537 1 14 fOUT Figure 12.Linear Phase-Locked Loop CS R VSYNC 2 DRIVER 13 +VS Noise on the input signal affects the loop operation only slightly; 1000pF 3 12 it appears as noise in the timing current, but this is averaged out 4 BUF TOCU-FRRRE-Q 11 CT by the timing capacitor. On the other hand, if the input fre- CONV quency changes there is a net error voltage at Pin 5 which acts VIN 5 10 to bring the oscillator back into quadrature. Thus, the output at NOTE: IF VSYNC >2V p-p 6 VT PRECISION 9 Pin 14 is a noise-free square-wave having exactly the same fre- USE THIS LIMITER CS 7 VR RVEOFELRTAENGCEE 8 quency as the input signal. The effectiveness of this circuit can VSYNC 2 be judged from Figure 13 which shows the response to an input 10k 1N4148 of 1V rms 1kHz sinusoid plus 1V rms Gaussian noise. The positive supply to the AD537 is reduced by about 4V in order to keep the voltages at Pins 11 and 12 within the common-mode Figure 10.Connection for Synchronous Operation range of the AD534. Figure 11 shows the maximum pull-in range available at a given Since this is also a first-order loop the circuit possesses a very signal level; the optimum signal is a 0.8 to 1.0 volt square wave; wide capture range. However, even better noise-integrating signals below 0.1 volt will have no effect; signals above 2 volts properties can be achieved by adding a filter between the multi- p-p will disable the oscillator. The AD537 can normally be syn- plier output and the VCO input. Details of suitable filter charac- chronized to a signal which forces it to a higher frequency up to teristics can be found in the standard texts on the subject. 30% above the nominal free-running frequency, it can only be brought down about 1–2%. 1V RMS SIGNAL +1V RMS NOISE 30% FREQUENCY LOCK-IN 20% RANGE 10% OUTPUT 0.2 0.4 0.6 0.8 1.0 VSYNC SQUARE-WAVE INPUT VOLTS p-p Figure 13. Performance of AD537 Linear Phase Locked Figure 11. Maximum Frequency Lock-ln Range vs. Loop Sync Signal By connecting the multiplier output to the lower end of the tim- LINEAR PHASE LOCKED LOOP ing resistor and moving the control input to Pin 5, a high resis- The phase-locked-loop F/V circuit described earlier operates tance frequency-control input is made available. However, due from an essentially noise-free binary input. PLL’s are also used to the reduced supply voltage, this input cannot exceed +6V. to extract frequency information from a noisy analog signal. To TRANSDUCER INTERFACE do this, the digital phase-comparator must be replaced by a lin- The AD537 was specifically designed to accept a broad range of ear multiplier. In the implementation shown in Figure 12, the input signals, particularly small voltage signals, which may be triangular waveform appearing across the timing capacitor is converted directly (unlike many V-F converters which require used as one of the multiplier inputs; the signal provides the signal preconditioning). The 1.00V stable reference output is other input. It can be shown that the mean value of the multi- also useful in interfacing situations, and the high input resis- plier output is zero when the two signals are in quadrature. In tance allows nonloading interfacing from a source of varying this condition, the ripple in the error signal is also quite small. resistance, such as the slider of a potentiometer. Thus, the voltage at Pin 5 is essentially zero, and the frequency is determined primarily by the current in the timing resistor, controlled either manually or by a control voltage. REV. C –7–

AD537 THERMOCOUPLE INPUT OUTLINE DIMENSIONS The output of a Chromel-Constantan (Type E) thermocouple, Dimensions shown in inches and (mm). using a reference junction at 0°C, varies from 0mV to 53.14 mV over the temperature range 0°C to +700°C with a slope of 14-Lead Side-Brazed Ceramic DIP (TO–116) 80.678µV/degree over most of its range and some nonlinearity (D–14) over the range 0°C to +200°C. For this example, we assume that it is desired to indicate temperature in Degrees Celsius 0.005 (0.13) MIN 0.098 (2.49) MAX using a counter/display with a 100ms gate width. Thus, the V-F C) converter must deliver an output of 7kHz for an input of 14 8 v. e 5sDo3em.v1ie4c essmo’ rVNt .oo Inff l livinneeerayar r pCizriiernccguis iietss onHpeaecnreadstsbiaooronyk ,d( sopewpe.,n 9f ot2or– 09ex°7Ca)m bispu ltiem i,n pA emnraaaltnoivyge, PIN 1 1 7 00..321200 ((75..8579)) 0.320 (8.13) –0–4/00 (r cases operation is only needed over part of the range. 0.785 (19.94) MAX 0.060 (1.52) 0.290 (7.37) 97f 0.015 (0.38) 3 The circuit shown in Figure 14 provides good accuracy from 0.200 C (5.08) +300°C to +700°C. The extrapolation of the temperature volt- MAX age curve back to 0°C shows that an offset of –3.34mV is 0.200 (5.08) 0(3.1.8510) required to fit the curve most exactly. This small amount of 0.125 (3.18) MIN 0.015 (0.38) 0.008 (0.20) voltage can be introduced without an additional calibration step SEATING using the +1.00V output of the AD537. To adjust the scale, the 0.023 (0.58) 0.100 0.070 (1.78) PLANE 0.014 (0.36) (2.54) 0.030 (0.76) thermocouple should be raised to a known reference tempera- BSC ture near 500°C and the frequency adjusted to value using R1. 10-Lead Metal Can (TO-100) The error should be within ±0.2% over the range 400°C to (H-10A) 700°C. REFERENCE PLANE 0.562 (14.30) 0.185 (4.70) 0.500 (12.70) AD537 VLOGIC 0.165 (4.19) TMEAS 1 14 10Hz/°C (01..02570) TREF 0 TO 53mV 2 DRIVER 13 +5V MAX (0°C) R1 SCALE 3 12 5 6 7 356F00SµA12407k 45 BUF TOCCU-OFRNRRVE-Q 1101 0.005µF 00..33730005.. 33((9850..5545 01((97))..0725)) (0B5.2.S83C40) 43 89 00..004259 ((10..1744)) IO≈ F2F1SµEAT 67 VVRT RPVEROFEELCRTIASEIGNOCENE 98 00..004342 ((10..1821)) 00..001196 ((00..4481)) (0B2..1S91C25) 2 10.0341 0(0.86) 0.021 (0.53) 0.028 (0.71) Figure 14.Thermocouple Interface with First-Order 00..004100 ((10..0215)) 0.016 (0.41) B36S°C BASE & SEATING PLANE Linearization A. S. U. N D I E T N RI P –8– REV. C

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