32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373 FEATURES 2.5 V to 5.5 V JEDEC-compliant digital levels Digital reset (RESET) 32-channel DAC in a 64-lead LQFP and 64-lead LFCSP Clear function to user-defined SIGGNDx AD5372/AD53731 guaranteed monotonic to 16/14 bits Simultaneous update of DAC outputs Maximum output voltage span of 4 × VREF (20 V) Nominal output voltage range of −4 V to +8 V APPLICATIONS Multiple, independent output voltage spans available Level setting in automatic test equipment (ATE) System calibration function allowing user-programmable Variable optical attenuators (VOA) offset and gain Optical switches Channel grouping and addressing features Industrial control systems Thermal shutdown function Instrumentation DSP/microcontroller-compatible serial interface SPI serial interface FUNCTIONAL BLOCK DIAGRAM DVCC VDD VSS AGND DGND LDAC RCEOGNITSRTOERL n nn == 1164 FFOORR AADD55337723 14 OFS0 n OFFSET BUFFER GROUP 0 VREF0 8 AR/BE GSIESLTEECRT 8 TMOUX 2s REGISTER DAC 0 BUFFER OUTPUT BUFFER VOUT0 nn X1 REGISTER nn n A/BMUX XX22AB RREEGGIISSTTEERR MUX2 n REDGAISCT 0ER n DAC 0 DOAWNDN PCOOWNTERRO-L VOUT1 M REGISTER VOUT2 n C REGISTER n VOUT3 VOUT4 VOUT5 VOUT6 SYNC INTSEERRFIAALCE nn X1 REGISTER nn n A/BMUX XX22AB RREEGGIISSTTEERR MUX2 n REDGAISCT 7ER n DAC 7 ODOUATWNPDNU PTC OOBWNUTEFRFREO-RL VSIOGUGTN7D0 SDI M REGISTER SCLK n n C REGISTER SDO VREF1 GROUP 1 BUSY 14 OFS1 n OFFSET BUFFER RESET 8 AR/BE GSIESLTEECRT 8 TMOUX 2s REGISTER DAC 1 BUFFER CLR nn X1 REGISTER nn n A/BMUX XX22AB RREEGGIISSTTEERR MUX2 n REDGAISCT 0ER n DAC 0 ODOUATWNPDNU PTC OOBWNUTEFRFREO-RL VVOOUUTT89 STATE M REGISTER VOUT10 MACHINE n n C REGISTER VOUT11 VOUT12 VOUT13 VOUT14 nn X1 REGISTER nn n A/BMUX XX22AB RREEGGIISSTTEERR MUX2 n REDGAISCT 7ER n DAC 7 ODOUATWNPDNU PTC OOBWNUTEFRFREO-RL VSIOGUGTN1D51 M REGISTER n n C REGISTER AADD55337723/ AREG RIDOEUNPT I2C TAOL TGOR OGURPO U3P 1 VGRREOFU1P S 1U PTOPL GIERSOUP 3 VTVOOOUUTT1361 SIGGND2 SIGGND3 05815-001 Figure 1. 1 Protected by U.S. Patent No. 5,969,657. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2011 Analog Devices, Inc. All rights reserved.

AD5372/AD5373 TABLE OF CONTENTS Features..............................................................................................1  Reference Selection....................................................................17  Applications.......................................................................................1  Calibration...................................................................................18  Functional Block Diagram..............................................................1  Additional Calibration...............................................................19  Revision History...............................................................................2  Reset Function............................................................................19  General Description.........................................................................3  Clear Function............................................................................19  Specifications.....................................................................................4  BUSY and LDAC Functions......................................................19  AC Characteristics........................................................................5  Power-Down Mode....................................................................20  Timing Characteristics................................................................6  Thermal Shutdown Function...................................................20  Absolute Maximum Ratings............................................................9  Toggle Mode................................................................................20  ESD Caution..................................................................................9  Serial Interface................................................................................21  Pin Configurations and Function Descriptions.........................10  SPI Write Mode..........................................................................21  Typical Performance Characteristics...........................................12  SPI Readback Mode...................................................................21  Terminology....................................................................................14  Register Update Rates................................................................21  Theory of Operation......................................................................15  Channel Addressing and Special Modes.................................22  DAC Architecture.......................................................................15  Special Function Mode..............................................................23  Channel Groups..........................................................................15  Applications Information..............................................................24  A/B Registers and Gain/Offset Adjustment............................16  Power Supply Decoupling.........................................................24  Load DAC....................................................................................16  Power Supply Sequencing.........................................................24  Offset DACs................................................................................16  Interfacing Examples.................................................................24  Output Amplifier........................................................................17  Outline Dimensions.......................................................................25  Transfer Function.......................................................................17  Ordering Guide..........................................................................26  REVISION HISTORY Changes to Absolute Maximum Ratings Section..........................9 Changes to Pin Configuration and Function Descriptions 7/11—Rev. B to Rev. C Section..............................................................................................10 Added 64-Lead LFCSP Package........................................Universal Changes to Reset Function Section..............................................18 Change to Features Section.............................................................1 Change to General Description Section........................................3 Changes to Table 5............................................................................9 12/07—Rev. 0 to Rev. A Added Figure 7; Renumbered Sequentially................................10 Changes to Table 3.............................................................................6 Changes to Table 6..........................................................................10 Changes to AD5373 Transfer Function Section.........................16 Updated Outline Dimensions.......................................................24 Changes to Calibration Section....................................................17 Changes to Ordering Guide..........................................................25 Changes to Table 8..........................................................................18 Changes to Register Update Rates Section..................................20 2/08—Rev. A to Rev. B Changes to Ordering Guide..........................................................25 Added Table 1....................................................................................3 Changes to t Parameter.................................................................6 10 8/07—Revision 0: Initial Version Added t Parameter.........................................................................6 23 Changes to Figure 4..........................................................................7 Rev. C | Page 2 of 28

AD5372/AD5373 GENERAL DESCRIPTION The AD5372/AD5373 contain 32 16-/14-bit DACs in 64-lead The AD5372/AD5373 have a high speed serial interface that is LQFP and LFCSP packages. The devices provide buffered compatible with SPI, QSPI™, MICROWIRE™, and DSP inter- voltage outputs with a nominal span of 4× the reference voltage. face standards and can handle clock speeds of up to 50 MHz. The gain and offset of each DAC can be independently trimmed The DAC registers are updated on reception of new data. All to remove errors. For even greater flexibility, the device is divided the outputs can be updated simultaneously by taking the LDAC into four groups of eight DACs. Two offset DACs allow the input low. Each channel has a programmable gain and an offset output range of the groups to be altered. Group 0 can be adjusted adjust register. by Offset DAC 0, and Group 1 to Group 3 can be adjusted by Each DAC output is gained and buffered on chip with respect Offset DAC 1. to an external SIGGNDx input. The DAC outputs can also be The AD5372/AD5373 offer guaranteed operation over a wide switched to SIGGNDx via the CLR pin. supply range: V from −16.5 V to −4.5 V and V from 9 V to SS DD 16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA. Table 1. High Channel Count Bipolar DACs Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB) AD5360 16 4 × V (20 V) 16 ±4 REF AD5361 14 4 × V (20 V) 16 ±1 REF AD5362 16 4 × V (20 V) 8 ±4 REF AD5363 14 4 × V (20 V) 8 ±1 REF AD5370 16 4 × V (12 V) 40 ±4 REF AD5371 14 4 × V (12 V) 40 ±1 REF AD5372 16 4 × V (12 V) 32 ±4 REF AD5373 14 4 × V (12 V) 32 ±1 REF AD5378 14 ±8.75 V 32 ±3 AD5379 14 ±8.75 V 40 ±3 Rev. C | Page 3 of 28

AD5372/AD5373 SPECIFICATIONS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −8 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; CC DD SS C = open circuit; R = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T to T , L L MIN MAX unless otherwise noted. Table 2. AD53721 AD53731 Parameter B Version B Version Unit Test Conditions/Comments2 ACCURACY Resolution 16 14 Bits Integral Nonlinearity (INL) ±4 ±1 LSB max Differential Nonlinearity (DNL) ±1 ±1 LSB max Guaranteed monotonic by design over temperature Zero-Scale Error ±10 ±10 mV max Before calibration Full-Scale Error ±10 ±10 mV max Before calibration Gain Error 0.1 0.1 % FSR Before calibration Zero-Scale Error2 1 1 LSB typ After calibration Full-Scale Error2 1 1 LSB typ After calibration Span Error of Offset DAC ±35 ±35 mV max See the Offset DACS section for details VOUTx Temperature Coefficient 5 5 ppm FSR/°C typ Includes linearity, offset, and gain drift DC Crosstalk2 100 100 μV max Typically 20 μV; measured channel at midscale, full-scale change on any other channel REFERENCE INPUTS (VREF0, VREF1)2 VREFx Input Current ±10 ±10 μA max Per input; typically ±30 nA VREFx Range 2/5 2/5 V min/V max ±2% for specified operation SIGGND INPUTS (SIGGND0 TO SIGGND3)2 DC Input Impedance 50 50 kΩ min Typically 55 kΩ Input Range ±0.5 ±0.5 V min/V max SIGGNDx Gain 0.995/1.005 0.995/1.005 min/max OUTPUT CHARACTERISTICS2 Output Voltage Range V + 1.4 V + 1.4 V min I = 1 mA SS SS LOAD V − 1.4 V − 1.4 V max I = 1 mA DD DD LOAD Nominal Output Voltage Range −4 to +8 −4 to +8 V min/V max Short-Circuit Current 15 15 mA max VOUTx to DV , V , or V CC DD SS Load Current ±1 ±1 mA max Capacitive Load 2200 2200 pF max DC Output Impedance 0.5 0.5 Ω max DIGITAL INPUTS JEDEC compliant Input High Voltage 1.7 1.7 V min DV = 2.5 V to 3.6 V CC 2.0 2.0 V min DV = 3.6 V to 5.5 V CC Input Low Voltage 0.8 0.8 V max DV = 2.5 V to 5.5 V CC Input Current ±1 ±1 μA max Excluding CLR pin CLR High Impedance Leakage Current ±20 ±20 μA max Input Capacitance2 10 10 pF max DIGITAL OUTPUTS (SDO, BUSY) Output Low Voltage 0.5 0.5 V max Sinking 200 μA Output High Voltage (SDO) DV − 0.5 DV − 0.5 V min Sourcing 200 μA CC CC SDO High Impedance Leakage Current ±5 ±5 μA max High Impedance Output Capacitance2 10 10 pF typ Rev. C | Page 4 of 28

AD5372/AD5373 AD53721 AD53731 Parameter B Version B Version Unit Test Conditions/Comments2 POWER REQUIREMENTS DV 2.5/5.5 2.5/5.5 V min/V max CC V 9/16.5 9/16.5 V min/V max DD V −16.5/−4.5 −16.5/−4.5 V min/V max SS Power Supply Sensitivity2 ∆Full Scale/∆V −75 −75 dB typ DD ∆Full Scale/∆V −75 −75 dB typ SS ∆Full Scale/∆DV −90 −90 dB typ CC DI 2 2 mA max DV = 5.5 V, V = DV , V = GND CC CC IH CC IL I 16 16 mA max Outputs unloaded, DAC outputs = 0 V DD 18 18 mA max Outputs unloaded, DAC outputs = full scale I −16 −16 mA max Outputs unloaded, DAC outputs = 0 V SS −18 −18 mA max Outputs unloaded, DAC outputs = full scale Power-Down Mode Bit 0 in the control register is 1 DI 5 5 μA typ CC I 35 35 μA typ DD I −35 −35 μA typ SS Power Dissipation (Unloaded) 250 250 mW typ V = −8 V, V = 9.5 V, DV = 2.5 V SS DD CC Junction Temperature3 130 130 °C max T = T + P × θ J A TOTAL JA 1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C. 2 Guaranteed by design and characterization; not production tested. 3 θJA represents the package thermal impedance. AC CHARACTERISTICS DV = 2.5 V; V = 15 V; V = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGNDx = 0 V; C = 200 pF; R = 10 kΩ; gain (M), CC DD SS L L offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. MIN MAX Table 3. Parameter B Version Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Output Voltage Settling Time 20 μs typ Full-scale change 30 μs max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs typ Digital-to-Analog Glitch Energy 5 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz DAC-to-DAC Crosstalk 10 nV-s typ Digital Crosstalk 0.2 nV-s typ Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V 1 Guaranteed by design and characterization; not production tested. Rev. C | Page 5 of 28

AD5372/AD5373 TIMING CHARACTERISTICS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; C = 200 pF to GND; CC DD SS L R = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. L MIN MAX Table 4. SPI Interface Parameter 1, 2, 3 Limit at T , T Unit Description MIN MAX t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 11 ns min SYNC falling edge to SCLK falling edge setup time 4 t5 20 ns min Minimum SYNC high time t 10 ns min 24th SCLK falling edge to SYNC rising edge 6 t 5 ns min Data setup time 7 t 5 ns min Data hold time 8 t 4 42 ns max SYNC rising edge to BUSY falling edge 9 t 1/1.5 μs typ/μs max BUSY pulse width low (single-channel update); see Table 9 10 t 600 ns max Single-channel update cycle time 11 t 20 ns min SYNC rising edge to LDAC falling edge 12 t 10 ns min LDAC pulse width low 13 t 3 μs max BUSY rising edge to DAC output response time 14 t 0 ns min BUSY rising edge to LDAC falling edge 15 t 3 μs max LDAC falling edge to DAC output response time 16 t 20/30 μs typ/μs max DAC output settling time 17 t 140 ns max CLR/RESET pulse activation time 18 t 30 ns min RESET pulse width low 19 t 400 μs max RESET time indicated by BUSY low 20 t 270 ns min Minimum SYNC high time in readback mode 21 t 5 25 ns max SCLK rising edge to SDO valid 22 t 80 ns max RESET rising edge to BUSY falling edge 23 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 t9 is measured with the load circuit shown in Figure 2. 5 t22 is measured with the load circuit shown in Figure 3. DVCC 200µA IOL R2.L2kΩ TO OUTPUT VOH (MIN) – VOL (MAX) OUTPTUOT VOL PIN CL 2 PIN C50LpF 05815-002 50pF 200µA IOH 05815-003 Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram Rev. C | Page 6 of 28

AD5372/AD5373 t 1 SCLK 1 2 24 1 24 t3 t2 t11 t4 t6 SYNC t5 t 7 t 8 SDI DB23 DB0 t 9 t BUSY 10 t12 t13 LDAC1 t 17 t VOUTx1 14 t 15 t 13 LDAC2 t 17 VOUTx2 t16 CLR t 18 VOUTx t 19 RESET VOUTx t 18 t 20 BUSY t 23 21LLDDAACC AACCTTIIVVEE DAUFTREINRG B BUUSSYY.. 05815-004 Figure 4. SPI Write Timing Rev. C | Page 7 of 28

AD5372/AD5373 t 22 SCLK 48 t 21 SYNC SDI DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB0 DB23 DB15 DB0 LSB FROM PREVIOUS WRITE SELECTED REGISTER DATA CLOCKED OUT 05815-005 Figure 5. SPI Read Timing OUTPUT VOLTAGE FULL-SCALE ERROR 8V + ZERO-SCALE ERROR ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION 0 DAC CODE 16383 ZERO-SCALE –4V ERROR 05815-006 Figure 6. DAC Transfer Function Rev. C | Page 8 of 28

AD5372/AD5373 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses above those listed under Absolute Maximum Ratings 60 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 5. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +17 V DD maximum rating conditions for extended periods may affect V to AGND −17 V to +0.3 V SS device reliability. DV to DGND −0.3 V to +7 V CC Digital Inputs to DGND −0.3 V to DV + 0.3 V CC ESD CAUTION Digital Outputs to DGND −0.3 V to DV + 0.3 V CC VREF0, VREF1 to AGND −0.3 V to +5.5 V VOUT0 through VOUT31 to AGND V − 0.3 V to V + 0.3 V SS DD SIGGNDx to AGND −1 V to +1 V AGND to DGND −0.3 V to +0.3 V Operating Temperature Range (TA) Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 130°C J θ Thermal Impedance JA 64-Lead LFCSP 25.5°C/W 64-Lead LQFP 45.5°C/W Reflow Soldering Peak Temperature 230°C Time at Peak Temperature 10 sec to 40 sec Rev. C | Page 9 of 28

AD5372/AD5373 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS CLRLDACVOUT26VOUT25VOUT24AGNDDGNDDVCCSDOSDISCLKSYNCDVCCDGNDVOUT7VOUT6 CLR LDAC VOUT26 VOUT25 VOUT24 AGND DGNDDVCC SDO SDI SCLK SYNCDVCC DGND VOUT7 VOUT6 PIN 1 64636261605958575655545352515049 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 INDICATOR RESET 1 48 VOUT5 BUSY 2 PININD I1CATOR 47 VOUT4 RESET 1 48VOUT5 VOUT27 3 46 SIGGND0 BUSY 2 47VOUT4 VOUT27 3 46SIGGND0 SIGGND3 4 45 VOUT3 SIGGND3 4 45VOUT3 VOUT28 5 44 VOUT2 VOUT28 5 44VOUT2 VOUT29 6 43 VOUT1 VVOOUUTT2390 67 4432VVOOUUTT10 VOUT30 7 AD5372/AD5373 42 VOUT0 VOUT31 8 AD5372/AD5373 41VREF0 VOUT31 8 TOP VIEW 41 VREF0 NC 9 TOP VIEW 40VOUT23 NC 9 (Not to Scale) 40 VOUT23 NC10 (Not to Scale) 39VOUT22 NC 10 39 VOUT22 NC 11 38VOUT21 NC 11 38 VOUT21 NC12 37VOUT20 NC 12 37 VOUT20 NNCC1134 3365VVSDSD NC 13 36 VSS NC15 34SIGGND2 NC 14 35 VDD VDD16 33VOUT19 NC 15 34 SIGGND2 VDD 16 33 VOUT19 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 V17SS18VREF119NC20NC21VOUT822VOUT923VOUT1024VOUT1125SIGGND126VOUT1227VOUT1328VOUT1429VOUT1530VOUT1631VOUT1732VOUT18 NC = NO CONNECVSST VREF1 NC NC VOUT8 VOUT9 VOUT10 VOUT11 SIGGND1 VOUT12 VOUT13 VOUT14 VOUT15 VOUT16 VOUT17 VOUT18 05815-007 NOTES 12 .. NTOHCNE =T LHNEEOA UDCN OFDNRENAREMSCEIDT C.EH. ICPO SNCNAELCET P TAHCEK EAXGPEO (SLEFDC SPPA)D H TAOS VASNS .EXPOSED PAD 05815-107 Figure 7. 64-Lead LFCSP Pin Configuration Figure 8. 64-Lead LQFP Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 0 EPAD Exposed Pad. The lead frame chip scale package (LFCSP) has an exposed pad on the underside. Connected the exposed pad to V . SS 1 RESET Digital Reset Input. 2 BUSY Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and LDAC Functions section for more information. 42 to 45, 47 to 50, 21 to 24, VOUT0 to DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is 26 to 33, 37 to 40, 60 to 62, VOUT31 capable of driving an output load of 10 kΩ to ground. Typical output impedance of these 3, 5 to 8 amplifiers is 0.5 Ω. 4 SIGGND3 Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage. 9 to 15, 19, 20 NC No Connect. 16, 35 V Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be DD decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 17, 36 V Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should SS be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 18 VREF1 Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND. 25 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage. 34 SIGGND2 Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage. 41 VREF0 Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND. 46 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage. 51, 58 DGND Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane. 52, 57 DV Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic CC capacitors and 10 μF capacitors. 53 SYNC Active Low Input. This is the frame synchronization signal for the serial interface. 54 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. 55 SDI Serial Data Input. Data must be valid on the falling edge of SCLK. Rev. C | Page 10 of 28

AD5372/AD5373 Pin No. Mnemonic Description 56 SDO Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. 59 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane. 63 LDAC Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information. 64 CLR Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for more information. Rev. C | Page 11 of 28

AD5372/AD5373 TYPICAL PERFORMANCE CHARACTERISTICS 0.0050 2 TA = 25°C VSS = –15V VDD = +15V VREFx = +4.096V 0.0025 1 V) B) DE ( INL (LS 0 AMPLITU 0 –0.0025 –1 –2 05815-008 –0.00500 1 2 3 4 505815-011 0 16384 32768 49152 65535 DACCODE TIME(µs) Figure 9. Typical AD5372 INL Plot Figure 12. Digital Crosstalk 1.0 1.0 VDD = +15V VSS = –15V DVCC = +5V VREFx = +3V 0.5 0.5 B) ERROR (LS 0 DNL (LSB) 0 L N I –0.5 –0.5 –1.0 05815-009 –1.00 16384 32768 49152 655305815-0125 0 20 40 60 80 TEMPERATURE (°C) DAC CODE Figure 10. Typical INL Error vs. Temperature Figure 13. Typical AD5372 DNL Plot 0 TA = 25°C 600 VSS = –15V VDD = +15V VREFx = +4.096V 500 Hz) PLITUDE (V)–0.01 NOISE (nV/√ 340000 M T A U TP 200 U O 100 –0.020 2 4TIME(µs) 6 8 10 05815-010 00 1 2 3 4 505815-013 FREQUENCY (Hz) Figure 11. Analog Crosstalk Due to LDAC Figure 14. Output Noise Spectral Density Rev. C | Page 12 of 28

AD5372/AD5373 0.50 VVVRSDSDE F== x –+ 1=12 2+VV3V 1142 TVVASDS D= = =2 5–+°11C55VV 0.45 S10 DVCC = +5.5V NIT (mA)C0.40 DVCC = +3.6V R OF U 8 C E DI 0.35 MB 6 DVCC = +2.5V NU 4 0.30 0.25 05815-014 20 12.6 12.8 13.0 13.2 13.4 05815-016 –40 –20 0 20 40 60 80 TEMPERATURE (°C) IDD (mA) Figure 15. DICC vs. Temperature Figure 17. Typical IDD Distribution 13.5 14 DVCC = 5V IDD TA = 25°C 12 13.0 S10 T NI mA) F U 8 /I (DSS12.5 ISS BER O 6 D M I U N 4 12.0 11.5 VVVSDRSDE F==x –+ 1=12 2+VV3V 05815-015 20 0.30 0.35 0.40 0.45 0.50 05815-017 –40 –20 0 20 40 60 80 DICC (mA) TEMPERATURE (°C) Figure 16. IDD/ISS vs. Temperature Figure 18. Typical DICC Distribution Rev. C | Page 13 of 28

AD5372/AD5373 TERMINOLOGY Integral Nonlinearity (INL) Output Voltage Settling Time Integral nonlinearity, or endpoint linearity, is a measure of Output voltage settling time is the amount of time it takes for the maximum deviation from a straight line passing through the output of a DAC to settle to a specified level for a full-scale the endpoints of the DAC transfer function. It is measured input change. after adjusting for zero-scale error and full-scale error and is Digital-to-Analog Glitch Energy expressed in least significant bits (LSB). Digital-to-analog glitch energy is the amount of energy that is Differential Nonlinearity (DNL) injected into the analog output at the major code transition. It is Differential nonlinearity is the difference between the measured specified as the area of the glitch in nV-s. It is measured by change and the ideal 1 LSB change between any two adjacent toggling the DAC register data between 0x7FFF and 0x8000 codes. A specified differential nonlinearity of 1 LSB maximum (AD5372) or 0x1FFF and 0x2000 (AD5373). ensures monotonicity. Channel-to-Channel Isolation Zero-Scale Error Channel-to-channel isolation refers to the proportion of input Zero-scale error is the error in the DAC output voltage when signal from the reference input of one DAC that appears at the all 0s are loaded into the DAC register. Zero-scale error is a output of another DAC operating from another reference. It is measure of the difference between VOUT (actual) and VOUT expressed in decibels and measured at midscale. (ideal), expressed in millivolts, when the channel is at its mini- DAC-to-DAC Crosstalk mum value. Zero-scale error is mainly due to offsets in the DAC-to-DAC crosstalk is the glitch impulse that appears at output amplifier. the output of one converter due to both the digital change Full-Scale Error and subsequent analog output change at another converter. It Full-scale error is the error in the DAC output voltage when is specified in nV-s. all 1s are loaded into the DAC register. Full-scale error is a Digital Crosstalk measure of the difference between VOUT (actual) and VOUT Digital crosstalk is defined as the glitch impulse transferred to (ideal), expressed in millivolts, when the channel is at its maxi- the output of one converter due to a change in the DAC register mum value. Full-scale error does not include zero-scale error. code of another converter. It is specified in nV-s. Gain Error Digital Feedthrough Gain error is the difference between full-scale error and When the device is not selected, high frequency logic activity zero-scale error. It is expressed as a percentage of the full- on the digital inputs of the device can be capacitively coupled scale range (FSR). both across and through the device to appear as noise on the Gain Error = Full-Scale Error − Zero-Scale Error VOUT pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. VOUT Temperature Coefficient The VOUT temperature coefficient includes output error Output Noise Spectral Density contributions from linearity, offset, and gain drift. Output noise spectral density is a measure of internally generated random noise. Random noise is characterized as a DC Output Impedance spectral density (voltage per √Hz). It is measured by loading DC output impedance is the effective output source resistance. all DACs to midscale and measuring noise at the output. It is It is dominated by package lead resistance. measured in nV/√Hz. DC Crosstalk The DAC outputs are buffered by op amps that share common V and V power supplies. If the dc load current changes in DD SS one channel (due to an update), this change can result in a further dc change in one or more channel outputs. This effect is more significant at high load currents and is reduced as the load currents are reduced. With high impedance loads, the effect is virtually immeasurable. Multiple V and V terminals are DD SS provided to minimize dc crosstalk. Rev. C | Page 14 of 28

AD5372/AD5373 THEORY OF OPERATION DAC ARCHITECTURE The output amplifier multiplies the DAC output voltage by 4. The nominal output span is 12 V with a 3 V reference and 20 V The AD5372/AD5373 contain 32 DAC channels and 32 output with a 5 V reference. amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit (AD5372) or 14-bit (AD5373) CHANNEL GROUPS resistor-string DAC followed by an output buffer amplifier. The 32 DAC channels of the AD5372/AD5373 are arranged into The resistor-string section is simply a string of resistors (of four groups of eight channels. The eight DACs of Group 0 derive equal value) from VREF0 or VREF1 to AGND. This type of their reference voltage from VREF0. Group 1 to Group 3 derive architecture guarantees DAC monotonicity. The 16-bit their reference voltage from VREF1. Each group has its own (AD5372) or 14-bit (AD5373) binary digital code loaded to signal ground pin. the DAC register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. Table 7. AD5372/AD5373 Registers Word Length Register Name in Bits Description X1A (Group) (Channel) 16 (14) Input Data Register A, one for each DAC channel. X1B (Group) (Channel) 16 (14) Input Data Register B, one for each DAC channel. M (Group) (Channel) 16 (14) Gain trim registers, one for each DAC channel. C (Group) (Channel) 16 (14) Offset trim registers, one for each DAC channel. X2A (Group) (Channel) 16 (14) Output Data Register A, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable or directly writable. X2B (Group) (Channel) 16 (14) Output Data Register B, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable or directly writable. DAC (Group) (Channel) Data registers from which the DACs take their final input data. The DAC registers are updated from the X2A or X2B registers. They are not readable or directly writable. OFS0 14 Offset DAC 0 data register: sets offset for Group 0. OFS1 14 Offset DAC 1 data register: sets offset for Group 1 to Group 3. Control 3 Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = global selection of X1B input data registers. Bit 1 = enable thermal shutdown. 0 = disable thermal shutdown. 1 = enable thermal shutdown. Bit 0 = software power-down. 0 = software power-up. 1 = software power-down. A/B Select 0 8 Each bit in this register determines whether a DAC in Group 0 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). A/B Select 1 8 Each bit in this register determines whether a DAC in Group 1 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). A/B Select 2 8 Each bit in this register determines whether a DAC in Group 2 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). A/B Select 3 8 Each bit in this register determines whether a DAC in Group 3 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). Table 8. AD5372/AD5373 Input Register Default Values Register Name AD5372 Default Value AD5373 Default Value X1A, X1B 0x5554 0x1555 M 0xFFFF 0x3FFF C 0x8000 0x2000 OFS0, OFS1 0x1555 0x1555 Control 0x00 0x00 A/B Select 0 to A/B Select 3 0x00 0x00 Rev. C | Page 15 of 28

AD5372/AD5373 A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT LOAD DAC Each DAC channel has seven data registers. The actual DAC All DACs in the AD5372/AD5373 can be updated simultane- data-word can be written to either the X1A or the X1B input ously by taking LDAC low when each DAC register is updated register, depending on the setting of the A/B bit in the control from either its X2A or X2B register, depending on the setting register. If the A/B bit is 0, data is written to the X1A register. of the A/B select registers. The DAC register is not readable or If the A/B bit is 1, data is written to the X1B register. Note that directly writable by the user. LDAC can be permanently tied this single bit is a global control and affects every DAC channel low, and the DAC output is updated whenever new data appears in the device. It is not possible to set up the device on a per- in the appropriate DAC register. channel basis so that some writes are to X1A registers and OFFSET DACs some writes are to X1B registers. In addition to the gain and offset trim for each DAC, there are two 14-bit offset DACs, one for Group 0 and one for Group 1 to X1A X2A REGISTER REGISTER DAC Group 3. These allow the output range of all DACs connected to MUX MUX REGISTER DAC X1B X2B them to be offset within a defined range. Thus, subject to the REGISTER REGISTER limitations of headroom, it is possible to set the output range of M Group 0 or Group 1 to Group 3 to be unipolar positive, unipolar REGISTER negative, or bipolar, either symmetrical or asymmetrical about REGICSTER 05815-018 0th Ve .o Tffhsee tD DAACCs si nse tth aet AthDe5ir3 d7e2f/aAuDlt 5v3a7lu3e asr. eT fhacist ogriyv etsr itmhem beedst w oiftfhse t Figure 19. Data Registers Associated with Each DAC Channel and gain performance for the default output range and span. Each DAC channel also has a gain (M) register and an offset When the output range is adjusted by changing the value of the (C) register, which allow trimming out of the gain and offset offset DAC, an extra offset is introduced due to the gain error of errors of the entire signal chain. Data from the X1A register is the offset DAC. The amount of offset is dependent on the operated on by a digital multiplier and adder controlled by the magnitude of the reference and how much the offset DAC contents of the M and C registers. The calibrated DAC data is moves from its default value. See the Specifications section for then stored in the X2A register. Similarly, data from the X1B this offset. The worst-case offset occurs when the offset DAC is register is operated on by the multiplier and adder and stored in at positive or negative full scale. This value can be added to the the X2B register. offset present in the main DAC channel to give an indication of Although a multiplier and adder symbol are shown in Figure 19 the overall offset for that channel. In most cases, the offset can for each channel, there is only one multiplier and one adder in the be removed by programming the C register of the channel with device, which are shared among all channels. This has implica- an appropriate value. The extra offset caused by the offset DAC tions for the update speed when several channels are updated at needs to be taken into account only when the offset DAC is once, as described in the Register Update Rates section. changed from its default value. Figure 20 shows the allowable Each time data is written to the X1A register, or to the M or code range that can be loaded to the offset DAC, depending on C register with the A/B control bit set to 0, the X2A data is the reference value used. Thus, for a 5 V reference, the offset recalculated and the X2A register is automatically updated. DAC should not be programmed with a value greater than 8192 Similarly, X2B is updated each time data is written to X1B, (0x2000). or to M or C with A/B set to 1. The X2A and X2B registers 5 are not readable or directly writable by the user. RESERVED Data output from the X2A and X2B registers is routed to the 4 final DAC register by a multiplexer. Whether each individual DAC takes its data from the X2A or from the X2B register is 3 controlled by an 8-bit A/B select register associated with each V) F ( group of eight DACs. If a bit in this register is 0, the DAC takes E R its data from the X2A register; if 1, the DAC takes its data from V 2 the X2B register (Bit 0 through Bit 7 control DAC 0 to DAC 7). Note that because there are 32 bits in four registers, it is possible to 1 sfreot mup t,h oen X a2 pAe or-rc Xh2aBn nreegl ibsatesri.s A, w ghloebthael rc oemacmh aDnAd Cis taalskoe sp ritosv didaetda 0 05815-019 that sets all bits in the A/B select registers to 0 or to 1. 0 4096 8192 12288 16383 OFFSET DAC CODE Figure 20. Offset DAC Code Range Rev. C | Page 16 of 28

AD5372/AD5373 OUTPUT AMPLIFIER where: DAC_CODE should be within the range of 0 to 65,535. Because the output amplifiers can swing to 1.4 V below the For 12 V span, VREFx = 3.0 V. positive supply and 1.4 V above the negative supply, this limits For 20 V span, VREFx = 5.0 V. how much the output can be offset for a given reference voltage. OFFSET_CODE is the code loaded to the offset DAC. It is For example, it is not possible to have a unipolar output range multiplied by 4 in the transfer function because this DAC is of 20 V, because the maximum supply voltage is ±16.5 V. a 14-bit device. On power-up, the default code loaded to the DAC S1 offset DAC is 5461 (0x1555). With a 3 V reference, this gives CHANNEL OUTPUT a span of −4 V to +8 V. R6 R5 S2 CLR 10kΩ AD5373 Transfer Function 60kΩ CLR The input code is the value in the X1A or X1B register that is R1 20kΩ CLR S3 applied to the DAC (X1A, X1B default code = 5461). 60Rk4Ω 20Rk3Ω R202kΩ SIGGNDx DAC_CODE = INPUT_CODE × (M + 1)/214 + C − 213 SIGGNDx where: OFDFASCET 05815-020 CM = = c cooddee iinn o gfafsinet r reeggiisstteerr − − d deeffaauulltt c cooddee = = 2 21143 –. 1. Figure 21. Output Amplifier and Offset DAC The DAC output voltage is calculated as follows: Figure 21 shows details of a DAC output amplifier and its VOUT = 4 × VREFx × (DAC_CODE – connections to the offset DAC. On power-up, S1 is open, OFFSET_CODE)/214 + V SIGGND disconnecting the amplifier from the output. S3 is closed, so where: the output is pulled to SIGGNDx (R1 and R2 are greater than DAC_CODE should be within the range of 0 to 16,383. R6). S2 is also closed to prevent the output amplifier from being For 12 V span, VREFx = 3.0 V. open-loop. If CLR is low at power-up, the output remains in this For 20 V span, VREFx = 5.0 V. condition until CLR is taken high. The DAC registers can be OFFSET_CODE is the code loaded to the offset DAC. programmed, and the outputs assume the programmed values On power-up, the default code loaded to the offset DAC when CLR is taken high. Even if CLR is high at power-up, the is 5461 (0x1555). With a 3 V reference, this gives a span output remains in the previous condition until V > 6 V and DD of −4 V to +8 V. V < −4 V and the initialization sequence has finished. The SS REFERENCE SELECTION outputs then go to their power-on default value. The AD5372/AD5373 have two reference input pins. The TRANSFER FUNCTION voltage applied to the reference pins determines the output The output voltage of a DAC in the AD5372/AD5373 is depend- voltage span on VOUT0 to VOUT31. VREF0 determines the ent on the value in the input register, the value of the M and C voltage span for VOUT0 to VOUT7 (Group 0), and VREF1 registers, and the value in the offset DAC. determines the voltage span for VOUT8 to VOUT31 (Group 1 AD5372 Transfer Function to Group 3). The reference voltage applied to each VREF pin can be different, if required, allowing the groups to have The input code is the value in the X1A or X1B register that is different voltage spans. The output voltage range and span applied to the DAC (X1A, X1B default code = 21,844). can be adjusted further by programming the offset and gain DAC_CODE = INPUT_CODE × (M + 1)/216 + C − 215 registers for each channel as well as programming the offset where: DACs. If the offset and gain features are not used (that is, the M = code in gain register − default code = 216 – 1. M and C registers are left at their default values), the required C = code in offset register − default code = 215. reference levels can be calculated as follows: The DAC output voltage is calculated as follows: VREF = (VOUT – VOUT )/4 MAX MIN VOUT = 4 × VREFx × (DAC_CODE – (OFFSET_CODE × If the offset and gain features of the AD5372/AD5373 are used, 4))/216 + VSIGGND the required output range is slightly different. The selected output range should take into account the system offset and gain errors that need to be trimmed out. Therefore, the selected output range should be larger than the actual required range. Rev. C | Page 17 of 28

AD5372/AD5373 The required reference levels can be calculated as follows: CALIBRATION 1. Identify the nominal output range on VOUT. The user can perform a system calibration on the AD5372/ 2. Identify the maximum offset span and the maximum gain AD5373 to reduce gain and offset errors to below 1 LSB. This required on the full output signal range. reduction is achieved by calculating new values for the M and C 3. Calculate the new maximum output range on VOUT, registers and reprogramming them. including the expected maximum offset and gain errors. The M and C registers should not be programmed until both 4. Choose the new required VOUT and VOUT , MAX MIN the zero-scale and full-scale errors are calculated. keeping the VOUT limits centered on the nominal values. Reducing Zero-Scale Error Note that V and V must provide sufficient headroom. DD SS 5. Calculate the value of VREF as follows: Zero-scale error can be reduced as follows: VREF = (VOUT – VOUT )/4 1. Set the output to the lowest possible value. MAX MIN 2. Measure the actual output voltage and compare it to the Reference Selection Example required value. This gives the zero-scale error. If 3. Calculate the number of LSBs equivalent to the error and add this number to the default value of the C register. Note Nominal output range = 12 V (−4 V to +8 V) that only negative zero-scale error can be reduced. Zero-scale error = ±70 mV Reducing Full-Scale Error Gain error = ±3%, and Full-scale error can be reduced as follows: SIGGNDx = AGND = 0 V 1. Measure the zero-scale error. Then 2. Set the output to the highest possible value. Gain error = ±3% 3. Measure the actual output voltage and compare it to the => Maximum positive gain error = 3% required value. Add this error to the zero-scale error. This => Output range including gain error = 12 + 0.03(12) = 12.36 V is the span error, which includes the full-scale error. 4. Calculate the number of LSBs equivalent to the span error Zero-scale error = ±70 mV and subtract this number from the default value of the M => Maximum offset error span = 2(70 mV) = 0.14 V register. Note that only positive full-scale error can be => Output range including gain error and zero-scale error = reduced. 12.36 V + 0.14 V = 12.5 V VREF calculation AD5372 Calibration Example Actual output range = 12.5 V, that is, −4.25 V to +8.25 V; This example assumes that a −4 V to +8 V output is required. VREF = (8.25 V + 4.25 V)/4 = 3.125 V The DAC output is set to −4 V but is measured at −4.03 V. This If the solution yields an inconvenient reference level, the user gives a zero-scale error of −30 mV. can adopt one of the following approaches: 1 LSB = 12 V/65,536 = 183.105 μV • Use a resistor divider to divide down a convenient, higher 30 mV = 164 LSBs reference level to the required level. The full-scale error can now be calculated. The output is set to • Select a convenient reference level above VREF and modify 8 V and a value of 8.02 V is measured. This gives a full-scale the gain and offset registers to digitally downsize the reference. error of +20 mV and a span error of +20 mV – (–30 mV) = In this way, the user can use almost any convenient reference +50 mV. level but can reduce the performance by overcompaction of 50 mV = 273 LSBs the transfer function. • Use a combination of these two approaches. The errors can now be removed as follows: 1. Add 164 LSBs to the default C register value: (32,768 + 164) = 32,932 2. Subtract 273 LSBs from the default M register value: (65,535 − 273) = 65,262 3. Program the M register to 65,262; program the C register to 32,932. Rev. C | Page 18 of 28

AD5372/AD5373 ADDITIONAL CALIBRATION BUSY AND LDAC FUNCTIONS The techniques described in the previous section are usually The value of an X2 (A or B) register is calculated each time the enough to reduce the zero-scale and full-scale errors in most user writes new data to the corresponding X1, C, or M register. applications. However, there are limitations whereby the errors During the calculation of X2, the BUSY output goes low. While may not be sufficiently reduced. For example, the offset (C) BUSY is low, the user can continue writing new data to the X1, register can only be used to reduce the offset caused by the M, or C register (see the Register Update Rates section for more negative zero-scale error. A positive offset cannot be reduced. details), but no DAC output updates can take place. Likewise, if the maximum voltage is below the ideal value, that The BUSY pin is bidirectional and has a 50 kΩ internal pull-up is, a negative full-scale error, the gain (M) register cannot be resistor. When multiple AD5372 or AD5373 devices are used in used to increase the gain to compensate for the error. one system, the BUSY pins can be tied together. This is useful These limitations can be overcome by increasing the reference when it is required that no DAC in any device be updated until value. With a 3 V reference, a 12 V span is achieved. The ideal all other DACs are ready. When each device has finished updating voltage range, for the AD5372 or the AD5373, is −4 V to +8 V. the X2 (A or B) registers, it releases the BUSY pin. If another Using a +3.1 V reference increases the range to −4.133 V to device has not finished updating its X2 registers, it holds BUSY +8.2667 V. Clearly, in this case, the offset and gain errors are low, thus delaying the effect of LDAC going low. insignificant, and the M and C registers can be used to raise the negative voltage to −4 V and then reduce the maximum The DAC outputs are updated by taking the LDAC input low. If voltage to +8 V to give the most accurate values possible. LDAC goes low while BUSY is active, the LDAC event is stored RESET FUNCTION and the DAC outputs are updated immediately after BUSY goes high. A user can also hold the LDAC input permanently low. In The reset function is initiated by the RESET pin. On the rising this case, the DAC outputs are updated immediately after BUSY edge of RESET, the AD5372/AD5373 state machine initiates a goes high. Whenever the A/B select registers are written to, BUSY reset sequence to reset the X, M, and C registers to their default also goes low, for approximately 500 ns. values. This sequence typically takes 300 μs, and the user should not write to the part during this time. On power-up, it is recom- The AD5372/AD5373 have flexible addressing that allows mended that the user bring RESET high as soon as possible to writing of data to a single channel, all channels in a group, the properly initialize the registers. same channel in Group 0 to Group 3, the same channel in Group 1 to Group 3, or all channels in the device. This means When the reset sequence is complete (and provided that CLR is that 1, 4, 8, or 32 DAC register values may need to be calculated high), the DAC output is at a potential specified by the default and updated. Because there is only one multiplier shared among register settings, which is equivalent to SIGGNDx. The DAC 32 channels, this task must be done sequentially so that the outputs remain at SIGGNDx until the X, M, or C register is length of the BUSY pulse varies according to the number of updated and LDAC is taken low. The AD5372/AD5373 can be channels being updated. returned to the default state by pulsing RESET low for at least 30 ns. Note that, because the reset function is triggered by the Table 9. BUSY Pulse Widths rising edge, bringing RESET low has no effect on the operation Action BUSY Pulse Width1 of the AD5372/AD5373. Loading input, C, or M to 1 channel2 1.5 μs maximum CLEAR FUNCTION Loading input, C, or M to 4 channels 3.3 μs maximum Loading input, C, or M to 8 channels 5.7 μs maximum CLR is an active low input that should be high for normal opera- Loading input, C, or M to 32 channels 20.1 μs maximum tion. The CLR pin has an internal 500 kΩ pull-down resistor. When CLR is low, the input to each of the DAC output buffer 1 BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns. 2 A single channel update is typically 1 μs. stages (VOUT0 to VOUT31) is switched to the externally set potential on the relevant SIGGNDx pin. While CLR is low, all The AD5372/AD5373 contain an extra feature whereby a DAC LDAC pulses are ignored. When CLR is taken high again, the register is not updated unless its X2A or X2B register has been DAC outputs return to their previous values. The contents of the written to since the last time LDAC was brought low. Normally, input registers and DAC Register 0 to DAC Register 31 are not when LDAC is brought low, the DAC registers are filled with the affected by taking CLR low. To prevent glitches from appearing contents of the X2A or X2B register, depending on the setting of on the outputs, CLR should be brought low whenever the output the A/B select registers. However, the AD5372/AD5373 update span is adjusted by writing to the offset DAC. the DAC register only if the X2A or X2B data has changed, thereby removing unnecessary digital crosstalk. Rev. C | Page 19 of 28

AD5372/AD5373 POWER-DOWN MODE TOGGLE MODE The AD5372/AD5373 can be powered down by setting Bit 0 in The AD5372/AD5373 have two X2 registers per channel, X2A the control register to 1. This turns off the DACs, thus reducing and X2B, which can be used to switch the DAC output between the current consumption. The DAC outputs are connected to two levels with ease. This approach greatly reduces the overhead their respective SIGGNDx potentials. The power-down mode required by a microprocessor, which would otherwise need to does not change the contents of the registers, and the DACs write to each channel individually. When the user writes to the return to their previous voltage when the power-down bit is X1A, X1B, M, or C register, the calculation engine takes a certain cleared to 0. amount of time to calculate the appropriate X2A or X2B value. If an application, such as a data generator, requires that the THERMAL SHUTDOWN FUNCTION DAC output switch between two levels only, any method that The AD5372/AD5373 can be programmed to shut down the reduces the amount of calculation time necessary is advanta- DACs if the temperature on the die exceeds 130°C. Setting Bit 1 geous. For the data generator example, the user needs only to in the control register to 1 enables this function (see Table 16). set the high and low levels for each channel once by writing to If the die temperature exceeds 130°C, the AD5372/AD5373 enter the X1A and X1B registers. The values of X2A and X2B are a thermal shutdown mode, which is equivalent to setting the calculated and stored in their respective registers. The calculation power-down bit in the control register to 1. To indicate that the delay, therefore, happens only during the setup phase, that is, AD5372/AD5373 have entered thermal shutdown mode, Bit 4 when programming the initial values. To toggle a DAC output of the control register is set to 1. The AD5372/AD5373 remain between the two levels, it is only required to write to the relevant in thermal shutdown mode, even if the die temperature falls, A/B select register to set the MUX2 register bit. Furthermore, until Bit 1 in the control register is cleared to 0. because there are eight MUX2 control bits per register, it is possible to update eight channels with a single write. Table 10 shows the bits that correspond to each DAC output. Table 10. DACs Selected by A/B Select Registers A/B Select Bits1 Register F7 F6 F5 F4 F3 F2 F1 F0 0 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0 1 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 2 VOUT23 VOUT22 VOUT21 VOUT20 VOUT19 VOUT18 VOUT17 VOUT16 3 VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24 1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected. Rev. C | Page 20 of 28

AD5372/AD5373 SERIAL INTERFACE The AD5372/AD5373 contain a high speed SPI operating at SPI READBACK MODE clock frequencies up to 50 MHz (20 MHz for read operations). The AD5372/AD5373 allow data readback via the serial To minimize both the power consumption of the device and interface from every register directly accessible to the serial on-chip digital noise, the interface powers up fully only when interface, that is, all registers except the X2A, X2B, and DAC the device is being written to, that is, on the falling edge of data registers. To read back a register, it is first necessary to tell SYNC. The serial interface is 2.5 V LVTTL-compatible when the AD5372/AD5373 which register is to be read. This is achieved operating from a 2.5 V to 3.6 V DV supply. It is controlled by CC by writing a word whose first two bits are the Special Function four pins: SYNC (frame synchronization input), SDI (serial Code 00 to the device. The remaining bits then determine which data input pin), SCLK (clocks data in and out of the device), register is to be read back. and SDO (serial data output pin for data readback). If a readback command is written to a special function register, SPI WRITE MODE data from the selected register is clocked out of the SDO pin The AD5372/AD5373 allow writing of data via the serial interface during the next SPI operation. The SDO pin is normally three- to every register directly accessible to the serial interface, that is, stated but becomes driven as soon as a read command is issued. all registers except the X2A, X2B, and DAC registers. The X2A The pin remains driven until the register data is clocked out. and X2B registers are updated when writing to the X1A, X1B, See Figure 5 for the read timing diagram. Note that due to the M, and C registers, and the DAC data registers are updated by timing requirements of t22 (25 ns), the maximum speed of the LDAC. The serial word (see Table 11 or Table 12) is 24 bits long: SPI interface during a read operation should not exceed 20 MHz. 16 (AD5372) or 14 (AD5373) of these bits are data bits; six bits REGISTER UPDATE RATES are address bits; and two bits are mode bits that determine what The value of the X2A register or the X2B register is calculated is done with the data. Two bits are reserved on the AD5373. each time the user writes new data to the corresponding X1, C, The serial interface works with both a continuous and a burst or M register. The calculation is performed by a three-stage (gated) serial clock. Serial data applied to SDI is clocked into process. The first two stages take approximately 600 ns each, and the AD5372/AD5373 by clock pulses applied to SCLK. The first the third stage takes approximately 300 ns. When the write to an falling edge of SYNC starts the write cycle. At least 24 falling X1, C, or M register is complete, the calculation process begins. clock edges must be applied to SCLK to clock in 24 bits of data If the write operation involves the update of a single DAC before SYNC is taken high again. If SYNC is taken high before channel, the user is free to write to another register, provided the 24th falling clock edge, the write operation is aborted. that the write operation does not finish until the first-stage calculation is complete (that is, 600 ns after the completion of If a continuous clock is used, SYNC must be taken high before the the first write operation). If a group of channels is being updated 25th falling clock edge. This inhibits the clock within the AD5372/ by a single write operation, the first-stage calculation is repeated AD5373. If more than 24 falling clock edges are applied before for each channel, taking 600 ns per channel. In this case, the SYNC is taken high again, the input data becomes corrupted. If user should not complete the next write operation until this time an externally gated clock of exactly 24 pulses is used, SYNC can has elapsed. be taken high any time after the 24th falling clock edge. The input register addressed is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be taken low again. Table 11. AD5372 Serial Word Bit Assignment I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 12. AD5373 Serial Word Bit Assignment I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I11 I01 M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 Bit I1 and Bit I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0. Rev. C | Page 21 of 28

AD5372/AD5373 CHANNEL ADDRESSING AND SPECIAL MODES Table 13. Mode Bits If the mode bits are not 00, the data-word D15 to D0 (AD5372) M1 M0 Action or D13 to D0 (AD5373) is written to the device. Address Bit A5 1 1 Write to DAC data (X) register to Address Bit A0 determine which channels are written to, and 1 0 Write to DAC offset (C) register the mode bits determine to which register (X1A, X1B, C, or M) 0 1 Write to DAC gain (M) register the data is written, as shown in Table 13 and Table 14. Data is to 0 0 Special function, used in combination with other be written to the X1A register when the A/B bit in the control bits of the data-word register is 0, or to the X1B register when the A/B bit is 1. The AD5372/AD5373 have very flexible addressing that allows the writing of data to a single channel, all channels in a group, the same channel in Group 0 to Group 3, the same channel in Group 1 to Group 3, or all channels in the device. Table 14 shows which groups and which channels are addressed for every combination of Address Bit A5 to Address Bit A0. Table 14. Group and Channel Addressing Address Bit A2 Address Bit A5 to Address Bit A3 to Address Bit A0 000 001 010 011 100 101 110 111 000 All groups, Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, all channels Channel 0 Channel 0 Channel 0 Channel 0 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 0 Channel 0 001 Group 0, all Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, channels Channel 1 Channel 1 Channel 1 Channel 1 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 1 Channel 1 010 Group 1, all Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, channels Channel 2 Channel 2 Channel 2 Channel 2 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 2 Channel 2 011 Group 2, all Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, channels Channel 3 Channel 3 Channel 3 Channel 3 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 3 Channel 3 100 Group 3, all Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, channels Channel 4 Channel 4 Channel 4 Channel 4 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 4 Channel 4 101 Reserved Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, Channel 5 Channel 5 Channel 5 Channel 5 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 5 Channel 5 110 Reserved Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, Channel 6 Channel 6 Channel 6 Channel 6 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 6 Channel 6 111 Reserved Group 0, Group 1, Group 2, Group 3, Reserved Group 0, Group 1, Channel 7 Channel 7 Channel 7 Channel 7 Group 1, Group 2, Group 2, Group 3; Group 3; Channel 7 Channel 7 Rev. C | Page 22 of 28

AD5372/AD5373 SPECIAL FUNCTION MODE If the mode bits are 00, then the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback. The codes for the special functions are shown in Table 16. Table 17 shows the addresses for data readback. Table 15. Special Function Mode I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 Table 16. Special Function Codes Special Function Code S5 S4 S3 S2 S1 S0 Data (F15 to F0) Action 0 0 0 0 0 0 0000 0000 0000 0000 NOP. 0 0 0 0 0 1 XXXX XXXX XXXX X[F2:F0] Write control register. F4 = overtemperature indicator (read-only bit). This bit should be 0 when writing to the control register. F3 = reserved. This bit should be 0 when writing to the control register. F2 = 1: Select Register X1B for input. F2 = 0: Select Register X1A for input. F1 = 1: Enable thermal shutdown mode. F1 = 0: Disable thermal shutdown mode. F0 = 1: Software power-down. F0 = 0: Software power-up. 0 0 0 0 1 0 XX[F13:F0] Write data in F13 to F0 to OFS0 register. 0 0 0 0 1 1 XX[F13:F0] Write data in F13 to F0 to OFS1 register. 0 0 0 1 0 0 Reserved 0 0 0 1 0 1 See Table 17 Select register for readback. 0 0 0 1 1 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 0. 0 0 0 1 1 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 1. 0 0 1 0 0 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 2. 0 0 1 0 0 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 3. 0 0 1 0 1 0 Reserved 0 0 1 0 1 1 XXXX XXXX [F7:F0] Block write to A/B select registers. F7 to F0 = 0: Write all 0s (all channels use the X2A register). F7 to F0 = 1: Write all 1s (all channels use the X2B register). Table 17. Address Codes for Data Readback1 F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read 0 0 0 X1A register 0 0 1 Bit F12 to Bit F7 select the channel to be read back, X1B register 0 1 0 from Channel 0 = 001000 to Channel 31 = 100111 C register 0 1 1 M register 1 0 0 0 0 0 0 0 1 Control register 1 0 0 0 0 0 0 1 0 OFS0 data register 1 0 0 0 0 0 0 1 1 OFS1 data register 1 0 0 0 0 0 1 0 0 Reserved 1 0 0 0 0 0 1 1 0 A/B Select Register 0 1 0 0 0 0 0 1 1 1 A/B Select Register 1 1 0 0 0 0 1 0 0 0 A/B Select Register 2 1 0 0 0 0 1 0 0 1 A/B Select Register 3 1 0 0 0 0 1 0 1 0 Reserved 1 Bit F6 to Bit F0 are don’t cares for the data readback function. Rev. C | Page 23 of 28

AD5372/AD5373 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative supplies are In any circuit where accuracy is important, careful consider- connected. This is required to prevent currents from flowing ation of the power supply and ground return layout helps to in directions other than toward an analog or digital ground. ensure the rated performance. The printed circuit boards on which the AD5372/AD5373 are mounted should be designed INTERFACING EXAMPLES so that the analog and digital sections are separated and con- The SPI interface of the AD5372/AD5373 is designed to allow fined to certain areas of the board. If the AD5372/AD5373 are the parts to be easily connected to industry-standard DSPs and in a system where multiple devices require an AGND-to-DGND microcontrollers. Figure 22 shows how the AD5372/AD5373 connection, the connection should be made at one point only. connects to the Analog Devices, Inc., Blackfin® DSP. The Blackfin The star ground point should be established as close as possible has an integrated SPI port that can be connected directly to the to the device. For supplies with multiple pins (V , V , DV ), SS DD CC SPI pins of the AD5372/AD5373 and programmable I/O pins it is recommended that these pins be tied together and that each that can be used to set or read the state of the digital input or supply be decoupled only once. output pins associated with the interface. The AD5372/AD5373 should have ample supply decoupling of AD5372/ 10 μF in parallel with 0.1 μF on each supply located as close to AD5373 the package as possible, ideally right up against the device. The SPISELx SYNC 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor SCK SCLK should have low effective series resistance (ESR) and low effective MOSI SDI series inductance (ESI)—typical of the common ceramic types MISO SDO that provide a low impedance path to ground at high frequencies— PF10 RESET to handle transient currents due to internal logic switching. ADSP-BF531 PF9 LDAC PF8 CLR Digital lines running under the device should be avoided because tshheoyu lcda nb ec oaullpowle endo tiose r ounnt ou nthdee rd tehvei cAe.D T5h3e7 2an/AalDog5 3g7r3o uton da vpoliadn e PF7 BUSY 05815-021 Figure 22. Interfacing to a Blackfin DSP noise coupling. The power supply lines of the AD5372/AD5373 The Analog Devices ADSP-21065L is a floating-point DSP with should use as large a trace as possible to provide low impedance two serial ports (SPORTs). Figure 23 shows how one SPORT can paths and reduce the effects of glitches on the power supply line. be used to control the AD5372/AD5373. In this example, the Fast switching digital signals should be shielded with digital transmit frame synchronization (TFSx) pin is connected to the ground to avoid radiating noise to other parts of the board, and receive frame synchronization (RFSx) pin. Similarly, the transmit they should never be run near the reference inputs. It is essential and receive clocks (TCLKx and RCLKx) are also connected. The to minimize noise on the VREF0 and VREF1 lines. user can write to the AD5372/AD5373 by writing to the transmit Avoid crossover of digital and analog signals. Traces on register of the ADSP-21065L. A read operation can be accom- opposite sides of the board should run at right angles to plished by first writing to the AD5372/AD5373 to tell the part each other. This reduces the effects of feedthrough through that a read operation is required. A second write operation with the board. A microstrip technique is by far the best approach, an NOP instruction causes the data to be read from the but it is not always possible with a double-sided board. In this AD5372/AD5373. The DSP receive interrupt can be used to technique, the component side of the board is dedicated to indicate when the read operation is complete. ground plane, while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid ADSP-21065L AD5372/ TFSx AD5373 flexing the package and to avoid a point load on the surface of RFSx SYNC this package during the assembly process. TCLKx RCLKx SCLK POWER SUPPLY SEQUENCING DTxA SDI When the supplies are connected to the AD5372/AD5373, it is DRxA SDO important that the AGND and DGND pins be connected to the FLAG0 RESET relevant ground plane before the positive or negative supplies FLAG1 LDAC agrreo uapnpdl ipeidn.s I fno rm tohset paopwpleirc astuiopnpsli,e tsh aisr ei sc nonotn aenct iesds utoe btheec agursoeu tnhde FFLLAAGG23 CBLURSY 05815-022 pins of the AD5372/AD5373 via ground planes. When the Figure 23. Interfacing to an ADSP-21065L DSP AD5372/AD5373 are to be used in a hot-swap card, care should Rev. C | Page 24 of 28

AD5372/AD5373 OUTLINE DIMENSIONS 9.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 49 64 1 48 PIN 1 INDICATOR 0.50 7.25 TOP VIEW BS8C.7 5SQ BSC EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6.95 0.50 0.40 33 16 32 17 0.30 0.25 MIN 7.50 REF 1.00 12° MAX 0.80 MAX 0.85 0.65 TYP FOR PROPER CONNECTION OF 0.05 MAX THE EXPOSED PAD, REFER TO 0.80 0.02 NOM THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SEATING 0.30 SECTION OF THIS DATA SHEET. PLANE 0.23 0.20 REF 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 080108-C Figure 24. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-3) Dimensions shown in millimeters 12.20 0.75 12.00 SQ 0.60 1.60 11.80 0.45 MAX 64 49 1 48 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 0.15 0° 16 33 0.05 SPLEAANTEING 0.08 17 32 COPLANARITY VIEW A 0.27 0.50 BSC 0.22 VIEW A LEAD PITCH 0.17 ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BCD 051706-A Figure 25. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters Rev. C | Page 25 of 28

AD5372/AD5373 ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD5372BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-2 AD5372BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-2 AD5372BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-3 AD5372BCPZ-RL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-3 AD5373BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-2 AD5373BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-2 AD5373BCPZ −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-3 AD5373BCPZ-RL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-3 EVAL-AD5372EBZ Evaluation Board EVAL-AD5373EBZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. C | Page 26 of 28

AD5372/AD5373 NOTES Rev. C | Page 27 of 28

AD5372/AD5373 NOTES ©2007–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05815-0-7/11(C) Rev. C | Page 28 of 28