40-Channel, 14-Bit, Serial Input, Voltage Output DAC AD5371 FEATURES 40-channel DAC in 80-lead LQFP and 100-ball CSP_BGA 2.5 V to 5.5 V digital interface Guaranteed monotonic to 14 bits Digital reset (RESET) Maximum output voltage span of 4 × V (20 V) Clear function to user-defined SIGGNDx REF Nominal output voltage span of −4 V to +8 V Simultaneous update of DAC outputs Multiple, independent output voltage spans available APPLICATIONS System calibration function allowing user-programmable offset and gain Level setting in automatic test equipment (ATE) Channel grouping and addressing features Variable optical attenuators (VOA) Thermal shutdown function Optical switches DSP/microcontroller-compatible serial interface Industrial control systems SPI/LVDS serial interface Instrumentation FUNCTIONAL BLOCK DIAGRAM DVCC VDD VSS AGND DGND LDAC VREF0 RCEOGNITSRTOELR 14 8 AR/BE GSIESLTEECRT 8 MTUOX2 14 REOGFISST0ER14 ODFAFCS E0T BUFFBEURFFEROUTPUT GBURFOFUEPR 0 1144 REGXXI11SABTER MUX 1 14 14 REGXXI22SABTER MUX 2 14 REDGAISCT 0ER14 DAC 0 POCWOEANRNT-DRDOOLWN VVVOOOUUUTTT012 REGISTER REGISTER 14 14 VOUT3 SPI/LVDS 14 M REGISTER 14 VOUT4 SYNC C REGISTER VOUT5 SDI VOUT6 OUTPUT BUFFER SSYCSNLDCKI INTSEERRFIAALCE 1144 REGXXI11SABTER MUX 1 14 14 REGXXI22SABTER MUX 2 14 REDGAISCT 7ER14 DAC 7 POCWOEANRNT-DRDOOLWN SVIOGUGTN7D0 REGISTER REGISTER SCLK 14 14 M REGISTER SDO 14 C REGISTER 14 VREF1 BUSY 14 14 BUFFER GROUP 1 OFS1 OFFSET RESET 8 AR/BE GSIESLTEECRT 8 MTUOX2 REGISTER DAC 1 BUFFER OUTPUT BUFFER CLR MSATCAHTINEE 1144 REGXXI11SABTER MUX 1 14 14 REGXXI22SABTER MUX 2 14 REDGAISCT 0ER14 DAC 0 POCWOEANRNT-DRDOOLWN VVVOOOUUUTTT8910 14 REGISTER 14 REGISTER VOUT11 14 M REGISTER 14 14 VOUT12 C REGISTER VOUT13 VOUT14 OUTPUT BUFFER 1144 REGXXI11SABTER MUX 1 14 14 REGXXI22SABTER MUX 2 14 REDGAISCT 7ER14 DAC 7 POCWOEANRNT-DRDOOLWN VSIOGUGTN1D51 REGISTER REGISTER 14 14 M REGISTER 14 14 VREF2 AD5371 C REGISTER VREF2 SUPPLIES GROUP 2 TO GROUP 4 GROUP 2 TO GROUP 4 VOUT16 ARE SAME AS GROUP 1 TO VOUT39 SIGGND2 SIGGND3 SIGGND4 05814-001 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5371 TABLE OF CONTENTS Features..............................................................................................1 Calibration...................................................................................19 Applications.......................................................................................1 Additional Calibration...............................................................19 Functional Block Diagram..............................................................1 Reset Function............................................................................20 Revision History...............................................................................2 Clear Function............................................................................20 General Description.........................................................................3 BUSY and LDAC Functions......................................................20 Specifications.....................................................................................4 Power-Down Mode....................................................................20 Performance Specifications.........................................................4 Thermal Shutdown Function...................................................20 AC Characteristics........................................................................5 Toggle Mode................................................................................21 Timing Characteristics................................................................6 Serial Interface................................................................................22 Absolute Maximum Ratings............................................................9 SPI Interface................................................................................22 ESD Caution..................................................................................9 LVDS Interface............................................................................22 Pin Configurations and Function Descriptions.........................10 SPI Write Mode..........................................................................22 Typical Performance Characteristics...........................................13 SPI Readback Mode...................................................................23 Terminology....................................................................................15 LVDS Operation.........................................................................23 Theory of Operation......................................................................16 Register Update Rates................................................................23 DAC Architecture.......................................................................16 Channel Addressing and Special Modes.................................23 Channel Groups..........................................................................16 Special Function Mode..............................................................25 A/B Registers and Gain/Offset Adjustment............................17 Applications Information..............................................................27 Load DAC....................................................................................17 Power Supply Decoupling.........................................................27 Offset DACs................................................................................17 Power Supply Sequencing.........................................................27 Output Amplifier........................................................................18 Interfacing Examples.................................................................27 Transfer Function.......................................................................18 Outline Dimensions.......................................................................28 Reference Selection....................................................................18 Ordering Guide..........................................................................28 REVISION HISTORY 3/08—Rev. A to Rev. B 11/07—Rev. 0 to Rev. A Added Table 1....................................................................................3 Reformatted Specifications Table 1.................................................3 Changes to Timing Characteristics Section..................................6 Reformatted Specifications Table 2.................................................6 Changes to Absolute Maximum Ratings Section.........................9 Change to A/B Registers and Gain/Offset Changes to Table 7..........................................................................11 Adjustment Section........................................................................19 Changes to Figure 16, Figure 18, and Figure 19.........................14 Change to SPI Write Mode Section..............................................24 Changes to A/B Registers and Gain/Offset Adjustment Changes to Ordering Guide..........................................................31 Section and Load DAC Section....................................................17 8/07—Revision 0: Initial Version Changes to Transfer Function Section.........................................18 Changes to Calibration Section....................................................19 Changes to Reset Function Section and Clear Function Section..............................................................................................20 Changes to Table 9..........................................................................20 Changes to Register Update Rates Section..................................23 Rev. B | Page 2 of 28

AD5371 GENERAL DESCRIPTION The AD53711 contains 40 14-bit DACs in a single 80-lead LQFP The AD5371 has a high speed serial interface that is compatible or 100-ball CSP_BGA. The device provides buffered voltage with SPI, QSPI™, MICROWIRE™, and DSP interface standards outputs with a span of 4× the reference voltage. The gain and and can handle clock speeds of up to 50 MHz. It also has a offset of each DAC can be independently trimmed to remove 100 MHz low voltage differential signaling (LVDS) serial errors. For even greater flexibility, the device is divided into five interface. groups of eight DACs. Three offset DACs allow the output range The DAC registers are updated on reception of new data. All the of the groups to be adjusted. Group 0 can be adjusted by Offset outputs can be updated simultaneously by taking the LDAC DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2 input low. Each channel has a programmable gain and an offset to Group 4 can be adjusted by Offset DAC 2. adjust register to allow removal of gain and offset errors. The AD5371 offers guaranteed operation over a wide supply Each DAC output is gained and buffered on chip with respect range, with V from −16.5 V to −4.5 V and V from 9 V to SS DD to an external SIGGNDx input. The DAC outputs can also be 16.5 V. The output amplifier headroom requirement is 1.4 V switched to SIGGNDx via the CLR pin. operating with a load current of 1 mA. 1 Protected by U.S. Patent No. 5,969,657; other patents pending. Table 1. High Channel Count Bipolar DACs Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB) AD5360 16 4 × V (20 V) 16 ±4 REF AD5361 14 4 × V (20 V) 16 ±1 REF AD5362 16 4 × V (20 V) 8 ±4 REF AD5363 14 4 × V (20 V) 8 ±1 REF AD5370 16 4 × V (12 V) 40 ±4 REF AD5371 14 4 × V (12 V) 40 ±1 REF AD5372 16 4 × V (12 V) 32 ±4 REF AD5373 14 4 × V (12 V) 32 ±1 REF AD5378 14 ±8.75 V 32 ±3 AD5379 14 ±8.75 V 40 ±3 Rev. B | Page 3 of 28

AD5371 SPECIFICATIONS PERFORMANCE SPECIFICATIONS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −8 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; C = open circuit; CC DD SS L R = open circuit; gain (M), offset (C), and DAC offset registers at default values; temperature range for the AD5371 is −40°C to +85°C; all L specifications T to T , unless otherwise noted. MIN MAX Table 2. Parameter Min Typ1 Max Unit Test Conditions/Comments1 ACCURACY Resolution 14 Bits Integral Nonlinearity (INL) −1 +1 LSB Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic by design Zero-Scale Error −10 +10 mV Before calibration Full-Scale Error −10 +10 mV Before calibration Gain Error 0.1 % FSR Zero-Scale Error2 1 LSB After calibration Full-Scale Error2 1 LSB After calibration Span Error of Offset DAC −35 +35 mV See the Offset DACs section for details VOUTx Temperature Coefficient 5 ppm Includes linearity, offset, and gain drift (VOUT0 to VOUT39) FSR/°C DC Crosstalk2 120 μV Typically 20 μV; measured channel at midscale, full-scale change on any other channel REFERENCE INPUTS (VREF0, VREF1, VREF2)2 VREFx Input Current −10 +10 μA Per input; typically ±30 nA VREFx Range 2 5 V ±2% for specified operation SIGGND INPUTS (SIGGND0 TO SIGGND4)2 DC Input Impedance 50 kΩ Typically 55 kΩ Input Range −0.5 +0.5 V SIGGNDx Gain 0.995 1.005 OUTPUT CHARACTERISTICS2 Output Voltage Range V + 1.4 V − 1.4 V I = 1 mA SS DD LOAD Nominal Output Voltage Range −4 +8 V Short-Circuit Current 15 mA VOUTx to DV , V , or V CC DD SS Load Current −1 +1 mA Capacitive Load 2200 pF DC Output Impedance 0.5 Ω DIGITAL INPUTS Input High Voltage 1.7 V DV = 2.5 V to 3.6 V CC 2.0 V DV = 3.6 V to 5.5 V CC Input Low Voltage 0.8 V DV = 2.5 V to 5.5 V CC Input Current −1 +1 μA Excluding CLR pin CLR High Impedance Leakage Current −20 +20 μA Input Capacitance2 10 pF DIGITAL OUTPUTS (SDO, BUSY) Output Low Voltage 0.5 V Sinking 200 μA Output High Voltage (SDO) DV − 0.5 V Sourcing 200 μA CC SDO High Impedance Leakage Current −5 +5 μA High Impedance Output Capacitance2 10 pF Rev. B | Page 4 of 28

AD5371 Parameter Min Typ1 Max Unit Test Conditions/Comments1 LVDS INTERFACE (REDUCED RANGE LINK) Digital Inputs2 Input Voltage Range 875 1575 mV Input Differential Threshold –0.1 +0.1 V External Termination Resistance 80 100 132 Ω Differential Input Voltage 100 mV POWER REQUIREMENTS DV 2.5 5.5 V CC V 9 16.5 V DD V −16.5 −4.5 V SS Power Supply Sensitivity2 ∆Full Scale/∆V −75 dB DD ∆Full Scale/∆V −75 dB SS ∆Full Scale/∆DV −90 dB CC DI 2 mA DV = 5.5 V, V = DV , V = GND; normal CC CC IH CC IL operating conditions I 18 mA Outputs unloaded, DAC outputs = 0 V DD 20 mA Outputs unloaded, DAC outputs = full scale I −18 mA Outputs unloaded, DAC outputs = 0 V SS −20 mA Outputs unloaded, DAC outputs = full scale Power Dissipation Unloaded (P) 280 mW V = −8 V, V = 9.5 V, DV = 2.5 V SS DD CC Power-Down Mode Control register power-down bit set DI 5 μA CC I 35 μA DD I −35 μA SS Junction Temperature3 130 °C T = T + P × θ J A TOTAL JA 1 Typical specifications are at 25°C. 2 Guaranteed by design and characterization; not production tested. 3 θJA represents the package thermal impedance. AC CHARACTERISTICS DV = 2.5 V; V = 15 V; V = −15 V; VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; C = 200 pF; R = 10 kΩ; gain (M), offset (C), CC DD SS L L and DAC offset registers at default values; all specifications T to T , unless otherwise noted. MIN MAX Table 3. AC Characteristics1 Parameter Min Typ Max Unit Test Conditions/Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 20 μs Settling to 1 LSB from a full-scale change 30 μs DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs Digital-to-Analog Glitch Energy 5 nV-s Glitch Impulse Peak Amplitude 10 mV Channel-to-Channel Isolation 100 dB VREF0, VREF1, VREF2 = 2 V p-p, 1 kHz DAC-to-DAC Crosstalk 20 nV-s Digital Crosstalk 0.2 nV-s Digital Feedthrough 0.02 nV-s Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 10 kHz 250 nV/√Hz V = 0 V REF 1 Guaranteed by design and characterization; not production tested. Rev. B | Page 5 of 28

AD5371 TIMING CHARACTERISTICS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; C = 200 pF to GND; CC DD SS L R = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. L MIN MAX Table 4. SPI Interface Parameter 1, 2, 3 Limit at T , T Unit Description MIN MAX t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 11 ns min SYNC falling edge to SCLK falling edge setup time 4 t5 20 ns min Minimum SYNC high time t 10 ns min 24th SCLK falling edge to SYNC rising edge 6 t 5 ns min Data setup time 7 t 5 ns min Data hold time 8 t 4 42 ns max SYNC rising edge to BUSY falling edge 9 t 1/1.5 μs typ/μs max BUSY pulse width low (single-channel update); see Table 9 10 t 600 ns max Single-channel update cycle time 11 t 20 ns min SYNC rising edge to LDAC falling edge 12 t 10 ns min LDAC pulse width low 13 t 3 μs max BUSY rising edge to DAC output response time 14 t 0 ns min BUSY rising edge to LDAC falling edge 15 t 3 μs max LDAC falling edge to DAC output response time 16 t 20/30 μs typ/μs max DAC output settling time 17 t 140 ns max CLR/RESET pulse activation time 18 t 30 ns min RESET pulse width low 19 t 400 μs max RESET time indicated by BUSY low 20 t 270 ns min Minimum SYNC high time in readback mode 21 t 5 25 ns max SCLK rising edge to SDO valid 22 t 80 ns max RESET rising edge to BUSY falling edge 23 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 t9 is measured with the load circuit shown in Figure 2. 5 t22 is measured with the load circuit shown in Figure 3. Table 5. LVDS Interface Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 12 ns min SCLK cycle time 1 t 5 ns min SCLK pulse width high and low time 2 t 5 ns min SYNC to SCLK setup time 3 t 3 ns min Data setup time 4 t 3 ns min Data hold time 5 t 3 ns min SCLK to SYNC hold time 6 t 10 ns min SYNC high time 7 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 6. Rev. B | Page 6 of 28

AD5371 Circuit and Timing Diagrams 200µA IOL DVCC TO OUTPUT VOH (MIN) – VOL (MAX) R2.L2kΩ PIN CL 2 TO 50pF OUTPUT VOL PIN C50LpF 05814-002 200µA IOH 05814-003 Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram t 1 SCLK 1 2 24 1 24 t3 t2 t11 t4 t6 SYNC t5 t 7 t 8 SDI DB23 DB0 t 9 t BUSY 10 t12 t13 LDAC1 t 17 t VOUTx1 14 t 15 t 13 LDAC2 t 17 VOUTx2 t16 CLR t 18 VOUTx t 19 RESET VOUTx t 18 t 20 BUSY t 23 21LLDDAACC AACCTTIIVVEE DAUFTREINRG B BUUSSYY.. 05814-004 Figure 4. SPI Write Timing Rev. B | Page 7 of 28

AD5371 t 22 SCLK 48 t 21 SYNC SDI DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB0 DB23 DB15 DB0 LSB FROM PREVIOUS WRITE SELECTED REGISTER DATA CLOCKED OUT 05814-005 Figure 5. SPI Read Timing SYNC SYNC t3 t1 t6 SCLK SCLK MSB t2 t4 LSB D23 D0 SDI SDI t5 05814-006 Figure 6. LVDS Timing Rev. B | Page 8 of 28

AD5371 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents of up to A Stresses above those listed under Absolute Maximum Ratings 60 mA do not cause SCR latch-up. may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any Table 6. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +17 V DD maximum rating conditions for extended periods may affect V to AGND −17 V to +0.3 V SS device reliability. DV to DGND −0.3 V to +7 V CC Digital Inputs to DGND −0.3 V to DV + 0.3 V CC ESD CAUTION Digital Outputs to DGND −0.3 V to DV + 0.3 V CC VREF0, VREF1, VREF2 to AGND −0.3 V to +5.5 V VOUT0 through VOUT39 to AGND V − 0.3 V to V + 0.3 V SS DD SIGGND0 through SIGGND4 to AGND −1 V to +1 V AGND to DGND −0.3 V to +0.3 V Operating Temperature Range (TA) Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Operating Junction Temperature 130°C (T max) J θ Thermal Impedance JA 80-Lead LQFP 38.72°C/W 100-Ball CSP_BGA 40°C/W Reflow Soldering Peak Temperature 230°C Time at Peak Temperature 10 sec to 40 sec Rev. B | Page 9 of 28

AD5371 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS S OUT26 OUT25 OUT24 GND GND VCCDO ESTO PI/LVD DI DI CLK CLK YNC YNC VCCGND OUT7 OUT6 OUT5 V V V A D D S T S S S S S S S D D V V V 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 LDAC 1 60 VOUT4 CLR 2 PIN 1 59 NC RESET 3 58 SIGGND0 BUSY 4 57 VOUT3 TESTI 5 56 VOUT2 VOUT27 6 55 VOUT1 SIGGND3 7 54 VOUT0 VOUT28 8 53 NC VOUT29 9 52 VREF0 AD5371 VOUT30 10 51 NC TOP VIEW VOUT31 11 (Not to Scale) 50 VREF2 VOUT32 12 49 VOUT23 VOUT33 13 48 VOUT22 VOUT34 14 47 VOUT21 VOUT35 15 46 VOUT20 SIGGND4 16 45 VSS VOUT36 17 44 VDD VOUT37 18 43 NC VDD 19 42 NC VSS 20 41 SIGGND2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC = NO CONNECT VREF1 NC NC NC VOUT38 VOUT39 VOUT8 VOUT9 VOUT10 VOUT11 SIGGND1 VOUT12 VOUT13 VOUT14 NC VOUT15 VOUT16 VOUT17 VOUT18 VOUT19 05814-007 Figure 7. 80-Lead LQFP Pin Configuration Rev. B | Page 10 of 28

AD5371 12 11 10 9 8 7 6 5 4 3 2 1 SPI/ DGND DGND DVCC SYNC SCLK SDI LVDS TESTO LDAC CLR NC AGND A VOUT6 VOUT7 DVCC SYNC SCLK SDI NC SDO RESET BUSY TESTI AGND B VOUT4 VOUT5 AGND AGND C VOUT3 SIGGND0 AGND AGND AGND AGND AGND AGND VOUT25 VOUT26 D VOUT1 VOUT2 AGND VSS VOUT24 VOUT27 E VOUT0 NC AGND VSS NC SIGGND3 F VREF0 NC AGND VSS VOUT28 NC G VOUT23 VREF2 AGND VSS VOUT30 VOUT29 H VOUT21 VOUT22 VDD VDD VDD VDD VDD VSS VOUT32 VOUT31 J VOUT20 VOUT19 VOUT34 VOUT33 K SIGGND2 VDD VOUT17 VOUT15 VOUT13 SIGGND1 VOUT10 VOUT8 VOUT38 SIGGND4 VSS VOUT35 L VDD VOUT18 VOUT16 VOUT14 VOUT12 VOUT11 VOUT9 VOUT39 VREF1 VOUT37 VOUT36 VSS M 05814-025 Figure 8. 100-Ball Grid Array Pin Configuration—Bottom View Table 7. Pin Function Descriptions Pin No. Ball No. Mnemonic Description 1 A4 LDAC Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information. 2 A3 CLR Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for more information. 3 B4 RESET Digital Reset Input. 4 B3 BUSY Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and LDAC Functions section for more information. 5 B2 TESTI Test Input Pin. Connect this pin to DGND. 73 A5 TESTO Test Output Pin. This pin remains unconnected. 54 to 57, F12, E12, E11, VOUT0 to DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output 60 to 63, D12, C12, C11, VOUT39 is capable of driving an output load of 10 kΩ to ground. Typical output impedance of these 27 to 30, B12, B11, L5, amplifiers is 0.5 Ω. 32 to 34, M6, L6, M7, 36 to 40, M8, L8, M9, L9, 46 to 49, M10, L10, M11, 78 to 80, K11, K12, J12, 6, 8 to 15, J11, H12, E2, 17, 18, D2, D1, E1, G2, 25, 26 H1, H2, J1, J2, K1, K2, L1, M2, M3, L4, M5 Rev. B | Page 11 of 28

AD5371 Pin No. Ball No. Mnemonic Description 58 D11 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage. 31 L7 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage. 41 L12 SIGGND2 Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage. 7 F1 SIGGND3 Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage. 16 L3 SIGGND4 Reference Ground for DAC 32 to DAC 39. VOUT32 to VOUT39 are referenced to this voltage. 52 G12 VREF0 Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND. 21 M4 VREF1 Reference Input for DAC 8 to DAC 15. This reference voltage is referred to AGND. 50 H11 VREF2 Reference Input for DAC 16 to DAC 39. This reference voltage is referred to AGND. 19, 44 J5 to J9, L11, V Positive Analog Power Supply; 9 V to 16.5 V for specified performance. Decouple these pins DD M12 with 0.1 μF ceramic capacitors and 10 μF capacitors. 20, 45 E4, F4, G4, H4, V Negative Analog Power Supply; −16.5 V to −8 V for specified performance. Decouple these SS J4, L2, M1 pins with 0.1 μF ceramic capacitors and 10 μF capacitors. 64, 76 A11, A12 DGND Ground for All Digital Circuitry. Connect both DGND pins to the DGND plane. 65, 75 A10, B10 DV Logic Power Supply; 2.5 V to 5.5 V. Decouple these pins with 0.1 μF ceramic capacitors and CC 10 μF capacitors. 66 A9 SYNC Active Low or Differential SYNC Input (Complement) for SPI or LVDS Interface. This is the frame synchronization signal for the SPI or LVDS serial interface. See the Timing Characteristics section for more details. 67 B9 SYNC Differential SYNC Input for LVDS Interface. This is the frame synchronization signal for the LVDS serial interface. See the Timing Characteristics section for more details. 68 A8 SCLK Serial Clock Input for SPI or LVDS Interface. See the Timing Characteristics section for more details. 69 B8 SCLK Differential Serial Clock Input (Complement) for LVDS Interface. See the Timing Characteristics section for more details. 70 A7 SDI Serial Data Input for SPI or LVDS Interface. See the Timing Characteristics section for more details. 71 B7 SDI Differential Serial Data Input (Complement) for LVDS Interface. See the Timing Characteristics section for more details. 72 A6 SPI/LVDS Interface Selection Pin. If the pin is low, the SPI interface is selected. If the pin is high, the LVDS interface is selected. 74 B5 SDO Serial Data Output for SPI Interface. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK. 77 A1, B1, C1, C2, AGND Ground for All Analog Circuitry. Connect the AGND pin to the AGND plane. D4 to D9, E9, F9, G9, H9 22 to 24, A2, B6, F2, F11, NC No Connect. Do not connect these pins. 35, 42, G1, G11 43, 51, 53, 59 Rev. B | Page 12 of 28

AD5371 TYPICAL PERFORMANCE CHARACTERISTICS 0.50 0 TA = 25°C VSS = –15V VDD = +15V VREF = +4.096V 0.25 V) B) E ( S D INL (L 0 MPLITU–0.01 A –0.25 –0.50 05814-009 –0.02 05814-012 0 4096 8192 12288 16383 0 2 4 6 8 10 DACCODE TIME(µs) Figure 9. Typical INL Plot Figure 12. Analog Crosstalk Due to LDAC 0.0050 7 VDD = +15V TA = 25°C VSS = –15V VSS = –15V TA = 25°C VDD = +15V 6 VREF = +4.096V 0.0025 OF UNITS 54 TUDE (V) 0 R LI E P B 3 M M A U N 2 –0.0025 10 05814-010 –0.00500 1 2 3 4 505814-013 –0.6 –0.3 0 0.3 0.6 TIME (µs) INL (LSB) Figure 10. Typical INL Distribution Figure 13. Digital Crosstalk 1.0 1.0 VDD = +15V VSS = –15V DVCC = +5V VREF = +3V 0.5 0.5 B) OR (LS 0 L (LSB) 0 R N R D E L N I –0.5 –0.5 –1.0 05814-011 –1.00 4096 8192 12288 163805814-0143 0 20 40 60 80 DACCODE TEMPERATURE (°C) Figure 11. Typical INL Error vs. Temperature Figure 14. Typical DNL Plot Rev. B | Page 13 of 28

AD5371 600 14 VSS = –15V VDD = +15V 500 12 TA = 25°C E (nV/ Hz) 400 OF UNITS 108 NOIS 300 BER 6 T M U U TP 200 N 4 U O 1000 05814-015 20 13.00 13.25 13.50 13.75 14.00 05814-018 0 1 2 3 4 5 IDD (mA) FREQUENCY(Hz) Figure 15. Output Noise Spectral Density Figure 18. Typical IDD Distribution 0.50 VVDSSD == –+1122VV 14 DTAV C=C 2 =5° 5CV VREF = +3V 12 0.45 S 10 DVCC = +5.5V NIT (mA)C 0.40 DVCC = +3.6V R OF U 8 DIC 0.35 MBE 6 DVCC = +2.5V NU 4 0.30 2 0.25 05814-016 0 05814-019 0.30 0.35 0.40 0.45 0.50 –40 –20 0 20 40 60 80 DICC (mA) TEMPERATURE (°C) Figure 16. DICC vs. Temperature Figure 19. Typical DICC Distribution 14.0 IDD 13.5 A| ) m ( |S 13.0 /IDS ISS D I 12.5 12.0 VVVDRSSDE F== –=+1 1+223VVV 05814-017 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 17. IDD/ISS vs. Temperature Rev. B | Page 14 of 28

AD5371 TERMINOLOGY Integral Nonlinearity (INL) Output Voltage Settling Time Integral nonlinearity, or endpoint linearity, is a measure of the Output voltage settling time is the amount of time it takes for maximum deviation from a straight line passing through the the output of a DAC to settle to a specified level for a full-scale endpoints of the DAC transfer function. It is measured after input change. adjusting for zero-scale error and full-scale error and is Digital-to-Analog Glitch Energy expressed in least significant bits (LSB). Digital-to-analog glitch energy is the amount of energy that is Differential Nonlinearity (DNL) injected into the analog output at the major code transition. It Differential nonlinearity is the difference between the measured is specified as the area of the glitch in nV-s. It is measured by change and the ideal 1 LSB change between any two adjacent toggling the DAC register data between 0x1FFF and 0x2000. codes. A specified differential nonlinearity of 1 LSB maximum Channel-to-Channel Isolation ensures monotonicity. Channel-to-channel isolation refers to the proportion of input Zero-Scale Error signal from the reference input of one DAC that appears at the output of another DAC operating from another reference. It is Zero-scale error is the error in the DAC output voltage when expressed in decibels and measured at midscale. all 0s are loaded into the DAC register. Zero-scale error is a measure of the difference between VOUT (actual) and VOUT DAC-to-DAC Crosstalk (ideal), expressed in millivolts (mV), when the channel is at its DAC-to-DAC crosstalk is the glitch impulse that appears at the minimum value. Zero-scale error is mainly due to offsets in the output of one converter due to both the digital change and output amplifier. subsequent analog output change at another converter. It is specified in nV-s. Full-Scale Error Full-scale error is the error in the DAC output voltage when all Digital Crosstalk 1s are loaded into the DAC register. Full-scale error is a measure Digital crosstalk is defined as the glitch impulse transferred to of the difference between VOUT (actual) and VOUT (ideal), the output of one converter due to a change in the DAC register expressed in millivolts, when the channel is at its maximum code of another converter. It is specified in nV-s. value. Full-scale error does not include zero-scale error. Digital Feedthrough Gain Error When the device is not selected, high frequency logic activity Gain error is the difference between full-scale error and on the digital inputs of the device can be capacitively coupled zero-scale error. It is expressed as a percentage of the full- both across and through the device to appear as noise on the scale range (FSR). VOUTx pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough. Gain Error = Full-Scale Error − Zero-Scale Error Output Noise Spectral Density VOUT Temperature Coefficient Output noise spectral density is a measure of internally gener- The VOUT temperature coefficient includes output error ated random noise. Random noise is characterized as a spectral contributions from linearity, offset, and gain drift. density (voltage per √Hz). It is measured by loading all DACs DC Output Impedance to midscale and measuring noise at the output. It is measured DC output impedance is the effective output source resistance. in nV/√Hz. It is dominated by package lead resistance. DC Crosstalk The DAC outputs are buffered by op amps that share common V and V power supplies. If the dc load current changes in DD SS one channel (due to an update), this change can result in a further dc change in one or more channel outputs. This effect is more significant at high load currents and is reduced as the load currents are reduced. With high impedance loads, the effect is virtually immeasurable. Multiple V and V terminals are DD SS provided to minimize dc crosstalk. Rev. B | Page 15 of 28

AD5371 THEORY OF OPERATION DAC ARCHITECTURE output voltage by 4. The nominal output span is 12 V with a 3 V reference and 20 V with a 5 V reference. The AD5371 contains 40 DAC channels and 40 output amplifiers in a single package. The architecture of a single DAC channel CHANNEL GROUPS consists of a 14-bit resistor-string DAC followed by an output The 40 DAC channels of the AD5371 are arranged into five buffer amplifier. The resistor-string section is simply a string of groups of eight channels. The eight DACs of Group 0 derive resistors, of equal value, from VREFx to AGND. This type of their reference voltage from VREF0. The eight DACs of Group 1 architecture guarantees DAC monotonicity. The 14-bit binary derive their reference voltage from VREF1. Group 2 to Group 4 digital code loaded to the DAC register determines at which derive their reference voltage from VREF2. Each group has its node on the string the voltage is tapped off before being fed into own signal ground pin. the output amplifier. The output amplifier multiplies the DAC Table 8. Register Descriptions Word Register Length Default Name (Bits) Value Description X1A 14 0x1555 Input Data Register A. One for each DAC channel. X1B 14 0x1555 Input Data Register B. One for each DAC channel. M 14 0x3FFF Gain trim registers. One for each DAC channel. C 14 0x2000 Offset trim registers. One for each DAC channel. X2A 14 Not user Output Data Register A. One for each DAC channel. These registers store the final, calibrated DAC accessible data after gain and offset trimming. They are not readable or directly writable. X2B 14 Not user Output Data Register B. One for each DAC channel. These registers store the final, calibrated DAC accessible data after gain and offset trimming. They are not readable or directly writable. DAC Not user Data registers from which the DACs take their final input data. The DAC registers are updated from accessible the X2A or X2B register. They are not readable or directly writable. OFS0 14 0x1555 Offset DAC 0 data register. Sets offset for Group 0. OFS1 14 0x1555 Offset DAC 1 data register. Sets offset for Group 1. OFS2 14 0x1555 Offset DAC 2 data register. Sets offset for Group 2 to Group 4. Control 3 0x00 Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = global selection of X1B input data registers. Bit 1 = enable thermal shutdown. 0 = disable thermal shutdown. 1 = enable thermal shutdown. Bit 0 = software power-down. 0 = software power-up. 1 = software power-down. A/B Select 0 8 0x00 Each bit in this register determines if a DAC in Group 0 takes its data from Register X2A or Register X2B. 0 = X2A. 1 = X2B. A/B Select 1 8 0x00 Each bit in this register determines if a DAC in Group 1 takes its data from Register X2A or Register X2B. 0 = X2A. 1 = X2B. A/B Select 2 8 0x00 Each bit in this register determines if a DAC in Group 2 takes its data from Register X2A or Register X2B. 0 = X2A. 1 = X2B. A/B Select 3 8 0x00 Each bit in this register determines if a DAC in Group 3 takes its data from Register X2A or Register X2B. 0 = X2A. 1 = X2B. A/B Select 4 8 0x00 Each bit in this register determines if a DAC in Group 4 takes its data from Register X2A or Register X2B. 0 = X2A. 1 = X2B. Rev. B | Page 16 of 28

AD5371 A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT LOAD DAC Each DAC channel has seven data registers. The actual DAC All DACs in the AD5371 can be updated simultaneously by data-word can be written to either the X1A or the X1B input taking LDAC low when each DAC register is updated from register, depending on the setting of the A/B bit in the control either its X2A or X2B register, depending on the setting of the register. If the A/B bit is 0, data is written to the X1A register. A/B select registers. The DAC register is not readable or directly If the A/B bit is 1, data is written to the X1B register. Note that writable by the user. LDAC can be permanently tied low, and this single bit is a global control and affects every DAC channel the DAC output is updated whenever new data appears in the in the device. It is not possible to set up the device on a per- appropriate DAC register. channel basis so that some writes are to X1A registers and OFFSET DACS some writes are to X1B registers. In addition to the gain and offset trim for each DAC, there are X1A X2A three 14-bit offset DACs, one for Group 0, one for Group 1, and REGISTER REGISTER MUX MUX REGDIASCTER DAC one for Group 2 to Group 4. These allow the output range of all X1B X2B DACs connected to them to be offset within a defined range. REGISTER REGISTER Thus, subject to the limitations of headroom, it is possible to set M REGISTER the output range of Group 0, Group 1, or Group 2 to Group 4 to REGICSTER 05814-020 briec auln oipr oalsayrm pmoseittirviec,a ul nabipooulta r0 nVe.g Tathive eD, oArC bsi pino ltahre, eAitDhe5r3 s7y1m amre et- Figure 20. Data Registers Associated with Each DAC Channel factory trimmed with the offset DACs set at their default values. This results in optimum offset and gain performance for the Each DAC channel also has a gain (M) register and an offset (C) default output range and span. register that allow trimming out of the gain and offset errors of the entire signal chain. Data from the X1A register is operated When the output range is adjusted by changing the value of the on by a digital multiplier and adder controlled by the contents of offset DAC, an extra offset is introduced due to the gain error of the M and C registers. The calibrated DAC data is then stored in the offset DAC. The amount of offset is dependent on the magni- the X2A register. Similarly, data from the X1B register is operated tude of the reference and how much the offset DAC deviates from on by the multiplier and adder and stored in the X2B register. its default value. See the Specifications section for this offset. The worst-case offset occurs when the offset DAC is at positive or Although Figure 20 shows a multiplier and adder for each negative full scale. This value can be added to the offset present channel, there is only one multiplier and one adder in the device in the main DAC channel to give an indication of the overall shared among all channels. This has implications for the update offset for that channel. In most cases, the offset can be removed speed when several channels are updated simultaneously, as by programming the C register of the channel with an appropriate described in the Register Update Rates section. value. The extra offset caused by the offset DAC needs to be taken Each time data is written to the X1A register, or to the M or C into account only when the offset DAC is changed from its default register with the A/B control bit set to 0, the X2A data is recal- value. Figure 21 shows the allowable code range that can be loaded culated and the X2A register is automatically updated. Similarly, to the offset DAC, depending on the reference value used. Thus, X2B is updated each time data is written to X1B, or to M or C for a 5 V reference, the offset DAC should not be programmed with A/B set to 1. The X2A and X2B registers are not readable with a value greater than 8192 (0x2000). or directly writable by the user. 5 RESERVED Data output from the X2A and X2B registers is routed to the final DAC register by a multiplexer. Whether each individual 4 DAC takes its data from the X2A or X2B register is controlled by an 8-bit A/B select register associated with each group of 3 eight DACs. If a bit in this register is 0, the DAC takes its data )V from the X2A register; if 1, the DAC takes its data from the X2B EF( R register (Bit 0 through Bit 7 control DAC 0 to DAC 7). V 2 Note that because there are 40 bits in five registers, it is possible to set up, on a per-channel basis, whether each DAC takes its 1 dpraotav ifdreodm t hthaet sXe2tAs a ollr bXit2sB i nre tghiset eAr./ AB sgelloebcat lr ceogmistmeras ntod 0is o arl stoo 1. 0 05814-021 0 4096 8192 12288 16383 OFFSET DAC CODE Figure 21. Offset DAC Code Range Rev. B | Page 17 of 28

AD5371 OUTPUT AMPLIFIER The input code is the value in the X1A or X1B register that is applied to the DAC (X1A, X1B default code = 5461). The output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, which limits how DAC_CODE = INPUT_CODE × (M + 1)/214 + C − 213. much the output can be offset for a given reference voltage. For where: example, it is not possible to have a unipolar output range of M = code in gain register − default code = 214 − 1. 20 V, because the maximum supply voltage is ±16.5 V. C = code in offset register − default code = 213. DAC S1 The DAC output voltage is calculated as follows: CHANNEL VOUT R6 VOUT = 4 × VREFx × (DAC_CODE – 60Rk5Ω S2 10kΩ OFFSET_CODE)/214 + VSIGGND CLR CLR where: R1 20kΩ CLR S3 DAC_CODE should be within the range of 0 to 16,383. R4 R3 R2 SIGGNDx VREF = 3.0 V for a 12 V span and 5.0 V for a 20 V span. 60kΩ 20kΩ 20kΩ OFFSET_CODE is the code loaded to the offset DAC. On SIGGNDx power-up, the default code loaded to the offset DAC is 5461 OFDFASCET 05814-022 (R0Ex1F5E5R5)E. NWCitEh Sa E3 LVE rCefTerIOenNce , this gives a span of −4 V to +8 V. Figure 22. Output Amplifier and Offset DAC The AD5371 has three reference input pins. The voltage applied Figure 22 shows details of a DAC output amplifier and its to the reference pins determines the output voltage span on connections to its corresponding offset DAC. On power-up, VOUT0 to VOUT39. VREF0 determines the voltage span for S1 is open, disconnecting the amplifier from the output. S3 is VOUT0 to VOUT7 (Group 0), VREF1 determines the voltage closed, so the output is pulled to the corresponding SIGGNDx span for VOUT8 to VOUT15 (Group 1), and VREF2 deter- (R1 and R2 are greater than R6). S2 is also closed to prevent the mines the voltage span for VOUT16 to VOUT39 (Group 2 to output amplifier from being open-loop. If CLR is low at power-up, Group 4). The reference voltage applied to each VREF pin can the output remains in this condition until CLR is taken high. be different, if required, allowing each group to have a different The DAC registers can be programmed, and the outputs assume voltage span. The output voltage range and span can be adjusted the programmed values when CLR is taken high. Even if CLR is further by programming the offset and gain registers for each high at power-up, the output remains in this condition until channel and by programming the offset DACs. If the offset and V > 6 V and V < −4 V and the initialization sequence has DD SS gain features are not used (that is, the M and C registers are left finished. The outputs then go to their power-on default value. at their default values), the required reference levels can be TRANSFER FUNCTION calculated as follows: VREF = (VOUT − VOUT )/4 OUTPUT MAX MIN VOLTAGE FULL-SCALE If the offset and gain features of the AD5371 are used, the ERROR 8V + required output range is slightly different. The selected output ZERO-SCALE ERROR range should take into account the system offset and gain errors ACTUAL TRANSFER that need to be trimmed out. Therefore, the selected output FUNCTION range should be larger than the actual required range. IDEAL TRANSFER Calculate the required reference levels as follows: FUNCTION 1. Identify the nominal output range on VOUT. 0 DAC CODE 16383 2. Identify the maximum offset span and the maximum gain required on the full output signal range. 3. Calculate the new maximum output range on VOUT, ZERO-SCALE including the expected maximum offset and gain errors. –4V ERROR 4. Choose the new required VOUT and VOUT , keeping MAX MIN 05814-008 tVhDeD V aOndU VTS lSi mmuitsst cpernotveirdeed sounf ftihciee nnto mheiandarlo voamlu.e s. Note that Figure 23. DAC Transfer Function 5. Calculate the value of VREF as follows: The output voltage of a DAC in the AD5371 is dependent on the VREF = (VOUT − VOUT )/4 value in the input register, the value of the M and C registers, MAX MIN and the value in the offset DAC. Rev. B | Page 18 of 28

AD5371 Reference Selection Example Reducing Full-Scale Error If Full-scale error can be reduced as follows: Nominal output range = 12 V (−4 V to +8 V) 1. Measure the zero-scale error. 2. Set the output to the highest possible value. Zero-scale error = ±70 mV 3. Measure the actual output voltage and compare it to the Gain error = ±3%, and required value. Add this error to the zero-scale error. This SIGGNDx = AGND = 0 V is the span error, which includes the full-scale error. 4. Calculate the number of LSBs equivalent to the span error Then and subtract this number from the default value of the M Gain error = ±3% register. Note that only positive full-scale error can be => Maximum positive gain error = 3% reduced. => Output range including gain error = 12 + 0.03(12) = 12.36 V AD5371 Calibration Example Zero-scale error = ±70 mV => Maximum offset error span = 2(70 mV) = 0.14 V This example assumes that a −4 V to +8 V output is required. => Output range including gain error and zero-scale error = The DAC output is set to −4 V but measured at −4.03 V. This 12.36 V + 0.14 V = 12.5 V gives a zero-scale error of −30 mV. 1 LSB = 12 V/16,384 = 732.42 μV VREF calculation 30 mV = 41 LSBs Actual output range = 12.5 V, that is, −4.25 V to +8.25 V; VREF = (8.25 V + 4.25 V)/4 = 3.125 V The full-scale error can now be calculated. The output is set to 8 V and a value of 8.02 V is measured. This gives a full-scale If the solution yields an inconvenient reference level, the user error of +20 mV and a span error of +20 mV − (−30 mV) = can adopt one of the following approaches: +50 mV. • Use a resistor divider to divide down a convenient, higher 50 mV = 68 LSBs reference level to the required level. • Select a convenient reference level above VREF and modify The errors can now be removed as follows: the gain and offset registers to digitally downsize the reference. 1. Add 41 LSBs to the default C register value: In this way, the user can use almost any convenient reference 8192 + 41 = 8233 level but can reduce the performance by overcompaction of 2. Subtract 68 LSBs from the default M register value: the transfer function. 16,383 − 68 = 16,315 • Use a combination of these two approaches. 3. Program the M register to 16,315; program the C register to 8233. CALIBRATION ADDITIONAL CALIBRATION The user can perform a system calibration on the AD5371 to reduce gain and offset errors to below 1 LSB. This reduction is The techniques described in the previous section are usually achieved by calculating new values for the M and C registers and enough to reduce the zero-scale and full-scale errors in most reprogramming them. applications. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (C) The M and C registers should not be programmed until both register can only be used to reduce the offset caused by the the zero-scale and full-scale errors are calculated. negative zero-scale error. A positive offset cannot be reduced. Reducing Zero-Scale Error Likewise, if the maximum voltage is below the ideal value, that Zero-scale error can be reduced as follows: is, a negative full-scale error, the gain (M) register cannot be 1. Set the output to the lowest possible value. used to increase the gain to compensate for the error. 2. Measure the actual output voltage and compare it to the These limitations can be overcome by increasing the reference required value. This gives the zero-scale error. value. With a 3 V reference, a 12 V span is achieved. The ideal 3. Calculate the number of LSBs equivalent to the error and voltage range for the AD5371 is −4 V to +8 V. Using a +3.1 V add this number to the default value of the C register. Note reference increases the range to −4.133 V to +8.2667 V. Clearly, that only negative zero-scale error can be reduced. in this case, the offset and gain errors are insignificant, and the M and C registers can be used to raise the negative voltage to −4 V and then reduce the maximum voltage to +8 V to give the most accurate values possible. Rev. B | Page 19 of 28

AD5371 RESET FUNCTION In this case, the DAC outputs are updated immediately after BUSY goes high. Whenever the A/B select registers are written The reset function is initiated by the RESET pin. On the rising to, BUSY also goes low for approximately 500 ns. edge of RESET, the AD5371 state machine initiates a reset sequence to reset the X, M, and C registers to their default values. The AD5371 has flexible addressing that allows writing of data This sequence typically takes 300 μs, and the user should not to a single channel, all channels in a group, the same channel in write to the part during this time. On power-up, it is recom- Group 0 to Group 4, the same channel in Group 1 to Group 4, or mended that the user bring RESET high as soon as possible to all channels in the device. This means that 1, 4, 5, 8, or 40 DAC properly initialize the registers. register values may need to be calculated and updated. Because there is only one multiplier shared among 40 channels, this task When the reset sequence is complete (and provided that CLR is must be done sequentially so that the length of the BUSY pulse high), the DAC output is at a potential specified by the default varies according to the number of channels being updated. register settings, which is equivalent to SIGGNDx. The DAC outputs remain at SIGGNDx until the X, M, or C register is Table 9. BUSY Pulse Widths updated and LDAC is taken low. The AD5371 can be returned Action BUSY Pulse Width1 to the default state by pulsing RESET low for at least 30 ns. Note Loading X1A, X1B, C, or M to 1 channel2 1.5 μs maximum that, because the reset function is triggered by the rising edge, Loading X1A, X1B, C, or M to 5 channels 3.9 μs maximum bringing RESET low has no effect on the operation of the AD5371. Loading X1A, X1B, C, or M to 8 channels 5.7 μs maximum CLEAR FUNCTION Loading X1A, X1B, C, or M to 40 channels 24.9 μs maximum CLR is an active low input that should be high for normal oper- 1 BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns. ation. The CLR pin has an internal 500 kΩ pull-down resistor. 2 A single channel update is typically 1 μs. When CLR is low, the input to each of the DAC output buffer The AD5371 contains an extra feature whereby a DAC register stages, VOUT0 to VOUT39, is switched to the externally set is not updated unless its X2A or X2B register has been written potential on the relevant SIGGNDx pin. While CLR is low, all to since the last time LDAC was brought low. Normally, when LDAC pulses are ignored. When CLR is taken high again, the LDAC is brought low, the DAC registers are filled with the contents DAC outputs return to their previous values. The contents of of the X2A or X2B register, depending on the setting of the A/B the input registers and the DAC registers are not affected by select registers. However, the AD5371 updates the DAC register taking CLR low. To prevent glitches from appearing on the only if the X2A or X2B data has changed, thereby removing outputs, bring CLR low before writing to the offset DAC to unnecessary digital crosstalk. adjust the output span. POWER-DOWN MODE BUSY AND LDAC FUNCTIONS The AD5371 can be powered down by setting Bit 0 in the control register to 1. This turns off the DACs, thus reducing the The value of an X2 (A or B) register is calculated each time the current consumption. The DAC outputs are connected to their user writes new data to the corresponding X1, C, or M register. respective SIGGNDx potentials. The power-down mode does During the calculation of X2, the BUSY output goes low. While not change the contents of the registers, and the DACs return to BUSY is low, the user can continue writing new data to the X1, their previous voltage when the power-down bit is cleared to 0. M, or C register (see the Register Update Rates section for more THERMAL SHUTDOWN FUNCTION details), but no DAC output updates can take place. The BUSY pin is bidirectional and has a 50 kΩ internal pull-up The AD5371 can be programmed to shut down the DACs if the temperature on the die exceeds 130°C. Setting Bit 1 in the resistor. When multiple AD5371 devices are used in one system, control register to 1 enables this function (see Table 17). If the the BUSY pins can be tied together. This is useful when it is die temperature exceeds 130°C, the AD5371 enters a thermal required that no DAC in any device be updated until all other shutdown mode that is equivalent to setting the power-down bit DACs are ready to be updated. When each device has finished in the control register to 1. To indicate that the AD5371 has updating the X2 (A or B) register, it releases the BUSY pin. If entered thermal shutdown mode, Bit 4 of the control register is another device has not finished updating its X2 register, it holds set to 1. The AD5371 remains in thermal shutdown mode, even BUSY low, thus delaying the effect of LDAC going low. if the die temperature falls, until Bit 1 in the control register is The DAC outputs are updated by taking the LDAC input low. If cleared to 0. LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs are updated immediately after BUSY goes high. A user can also hold the LDAC input permanently low. Rev. B | Page 20 of 28

AD5371 TOGGLE MODE For the data generator example, the user needs only to set the The AD5371 has two X2 registers per channel, X2A and X2B, high and low levels for each channel once by writing to the X1A that can be used to switch the DAC output between two levels and X1B registers. The values of X2A and X2B are calculated and with ease. This approach greatly reduces the overhead required stored in their respective registers. The calculation delay, therefore, by a microprocessor, which would otherwise need to write to happens only during the setup phase, that is, when programming each channel individually. When the user writes to the X1A, the initial values. To toggle a DAC output between the two levels, X1B, M, or C register, the calculation engine takes a certain it is only required to write to the relevant A/B select register to amount of time to calculate the appropriate X2A or X2B value. set the MUX2 register bit. Furthermore, because there are eight If an application, such as a data generator, requires that the MUX2 control bits per register, it is possible to update eight DAC output switch between two levels only, any method that channels with a single write. Table 10 shows the bits that corre- reduces the amount of calculation time necessary is advantageous. spond to each DAC output. Table 10. DACs Selected by A/B Select Registers A/B Select Bits1 Register F7 F6 F5 F4 F3 F2 F1 F0 0 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0 1 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8 2 VOUT23 VOUT22 VOUT21 VOUT20 VOUT19 VOUT18 VOUT17 VOUT16 3 VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24 4 VOUT39 VOUT38 VOUT37 VOUT36 VOUT35 VOUT34 VOUT33 VOUT32 1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected. Rev. B | Page 21 of 28

AD5371 SERIAL INTERFACE The AD5371 contains two high speed serial interfaces: an SPI- SPI WRITE MODE compatible interface operating at clock frequencies up to 50 MHz The AD5371 allows writing of data via the serial interface to (20 MHz for read operations) and an LVDS interface. To minimize every register directly accessible to the serial interface, that is, both the power consumption of the device and the on-chip digital all registers except the X2A, X2B, and DAC registers. The X2A noise, the interface powers up fully only when the device is being and X2B registers are updated when the user writes to the X1A, written to, that is, on the falling edge of SYNC. X1B, M, or C register, and the DAC data registers are updated SPI INTERFACE by LDAC. The serial interface is 2.5 V LVTTL-compatible when operating The serial word (see Table 13) is 24 bits long: 14 of these bits are from a 2.5 V to 3.6 V DV supply. The SPI interface is selected data bits; six bits are address bits; two bits are mode bits that CC when the SPI/LVDS pin is held low. It is controlled by four pins, determine what is done with the data; and two bits are reserved. as described in Table 11. The serial interface works with both a continuous and a burst (gated) serial clock. Serial data applied to SDI is clocked into Table 11. Pins That Control the SPI Interface the AD5371 by clock pulses applied to SCLK. The first falling Pin Description edge of SYNC starts the write cycle. At least 24 falling clock edges SYNC Frame synchronization input must be applied to SCLK to clock in 24 bits of data before SYNC SDI Serial data input pin is taken high again. If SYNC is taken high before the 24th falling SCLK Clocks data in and out of the device clock edge, the write operation is aborted. SDO Serial data output pin for data readback If a continuous clock is used, SYNC must be taken high before When the SPI mode is used, the SYNC, SDI, and SCLK pins the 25th falling clock edge. This inhibits the clock within the should be connected to DGND either directly or by using pull- AD5371. If more than 24 falling clock edges are applied before down resistors. SYNC is taken high again, the input data becomes corrupted. If LVDS INTERFACE an externally gated clock of exactly 24 pulses is used, SYNC can The LVDS interface uses the same input pins, with the same be taken high any time after the 24th falling clock edge. designations, as the SPI interface; however, SDO is not used. In The input register addressed is updated on the rising edge of addition, three other pins are provided for the complementary SYNC. For another serial transfer to take place, SYNC must be signals needed for differential operation, as described in Table 12. taken low again. Table 12. Pins That Control the LVDS Interface Pin Description SYNC Differential frame synchronization signal SYNC Differential frame synchronization signal (complement) SDI Differential serial data input SDI Differential serial data input (complement) SCLK Differential serial clock input SCLK Differential serial clock input (complement) Table 13. Serial Word Bit Assignment I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I11 I01 M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 Bit I1 and Bit I0 are reserved for future use and should be set to 0 when writing the serial word. These bits read back as 0. Rev. B | Page 22 of 28

AD5371 SPI READBACK MODE REGISTER UPDATE RATES The AD5371 allows data readback via the serial interface from The value of the X2A register or the X2B register is calculated every register directly accessible to the serial interface, that is, each time the user writes new data to the corresponding X1, C, or all registers except the X2A, X2B, and DAC data registers. To M register. The calculation is performed by a three-stage process. read back a register, it is first necessary to tell the AD5371 The first two stages take approximately 600 ns each, and the which register is to be read. This is achieved by writing a word third stage takes approximately 300 ns. When the write to the whose first two bits are the Special Function Code 00 to the X1, C, or M register is complete, the calculation process begins. device. The remaining bits then determine which register is to If the write operation involves the update of a single DAC channel, be read back. the user is free to write to another register, provided that the write operation does not finish until the first-stage calculation is If a readback command is written to a special function register, complete, that is, 600 ns after the completion of the first write data from the selected register is clocked out of the SDO pin operation. If a group of channels is being updated by a single during the next SPI operation. The SDO pin is normally three- write operation, the first-stage calculation is repeated for each stated but becomes driven as soon as a read command is issued. channel, taking 600 ns per channel. In this case, the user should The pin remains driven until the register data is clocked out. not complete the next write operation until this time has elapsed. See Figure 5 for the read timing diagram. Note that due to the timing requirements of t (25 ns), the maximum speed of the CHANNEL ADDRESSING AND SPECIAL MODES 22 SPI interface during a read operation should not exceed 20 MHz. If the mode bits are not 00, the data-word D13 to D0 is written LVDS OPERATION to the device. Address Bit A5 to Address Bit A0 determine which channels are written to, and the mode bits determine to The LVDS interface operates as follows. Note that, because the which register (X1A, X1B, C, or M) the data is written, as shown in LVDS signals are differential, when a signal goes high, its Table 14 and Table 15. Data is to be written to the X1A register complementary signal goes low, and vice versa. when the A/B bit in the control register is 0, or to the X1B 1. The SYNC signal frames the data. SCLK is initially high. register when the A/B bit is 1. 2. After SYNC goes high and the SYNC-to-SCLK setup time has elapsed, SCLK can start to clock in the data. Table 14. Mode Bits 3. Data is clocked into the AD5371 on the high-to-low M1 M0 Action transition of SCLK and must be stable at this time (observe 1 1 Write to DAC input data (X) register setup and hold time specifications). 1 0 Write to DAC offset (C) register 4. SYNC can then be taken low after the SCLK-to-SYNC hold 0 1 Write to DAC gain (M) register time to latch the data. 0 0 Special function, used in combination with other bits of the data-word The same comments about burst and continuous clocks for the The AD5371 has very flexible addressing that allows the writing SPI interface apply to the LVDS interface. However, readback is not available when using the LVDS interface. of data to a single channel, all channels in a group, the same channel in Group 0 to Group 4, the same channel in Group 1 to Group 4, or all channels in the device (see Table 15). Rev. B | Page 23 of 28

AD5371 Table 15 shows which groups and which channels are addressed for every combination of Address Bit A5 to Address Bit A0. Table 15. Group and Channel Addressing Address Bit A2 Address Bit A5 to Address Bit A3 to Address Bit A0 000 001 010 011 100 101 110 111 000 All groups, Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, all channels Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 0 Channel 0 000 Group 0, Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, all channels Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 1 Channel 1 010 Group 1, Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, all channels Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 2 Channel 2 011 Group 2, Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, all channels Channel 3 Channel 3 Channel 3 Channel 3 Channel 3 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 3 Channel 3 100 Group 3, Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, all channels Channel 4 Channel 4 Channel 4 Channel 4 Channel 4 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 4 Channel 4 101 Group 4, Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, all channels Channel 5 Channel 5 Channel 5 Channel 5 Channel 5 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 5 Channel 5 110 Reserved Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, Channel 6 Channel 6 Channel 6 Channel 6 Channel 6 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 6 Channel 6 111 Reserved Group 0, Group 1, Group 2, Group 3, Group 4, Group 0, Group 1, Channel 7 Channel 7 Channel 7 Channel 7 Channel 7 Group 1, Group 2, Group 2, Group 3, Group 3, Group 4; Group 4; Channel 7 Channel 7 Rev. B | Page 24 of 28

AD5371 SPECIAL FUNCTION MODE If the mode bits are 00, the special function mode is selected, as shown in Table 16. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback. The codes for the special functions are shown in Table 17. Table 18 shows the addresses for data readback. Table 16. Special Function Mode I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 Table 17. Special Function Codes Special Function Code S5 S4 S3 S2 S1 S0 Data (F15 to F0) Action 0 0 0 0 0 0 0000 0000 0000 0000 No operation (NOP). 0 0 0 0 0 1 XXXX XXXX XXXX X[F2:F0] Write control register. F4 = overtemperature indicator (read-only bit). This bit should be 0 when writing to the control register. F3 = reserved. This bit should be 0 when writing to the control register. F2 = 1: Select Register X1B for input. F2 = 0: Select Register X1A for input. F1 = 1: Enable thermal shutdown mode. F1 = 0: Disable thermal shutdown mode. F0 = 1: Software power-down. F0 = 0: Software power-up. 0 0 0 0 1 0 XX[F13:F0] Write data in F13 to F0 to OFS0 register. 0 0 0 0 1 1 XX[F13:F0] Write data in F13 to F0 to OFS1 register. 0 0 0 1 0 0 XX[F13:F0] Write data in F13 to F0 to OFS2 register. 0 0 0 1 0 1 See Table 18 Select register for readback. 0 0 0 1 1 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 0. 0 0 0 1 1 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 1. 0 0 1 0 0 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 2. 0 0 1 0 0 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 3. 0 0 1 0 1 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 4. 0 0 1 0 1 1 XXXX XXXX [F7:F0] Block write to A/B select registers. F7 to F0 = 0: Write all 0s (all channels use the X2A register). F7 to F0 = 1: Write all 1s (all channels use the X2B register). 0 1 1 1 0 0 Reserved Rev. B | Page 25 of 28

AD5371 Table 18. Address Codes for Data Readback1 F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read 0 0 0 X1A register 0 0 1 Bit F12 to Bit F7 select the channel to be read back, X1B register 0 1 0 from Channel 0 = 001000 to Channel 39 = 101111 C register 0 1 1 M register 1 0 0 0 0 0 0 0 1 Control register 1 0 0 0 0 0 0 1 0 OFS0 data register 1 0 0 0 0 0 0 1 1 OFS1 data register 1 0 0 0 0 0 1 0 0 OFS2 data register 1 0 0 0 0 0 1 1 0 A/B Select Register 0 1 0 0 0 0 0 1 1 1 A/B Select Register 1 1 0 0 0 0 1 0 0 0 A/B Select Register 2 1 0 0 0 0 1 0 0 1 A/B Select Register 3 1 0 0 0 0 1 0 1 0 A/B Select Register 4 1 Bit F6 to Bit F0 are don’t cares for the data readback function. Rev. B | Page 26 of 28

AD5371 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING negative supplies are connected. This is required to prevent currents from flowing in directions other than toward an analog In any circuit where accuracy is important, careful consideration or digital ground. of the power supply and ground return layout helps to ensure INTERFACING EXAMPLES the rated performance. Design the PCB on which the AD5371 is mounted so that the analog and digital sections are separated The SPI interface of the AD5371 is designed to allow the and confined to certain areas of the board. If the AD5371 is in a part to be easily connected to industry-standard DSPs and system where multiple devices require an AGND-to-DGND microcontrollers. Figure 24 shows how the AD5371 connects to connection, make the connection at one point only. Establish the the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an star ground point as close as possible to the device. For supplies integrated SPI port that can be connected directly to the SPI with multiple pins (VSS, VDD, DVCC), it is recommended that pins of the AD5371, as well as programmable input/output pins these pins be tied together and that each supply be decoupled that can be used to set or read the state of the digital input or only once. output pins associated with the interface. The AD5371 should have ample supply decoupling of 10 μF in AD5371 parallel with 0.1 μF on each supply, located as close to the package SPISELx SYNC as possible, ideally right up against the device. The 10 μF capacitors SCK SCLK are the tantalum bead type. The 0.1 μF capacitor should have low MOSI SDI effective series resistance (ESR) and low effective series inductance MISO SDO (ESI)—typical of the common ceramic types that provide a low PF10 RESET impedance path to ground at high frequencies—to handle transient ADSP-BF531 PF9 LDAC currents due to internal logic switching. PF8 CLR Acovuopidle d nigoiitsael olinnteos trhuen dneivnigc eu.n Adlelor wth teh dee avnicaelo bge gcraouusen dth pelya ncaen, PF7 BUSY 05814-023 however, to run under the AD5371 to avoid noise coupling. The Figure 24. Interfacing to a Blackfin DSP power supply lines of the AD5371 should use as large a trace as The Analog Devices ADSP-21065L is a floating-point DSP with possible to provide low impedance paths and reduce the effects of two serial ports (SPORTs). Figure 25 shows how one SPORT glitches on the power supply line. Shield fast switching digital can be used to control the AD5371. In this example, the transmit signals with digital ground to avoid radiating noise to other frame synchronization (TFSx) pin is connected to the receive parts of the board, and never run them near the reference frame synchronization (RFSx) pin. Similarly, the transmit and inputs. It is essential to minimize noise on all VREF lines. receive clocks (TCLKx and RCLKx) are also connected. The user Avoid crossover of digital and analog signals. Run traces on can write to the AD5371 by writing to the transmit register of opposite sides of the board at right angles to each other. This the ADSP-21065L. A read operation can be accomplished by reduces the effects of feedthrough through the board. A microstrip first writing to the AD5371 to tell the part that a read operation technique is by far the best approach, but it is not always possible is required. A second write operation with an NOP instruction with a double-sided board. In this technique, the component side causes the data to be read from the AD5371. The DSP receive of the board is dedicated to ground plane, while signal traces interrupt can be used to indicate when the read operation is are placed on the solder side. complete. As is the case for all thin packages, care must be taken to avoid ADSP-21065L AD5371 flexing the package and to avoid a point load on the surface of TFSx this package during the assembly process. RFSx SYNC TCLKx POWER SUPPLY SEQUENCING RCLKx SCLK DTxA SDI When the supplies are connected to the AD5371, it is important DRxA SDO that the AGND and DGND pins be connected to the relevant ground plane before the positive or negative supplies are applied. FLAG0 RESET In most applications, this is not an issue because the ground pins FLAG1 LDAC fAoDr t5h3e7 1p ovwiae gr rsouupnpdli epsl aanree sc. oWnnheecnt etdh et oA tDhe5 3g7r1o uisn tdo p bien su osef dth ine a FFLLAAGG23 CBLURSY 05814-024 hot-swap card, care should be taken to ensure that the ground Figure 25. Interfacing to an ADSP-21065L DSP pins are connected to the supply grounds before the positive or Rev. B | Page 27 of 28

AD5371 OUTLINE DIMENSIONS 14.20 14.00 SQ 0.75 13.80 0.60 1.60 MAX 0.45 80 61 1 60 PIN 1 12.20 12.00 SQ TOP VIEW 11.80 1.45 (PINS DOWN) 0.20 1.40 0.09 1.35 7° 3.5° 20 41 0.15 0° 0.05 SEATING 0.08 21 40 PLANE COPLANARITY VIEW A 0.50 0.27 BSC 0.22 VIEW A LEAD PITCH 0.17 ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BDD 051706-A Figure 26. 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-1 Dimensions shown in millimeters A1 CORNER 10.00 INDEX AREA BSC SQ 1211109 87 6 5 4 3 2 1 A B 2.50 SQ BALL A1 CD PAD CORNER 8.80 E BSC SQ BOTTOM F TOP VIEW VIEW G H J K L M 0.80 BSC 1.40 DETAIL A 1.35 1.20 DETAIL A 1.11 0.65 REF 1.01 0.91 0.34 NOM 0.29 MIN *0.50 0.12 MAX SEATING COPLANARITY 0.45 PLANE 0.40 BALL DIAMETER * CWOITMHP LTIHAEN TE XTCOE JPETDIOENC TSOTA BNADLALR DDISA MMEOT-E20R5.AC 012006-0 Figure 27. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-100-2) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD5371BSTZ1 −40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-1 AD5371BSTZ-REEL1 −40°C to +85°C 80-Lead Low Profile Quad Flat Package [LQFP] ST-80-1 AD5371BBCZ1 −40°C to +85°C 100-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-100-2 AD5371BBCZ-REEL1 −40°C to +85°C 100-Ball Chip Scale Package Ball Grid Array (CSP_BGA) BC-100-2 EVAL-AD5371EBZ1 Evaluation Board 1 Z = RoHS Compliant Part. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05814-0-3/08(B) Rev. B | Page 28 of 28