8-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5362/AD5363 FEATURES 8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages 2.5 V to 5.5 V digital interface Guaranteed monotonic to 16/14 bits Digital reset (RESET) Nominal output voltage range of −10 V to +10 V Clear function to user-defined SIGGNDx Multiple output voltage spans available Simultaneous update of DAC outputs Thermal shutdown function APPLICATIONS Channel monitoring multiplexer GPIO function Instrumentation System calibration function allowing user-programmable Industrial control systems offset and gain Level setting in automatic test equipment (ATE) Channel grouping and addressing features Variable optical attenuators (VOA) Data error checking feature Optical line cards SPI-compatible serial interface FUNCTIONAL BLOCK DIAGRAM DVCC VDD VSS AGND DGND LDAC TEMP_OUT SETNEMSOPR n = 16 FOR AD5362 VREF0 PEC RCEOGNITSRTOERL 8 n = 14 FOR AD5363 14 OFS0 14 OFFSET BUFFER GROUP 0 MON_IN0 VOUT0 TO 8 A/B SELECT 8 TO REGISTER DAC 0 VOUT7 REGISTER MUX 2s BUFFER MON_IN1 MUX 6 n X1 REGISTERn n AM/UBX XX22AB RREEGGIISSTTEERR M2UXn REDGAISCT 0ER n DAC 0 ODOUATWNPDNU PTCO OBWNUTEFRRFEO-RL VOUT0 n n MON_OUT n M REGISTER n · · · · VOUT1 GPIO REGGPISIOTER 2 C REGI··STER ·· ·· ·· ·· ·· ·· ·· VOUT2 · · · · BIN/2SCOMP SYNC nn X1 REGISTERnn n AM/UBX XX22AB RREEGGIISSTTEERR M2UXn REDGAISCT 3ER n DAC 3 ODOUATWNPDNU PTCO OBWNUTEFRRFEO-RL VSIOGUGTN3D0 SDI M REGISTER SERIAL SCLK INTERFACE n C REGISTER n VREF1 SDO GROUP 1 BUSY 8 A/B SELECT 8 TO 14 REOGFISST1ER n ODFAFCSE 1T BUFFER RESET REGISTER MUX 2s BUFFER CLR n X1 REGISTERn n AM/UBX X2A REGISTER M2UXn REDGAISCT 4ER n DAC 4 ODOUATWNPDNU PTCO OBWNUTEFRRFEO-RL VOUT4 X2B REGISTER n n STATE M REGISTER · · · · VOUT5 MACHINE n C REGISTER n · · · · · · · · n · · · · · · · · VOUT6 · · · · · AD5362/ nn X1 REGISTERnn n AM/UBX XX22AB RREEGGIISSTTEERR M2UX n REDGAISCT 7ER n DAC 7 ODOUATWNPDNU PTCO OBWNUTEFRRFEO-RL VSIOGUGTN7D1 AD5363 M REGISTER n C REGISTER n 05762-001 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.

AD5362/AD5363 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 20 Applications ....................................................................................... 1 Clear Function ............................................................................ 20 Functional Block Diagram .............................................................. 1 BUSY and LDAC Functions...................................................... 20 Revision History ............................................................................... 2 BIN/2SCOMP Pin ...................................................................... 20 General Description ......................................................................... 3 Temperature Sensor ................................................................... 20 Specifications ..................................................................................... 4 Monitor Function ....................................................................... 21 AC Characteristics ........................................................................ 6 GPIO Pin ..................................................................................... 21 Timing Characteristics ................................................................ 7 Power-Down Mode .................................................................... 21 Absolute Maximum Ratings .......................................................... 10 Thermal Shutdown Function ................................................... 21 ESD Caution ................................................................................ 10 Toggle Mode ................................................................................ 21 Pin Configuration and Function Descriptions ........................... 11 Serial Interface ................................................................................ 22 Typical Performance Characteristics ........................................... 13 SPI Write Mode .......................................................................... 22 Terminology .................................................................................... 15 SPI Readback Mode ................................................................... 22 Theory of Operation ...................................................................... 16 Register Update Rates ................................................................ 22 DAC Architecture ....................................................................... 16 Packet Error Checking ............................................................... 23 Channel Groups .......................................................................... 16 Channel Addressing and Special Modes ................................. 23 A/B Registers and Gain/Offset Adjustment ............................ 17 Special Function Mode .............................................................. 24 Offset DACs ................................................................................ 17 Applications Information .............................................................. 26 Output Amplifier ........................................................................ 18 Power Supply Decoupling ......................................................... 26 Transfer Function ....................................................................... 18 Power Supply Sequencing ......................................................... 26 Reference Selection .................................................................... 18 Interfacing Examples ................................................................. 26 Calibration ................................................................................... 19 Outline Dimensions ....................................................................... 27 Additional Calibration ............................................................... 19 Ordering Guide .......................................................................... 28 REVISION HISTORY 3/08—Rev. 0 to Rev. A Added 56-Lead LFCSP_VQ .............................................. Universal Changes to Calibration Section .................................................... 19 Changes to Table 2 ............................................................................ 4 Changes to Reset Function Section and BUSY and LDAC Added t23 Parameter ......................................................................... 7 Functions Section ........................................................................... 20 Changes to Figure 4 .......................................................................... 8 Changes to Channel Addressing and Special Modes Section .. 23 Changes to Table 6 .......................................................................... 11 Updated Outline Dimensions ....................................................... 27 Changes to A/B Registers and Gain/Offset Adjustment Changes to Ordering Guide .......................................................... 28 Section .............................................................................................. 17 1/08—Revision 0: Initial Version Rev. A | Page 2 of 28

AD5362/AD5363 GENERAL DESCRIPTION The AD5362/AD5363 contain eight 16-/14-bit DACs in a single The AD5362/AD5363 have a high speed 4-wire serial interface 52-lead LQFP package or 56-lead LFCSP package. The devices that is compatible with SPI, QSPI™, MICROWIRE™, and DSP provide buffered voltage outputs with a span of 4× the reference interface standards and can handle clock speeds of up to voltage. The gain and offset of each DAC can be independently 50 MHz. All the outputs can be updated simultaneously by trimmed to remove errors. For even greater flexibility, the device taking the LDAC input low. Each channel has a programmable is divided into two groups of four DACs, and the output range gain and an offset adjust register. of each group can be independently adjusted by an offset DAC. Each DAC output is gained and buffered on chip with respect The AD5362/AD5363 offer guaranteed operation over a wide to an external SIGGNDx input. The DAC outputs can also be supply range with VSS from −16.5 V to −4.5 V and VDD from 8 V switched to SIGGNDx via the CLR pin. to 16.5 V. The output amplifier headroom requirement is 1.4 V, operating with a load current of 1 mA. Table 1. High Channel Count Bipolar DACs Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB) AD5360 16 4 × V (20 V) 16 ±4 REF AD5361 14 4 × V (20 V) 16 ±1 REF AD5362 16 4 × V (20 V) 8 ±4 REF AD5363 14 4 × V (20 V) 8 ±1 REF AD5370 16 4 × V (12 V) 40 ±4 REF AD5371 14 4 × V (12 V) 40 ±1 REF AD5372 16 4 × V (12 V) 32 ±4 REF AD5373 14 4 × V (12 V) 32 ±1 REF AD5378 14 ±8.75 V 32 ±3 AD5379 14 ±8.75 V 40 ±3 Rev. A | Page 3 of 28

AD5362/AD5363 SPECIFICATIONS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −4.5 V; V = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; CC DD SS REF R = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. L MIN MAX Table 2. Parameter B Version1 Unit Test Conditions/Comments ACCURACY Resolution 16 Bits AD5362 14 Bits AD5363 Integral Nonlinearity (INL) ±4 LSB max AD5362 ±1 LSB max AD5363 Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic by design over temperature Zero-Scale Error ±15 mV max Before calibration Full-Scale Error ±20 mV max Before calibration Gain Error 0.1 % FSR Before calibration Zero-Scale Error2 1 LSB typ After calibration Full-Scale Error2 1 LSB typ After calibration Span Error of Offset DAC ±75 mV max See the Offset DACs section for details VOUTx3 Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift DC Crosstalk2 180 μV max Typically 20 μV; measured channel at midscale, full-scale change on any other channel REFERENCE INPUTS (VREF0, VREF1)2 VREFx Input Current ±10 μA max Per input; typically ±30 nA VREFx Range2 2/5 V min/V max ±2% for specified operation SIGGND0 AND SIGGND1 INPUTS2 DC Input Impedance 50 kΩ min Typically 55 kΩ Input Range ±0.5 V min/V max SIGGNDx Gain 0.995/1.005 min/max OUTPUT CHARACTERISTICS2 Output Voltage Range V + 1.4 V min I = 1 mA SS LOAD V − 1.4 V max I = 1 mA DD LOAD Nominal Output Voltage Range −10 to +10 V Short-Circuit Current 15 mA max VOUTx3 to DV , V , or V CC DD SS Load Current ±1 mA max Capacitive Load 2200 pF max DC Output Impedance 0.5 Ω max MONITOR PIN (MON_OUT)2 Output Impedance DAC Output at Positive Full Scale 1000 Ω typ DAC Output at Negative Full Scale 500 Ω typ Three-State Leakage Current 100 nA typ Continuous Current Limit 2 mA max DIGITAL INPUTS Input High Voltage 1.7 V min DV = 2.5 V to 3.6 V CC 2.0 V min DV = 3.6 V to 5.5 V CC Input Low Voltage 0.8 V max DV = 2.5 V to 5.5 V CC Input Current ±1 μA max RESET, SYNC, SDI, and SCLK pins ±20 μA max CLR, BIN/2SCOMP, and GPIO pins Input Capacitance2 10 pF max Rev. A | Page 4 of 28

AD5362/AD5363 Parameter B Version1 Unit Test Conditions/Comments DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC) Output Low Voltage 0.5 V max Sinking 200 μA Output High Voltage (SDO) DV − 0.5 V min Sourcing 200 μA CC High Impedance Leakage Current ±5 μA max SDO only High Impedance Output Capacitance2 10 pF typ TEMPERATURE SENSOR (TEMP_OUT)2 Accuracy ±1 °C typ @ 25°C ±5 °C typ −40°C < T < +85°C Output Voltage at 25°C 1.46 V typ Output Voltage Scale Factor 4.4 mV/°C typ Output Load Current 200 μA max Current source only Power-On Time 10 ms typ To within ±5°C POWER REQUIREMENTS DV 2.5/5.5 V min/V max CC V 8/16.5 V min/V max DD V −16.5/−4.5 V min/V max SS Power Supply Sensitivity2 ∆Full Scale/∆V −75 dB typ DD ∆Full Scale/∆V −75 dB typ SS ∆Full Scale/∆DV −90 dB typ CC DI 2 mA max DV = 5.5 V, V = DV , V = GND CC CC IH CC IL I 8.5 mA max Outputs = 0 V and unloaded DD I 8.5 mA max Outputs = 0 V and unloaded SS Power-Down Mode Bit 0 in the control register is 1 DI 5 μA typ CC I 35 μA typ DD I −35 μA typ SS Power Dissipation Power Dissipation Unloaded (P) 209 mW max V = −12 V, V = 12 V, DV = 2.5 V SS DD CC Junction Temperature4 130 °C max T = T + P × θ J A TOTAL JA 1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C. 2 Guaranteed by design and characterization; not production tested. 3 VOUTx refers to any of VOUT0 to VOUT7. 4 θJA represents the package thermal impedance. Rev. A | Page 5 of 28

AD5362/AD5363 AC CHARACTERISTICS DV = 2.5 V; V = 15 V; V = −15 V; V = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; C = 200 pF; R = 10 kΩ; gain (M), CC DD SS REF L L offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. MIN MAX Table 3. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Output Voltage Settling Time 20 μs typ Full-scale change 30 μs max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs typ Digital-to-Analog Glitch Energy 5 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz DAC-to-DAC Crosstalk 10 nV-s typ Digital Crosstalk 0.2 nV-s typ Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V 1 Guaranteed by design and characterization; not production tested. Rev. A | Page 6 of 28

AD5362/AD5363 TIMING CHARACTERISTICS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −8 V; V = 5 V; AGND = DGND = SIGGND = 0 V; C = 200 pF to GND; CC DD SS REF L R = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. L MIN MAX Table 4. SPI Interface Parameter1, 2, 3 Limit at T , T Unit Description MIN MAX t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 11 ns min SYNC falling edge to SCLK falling edge setup time 4 t5 20 ns min Minimum SYNC high time t 10 ns min 24th SCLK falling edge to SYNC rising edge 6 t 5 ns min Data setup time 7 t 5 ns min Data hold time 8 t 4 42 ns max SYNC rising edge to BUSY falling edge 9 t 1/1.5 μs typ/μs max BUSY pulse width low (single-channel update); see Table 9 10 t 600 ns max Single-channel update cycle time 11 t 20 ns min SYNC rising edge to LDAC falling edge 12 t 10 ns min LDAC pulse width low 13 t 3 μs max BUSY rising edge to DAC output response time 14 t 0 ns min BUSY rising edge to LDAC falling edge 15 t 3 μs max LDAC falling edge to DAC output response time 16 t 20/30 μs typ/μs max DAC output settling time 17 t 140 ns max CLR/RESET pulse activation time 18 t 30 ns min RESET pulse width low 19 t 400 μs max RESET time indicated by BUSY low 20 t 270 ns min Minimum SYNC high time in readback mode 21 t 5 25 ns max SCLK rising edge to SDO valid 22 t 80 ns max RESET rising edge to BUSY falling edge 23 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 4 and Figure 5. 4 t9 is measured with the load circuit shown in Figure 2. 5 t22 is measured with the load circuit shown in Figure 3. 200µA IOL DVCC TO OUTPUT VOH (MIN) – VOL (MAX) R2.L2kΩ PIN CL 2 TO 50pF OUTPUT VOL PIN C50LpF 05762-002 200µA IOH 05762-003 Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram Rev. A | Page 7 of 28

AD5362/AD5363 t 1 SCLK 1 2 24 1 24 t3 t2 t11 t4 t6 SYNC t5 t 7 t 8 SDI DB23 DB0 t 9 t BUSY 10 t12 t13 LDAC1 t 17 t VOUTx1 14 t 15 t 13 LDAC2 t 17 VOUTx2 t16 CLR t 18 VOUTx t 19 RESET VOUTx t 18 t 20 BUSY t 23 21LLDDAACC AACCTTIIVVEE DAUFTREINRG B BUUSSYY.. 05762-004 Figure 4. SPI Write Timing Rev. A | Page 8 of 28

AD5362/AD5363 t 22 SCLK 48 t 21 SYNC SDI DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB0 DB23 DB15 DB0 LSB FROM PREVIOUS WRITE SELECTED REGISTER DATA CLOCKED OUT 05762-005 Figure 5. SPI Read Timing OUTPUT VOLTAGE FULL-SCALE ERROR VMAX + ZERO-SCALE ERROR ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION 0 DAC CODE 2N – 1 n = 16 FOR AD5362 n = 14 FOR AD5363 ZERO-SCALE VMIN ERROR 05762-006 Figure 6. DAC Transfer Function Rev. A | Page 9 of 28

AD5362/AD5363 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings T = 25°C, unless otherwise noted. Transient currents of up to A may cause permanent damage to the device. This is a stress 60 mA do not cause SCR latch-up. rating only; functional operation of the device at these or any Table 5. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +17 V maximum rating conditions for extended periods may affect DD V to AGND −17 V to +0.3 V device reliability. SS DVCC to DGND −0.3 V to +7 V Digital Inputs to DGND −0.3 V to DV + 0.3 V CC ESD CAUTION Digital Outputs to DGND −0.3 V to DV + 0.3 V CC VREF0, VREF1 to AGND −0.3 V to +5.5 V VOUT0 through VOUT7 to AGND V − 0.3 V to V + 0.3 V SS DD SIGGND0, SIGGND1 to AGND −1 V to +1 V AGND to DGND −0.3 V to +0.3 V MON_IN0, MON_IN1, MON_OUT VSS − 0.3 V to VDD + 0.3 V to AGND Operating Temperature Range (T ) A Industrial (J Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Operating Junction Temperature 130°C (T max) J θ Thermal Impedance JA 52-Lead LQFP 38°C/W 56-Lead LFCSP 25°C/W Reflow Soldering Peak Temperature 230°C Time at Peak Temperature 10 sec to 40 sec Rev. A | Page 10 of 28

AD5362/AD5363 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GNDGNDVCCDOECDICLKYNCVCCGNDCCC LRDACGNDGNDVCCDOECIDCLKYNCVCCGNDCC ADDSPSSSDDNNN CLADDSPSSSDDNN 52 51 50 49 48 47 46 45 44 43 42 41 40 5655545352515049847464544443 LDAC 1 39 NC CLR 2 PIN 1 38 SIGGND0 RESET 1 42 NC RESET 3 INDICATOR 37 VOUT3 BIN/2SCOMP 2 41 NC BUSY 3 PIN 1 40 SIGGND0 BIN/2SCOMP 4 36 VOUT2 GPIO 4 INDICATOR 39 VOUT3 BUSY 5 35 VOUT1 MON_OUT 5 38 VOUT2 GPIO 6 AADD55336623/ 34 VOUT0 MON_INNC0 67 AADD55336623/ 3376 VVOOUUTT10 MON_OUT 7 33 TEMP_OUT NC 8 35 TEMP_OUT MON_IN0 8 TOP VIEW 32 MON_IN1 NC 9 TOP VIEW 34 MON_IN1 (Not to Scale) NC 10 (Not to Scale) 33 VREF0 NC 9 31 VREF0 NC 11 32 NC NC 10 30 NC VDD 12 31 NC VDD 11 29 VSS VREVFSS1 1134 3209 VVSDSD VSS 12 28 VDD VREF1 13 27 NC NC = NO CONNECT 56789012345678 14 15 16 17 18 19 20 21 22 23 24 25 26 11111222222222 NC = NO CONNECT NC VOUT4VOUT5VOUT6VOUT7SIGGND1NCNCNCNCNCNCNC 05762-007 NCNCVOUT4VOUT5VOUT6VOUT7IGSGND1NCNCNCNCNCNCNC 05762-025 Figure 7. 52-Lead LQFP Pin Configuration Figure 8. 56-Lead LFCSP Pin Configuration Table 6. Pin Function Descriptions Pin No. LQFP LFCSP Mnemonic Description 1 55 LDAC Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information. 2 56 CLR Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for more information. 3 1 RESET Digital Reset Input. 4 2 BIN/2SCOMP Data Format Digital Input. Connecting this pin to DGND selects offset binary. Setting this pin to 1 selects twos complement. This input has a weak pull-down. 5 3 BUSY Digital Input/Open-Drain Output. BUSY is open drain when it is an output. See the BUSY and LDAC Functions section for more information. 6 4 GPIO Digital I/O Pin. This pin can be configured as an input or output that can be read back or programmed high or low via the serial interface. When configured as an input, this pin has a weak pull-down. 7 5 MON_OUT Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the MON_IN1 input can be routed to this output for monitoring. 8, 32 6, 34 MON_IN0, Analog Multiplexer Inputs. Can be routed to MON_OUT. MON_IN1 9, 10, 14, 20 to 7 to 11, 15, 16, NC No Connect. 27, 30, 39 to 42 22 to 28, 31, 32, 41 to 44 11, 28 12, 29 V Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These DD pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 12, 29 13, 30 V Negative Analog Power Supply; −16.5 V to −8 V for specified performance. SS These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 13 14 VREF1 Reference Input for DAC 4 to DAC 7. This reference voltage is referred to AGND. 34 to 37, 15 to 18 36 to 39, 17 to 20 VOUT0 to VOUT7 DAC Outputs. Buffered analog outputs for each of the eight DAC channels. Each analog output is capable of driving an output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 0.5 Ω. 19 21 SIGGND1 Reference Ground for DAC 4 to DAC 7. VOUT4 to VOUT7 are referenced to this voltage. 31 33 VREF0 Reference Input for DAC 0 to DAC 3. This reference voltage is referred to AGND. Rev. A | Page 11 of 28

AD5362/AD5363 Pin No. LQFP LFCSP Mnemonic Description 33 35 TEMP_OUT Provides an output voltage proportional to the chip temperature, typically 1.46 V at 25°C with an output variation of 4.4 mV/°C. 38 40 SIGGND0 Reference Ground for DAC 0 to DAC 3. VOUT0 to VOUT3 are referenced to this voltage. 43, 51 45, 53 DGND Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane. 44, 50 46, 52 DV Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF CC ceramic capacitors and 10 μF capacitors. 45 47 SYNC Active Low or SYNC Input for SPI Interface. This is the frame synchronization signal for the SPI serial interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 46 48 SCLK Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 47 49 SDI Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 48 50 PEC Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up that goes low if the packet error check fails. 49 51 SDO Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 52 54 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane. Exposed Paddle EP Exposed Paddle. Connect to V . SS Rev. A | Page 12 of 28

AD5362/AD5363 TYPICAL PERFORMANCE CHARACTERISTICS 2 0.0050 TA = 25°C VSS = –15V VDD = +15V VREF = +4.096V 1 0.0025 V) B) E ( S D INL (L 0 MPLITU 0 A –1 –0.0025 –2 –0.0050 0 16384 DA3C27C6O8DE 49152 65535 05762-008 0 1 2TIME(µs)3 4 5 05762-011 Figure 9. Typical AD5362 INL Plot Figure 12. Digital Crosstalk 1.0 1.0 VDD = +15V VSS = –15V DVCC = +5V VREF = +3V 0.5 0.5 B) LS B) ERROR ( 0 DNL (LS 0 L N I –0.5 –0.5 –1.0 –1.00 20 TEMPER40ATURE (°C) 60 80 05762-009 0 16384 DA3C2 7C6O8DE 49152 65535 05762-012 Figure 10. Typical INL Error vs. Temperature Figure 13. Typical AD5362 DNL Plot 0 TA = 25°C 600 VSS = –15V VDD = +15V VREF = +4.096V 500 Hz) PLITUDE (V)–0.01 NOISE (nV/√ 340000 M T A U TP 200 U O 100 –0.020 2 4TIME(µs) 6 8 10 05762-010 00 1 FR2EQUENCY (H3z) 4 5 05762-013 Figure 11. Analog Crosstalk Due to LDAC Figure 14. Output Noise Spectral Density Rev. A | Page 13 of 28

AD5362/AD5363 0.50 VVDSDS == +–1122VV 14 TDAV C=C 2 =5° 5CV VREF = +3V 12 0.45 S10 T DVCC = +5.5V NI DI (mA)CC00..4305 DVCC = +3.6V MBER OF U 86 DVCC = +2.5V NU 4 0.30 2 0.25–40 –20 0TEMPER2A0TURE (°4C0) 60 80 05762-014 0 0.30 0.35 DIC0C. 4(0mA) 0.45 0.50 05762-017 Figure 15. DICC vs. Temperature Figure 18. Typical DICC Distribution 6.5 2.0 IDD 1.9 1.8 6.0 1.7 mA) E (V) 1.6 (S 5.5 AG 1.5 I/IDDS ISS VOLT 1.4 1.3 5.0 1.2 VVDSSD == –+1122VV 1.1 VREF = +3V 4.5–40 –20 0TEMPER2A0TURE (°4C0) 60 80 05762-015 1.0–40 –25 –10 TE5MPER2A0TURE3 5(°C) 50 65 80 05762-018 Figure 16. IDD/ISS vs. Temperature Figure 19. TEMP_OUT Voltage vs. Temperature 14 VSS = –15V 1.0 VDD = +15V FULL-SCALE 12 TA = 25°C 0.5 MIDSCALE S10 V) OF UNIT 8 N_OUT ( ZERO-SCALE BER 6 – MO 0 M x U T N U 4 VO –0.5 2 0 5.8 6.0 IDD6 (.m2A) 6.4 6.6 05762-016 –1.0–1.0 –0.5MON_OUT CU0RRENT (mA)0.5 –1.0 05762-019 Figure 17. Typical IDD Distribution Figure 20. VOUTx MON_OUT Error vs. MON_OUT Current Rev. A | Page 14 of 28

AD5362/AD5363 TERMINOLOGY Output Voltage Settling Time Integral Nonlinearity (INL) Output voltage settling time is the amount of time it takes for Integral nonlinearity, or endpoint linearity, is a measure of the output of a DAC to settle to a specified level for a full-scale the maximum deviation from a straight line passing through input change. the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is Digital-to-Analog Glitch Energy expressed in least significant bits (LSB). Digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. It is Differential Nonlinearity (DNL) specified as the area of the glitch in nV-s. It is measured by Differential nonlinearity is the difference between the measured toggling the DAC register data between 0x7FFF and 0x8000 change and the ideal 1 LSB change between any two adjacent (AD5362) or 0x1FFF and 0x2000 (AD5363). codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Channel-to-Channel Isolation Channel-to-channel isolation refers to the proportion of input Zero-Scale Error signal from one DAC reference input that appears at the output Zero-scale error is the error in the DAC output voltage when of another DAC operating from another reference. It is all 0s are loaded into the DAC register. Zero-scale error is a expressed in decibels and measured at midscale. measure of the difference between VOUT (actual) and VOUT (ideal), expressed in millivolts, when the channel is at its mini- DAC-to-DAC Crosstalk mum value. Zero-scale error is mainly due to offsets in the DAC-to-DAC crosstalk is the glitch impulse that appears at output amplifier. the output of one converter due to both the digital change and subsequent analog output change at another converter. Full-Scale Error It is specified in nV-s. Full-scale error is the error in the DAC output voltage when all 1s are loaded into the DAC register. Full-scale error is a Digital Crosstalk measure of the difference between VOUT (actual) and VOUT Digital crosstalk is defined as the glitch impulse transferred to (ideal), expressed in millivolts, when the channel is at its maxi- the output of one converter due to a change in the DAC register mum value. Full-scale error does not include zero-scale error. code of another converter. It is specified in nV-s. Gain Error Digital Feedthrough Gain error is the difference between full-scale error and When the device is not selected, high frequency logic activity zero-scale error. It is expressed as a percentage of the full- on the digital inputs of the device can be capacitively coupled scale range (FSR). both across and through the device to appear as noise on the VOUT pins. It can also be coupled along the supply and ground Gain Error = Full-Scale Error − Zero-Scale Error lines. This noise is digital feedthrough. VOUT Temperature Coefficient Output Noise Spectral Density The VOUT temperature coefficient includes output error Output noise spectral density is a measure of internally contributions from linearity, offset, and gain drift. generated random noise. Random noise is characterized as a DC Output Impedance spectral density (voltage per √Hz). It is measured by loading DC output impedance is the effective output source resistance. all DACs to midscale and measuring noise at the output. It is It is dominated by package lead resistance. measured in nV/√Hz. DC Crosstalk The DAC outputs are buffered by op amps that share common V and V power supplies. If the dc load current changes in DD SS one channel (due to an update), this change can result in a further dc change in one or more channel outputs. This effect is more significant at high load currents and is reduced as the load currents are reduced. With high impedance loads, the effect is virtually immeasurable. Multiple V and V terminals are DD SS provided to minimize dc crosstalk. Rev. A | Page 15 of 28

AD5362/AD5363 THEORY OF OPERATION DAC ARCHITECTURE tapped off before being fed into the output amplifier. The output amplifier multiplies the DAC output voltage by 4. The nominal The AD5362/AD5363 contain eight DAC channels and eight output span is 12 V with a 3 V reference and 20 V with a 5 V output amplifiers in a single package. The architecture of a reference. single DAC channel consists of a 16-bit (AD5362) or 14-bit (AD5363) resistor-string DAC followed by an output buffer CHANNEL GROUPS amplifier. The resistor-string section is simply a string of resistors, The eight DAC channels of the AD5362/AD5363 are arranged of equal value, from VREF0 or VREF1 to AGND. This type of into two groups of four channels. The four DACs of Group 0 architecture guarantees DAC monotonicity. The 16-bit (AD5362) derive their reference voltage from VREF0. The four DACs of or 14-bit (AD5363) binary digital code loaded to the DAC Group 1 derive their reference voltage from VREF1. Each group register determines at which node on the string the voltage is has its own signal ground pin. Table 7. AD5362/AD5363 Registers Register Name Word Length in Bits Description X1A (Group) (Channel) 16 (14) Input Data Register A, one for each DAC channel. X1B (Group) (Channel) 16 (14) Input Data Register B, one for each DAC channel. M (Group) (Channel) 16 (14) Gain trim registers, one for each DAC channel. C (Group) (Channel) 16 (14) Offset trim registers, one for each DAC channel. X2A (Group) (Channel) 16 (14) Output Data Register A, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable or directly writable. X2B (Group) (Channel) 16 (14) Output Data Register B, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable or directly writable. DAC (Group) (Channel) Data registers from which the DACs take their final input data. The DAC registers are updated from the X2A or X2B registers. They are not readable or directly writable. OFS0 14 Offset DAC 0 data register: sets offset for Group 0. OFS1 14 Offset DAC 1 data register: sets offset for Group 1. Control 5 Bit 4 = overtemperature indicator. Bit 3 = PEC error flag. Bit 2 = A/B select. Bit 1 = thermal shutdown. Bit 0 = software power-down. Monitor 6 Bit 5 = monitor enable. Bit 4 = monitor DACs or monitor MON_INx pin. Bit 3 to Bit 0 = monitor selection control. GPIO 2 Bit 1 = GPIO configuration. Bit 0 = GPIO data. A/B Select 0 8 Bits [3:0] in this register determine whether a DAC in Group 0 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). A/B Select 1 8 Bits [3:0] in this register determine whether a DAC in Group 1 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). Table 8. AD5362/AD5363 Input Register Default Values Register Name AD5362 Default Value AD5363 Default Value X1A, X1B 0x8000 0x2000 M 0xFFFF 0x3FFF C 0x8000 0x2000 OFS0, OFS1 0x2000 0x2000 Control 0x00 0x00 A/B Select 0 and A/B Select 1 0x00 0x00 Rev. A | Page 16 of 28

AD5362/AD5363 A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT All DACs in the AD5362/AD5363 can be updated simultane- ously by taking LDAC low when each DAC register is updated Each DAC channel has seven data registers. The actual DAC from either its X2A or X2B register, depending on the setting of data-word can be written to either the X1A or X1B input the A/B select registers. The DAC register is not readable or register, depending on the setting of the A/B bit in the control directly writable by the user. LDAC can be permanently tied register. If the A/B bit is 0, data is written to the X1A register. low, and the DAC output is updated whenever new data appears If the A/B bit is 1, data is written to the X1B register. Note that in the appropriate DAC register. this single bit is a global control and affects every DAC channel in the device. It is not possible to set up the device on a per- OFFSET DACS channel basis so that some writes are to X1A registers and some In addition to the gain and offset trim for each DAC, there are writes are to X1B registers. two 14-bit offset DACs, one for Group 0 and one for Group 1. These allow the output range of all DACs connected to them to X1A X2A REGISTER REGISTER DAC be offset within a defined range. Thus, subject to the limitations MUX MUX REGISTER DAC X1B X2B of headroom, it is possible to set the output range of Group 0 or REGISTER REGISTER Group 1 to be unipolar positive, unipolar negative, or bipolar, M either symmetrical or asymmetrical about 0 V. The DACs in the REGISTER AD5362/AD5363 are factory trimmed with the offset DACs set REGICSTER 05762-020 amt atnhceeir f odre ftahuel dt evfaaluulets o. uTthpiust griavnegse t ahned b sepsta no.f fset and gain perfor- Figure 21. Data Registers Associated with Each DAC Channel When the output range is adjusted by changing the value of the Each DAC channel also has a gain (M) register and an offset (C) offset DAC, an extra offset is introduced due to the gain error of register, which allow trimming out of the gain and offset errors the offset DAC. The amount of offset is dependent on the mag- of the entire signal chain. Data from the X1A register is operated nitude of the reference and how much the offset DAC moves on by a digital multiplier and adder controlled by the contents of from its default value. See the Specifications section for this the M and C registers. The calibrated DAC data is then stored in offset. The worst-case offset occurs when the offset DAC is at the X2A register. Similarly, data from the X1B register is operated positive or negative full scale. This value can be added to the on by the multiplier and adder and stored in the X2B register. offset present in the main DAC channel to give an indication of Although a multiplier and an adder symbol are shown in Figure 21 the overall offset for that channel. In most cases, the offset can for each channel, there is only one multiplier and one adder in be removed by programming the C register of the channel with the device, which are shared among all channels. This has impli- an appropriate value. The extra offset caused by the offset DAC cations for the update speed when several channels are updated needs to be taken into account only when the offset DAC is at once, as described in the Register Update Rates section. changed from its default value. Figure 22 shows the allowable Each time data is written to the X1A register, or to the M or C code range that can be loaded to the offset DAC, depending on register with the A/B control bit set to 0, the X2A data is recal- the reference value used. Thus, for a 5 V reference, the offset culated and the X2A register is automatically updated. Similarly, DAC should not be programmed with a value greater than 8192 X2B is updated each time data is written to X1B, or to M or C (0x2000). with A/B set to 1. The X2A and X2B registers are not readable 5 or directly writable by the user. RESERVED Data output from the X2A and X2B registers is routed to the 4 final DAC register by a multiplexer. A 4-bit A/B select register associated with each group of four DACs controls whether each 3 individual DAC takes its data from the X2A or X2B register. If a )V F( bit in this register is 0, the DAC takes its data from the X2A RE register; if 1, the DAC takes its data from the X2B register. V 2 Note that because there are eight bits in two registers, it is possible to set up, on a per-channel basis, whether each DAC takes its 1 data from the X2A or X2B register. A global command is also provided that sets all bits in the A/B select registers to 0 or to 1. 00 4096 OFFSET8 1D9A2C CODE 12288 16383 05762-021 Figure 22. Offset DAC Code Range Rev. A | Page 17 of 28

AD5362/AD5363 OUTPUT AMPLIFIER offset DAC is 8192 (0x2000). With a 5 V reference, this gives a span of −10 V to +10 V. Because the output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, this limits AD5363 Transfer Function how much the output can be offset for a given reference voltage. The input code is the value in the X1A or X1B register that is For example, it is not possible to have a unipolar output range applied to the DAC (X1A, X1B default code = 8192). of 20 V, because the maximum supply voltage is ±16.5 V. DAC_CODE = INPUT_CODE × (M + 1)/214 + C − 213 DAC S1 CHANNEL where: OUTPUT R6 M = code in gain register − default code = 214 – 1. R5 S2 10kΩ C = code in offset register − default code = 213. 60kΩ CLR CLR The DAC output voltage is calculated as follows: R1 20kΩ CLR S3 VOUT = 4 × VREF × (DAC_CODE − OFFSET_CODE)/ 60Rk4Ω 20Rk3Ω R202kΩ SIGGNDx 214 + VSIGGND SIGGNDx where: OFDFASCET 05762-022 DFoArC 1_2C VO sDpEan s,h VouRlEdF b =e w3.i0t hVi.n the range of 0 to 16,383. Figure 23. Output Amplifier and Offset DAC For 20 V span, VREF = 5.0 V. OFFSET_CODE is the code loaded to the offset DAC. On power- Figure 23 shows details of a DAC output amplifier and its connec- up, the default code loaded to the offset DAC is 8192 (0x2000). tions to the offset DAC. On power-up, S1 is open, disconnecting With a 5 V reference, this gives a span of −10 V to +10 V. the amplifier from the output. S3 is closed, so the output is pulled to SIGGNDx (R1 and R2 are greater than R6). S2 is also closed to REFERENCE SELECTION prevent the output amplifier from being open-loop. If CLR is low at The AD5362/AD5363 have two reference input pins. The power-up, the output remains in this condition until CLR is taken voltage applied to the reference pins determines the output high. The DAC registers can be programmed, and the outputs voltage span on VOUT0 to VOUT7. VREF0 determines the assume the programmed values when CLR is taken high. Even if voltage span for VOUT0 to VOUT3 (Group 0), and VREF1 CLR is high at power-up, the output remains in this condition determines the voltage span for VOUT4 to VOUT7 (Group 1). until V > 6 V and V < −4 V and the initialization sequence has The reference voltage applied to each VREF pin can be differ- DD SS finished. The outputs then go to their power-on default value. ent, if required, allowing each group of four channels to have a different voltage span. The output voltage range and span can TRANSFER FUNCTION be adjusted further by programming the offset and gain The output voltage of a DAC in the AD5362/AD5363 is depen- registers for each channel as well as programming the offset dent on the value in the input register, the value of the M and C DAC. If the offset and gain features are not used (that is, the M registers, and the value in the offset DAC. and C registers are left at their default values), the required AD5362 Transfer Function reference levels can be calculated as follows: The input code is the value in the X1A or X1B register that is VREF = (VOUT − VOUT )/4 MAX MIN applied to the DAC (X1A, X1B default code = 32,768). If the offset and gain features of the AD5362/AD5363 are used, DAC_CODE = INPUT_CODE × (M + 1)/216 + C − 215 the required output range is slightly different. The selected output range should take into account the system offset and where: gain errors that need to be trimmed out. Therefore, the selected M = code in gain register − default code = 216 – 1. output range should be larger than the actual, required range. C = code in offset register − default code = 215. The required reference levels can be calculated as follows: The DAC output voltage is calculated as follows: 1. Identify the nominal output range on VOUT. VOUT = 4 × VREF × (DAC_CODE − (OFFSET_CODE × 2. Identify the maximum offset span and the maximum gain 4))/216 + V SIGGND required on the full output signal range. where: 3. Calculate the new maximum output range on VOUT, DAC_CODE should be within the range of 0 to 65,535. including the expected maximum offset and gain errors. For 12 V span, VREF = 3.0 V. 4. Choose the new required VOUT and VOUT , keep- MAX MIN For 20 V span, VREF = 5.0 V. ing the VOUT limits centered on the nominal values. Note OFFSET_CODE is the code loaded to the offset DAC. It is that V and V must provide sufficient headroom. DD SS multiplied by 4 in the transfer function because this DAC is a 5. Calculate the value of VREF as follows: 14-bit device. On power-up, the default code loaded to the VREF = (VOUT − VOUT )/4 MAX MIN Rev. A | Page 18 of 28

AD5362/AD5363 Reference Selection Example Reducing Full-Scale Error If Full-scale error can be reduced as follows: Nominal output range = 20 V (−10 V to +10 V) 1. Measure the zero-scale error. 2. Set the output to the highest possible value. Offset error = ±100 mV 3. Measure the actual output voltage and compare it to the Gain error = ±3%, and required value. Add this error to the zero-scale error. This SIGGND = AGND = 0 V is the span error, which includes the full-scale error. 4. Calculate the number of LSBs equivalent to the span error Then and subtract this number from the default value of the M Gain error = ±3% register. Note that only positive full-scale error can be => Maximum positive gain error = 3% reduced. => Output range including gain error = 20 + 0.03(20) = 20.6 V AD5362 Calibration Example Offset error = ±100 mV => Maximum offset error span = 2(100 mV) = 0.2 V This example assumes that a −10 V to +10 V output is required. => Output range including gain error and offset error = The DAC output is set to −10 V but measured at −10.03 V. This 20.6 V + 0.2 V = 20.8 V gives a zero-scale error of −30 mV. VREF calculation 1 LSB = 20 V/65,536 = 305.176 μV Actual output range = 20.6 V, that is, −10.3 V to +10.3 V 30 mV = 98 LSBs (centered); The full-scale error can now be calculated. The output is set to VREF = (10.3 V + 10.3 V)/4 = 5.15 V 10 V and a value of 10.02 V is measured. This gives a full-scale If the solution yields an inconvenient reference level, the user error of +20 mV and a span error of +20 mV – (–30 mV) = can adopt one of the following approaches: +50 mV. • Use a resistor divider to divide down a convenient, higher 50 mV = 164 LSBs reference level to the required level. The errors can now be removed as follows: • Select a convenient reference level above VREF and modify 1. Add 98 LSBs to the default C register value: the gain and offset registers to digitally downsize the reference. (32,768 + 98) = 32,866 In this way, the user can use almost any convenient reference 2. Subtract 164 LSBs from the default M register value: level but can reduce the performance by overcompaction of (65,535 − 164) = 65,371 the transfer function. 3. Program the M register to 65,371; program the C register • Use a combination of these two approaches. to 32,866. CALIBRATION ADDITIONAL CALIBRATION The user can perform a system calibration on the AD5362/ The techniques described in the previous section are usually AD5363 to reduce gain and offset errors to below 1 LSB. This enough to reduce the zero-scale and full-scale errors in most reduction is achieved by calculating new values for the M and applications. However, there are limitations whereby the errors C registers and reprogramming them. may not be sufficiently reduced. For example, the offset (C) The M and C registers should not be programmed until both register can only be used to reduce the offset caused by the the zero-scale and full-scale errors are calculated. negative zero-scale error. A positive offset cannot be reduced. Reducing Zero-Scale Error Likewise, if the maximum voltage is below the ideal value, that is, a negative full-scale error, the gain (M) register cannot be Zero-scale error can be reduced as follows: used to increase the gain to compensate for the error. 1. Set the output to the lowest possible value. These limitations can be overcome by increasing the reference 2. Measure the actual output voltage and compare it to the value. With a 2.5 V reference, a 10 V span is achieved. The ideal required value. This gives the zero-scale error. voltage range, for the AD5362 or the AD5363, is −5 V to +5 V. 3. Calculate the number of LSBs equivalent to the error and Using a +2.6 V reference increases the range to −5.2 V to +5.2 V. add this number to the default value of the C register. Note Clearly, in this case, the offset and gain errors are insignificant, that only negative zero-scale error can be reduced. and the M and C registers can be used to raise the negative voltage to −5 V and then reduce the maximum voltage to +5 V to give the most accurate values possible. Rev. A | Page 19 of 28

AD5362/AD5363 RESET FUNCTION The DAC outputs are updated by taking the LDAC input low. If The reset function is initiated by the RESET pin. On the rising LDAC goes low while BUSY is active, the LDAC event is stored edge of RESET, the AD5362/AD5363 state machine initiates a and the DAC outputs are updated immediately after BUSY goes reset sequence to reset the X, M, and C registers to their default high. A user can also hold the LDAC input permanently low. In values. This sequence typically takes 300 μs, and the user should this case, the DAC outputs update immediately after BUSY goes not write to the part during this time. On power-up, it is recom- high. Whenever the A/B select registers are written to, BUSY mended that the user bring RESET high as soon as possible to also goes low, for approximately 600 ns. properly initialize the registers. The AD5362/AD5363 have flexible addressing that allows When the reset sequence is complete (and provided that CLR is writing of data to a single channel, all channels in a group, or high), the DAC output is at a potential specified by the default all channels in the device. This means that one, two, four, or register settings, which is equivalent to SIGGNDx. The DAC eight DAC register values may need to be calculated and outputs remain at SIGGNDx until the X, M, or C register is updated. Because there is only one multiplier shared between updated and LDAC is taken low. The AD5362/AD5363 can be eight channels, this task must be done sequentially, so the returned to the default state by pulsing RESET low for at least length of the BUSY pulse varies according to the number of channels being updated. 30 ns. Note that, because the reset function is triggered by the rising edge, bringing RESET low has no effect on the operation Table 9. BUSY Pulse Widths of the AD5362/AD5363. Action BUSY Pulse Width1 CLEAR FUNCTION Loading input, C, or M to 1 channel2 1.5 μs maximum CLR is an active low input that should be high for normal Loading input, C, or M to 2 channels 2.1 μs maximum operation. The CLR pin has an internal 500 kΩ pull-down Loading input, C, or M to 8 channels 5.7 μs maximum resistor. When CLR is low, the input to each of the DAC output 1 BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns. buffer stages (VOUT0 to VOUT7) is switched to the externally 2 A single channel update is typically 1 μs. set potential on the relevant SIGGNDx pin. While CLR is low, The AD5362/AD5363 contain an extra feature whereby a DAC all LDAC pulses are ignored. When CLR is taken high again, register is not updated unless its X2A or X2B register has been the DAC outputs return to their previous values. The contents written to since the last time LDAC was brought low. Normally, of the input registers and DAC Register 0 to DAC Register 7 are when LDAC is brought low, the DAC registers are filled with not affected by taking CLR low. To prevent glitches appearing the contents of the X2A or X2B registers, depending on the on the outputs, CLR should be brought low whenever the setting of the A/B select registers. However, the AD5362/ output span is adjusted by writing to the offset DAC. AD5363 update the DAC register only if the X2A or X2B data BUSY AND LDAC FUNCTIONS has changed, thereby removing unnecessary digital crosstalk. The value of an X2 (A or B) register is calculated each time the BIN/2SCOMP PIN user writes new data to the corresponding X1, C, or M registers. The BIN/2SCOMP pin determines if the output data is presented During the calculation of X2, the BUSY output goes low. While as offset binary or twos complement. If this pin is low, the data BUSY is low, the user can continue writing new data to the X1, is straight binary. If it is high, the data is twos complement. This M, or C registers (see the Register Update Rates section for affects only the X, C, and offset DAC registers; the M register and more details), but no DAC output updates can take place. the control and command data are interpreted as straight binary. The BUSY pin is bidirectional and has a 50 kΩ internal pull-up TEMPERATURE SENSOR resistor. When multiple AD5362 or AD5363 devices are used in The on-chip temperature sensor provides a voltage output one system, the BUSY pins can be tied together. This is useful at the TEMP_OUT pin that is linearly proportional to the when it is required that no DAC in any device be updated until Centigrade temperature scale. The typical accuracy of the all other DACs are ready. When each device has finished updat- temperature sensor is +1°C at +25°C and ±5°C over the −40°C ing the X2 (A or B) registers, it releases the BUSY pin. If to +85°C range. Its nominal output voltage is 1.46 V at 25°C, another device has not finished updating its X2 registers, it varying at 4.4 mV/°C. Its low output impedance, low self- holds BUSY low, thus delaying the effect of LDAC going low. heating, and linear output simplify interfacing to temperature control circuitry and analog-to-digital converters. Rev. A | Page 20 of 28

AD5362/AD5363 MONITOR FUNCTION When Bit F1 is set, the GPIO pin becomes an output and Bit F0 determines whether the pin is high or low. The GPIO pin can be The AD5362/AD5363 contain a channel monitor function set as an input by writing 0 to both Bit F1 and Bit F0. The status that consists of an analog multiplexer addressed via the serial of the GPIO pin can be determined by initiating a read operation interface, allowing any channel output to be routed to the using the appropriate bits in Table 17. The status of the pin is MON_OUT pin for monitoring using an external ADC. In indicated by the LSB of the register read. addition, two monitor inputs, MON_IN0 and MON_IN1, are provided, which can also be routed to MON_OUT. The POWER-DOWN MODE monitor function is controlled by the monitor register, which The AD5362/AD5363 can be powered down by setting Bit 0 in allows the monitor output to be enabled or disabled, and selects the control register to 1. This turns off the DACs, thus reducing a DAC channel or one of the monitor pins. When disabled, the the current consumption. The DAC outputs are connected to monitor output is high impedance so that several monitor their respective SIGGNDx potentials. The power-down mode outputs can be connected in parallel with only one enabled at does not change the contents of the registers, and the DACs a time. Table 10 shows the monitor register settings. return to their previous voltage when the power-down bit is cleared to 0. Table 10. Monitor Register Functions F5 F4 F3 F2 F1 F0 Function THERMAL SHUTDOWN FUNCTION 0 X X X X X MON_OUT disabled The AD5362/AD5363 can be programmed to shut down the 1 X X X X X MON_OUT enabled DACs if the temperature on the die exceeds 130°C. Setting Bit 1 1 0 0 0 0 0 MON_OUT = VOUT0 in the control register to 1 enables this function (see Table 16). 1 0 0 0 0 1 MON_OUT = VOUT1 If the die temperature exceeds 130°C, the AD5362/AD5363 1 0 0 0 1 0 MON_OUT = VOUT2 enter a thermal shutdown mode, which is equivalent to setting 1 0 0 0 1 1 MON_OUT = VOUT3 the power-down bit in the control register. To indicate that the 1 0 1 0 0 0 MON_OUT = VOUT4 AD5362/AD5363 have entered thermal shutdown mode, Bit 4 1 0 1 0 0 1 MON_OUT = VOUT5 of the control register is set to 1. The AD5362/AD5363 remain 1 0 1 0 1 0 MON_OUT = VOUT6 in thermal shutdown mode, even if the die temperature falls, 1 0 1 0 1 1 MON_OUT = VOUT7 until Bit 1 in the control register is cleared to 0. 1 1 0 0 0 0 MON_OUT = MON_IN0 TOGGLE MODE 1 1 0 0 0 1 MON_OUT = MON_IN1 The AD5362/AD5363 have two X2 registers per channel, X2A The multiplexer is implemented as a series of analog switches. and X2B, which can be used to switch the DAC output between Because this could conceivably cause a large amount of current two levels with ease. This approach greatly reduces the overhead to flow from the input of the multiplexer (VOUTx or MON_INx) required by a microprocessor, which would otherwise need to to the output of the multiplexer (MON_OUT), care should be write to each channel individually. When the user writes to the taken to ensure that whatever is connected to the MON_OUT X1A, X1B, M, or C register, the calculation engine takes a certain pin is of high enough impedance to prevent the continuous amount of time to calculate the appropriate X2A or X2B value. current limit specification from being exceeded. Because the If an application, such as a data generator, requires that the DAC MON_OUT pin is not buffered, the amount of current drawn output switch between two levels only, any method that reduces from this pin creates a voltage drop across the switches, which the amount of calculation time necessary is advantageous. For in turn leads to an error in the voltage being monitored. Where the data generator example, the user needs only to set the high accuracy is important, it is recommended that the MON_OUT and low levels for each channel once by writing to the X1A and pin be buffered. Figure 20 shows the typical error due to X1B registers. The values of X2A and X2B are calculated and MON_OUT current. stored in their respective registers. The calculation delay, GPIO PIN therefore, happens only during the setup phase, that is, when The AD5362/AD5363 have a general-purpose I/O pin, GPIO. programming the initial values. To toggle a DAC output between This pin can be configured as an input or an output and read the two levels, it is only required to write to the relevant A/B back or programmed (when configured as an output) via the select register to set the MUX2 register bit. Furthermore, serial interface. Typical applications for this pin include moni- because there are four MUX2 control bits per register, it is toring the status of a logic signal, a limit switch, or controlling possible to update eight channels with just two writes. Table 18 an external multiplexer. The GPIO pin is configured by writing shows the bits that correspond to each DAC output. to the GPIO register, which has the special function code of 001101 (see Table 15 and Table 16). Rev. A | Page 21 of 28

AD5362/AD5363 SERIAL INTERFACE The AD5362/AD5363 contain a high speed SPI operating at The input register addressed is updated on the rising edge of clock frequencies up to 50 MHz (20 MHz for read operations). SYNC. For another serial transfer to take place, SYNC must be To minimize both the power consumption of the device and taken low again. on-chip digital noise, the interface powers up fully only when SPI READBACK MODE the device is being written to, that is, on the falling edge of SYNC. The serial interface is 2.5 V LVTTL-compatible when The AD5362/AD5363 allow data readback via the serial interface from every register directly accessible to the serial operating from a 2.5 V to 3.6 V DV supply. It is controlled by CC interface, that is, all registers except the X2A, X2B, and DAC four pins: SYNC (frame synchronization input), SDI (serial data data registers. To read back a register, it is first necessary to input pin), SCLK (clocks data in and out of the device), and tell the AD5362/AD5363 which register is to be read. This is SDO (serial data output pin for data readback). achieved by writing a word whose first two bits are the Special SPI WRITE MODE Function Code 00 to the device. The remaining bits then The AD5362/AD5363 allow writing of data via the serial inter- determine which register is to be read back. face to every register directly accessible to the serial interface, If a readback command is written to a special function register, that is, all registers except the X2A, X2B, and DAC registers. data from the selected register is clocked out of the SDO pin The X2A and X2B registers are updated when writing to the during the next SPI operation. The SDO pin is normally three- X1A, X1B, M, and C registers, and the DAC data registers are stated but becomes driven as soon as a read command is issued. updated by LDAC. The serial word (see Table 11 or Table 12) The pin remains driven until the register data is clocked out. is 24 bits long: 16 (AD5362) or 14 (AD5363) of these bits are See Figure 5 for the read timing diagram. Note that due to the data bits; six bits are address bits; and two bits are mode bits timing requirements of t (25 ns), the maximum speed of the 22 that determine what is done with the data. Two bits are reserved SPI interface during a read operation should not exceed 20 MHz. on the AD5363. REGISTER UPDATE RATES The serial interface works with both a continuous and a burst The value of the X2A register or the X2B register is calculated (gated) serial clock. Serial data applied to SDI is clocked into each time the user writes new data to the corresponding X1, C, the AD5362/AD5363 by clock pulses applied to SCLK. The first or M register. The calculation is performed by a three-stage falling edge of SYNC starts the write cycle. At least 24 falling process. The first two stages take approximately 600 ns each, and clock edges must be applied to SCLK to clock in 24 bits of data the third stage takes approximately 300 ns. When the write to an before SYNC is taken high again. If SYNC is taken high before X1, C, or M register is complete, the calculation process begins. the 24th falling clock edge, the write operation is aborted. If the write operation involves the update of a single DAC If a continuous clock is used, SYNC must be taken high before the channel, the user is free to write to another register, provided 25th falling clock edge. This inhibits the clock within the AD5362/ that the write operation does not finish until the first-stage AD5363. If more than 24 falling clock edges are applied before calculation is complete, that is, 600 ns after the completion of SYNC is taken high again, the input data becomes corrupted. the first write operation. If a group of channels is being updated If an externally gated clock of exactly 24 pulses is used, SYNC by a single write operation, the first-stage calculation is repeated can be taken high any time after the 24th falling clock edge. for each channel, taking 600 ns per channel. In this case, the user should not complete the next write operation until this time has elapsed. Table 11. AD5362 Serial Word Bit Assignment I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 12. AD5363 Serial Word Bit Assignment I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I11 I01 M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 Bit I1 and Bit I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0. Rev. A | Page 22 of 28

AD5362/AD5363 PACKET ERROR CHECKING CHANNEL ADDRESSING AND SPECIAL MODES To verify that data has been received correctly in noisy environ- If the mode bits are not 00, the data-word D15 to D0 (AD5362) ments, the AD5362/AD5363 offer the option of error checking or D13 to D0 (AD5363) is written to the device. Address Bit A4 based on an 8-bit (CRC-8) cyclic redundancy check. The device to Address Bit A0 determine which channels are written to, and controlling the AD5362/AD5363 should generate an 8-bit the mode bits determine to which register (X1A, X1B, C, or M) checksum using the polynomial C(x) = x8 + x2 + x1 + 1. This is the data is written, as shown in Table 13 and Table 14. Data is to added to the end of the data-word, and 32 data bits are sent to be written to the X1A register when the A/B bit in the control the AD5362/AD5363 before taking SYNC high. If the AD5362/ register is 0, or to the X1B register when the A/B bit is 1. AD5363 see a 32-bit data frame, an error check is performed The AD5362/AD5363 have very flexible addressing that allows when SYNC goes high. If the checksum is valid, the data is the writing of data to a single channel, all channels in a group, written to the selected register. If the checksum is invalid, the or all channels in the device. packet error check (PEC) output goes low and Bit 3 of the Table 14 shows which groups and which channels are addressed control register is set. After reading the control register, Bit 3 for every combination of Address Bit A4 to Address Bit A0. is cleared automatically and PEC goes high again. UPDATE ON SYNC HIGH Table 13. Mode Bits SYNC M1 M0 Action 1 1 Write to DAC data (X) register 1 0 Write to DAC offset (C) register SCLK MSB LSB 0 1 Write to DAC gain (M) register D23 D0 0 0 Special function, used in combination with other SDI 24-BIT DATA bits of the data-word 24-BIT DATA TRANSFER—NO ERROR CHECKING UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC SCLK MSB LSB D31 D8 D7 D0 SDI 24-BIT DATA 8-BIT FCS PEC PEC GOES LOW IF ERROR CHECK FAILS 24-BIT DATA TRANSFER WITH ERROR CHECKING 05762-026 Figure 24. SPI Write With and Without Error Checking Table 14. Group and Channel Addressing Address Bit A2 Address Bit A4 to Address Bit A3 to Address Bit A0 00 01 10 11 000 All groups, all channels Group 0, Channel 0 Group 1, Channel 0 Unused 001 Group 0, all channels Group 0, Channel 1 Group 1, Channel 1 Unused 010 Group 1, all channels Group 0, Channel 2 Group 1, Channel 2 Unused 011 Unused Group 0, Channel 3 Group 1, Channel 3 Unused 100 Unused Unused Unused Unused 101 Unused Unused Unused Unused 110 Unused Unused Unused Unused 111 Unused Unused Unused Unused Rev. A | Page 23 of 28

AD5362/AD5363 SPECIAL FUNCTION MODE If the mode bits are 00, the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback. The codes for the special functions are shown in Table 16. Table 17 shows the addresses for data readback. Table 15. Special Function Mode I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 Table 16. Special Function Codes Special Function Code S5 S4 S3 S2 S1 S0 Data (F15 to F0) Action 0 0 0 0 0 0 0000 0000 0000 0000 NOP. 0 0 0 0 0 1 XXXX XXXX XXXX X [F2:F0] Write control register. F4 = 1: Temperature over 130°C. F4 = 0: Temperature below 130°C. Read-only bit. This bit should be 0 when writing to the control register. F3 = 1: PEC error. F3 = 0: No PEC error. Reserved. Read-only bit. This bit should be 0 when writing to the control register. F2 = 1: Select Register X1B for input. F2 = 0: Select Register X1A for input. F1 = 1: Enable thermal shutdown mode. F1 = 0: Disable thermal shutdown mode. F0 = 1: Software power-down. F0 = 0: Software power-up. 0 0 0 0 1 0 XX [F13:F0] Write data in F13 to F0 to OFS0 register. 0 0 0 0 1 1 XX [F13:F0] Write data in F13 to F0 to OFS1 register. 0 0 0 1 0 0 Reserved 0 0 0 1 0 1 See Table 17 Select register for readback. 0 0 0 1 1 0 XXXX XXXX XXXX [F3:F0] Write data in F3 to F0 to A/B Select Register 0. 0 0 0 1 1 1 XXXX XXXX XXXX [F3:F0] Write data in F3 to F0 to A/B Select Register 1. 0 0 1 0 0 0 Reserved 0 0 1 0 0 1 Reserved 0 0 1 0 1 0 Reserved 0 0 1 0 1 1 XXXX XXXX [F7:F0] Block write to A/B select registers. F7 to F0 = 0: Write all 0s (all channels use X2A register). F7 to F0 = 1: Write all 1s (all channels use X2B register). 0 0 1 1 0 0 XXXX XXXX XX [F5:F0] F5 = 1: Monitor enable. F5 = 0: Monitor disable. F4 = 1: Monitor input pin selected by F0. F4 = 0: Monitor DAC channel selected by F3:F0 (see Table 10). F3 = not used if F4 = 1. F2 = not used if F4 = 1. F1 = not used if F4 = 1. F0 = 0: MON_IN0 selected for monitoring (if F4 and F5 = 1). F0 = 1: MON_IN1 selected for monitoring (if F4 and F5 = 1). 0 0 1 1 0 1 XXXX XXXX XXXX XX [F1:F0] GPIO configure and write. F1 = 1: GPIO is an output. Data to output is written to F0. F1 = 0: GPIO is an input. Data can be read from F0 on readback. Rev. A | Page 24 of 28

AD5362/AD5363 Table 17. Address Codes for Data Readback1 F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read 0 0 0 X1A register Bit F12 to Bit F7 select the channel to be read back; 0 0 1 X1B register Channel 0 = 001000 to Channel 3 = 001011 0 1 0 C register Channel 4 = 010000 to Channel 7 = 010011 0 1 1 M register 1 0 0 0 0 0 0 0 1 Control register 1 0 0 0 0 0 0 1 0 OFS0 data register 1 0 0 0 0 0 0 1 1 OFS1 data register 1 0 0 0 0 0 1 0 0 Reserved 1 0 0 0 0 0 1 1 0 A/B Select Register 0 1 0 0 0 0 0 1 1 1 A/B Select Register 1 1 0 0 0 0 1 0 0 0 Reserved 1 0 0 0 0 1 0 0 1 Reserved 1 0 0 0 0 1 0 1 0 Reserved 1 0 0 0 0 1 0 1 1 GPIO read (data in F0)2 1 Bit F6 to Bit F0 are don’t cares for the data readback function. 2 Bit F6 to Bit F0 should be 0 for GPIO read. Table 18. DACs Selected by A/B Select Registers A/B Select Bits1 Register F7 F6 F5 F4 F3 F2 F1 F0 0 Reserved Reserved Reserved Reserved DAC 3 DAC 2 DAC 1 DAC 0 1 Reserved Reserved Reserved Reserved DAC 7 DAC 6 DAC 5 DAC 4 1 If the bit is set to 0, Register X2A is selected. If the bit is set to 1, Register X2B is selected. Rev. A | Page 25 of 28

AD5362/AD5363 APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING care should be taken to ensure that the ground pins are connected to the supply grounds before the positive or negative In any circuit where accuracy is important, careful considera- supplies are connected. This is required to prevent currents tion of the power supply and ground return layout helps to from flowing in directions other than toward an analog or ensure the rated performance. The printed circuit boards on digital ground. which the AD5362/AD5363 are mounted should be designed so INTERFACING EXAMPLES that the analog and digital sections are separated and confined to certain areas of the board. If the AD5362/AD5363 are in a The SPI interface of the AD5362/AD5363 is designed to allow system where multiple devices require an AGND-to-DGND the parts to be easily connected to industry-standard DSPs and connection, the connection should be made at one point only. microcontrollers. Figure 25 shows how the AD5362/AD5363 can The star ground point should be established as close as possible connect to the Analog Devices, Inc., Blackfin® DSP. The Blackfin to the device. For supplies with multiple pins (VSS, VDD, DVCC), has an integrated SPI port that can be connected directly to the it is recommended that these pins be tied together and that each SPI pins of the AD5362 or AD5363, and programmable I/O supply be decoupled only once. pins that can be used to set or read the state of the digital input or output pins associated with the interface. The AD5362/AD5363 should have ample supply decoupling of 10 μF in parallel with 0.1 μF on each supply located as close to AD5362/ the package as possible, ideally right up against the device. The AD5363 SPISELx SYNC 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor SCK SCLK should have low effective series resistance (ESR) and low effective MOSI SDI series inductance (ESI)—typical of the common ceramic types MISO SDO that provide a low impedance path to ground at high frequencies— to handle transient currents due to internal logic switching. PF10 RESET ADSP-BF531 PF9 LDAC Digital lines running under the device should be avoided because PF8 CLR they can couple noise onto the device. The analog ground plane should be allowed to run under the AD5362/AD5363 to avoid PF7 BUSY 05762-023 noise coupling. The power supply lines of the AD5362/AD5363 Figure 25. Interfacing to a Blackfin DSP should use as large a trace as possible to provide low impedance The Analog Devices ADSP-21065L is a floating-point DSP with paths and reduce the effects of glitches on the power supply line. two serial ports (SPORTs). Figure 26 shows how one SPORT can Fast switching digital signals should be shielded with digital be used to control the AD5362 or AD5363. In this example, the ground to avoid radiating noise to other parts of the board, and transmit frame synchronization (TFSx) pin is connected to the they should never be run near the reference inputs. It is essential receive frame synchronization (RFSx) pin. Similarly, the transmit to minimize noise on the VREF0 and VREF1 lines. and receive clocks (TCLKx and RCLKx) are also connected. The Avoid crossover of digital and analog signals. Traces on oppo- user can write to the AD5362/AD5363 by writing to the transmit site sides of the board should run at right angles to each other. register of the ADSP-21065L. A read operation can be accom- This reduces the effects of feedthrough through the board. A plished by first writing to the AD5362/AD5363 to tell the part microstrip technique is by far the best approach, but it is not that a read operation is required. A second write operation with always possible with a double-sided board. In this technique, an NOP instruction causes the data to be read from the the component side of the board is dedicated to ground plane, AD5362/AD5363. The DSP receive interrupt can be used to while signal traces are placed on the solder side. indicate when the read operation is complete. As is the case for all thin packages, care must be taken to avoid ADSP-21065L AD5362/ flexing the package and to avoid a point load on the surface of TFSx AD5363 this package during the assembly process. RFSx SYNC TCLKx POWER SUPPLY SEQUENCING RCLKx SCLK DTxA SDI When the supplies are connected to the AD5362/AD5363, it DRxA SDO is important that the AGND and DGND pins be connected to the relevant ground plane before the positive or negative FLAG0 RESET supplies are applied. In most applications, this is not an issue FLAG1 LDAC btoe cthaue sger tohuen gdr opuinnsd o pf itnhse fAorD t5h3e6 p2o/AwDer5 s3u6p3p vliieas garroeu cnodn npelacnteeds. FFLLAAGG23 CBLURSY 05762-024 When the AD5362/AD5363 are to be used in a hot-swap card, Figure 26. Interfacing to an ADSP-21065L DSP Rev. A | Page 26 of 28

AD5362/AD5363 OUTLINE DIMENSIONS 12.20 0.75 12.00 SQ 0.60 1.60 11.80 0.45 MAX 52 40 1 39 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 13 27 0.15 0° 14 26 0.05 SPLEAANTEING 0C.O10PLANARITY VIEW A 0.65 0.38 BSC 0.32 LEAD PITCH 0.22 VIEW A ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BCC 051706-A Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters 0.30 8.00 0.60 MAX 0.23 BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 43 56 1 PIN 1 42 INDICATOR TOP 7.75 EXPOSED 6.25 VIEW BSC SQ PAD 6.10 SQ (BOTTOM VIEW) 5.95 0.50 0.40 29 0.30 28 15 14 0.25 MIN 6.50 1.00 12° MAX 0.80 MAX REF 0.85 0.65 TYP 0.80 0.05 MAX 0.02 NOM SEATING 0.50 BSC COPLANARITY PLANE 0.20 REF 0.08 COMPLIANTTO JEDEC STANDARDS MO-220-VLLD-2 112805-0 Figure 28. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm Body, Very Thin Quad (CP-56-1) Dimensions shown in millimeters Rev. A | Page 27 of 28

AD5362/AD5363 ORDERING GUIDE Model Temperature Range Package Description Package Option AD5362BSTZ1 −40°C to +85°C 52-Lead Low Profile Quad Flat Package [LQFP] ST-52 AD5362BSTZ-REEL1 −40°C to +85°C 52-Lead Low Profile Quad Flat Package [LQFP] ST-52 AD5362BCPZ1 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 AD5362BCPZ-REEL71 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 EVAL-AD5362EBZ1 Evaluation Board AD5363BSTZ1 −40°C to +85°C 52-Lead Low Profile Quad Flat Package [LQFP] ST-52 AD5363BSTZ-REEL1 −40°C to +85°C 52-Lead Low Profile Quad Flat Package [LQFP] ST-52 AD5363BCPZ1 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 AD5363BCPZ-REEL71 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-56-1 EVAL-AD5363EBZ1 Evaluation Board 1 Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05762-0-3/08(A) Rev. A | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5362BCPZ AD5362BCPZ-REEL7 AD5362BSTZ AD5362BSTZ-REEL AD5363BCPZ AD5363BCPZ-REEL7 AD5363BSTZ AD5363BSTZ-REEL EVAL-AD5362EBZ EVAL-AD5363EBZ