16-Channel, 16-/14-Bit, Serial Input, Voltage-Output DAC AD5360/AD5361 FEATURES SPI-compatible serial interface 2.5 V to 5.5 V digital interface 16-channel DAC in 52-lead LQFP and 56-lead LFCSP Digital reset (RESET) packages Clear function to user-defined SIGGNDx Guaranteed monotonic to 16/14 bits Simultaneous update of DAC outputs Nominal output voltage range of −10 V to +10 V Multiple output spans available APPLICATIONS Temperature monitoring function Instrumentation Channel monitoring multiplexer Industrial control systems GPIO function Level setting in automatic test equipment (ATE) System calibration function allowing user-programmable Variable optical attenuators (VOA) offset and gain Optical line cards Channel grouping and addressing features Data error checking feature FUNCTIONAL BLOCK DIAGRAM DVCC VDD VSS AGND DGND LDAC TEMP_OPEUCT RCSEOETGNNEITMSSRTOPOERRL 8 nn == 1164 FFOORR AADD55336601 14 OFS0 14 OFFSET BUFFER GROUP 0 VREF0 MON_IN0 VVOOUUTT01 5TO 8 AR/BE GSIESLTEECRT 8 TMOUX 2s REGISTER DAC 0 BUFFER BINM/M2OSONCN_GOO_PIMUNIOPT1 MRUEXGGPISIOTER 62 nnn XMC1 RRREEEGG·····GIIISSSTTTEEERRR nn ····· n ·····n AM·····/UBX XX22AB RREE····GGIISSTTEERR M····2UX n REDGA·····ISCT 0ERn DA······C 0 ODOUATWNPDNU PTC······O OBWNUTEFRFREO-RL VVVVVVVOOOOOOOUUUUUUUTTTTTTT0123456 · · · · · · · SSYCSNLDCKI INTSEERRFIAALCE nnn XMC1 RRREEEGGGIIISSSTTTEEERRR nn n n AM/UBX XX22AB RREEGGIISSTTEERR M2UXn REDGAISCT 7ERn DAC 7 ODOUATWNPDNU PTCO OBWNUTEFRFREO-RL VSVORIGEUGFTN17D0 SDO GROUP 1 BUSY 8 A/B SELECT 8 TO 14 REOGFISST1ERn ODFAFCS E1T RECSLERT MSATCAHTIENEn nnn XMC1 R RRREEEEGGG······GIIISISSSTTTTEEEERRRR nn ······ n M······nUXAM 2······/UsBX XX22AB RREE······GGIISSTTEERR M······2UX n REDGAI·····SCT 0ERn DA······C 0 BUFFER ODOUATWNPDNU PTC······O OBWNUTEFRFREO-RL VVVVVVVOOOOOOOUUUUUUUTTTTTTT891111101234 AADD55336601/ nnn XM1 RREEGGIISSTTEERR nn n n AM/UBX XX22AB RREEGGIISSTTEERR M2UX n REDGAISCT 7ERn DAC 7 ODOUATWNPDNU PTCO OBWNUTEFRFREO-RL VSOIGUGTN1D51 C REGISTER 05761-007 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5360/AD5361 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 19 Applications ....................................................................................... 1 Clear Function ............................................................................ 19 Functional Block Diagram .............................................................. 1 BUSY and LDAC Functions...................................................... 19 Revision History ............................................................................... 2 BIN/2SCOMP PIN ..................................................................... 19 General Description ......................................................................... 3 Temperature Sensor ................................................................... 19 Specifications ..................................................................................... 4 Monitor Function ....................................................................... 20 AC Characteristics ........................................................................ 5 GPIO Pin ..................................................................................... 20 Timing Characteristics ................................................................ 6 Power-Down Mode .................................................................... 20 Absolute Maximum Ratings ............................................................ 9 Thermal Monitoring Function ................................................. 20 ESD Caution .................................................................................. 9 Toggle Mode ................................................................................ 20 Pin Configuration and Function Descriptions ........................... 10 Serial Interface ................................................................................ 21 Typical Performance Characteristics ........................................... 12 SPI Write Mode .......................................................................... 21 Terminology .................................................................................... 14 SPI Readback Mode ................................................................... 22 Functional Description .................................................................. 15 Register Update Rates ................................................................ 22 DAC Architecture ....................................................................... 15 Packet Error Checking ............................................................... 22 Channel Groups .......................................................................... 15 Channel Addressing and Special Modes ................................. 23 A/B Registers Gain/Offset Adjustment ................................... 16 Special Function Mode .............................................................. 24 Offset DACs ................................................................................ 16 Power Supply Decoupling ......................................................... 25 Output Amplifier ........................................................................ 17 Power Supply Sequencing ......................................................... 25 Transfer Function ....................................................................... 17 Interfacing Examples ...................................................................... 26 Reference Selection .................................................................... 17 Outline Dimensions ....................................................................... 27 Calibration ................................................................................... 18 Ordering Guide .......................................................................... 27 REVISION HISTORY 2/08—Rev. 0 to Rev. A Added LFCSP Package ....................................................... Universal Change to DC Crosstalk Parameter ............................................... 4 Change to Power Dissipation Unloaded (P) Parameter .............. 5 Added t Parameter ......................................................................... 6 23 Change to Figure 4 ........................................................................... 7 Change to Table 5 Summary ........................................................... 9 Added Figure 8 ................................................................................ 10 Changes to Table 6 .......................................................................... 10 Changes to Calibration Section .................................................... 18 Changes to Reset Function Section .............................................. 19 Added Packet Error Checking Section ........................................ 22 Updated Outline Dimensions ....................................................... 27 Changes to Ordering Guide .......................................................... 27 10/07—Revision 0: Initial Version Rev. A | Page 2 of 28

AD5360/AD5361 GENERAL DESCRIPTION The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a The AD5360/AD5361 have a high speed 4-wire serial interface, single 52-lead LQFP or 56-lead LFCSP package. They provide which is compatible with SPI, QSPI™, MICROWIRE™, and DSP buffered voltage outputs with a span four times the reference interface standards and can handle clock speeds of up to voltage. The gain and offset of each DAC can be independently 50 MHz. All the outputs can be updated simultaneously by trimmed to remove errors. For even greater flexibility, the device is taking the LDAC input low. Each channel has a programmable divided into two groups of eight DACs, and the output range of gain register and an offset adjust register. each group can be independently adjusted by an offset DAC. Each DAC output is amplified and buffered on-chip with The AD5360/AD5361 offer guaranteed operation over a wide respect to an external SIGGNDx input. The DAC outputs can supply range with V from −4.5 V to −16.5 V and V from SS DD also be switched to SIGGNDx via the CLR pin. +8 V to +16.5 V. The output amplifier headroom requirement is 1.4 V. Rev. A | Page 3 of 28

AD5360/AD5361 SPECIFICATIONS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −16.5 V to −4.5 V; V = 5 V; AGND = DGND = SIGGND = 0 V; R = open circuit; CC DD SS REF L gain (M), offset (C), and DAC offset registers at default value; all specifications T to T , unless otherwise noted. MIN MAX Table 1. Parameter B Version1 Unit Test Conditions/Comments ACCURACY Resolution AD5360 16 Bits AD5361 14 Bits Relative Accuracy AD5360 ±4 LSB max AD5361 ±1 LSB max Differential Nonlinearity ±1 LSB max Guaranteed monotonic by design over temperature Zero-Scale Error ±15 mV max Before calibration Full-Scale Error ±20 mV max Before calibration Gain Error 0.1 % FSR Before calibration Zero-Scale Error2 1 LSB typ After calibration Full-Scale Error2 1 LSB typ After calibration Span Error of Offset DAC ±75 mV max See the Offset DACS section for details VOUTx3 Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift DC Crosstalk4 180 μV max Typically 20 μV; measured channel at midscale, full-scale change on any other channel REFERENCE INPUTS (VREF0, VREF1)2 VREF Input Current ±10 μA max Per input; typically ±30 nA VREF Range2 2/5 V min/max ±2% for specified operation SIGGND INPUT (SIGGND0 to SIGGND1)4 DC Input Impedance 50 kΩ min Typically 55 kΩ Input Range ±0.5 V max SIGGND Gain 0.995/1.005 Min/max OUTPUT CHARACTERISTICS2 Output Voltage Range V + 1.4 V min I = 1 mA SS LOAD V − 1.4 V max I = 1 mA DD LOAD Nominal Output Voltage Range −10 to +10 V nominal Short-Circuit Current 15 mA max VOUTx3 to DV , V , or V CC DD SS Load Current ±1 mA max Capacitive Load 2200 pF max DC Output Impedance 0.5 Ω max MONITOR PIN (MON_OUT)4 Output Impedance DAC Output at Positive Full-Scale 1000 Ω typ DAC Output at Negative Full-Scale 500 Ω typ Three-State Leakage Current 100 nA typ Continuous Current Limit 2 mA max DIGITAL INPUTS JEDEC compliant Input High Voltage 1.7 V min DV = 2.5 V to 3.6 V CC 2.0 V min DV = 3.6 V to 5.5 V CC Input Low Voltage 0.8 V max DV = 2.5 V to 5.5 V CC Input Current ±1 μA max RESET, SYNC, SDI, and SCLK pins ±20 μA max CLR, BIN/2SCOMP, and GPIO pins Input Capacitance4 10 pF max Rev. A | Page 4 of 28

AD5360/AD5361 Parameter B Version1 Unit Test Conditions/Comments DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC) Output Low Voltage 0.5 V max Sinking 200 μA Output High Voltage (SDO) DV − 0.5 V min Sourcing 200 μA CC High Impedance Leakage Current ±5 μA max SDO only High Impedance Output Capacitance4 10 pF typ TEMPERATURE SENSOR (TEMP_OUT)4 Accuracy ±1 °C typ @ 25°C ±5 °C typ −40°C < T < +85°C Output Voltage at 25°C 1.46 V typ Output Voltage Scale Factor 4.4 mV/°C typ Output Load Current 200 μA max Current source only Power-On Time 10 ms typ To within ±5°C POWER REQUIREMENTS DV 2.5/5.5 V min/max CC V 8/16.5 V min/max DD V −4.5/−16.5 V min/max SS Power Supply Sensitivity4 ∆ Full Scale/∆ V −75 dB typ DD ∆ Full Scale/∆ V −75 dB typ SS ∆ Full Scale/∆ DV −90 dB typ CC DI 2 mA max V = 5.5 V, V = DV , V = GND CC CC IH CC IL I 10 mA max Outputs unloaded DD I 10 mA max Outputs unloaded SS Power-Down Mode Bit 0 in the Control Register is 1 DI 5 μA typ CC I 35 μA typ DD I −35 μA typ SS Power Dissipation Power Dissipation Unloaded (P) 245 mW max V = −12 V, V = +12 V, DV = 2.5 V SS DD CC Junction Temperature 130 °C max T = T + P × θ J A TOTAL JA 1 Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C. 2 Specifications are guaranteed for a 5 V reference only. 3 VOUTx refers to any of VOUT0 to VOUT15. 4 Guaranteed by design and characterization, not production tested. AC CHARACTERISTICS DV = 2.5 V; V = 15 V; V = −15 V; V = 5 V; AGND = DGND = SIGGND = 0 V; C = 200 pF; R = 10 kΩ; gain (M), offset (C), and CC DD SS REF L L DAC offset registers at default value; all specifications T to T , unless otherwise noted. MIN MAX Table 2. Parameter B Version1 Unit Test Conditions/Comments DYNAMIC PERFORMANCE1 Output Voltage Settling Time 20 μs typ Full-scale change 30 μs max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs typ Digital-to-Analog Glitch Energy 5 nV-s typ Glitch Impulse Peak Amplitude 10 mV max Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz DAC-to-DAC Crosstalk 10 nV-s typ Digital Crosstalk 0.2 nV-s typ Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V 1 Guaranteed by design and characterization, not production tested. Rev. A | Page 5 of 28

AD5360/AD5361 TIMING CHARACTERISTICS DV = 2.5 V to 5.5 V; V = 9 V to 16.5 V; V = −8 V to −16.5 V; V = 5 V; AGND = DGND = SIGGND = 0 V; C = 200 pF to GND; CC DD SS REF L R = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T to T , unless otherwise noted. L MIN MAX Table 3. SPI Interface (See Figure 4 and Figure 5) Parameter1, 2 Limit at T , T Unit Description MIN MAX t 20 ns min SCLK cycle time 1 t 8 ns min SCLK high time 2 t 8 ns min SCLK low time 3 t 11 ns min SYNC falling edge to SCLK falling edge setup time 4 t5 20 ns min Minimum SYNC high time t 10 ns min 24th SCLK falling edge to SYNC rising edge 6 t 5 ns min Data setup time 7 t 5 ns min Data hold time 8 t 3 42 ns max SYNC rising edge to BUSY falling edge 9 t 1/1.5 μs typ/max BUSY pulse width low (single-channel update); see Table 8 10 t 600 ns max Single-channel update cycle time 11 t 20 ns min SYNC rising edge to LDAC falling edge 12 t 10 ns min LDAC pulse width low 13 t 3 μs max BUSY rising edge to DAC output response time 14 t 0 ns min BUSY rising edge to LDAC falling edge 15 t 3 μs max LDAC falling edge to DAC output response time 16 t 20/30 μs typ/max DAC output settling time 17 t 140 ns max CLR/RESET pulse activation time 18 t 30 ns min RESET pulse width low 19 t 400 μs max RESET time indicated by BUSY low 20 t 270 ns min Minimum SYNC high time in readback mode 21 t 4 25 ns max SCLK rising edge to SDO valid 22 t 80 ns max RESET rising edge to BUSY falling edge 23 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 This is measured with the load circuit shown in Figure 2. 4 This is measured with the load circuit shown in Figure 3. 200µA IOL DVCC TO OUTPUT VOH (MIN) – VOL (MAX) R2.L2kΩ PIN CL 2 TO 50pF OUTPUT VOL PIN C50LpF 05761-008 200µA IOH 05761-009 Figure 2. Load Circuit for BUSY Timing Diagram Figure 3. Load Circuit for SDO Timing Diagram Rev. A | Page 6 of 28

AD5360/AD5361 t 1 SCLK 1 2 24 1 24 t3 t2 t11 t4 t6 SYNC t5 t 7 t 8 SDI DB23 DB0 t 9 t BUSY 10 t12 t13 LDAC1 t 17 t VOUTx1 14 t 15 t 13 LDAC2 t 17 VOUTx2 t16 CLR t 18 VOUTx t 19 RESET VOUTx t 18 t 20 BUSY t 23 21LLDDAACC AACCTTIIVVEE DAUFTREINRG B BUUSSYY.. 05761-010 Figure 4. SPI Write Timing Rev. A | Page 7 of 28

AD5360/AD5361 t 22 SCLK 48 t 21 SYNC SDI DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES NOP CONDITION REGISTER TO BE READ SDO DB0 DB23 DB15 DB0 LSB FROM PREVIOUS WRITE SELECTED REGISTER DATA CLOCKED OUT 05761-011 Figure 5. SPI Read Timing OUTPUT VOLTAGE FULL-SCALE ERROR VMAX + ZERO-SCALE ERROR ACTUAL TRANSFER FUNCTION IDEAL TRANSFER FUNCTION 0 DAC CODE 2N – 1 n = 16 FOR AD5360 n = 14 FOR AD5361 ZERO-SCALE VMIN ERROR 05761-001 Figure 6. DAC Transfer Function Rev. A | Page 8 of 28

AD5360/AD5361 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings T = 25°C, unless otherwise noted. Transient currents of up to A may cause permanent damage to the device. This is a stress 60 mA do not cause SCR latch-up. rating only; functional operation of the device at these or any Table 4. other conditions above those indicated in the operational Parameter Rating section of this specification is not implied. Exposure to absolute V to AGND −0.3 V to +17 V maximum rating conditions for extended periods may affect DD V to AGND −17 V to +0.3 V device reliability. SS DV to DGND −0.3 V to +7 V CC Digital Inputs to DGND −0.3 V to DV + 0.3 V CC ESD CAUTION Digital Outputs to DGND −0.3 V to DV + 0.3 V CC VREF0, VREF1 to AGND −0.3 V to +5.5 V VOUT0 to VOUT15 to AGND V − 0.3 V to V + 0.3 V SS DD SIGGND0, SIGGND1 to AGND −1 V to +1 V AGND to DGND −0.3 V to +0.3 V MON_IN0, MON_IN1, MON_OUT to AGND V − 0.3 V to V + 0.3 V SS DD Operating Temperature (T ) A Industrial (B Version) −40°C to +85°C Storage −65°C to +150°C Junction (T max) 130°C J θ Thermal Impedance JA 52-Lead LQFP 38°C/W 56-Lead LFCSP 25°C/W Reflow Soldering Peak Temperature 230°C Time at Peak Temperature 10 sec to 40 sec Rev. A | Page 9 of 28

AD5360/AD5361 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGNDDGNDDVCCSDOPECSDISCLKSYNCDVCCDGNDVOUT7VOUT6VOUT5 RLCADDNGDNGVCCODCEIDKLCCNYVCCDNG7TUO6TUO 52 51 50 49 48 47 46 45 44 43 42 41 40 CLADDSPSSSDDVV 6555453525150594847464544434 LDAC 1 39 VOUT4 CLR 2 PIN 1 38 SIGGND0 RESET 1 PIN 1 42VOUT5 RESET 3 INDICATOR 37 VOUT3 BIN/2SCOMP 2 INDICATOR 41VOUT4 BIN/2SCOMP 4 36 VOUT2 BUSY 3 40SIGGND0 GPIO 4 39VOUT3 MONB_GOUPSUIOYT 567 AADD55336601/ 333543 VVTEOOMUUPTT10_OUT MMOONN_O_INUNCT0 567 AADD55336601/ 333678VVVOOOUUUTTT012 MON_IN0 8 (NToOt Pto V SIEcaWle) 32 MON_IN1 NNCC 89 (NToOt Pto V SIEcaWle) 3354TMEOMNP__INO1UT NC 9 31 VREF0 NC10 33VREF0 NC 10 30 NC NC11 32NC VDD 11 29 VSS VDD12 31NC VREVFSS1 1132 2287 VNDCD VREVFSS11134 2390VVSDSD NC = NO CONNECT 14 15 16 17 18 19 20 21 22 23 24 25 26 5161718191021222324252627282 NC = NO CONNECT NCVOUT8VOUT9VOUT10VOUT11SIGGND1VOUT12VOUT13VOUT14VOUT15NCNCNC 05761-022 CNCN8TUOV9TUOV01TUOV11TUOV1DNGGIS21TUOV31TUOV41TUOV51TUOVCNCNCN 05761-028 Figure 7. 52-Lead LQFP Pin Configuration Figure 8. 56-Lead LFCSP Pin Configuration Table 5. LQFP Pin Function Descriptions Pin No. LQFP LFCSP Mnemonic Description 1 55 LDAC Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more information. 2 56 CLR Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for more information. 3 1 RESET Digital Reset Input. 4 2 BIN/2SCOMP Data Format Digital Input. Connecting this pin to DGND selects offset binary. Connecting this pin to logic 1 selects twos complement. This input has a weak pull-down. 5 3 BUSY Digital Input/Open-Drain Output. BUSY is open drain when it is an output. See the BUSY and LDAC Functions section for more information. 6 4 GPIO Digital I/O Pin. This pin can be configured as an input or output that can be read or programmed high or low via the serial interface. When configured as an input, it has a weak pull-down. 7 5 MON_OUT Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the MON_IN1 input can be switched to this output. 8, 32 6, 34 MON_IN0, MON_IN1 Analog Multiplexer Inputs. Can be switched to MON_OUT. 9, 10, 14, 24, 25, 7 to 11, 15, 16, NC No Connect. 26, 27, 30 26 to 28, 31, 32 11, 28 12, 29 V Positive Analog Power Supply; +9 V to +16.5 V for specified performance. DD These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 12, 29 13, 30 V Negative Analog Power Supply; −16.5 V to −8 V for specified performance. SS These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. 13 14 VREF1 Reference Input for DAC 8 to DAC 15. This voltage is referred to AGND. 19 21 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage. 31 33 VREF0 Reference Input for DAC 0 to DAC 7. This voltage is referred to AGND. 33 35 TEMP_OUT Provides an output voltage proportional to chip temperature. This is typically 1.46 V at 25°C with an output variation of 4.4 mV/°C. 34 to 37, 39 to 36 to 39, 41 to VOUT0 to VOUT15 DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each 42, 15 to 18, 20 44, 17 to 20, 22 analog output is capable of driving an output load of 10 kΩ to ground. to 23 to 25 Typical output impedance of these amplifiers is 0.5 Ω. Rev. A | Page 10 of 28

AD5360/AD5361 Pin No. LQFP LFCSP Mnemonic Description 38 40 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage. 43, 51 45, 53 DGND Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane. 44, 50 46, 52 DV Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 CC μF ceramic capacitors and 10 μF capacitors. 45 47 SYNC Active Low or SYNC Input for SPI Interface. This is the frame synchronization signal for the SPI serial interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 46 48 SCLK Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 47 49 SDI Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 48 50 PEC Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up that goes low if the packet error check fails. 49 51 SDO Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial Interface section for more details. 52 54 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane. EP Connect to V Exposed Paddle. SS Rev. A | Page 11 of 28

AD5360/AD5361 TYPICAL PERFORMANCE CHARACTERISTICS 2 0.0050 TA = 25°C VSS = –15V VDD = +15V VREF = +4.096V 1 0.0025 V) B) E ( S D INL (L 0 MPLITU 0 A –1 –0.0025 –2 –0.0050 0 16384 DA3C27C6O8DE 49152 65535 05761-012 0 1 2TIME(µs)3 4 5 05761-015 Figure 9. Typical AD5360 INL Plot Figure 12. Digital Crosstalk 1.0 1.0 VDD = +15V VSS = –15V DVCC = +5V VREF = +3V 0.5 0.5 B) LS B) ERROR ( 0 DNL (LS 0 L N I –0.5 –0.5 –1.0 –1.00 20 TEMPER40ATURE (°C) 60 80 05761-013 0 16384 DA3C2 7C6O8DE 49152 65535 05761-016 Figure 10. Typical INL Error vs. Temperature Figure 13. Typical AD5360 DNL Plot 0 600 TA = 25°C VSS = –15V VDD = +15V 500 VREF = +4.096V Hz) √ 400 DE (V) SE (nV/ PLITU–0.01 T NOI 300 M U A TP 200 U O 100 –0.020 2 4TIME(µs) 6 8 10 05761-014 00 1 FR2EQUENCY (H3z) 4 5 05761-017 Figure 11. Analog Crosstalk Due to LDAC Figure 14. Noise Spectral Density Rev. A | Page 12 of 28

AD5360/AD5361 0.50 6 VVDSDS == +–1122VV TDAV C=C 2 =5° 5CV VREF = +3V 5 0.45 DVCC = +5.5V NITS 4 0.40 U A) F I (mCC0.35 DVCC = +3.6V MBER O 3 DVCC = +2.5V NU 2 0.30 1 0.25–40 –20 0TEMPER2A0TURE (°4C0) 60 80 05761-018 00.48 0.50 0.52 ICC (mA)0.54 0.56 0.58 05761-021 Figure 15. ICC vs. Temperature Figure 18. Typical ICC Distribution 8.0 2.0 1.9 1.8 7.5 1.7 IDD mA) E (V) 1.6 (S 7.0 AG 1.5 /IDDS ISS OLT 1.4 I V 1.3 6.5 1.2 6.0 VVVSDRSDEF == = –+ 1+1232VVV 11..01 05761-027 –40 –20 0TEMPER2A0TURE (°4C0) 60 80 05761-019 –40 –25 –10 TE5MPER2A0TURE3 5(°C) 50 65 80 Figure 16. IDD/ISS vs. Temperature Figure 19. TEMP_OUT Voltage vs. Temperature 1.0 14 VDD = 15V FULL-SCALE VSS = 15V TA = 25°C 12 0.5 MIDSCALE F UNITS108 N_OUT (V) ZERO-SCALE O O 0 R M MBE 6 Tx – U U N O 4 V –0.5 2 0 7.00 7.25 IDD7 .(5m0A) 7.75 8.00 05761-020 –1.0–1.0 –0.5MON_OUT CU0RRENT (mA)0.5 1.0 05761-026 Figure 17. Typical IDD Distribution Figure 20. (VOUTx − MON_OUT Voltage) vs. MON_OUT Current Rev. A | Page 13 of 28

AD5360/AD5361 TERMINOLOGY Output Voltage Settling Time Integral Nonlinearity (INL) The amount of time it takes for the output of a DAC to settle to Integral nonlinearity, or relative accuracy, is a measure of the a specified level for a full-scale input change. maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after Digital-to-Analog Glitch Energy adjusting for zero-scale error and full-scale error and is This is the amount of energy injected into the analog output at expressed in least significant bits (LSB). the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between Differential Nonlinearity (DNL) 0x7FFF and 0x8000 (AD5360) or 0x1FFF and 0x2000 (AD5361). Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent Channel-to-Channel Isolation codes. A specified differential nonlinearity of 1 LSB maximum Channel-to-channel isolation refers to the proportion of input ensures monotonicity. signal from the reference input of one DAC that appears at the output of another DAC operating from another reference. It is Zero-Scale Error expressed in decibels and measured at midscale. Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the Zero-scale error is a measure of the difference between VOUT output of one converter due to both the digital change and (actual) and VOUT (ideal), expressed in millivolts, when the subsequent analog output change at another converter. It is channel is at its minimum value. Zero-scale error is mainly due specified in nV-s. to offsets in the output amplifier. Digital Crosstalk Full-Scale Error Digital crosstalk is defined as the glitch impulse transferred to Full-scale error is the error in DAC output voltage when all 1s the output of one converter due to a change in the DAC register are loaded into the DAC register. code of another converter and is specified in nV-s. Full-scale error is a measure of the difference between VOUT Digital Feedthrough (actual) and VOUT (ideal), expressed in millivolts, when When the device is not selected, high frequency logic activity the channel is at its maximum value. It does not include zero- on the device’s digital inputs can be capacitively coupled both scale error. across and through the device to show up as noise on the Gain Error VOUTx pins. It can also be coupled along the supply and Gain error is the difference between full-scale error and zero- ground lines. This noise is digital feedthrough. scale error. It is expressed in millivolts. Output Noise Spectral Density Gain Error = Full-Scale Error − Zero-Scale Error Output noise spectral density is a measure of internally VOUT Temperature Coefficient generated random noise. Random noise is characterized as a This includes output error contributions from linearity, offset, spectral density (voltage per √Hz). It is measured by loading all and gain drift. DACs to midscale and measuring noise at the output. It is measured in nV/√Hz. DC Output Impedance DC output impedance is the effective output source resistance. It is dominated by package lead resistance. DC Crosstalk The DAC outputs are buffered by op amps that share common V and V power supplies. If the dc load current changes in DD SS one channel (due to an update), this can result in a further dc change in one or more channel outputs. This effect is more significant at high load currents and reduces as the load currents are reduced. With high impedance loads, the effect is virtually immeasurable. Multiple V and V terminals are DD SS provided to minimize dc crosstalk. Rev. A | Page 14 of 28

AD5360/AD5361 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE CHANNEL GROUPS The AD5360/AD5361 contain 16 DAC channels and 16 output The 16 DAC channels of the AD5360/AD5361 are arranged into amplifiers in a single package. The architecture of a single DAC two groups of eight channels. The eight DACs of Group 0 derive channel consists of a 16-bit resistor-string DAC in the case of their reference voltage from VREF0. Group 1 derives its refer- the AD5360 and a 14-bit DAC in the case of the AD5361, ence voltage from VREF1. Each group has its own signal followed by an output buffer amplifier. The resistor-string ground pin. section is simply a string of resistors, of equal value, from VREF0 or VREF1 to AGND. This type of architecture guarantees DAC monotonicity. The 16-/14-bit binary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. The output amplifier multiplies the DAC output voltage by 4. The nominal output span is 12 V with a 3 V reference and 20 V with a 5 V reference. Table 6. AD5360/AD5361 Registers Register Name Word Length in Bits Description X1A (group) (channel) 16 (14) Input Data Register A, one for each DAC channel. X1B (group) (channel) 16 (14) Input Data Register B, one for each DAC channel. M (group) (channel) 16 (14) Gain trim register, one for each DAC channel. C (group) (channel) 16 (14) Offset trim register, one for each DAC channel. X2A (group) (channel) 16 (14) Output Data Register A, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable or directly writable. X2B (group) (channel) 16 (14) Output Data Register B, one for each DAC channel. These registers store the final, calibrated DAC data after gain and offset trimming. They are not readable or directly writable. DAC (group) (channel) Data registers from which the DACs take their final input data. The DAC registers are updated from the X2A or X2B registers. They are not readable or directly writable. OFS0 14 Offset DAC 0 data register, sets offset for Group 0. OFS1 14 Offset DAC 1 data register, sets offset for Group 1. Control 5 Control register. Monitor 6 Monitor enable and configuration register. GPIO 2 GPIO configuration register. Table 7. AD5360/AD5361 Input Register Default Values Register Name AD5360 Default Value AD5361 Default Value X1A, X1B 0x8000 0x2000 M 0xFFFF 0x3FFF C 0x8000 0x2000 OFS0, OFS1 0x2000 0x2000 Control 0x00 0x00 A/B Select 0 and A/B Select 1 0x00 0x00 Rev. A | Page 15 of 28

AD5360/AD5361 A/B REGISTERS GAIN/OFFSET ADJUSTMENT Each DAC channel has seven data registers. The actual DAC All DACs in the AD5360/AD5361 can be updated simultane- data word can be written to either the X1A or X1B input ously by taking LDAC low, when each DAC register is updated register, depending on the setting of the A/B bit in the control from either its X2A or X2B register, depending on the setting of register. If the A/B bit is 0, data is written to the X1A register. If the A/B select registers. The DAC register is not readable or the A/B bit is 1, data is written to the X1B register. Note that directly writable by the user. this single bit is a global control and affects every DAC channel OFFSET DACs in the device. It is not possible to set up the device on a per- In addition to the gain and offset trim for each DAC, there are channel basis so that some writes are to the X1A register and two 14-bit offset DACs, one for Group 0, and one for Group 1. some writes are to the X1B register. These allow the output range of all DACs connected to them to X1A X2A be offset within a defined range. Thus, subject to the limitations REGISTER REGISTER MUX MUX REGDIASCTER DAC of headroom, it is possible to set the output range of Group 0 X1B X2B REGISTER REGISTER and/or Group 1 to be unipolar positive, unipolar negative, or bipolar (either symmetrical or asymmetrical) about 0 V. The M REGISTER DACs in the AD5360/AD5361 are factory trimmed with the REGICSTER 05761-023 oanffdse gt aDinA pCesr fsoert mata tnhceei rf odre ftahuel td vefaaluuelts .o Tuthpisu tg rivaensg teh aen bde sstp oanff.s e t Figure 21. Data Registers Associated with Each DAC Channel When the output range is adjusted by changing the value of Each DAC channel also has a gain register (M) and an offset (C) the offset DAC, an extra offset is introduced due to the gain register, which allow trimming out of the gain and offset errors error of the offset DAC. The amount of offset is dependent on of the entire signal chain. Data from the X1A register is oper- the magnitude of the reference and how much the offset DAC ated on by a digital multiplier and adder by the contents of the moves from its default value. This offset is shown in Table 1. The M and C registers. The calibrated DAC data is then stored in the worst-case offset occurs when the offset DAC is at positive full X2A register. Similarly, data from the X1B register is operated scale or negative full scale. This value can be added to the offset on by the multiplier and adder and stored in the X2B register. present in the main DAC of a channel to give an indication of the overall offset for that channel. In most cases, the offset can be Although a multiplier and adder symbol are shown for each removed by programming the C register of the channel with an channel, there is only one multiplier and one adder in the appropriate value. The extra offset caused by the offset DACs device, which are shared among all channels. This has needs to be taken into account only when the offset DAC is implications for the update speed when several channels are changed from its default value. Figure 22 shows the allowable updated at once, as described in the Register Update Rates code range that can be loaded to the offset DAC, and this is section. dependent on the reference value used. Thus, for a 5 V Each time data is written to the X1A register, or to the M or reference, the offset DAC should not be programmed with C register with the A/B control bit set to 0, the X2A data is a value greater than 8192 (0x2000). recalculated and the X2A register is automatically updated. 5 Similarly, X2B is updated each time data is written to X1B, or RESERVED to M or C with A/B set to 1. The X2A and X2B registers are 4 not readable or directly writable by the user. Data output from the X2A and X2B registers is routed to the 3 final DAC register by a multiplexer. An 8-bit A/B select register )V associated with each group of eight DACs controls whether EF( R each individual DAC takes its data from the X2A or X2B V 2 register. If a bit in this register is 0, the DAC takes its data from the X2A register; if 1, the DAC takes its data from the 1 X2B register (Bit 0 through Bit 7 control DAC 0 through DAC 7, respectively). Ntoo steet tuhpa,t obne caa upseer -tchhearne naerle b1a6s ibsi,t ws ihne tthweor reeagcihst DerAs,C it tiask peos sistsib le 00 4096 OFFSET8 1D9A2C CODE 12288 16383 05761-005 Figure 22. Offset DAC Code Range data from the X2A register or X2B register. A global command is also provided that sets all bits in the A/B select registers to 0 or to 1. Rev. A | Page 16 of 28

AD5360/AD5361 OUTPUT AMPLIFIER OFFSET_CODE is the code loaded to the offset DAC. It is multiplied by 4 in the transfer function because this DAC is a Because the output amplifiers can swing to 1.4 V below the 14-bit device. On power-up, the default code loaded to the positive supply and 1.4 V above the negative supply, this limits offset DAC is 8192 (0x2000). With a 10 V reference, this gives how much the output can be offset for a given reference voltage. a span of −10 V to +10 V. For example, it is not possible to have a unipolar output range of 20 V because the maximum supply voltage is ±16.5 V. AD5361 Transfer Function DAC S1 The input code is the value in the X1A or X1B register that is CHANNEL OUTPUT applied to DAC (X1A, X1B default code = 8192) R6 R5 S2 10kΩ DAC_CODE = INPUT_CODE × (M + 1)/214 + C − 213 60kΩ CLR CLR DAC output voltage R1 20kΩ CLR S3 V = 4 × V × (DAC_CODE − OFFSET_CODE)/214 + OUT REF 60Rk4Ω 20Rk3Ω R202kΩ SIGGND VSIGGND where: SIGGND DAC_CODE should be within the range of 0 to 16,383. OFDFASCET 05761-006 VVREF == 35..00 VV,, ffoorr aa 1220 VV ssppaann.. REF Figure 23. Output Amplifier and Offset DAC M = code in gain register − default code = 214 − 1. Figure 23 shows details of a DAC output amplifier and its C = code in offset register − default code = 213. connections to the offset DAC. On power-up, S1 is open, OFFSET_CODE is the code loaded to the offset DAC. disconnecting the amplifier from the output. S3 is closed, so On power-up, the default code loaded to the offset DAC the output is pulled to SIGGND. S2 is also closed to prevent is 8192 (0x2000). With a 5 V reference, this gives a span of the output amplifier from being open-loop. If CLR is low at −10 V to +10 V. power-up, the output remains in this condition until CLR is REFERENCE SELECTION taken high. The DAC registers can be programmed, and the outputs assume the programmed values when CLR is taken The AD5360/AD5361 have two reference input pins. The high. Even if CLR is high at power-up, the output remains voltage applied to the reference pins determines the output in this condition until V > 6 V and V < −4 V and the voltage span on VOUT0 to VOUT15. VREF0 determines the DD SS initialization sequence has finished. The outputs then go to voltage span for VOUT0 to VOUT7 (Group 0), and VREF1 their power-on default values. determines the voltage span for VOUT8 to VOUT15 (Group 1). The reference voltage applied to each VREF pin can be different, TRANSFER FUNCTION if required, allowing each group of eight channels to have a The output voltage of a DAC in the AD5360/AD5361 is dependent different voltage span. The output voltage range and span can on the value in the input register, the value of the M and C be adjusted by programming the offset register and gain register registers, and the value in the offset DAC. The transfer functions for each channel as well as programming the offset DAC. If the for the AD5360/AD5361 are shown in the following sections. offset and gain features are not used (that is, the M and C AD5360 Transfer Function registers are left at their default values), the required reference levels can be calculated as follows: The input code is the value in the X1A or X1B register that is applied to DAC (X1A, X1B default code = 32,768) VREF = (VOUTMAX − VOUTMIN)/4 DAC_CODE = INPUT_CODE × (M + 1)/216 + C − 215 If the offset and gain features of the AD5360/AD5361 are used, the required output range is slightly different. The chosen DAC output voltage output range should take into account the system offset and VOUT = 4 × VREF × (DAC_CODE − (OFFSET_CODE × 4))/ gain errors that need to be trimmed out. Therefore, the chosen 216 + VSIGGND output range should be larger than the actual, required range. where: The required reference levels can be calculated as follows: DAC_CODE should be within the range of 0 to 65,535. 1. Identify the nominal output range on VOUT. V = 3.0 V, for a 12 V span. REF 2. Identify the maximum offset span and the maximum gain V = 5.0 V, for a 20 V span. REF required on the full output signal range. M = code in gain register − default code = 216 – 1. 3. Calculate the new maximum output range on VOUT, C = code in offset register − default code = 215. including the expected maximum offset and gain errors. Rev. A | Page 17 of 28

AD5360/AD5361 4. Choose the new required VOUT and VOUT , keeping Full-scale error can be reduced as follows: MAX MIN the VOUT limits centered on the nominal values. Note that 1. Measure the zero-scale error. V and V must provide sufficient headroom. DD SS 2. Set the output to the highest possible value. 5. Calculate the value of VREF as follows: 3. Measure the actual output voltage and compare it with the VREF = (VOUT − VOUT )/4 MAX MIN required value. Add this error to the zero-scale error. This Reference Selection Example is the span error, which includes full-scale error. Nominal output range = 20 V (−10 V to +10 V) 4. Calculate the number of LSBs equivalent to the span error Offset error = ±100 mV and subtract it from the default value of the M register. Gain error = ±3% Note that only positive full-scale error can be reduced. SIGGND = AGND = 0 V The M and C registers should not be programmed until both Gain error = ±3% zero-scale errors and full-scale errors have been calculated. Maximum positive gain error = +3% AD5360 Calibration Example Output range including gain error = 20 + 0.03 (20) = This example assumes that a −10 V to +10 V output is required. 20.6 V The DAC output is set to −10 V but is measured at −10.03 V. Offset error = ±100 mV This gives a zero-scale error of −30 mV. Maximum offset error span = 2 (100 mV) = 0.2 V 1 LSB = 20 V/65,536 = 305.176 μV Output range including gain error and offset error = 20.6 V + 0.2 V = 20.8 V 30 mV = 98 LSBs VREF calculation The full-scale error can now be removed. The output is set to +10 V, and a value of +10.02 V is measured. The full-scale Actual output range = 20.6 V, that is, −10.3 V to +10.3 V error is +20 mV. The span error is +20 mV − (−30 mV) = (centered); +50 mV. VREF = (10.3 V + 10.3 V)/4 = 5.15 V +50 mV = 164 LSBs If the solution yields an inconvenient reference level, the user The errors can now be removed. can adopt one of the following approaches: 1. 98 LSBs should be added to the default C register value; • Use a resistor divider to divide down a convenient, higher (32,768 + 98) = 32,866. reference level to the required level. 2. 32,866 should be programmed to the C register. • Select a convenient reference level above VREF and modify 3. 164 LSBs should be subtracted from the default M register the gain and offset registers to digitally downsize the value; (65,535 − 164) = 65,371. reference. In this way, the user can use almost any conven- 4. 65,371 should be programmed to the M register. ient reference level but may reduce the performance by overcompaction of the transfer function. Additional Calibration • Use a combination of these two approaches. The techniques described in the previous section are usually enough to reduce the zero-scale errors and full-scale errors in CALIBRATION most applications. However, there are limitations whereby the The user can perform a system calibration on the AD5360 and errors may not be sufficiently removed. For example, the offset AD5361 to reduce gain and offset errors to below 1 LSB. This is (C) register can only be used to reduce the offset caused by the achieved by calculating new values for the M and C registers and negative zero-scale error. A positive offset cannot be reduced. reprogramming them. Likewise, if the maximum voltage is below the ideal value, that Reducing Zero-Scale and Full-Scale Error is, a negative full-scale error, the gain (M) register cannot be used to increase the gain to compensate for the error. Zero-scale error can be reduced as follows: 1. Set the output to the lowest possible value. These limitations can be overcome by increasing the refer- 2. Measure the actual output voltage and compare it with the ence value. With a 2.5 V reference, a 10 V span is achieved. required value. This gives the zero-scale error. The ideal voltage range, for the AD5360 or AD5361, is 3. Calculate the number of LSBs equivalent to the error and −5 V to +5 V. Using a 2.6 V reference increases the range add this from the default value of the C register. Note that to −5.2 V to +5.2 V. Clearly, in this case, the offset and gain only negative zero-scale error can be reduced. errors are insignificant and the M and C registers can be used to raise the negative voltage to −5 V and then reduce the maximum voltage down to +5 V to give the most accurate values possible. Rev. A | Page 18 of 28

AD5360/AD5361 RESET FUNCTION high. Whenever the A/B select registers are written to, BUSY also goes low, for approximately 600 ns. The reset function is initiated by the RESET pin. On the rising edge of RESET, the AD5360/AD5361 state machine initiates a The AD5360/AD5361 have flexible addressing that allows reset sequence to reset the X, M, and C registers to their default writing of data to a single channel, all channels in a group, the values. This sequence typically takes 300 μs, and the user should same channel in Group 0 and Group 1, or all channels in the not write to the part during this time. On power-up, it is recom- device. This means that 1, 2, 8, or 16 DAC register values may mended that the user bring RESET high as soon as possible to need to be calculated and updated. Because there is only one properly initialize the registers. multiplier shared among 16 channels, this task must be done sequentially, so the length of the BUSY pulse varies according to When the reset sequence is complete (and provided that CLR is the number of channels being updated. high), the DAC output is at a potential specified by the default register settings, which are equivalent to SIGGNDx. The DAC Table 8. BUSY Pulse Widths outputs remain at SIGGNDx until the X, M, or C register is Action BUSY Pulse Width1 updated and LDAC is taken low. The AD5360/AD5361 can be Loading Input, C, or M to 1 Channel2 1.5 μs maximum returned to the default state by pulsing RESET low for at least Loading Input, C, or M to 2 Channels 2.1 μs maximum 30 ns. Note that, because the reset function is rising edge trig- Loading Input, C, or M to 8 Channels 5.7 μs maximum gered, bringing RESET low has no effect on the operation of Loading Input, C, or M to 16 Channels 10.5 μs maximum the AD5360/AD5361. 1 BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns. CLEAR FUNCTION 2 A single channel update is typically 1 μs. CLR is an active low input that should be high for normal The AD5360/AD5361 contain an extra feature whereby a DAC operation. The CLR pin has an internal 500 kΩ pull-down register is not updated unless its X2A or X2B register has been resistor. When CLR is low, the input to each of the DAC output written to since the last time LDAC was brought low. Normally, buffer stages (VOUT0 to VOUT15) is switched to the externally when LDAC is brought low, the DAC registers are filled with set potential on the relevant SIGGNDx pin. While CLR is low, the contents of the X2A or X2B registers, depending on the all LDAC pulses are ignored. When CLR is taken high again, the setting of the A/B select register. However, the AD5360/ DAC outputs return to their previous values. The contents of AD5361 update the DAC register only if the X2A or X2B data has input registers and DAC Register 0 to DAC Register 15 are not changed, thereby removing unnecessary digital crosstalk. affected by taking CLR low. To prevent glitches appearing on BIN/2SCOMP PIN the outputs, CLR should be brought low whenever the output span is adjusted by writing to the offset DAC. The BIN/2SCOMP pin determines if the output data is presented BUSY AND LDAC FUNCTIONS as offset binary or twos complement. If this pin is low, the data is straight binary. If it is high, the data is twos complement. This The value of an X2 (A or B) register is calculated each time the affects only the X, C, and offset DAC registers; the M register user writes new data to the corresponding X1, C, or M register. and the control and command data are interpreted as straight During the calculation of X2, the BUSY output goes low. While binary. BUSY is low, the user can continue writing new data to the X1, TEMPERATURE SENSOR M, or C register (see the Register Update Rates section for more details), but no DAC output updates can take place. The on-chip temperature sensor provides a voltage output at the TEMP_OUT pin that is linearly proportional to the The BUSY pin is bidirectional and has a 50 kΩ internal pull-up Centigrade temperature scale. The typical accuracy of the resistor. When multiple AD5360 or AD5361 devices may be temperature sensor is ±1°C at +25°C and ±5°C over the −40°C used in one system, the BUSY pins can be tied together. This is to +85°C range. Its nominal output voltage is 1.46 V at +25°C, useful when it is required that no DAC in any device be updated varying at 4.4 mV/°C. Its low output impedance, low self- until all other DACs are ready. When each device has finished heating, and linear output simplify interfacing to temperature updating the X2 (A or B) register, it releases the BUSY pin. If control circuitry and analog-to-digital converters. another device has not finished updating its X2 registers, it holds BUSY low, thus delaying the effect of LDAC going low. The DAC outputs are updated by taking the LDAC input low. If LDAC goes low while BUSY is active, the LDAC event is stored and the DAC outputs update immediately after BUSY goes high. A user can also hold the LDAC input permanently low. In this case, the DAC outputs update immediately after BUSY goes Rev. A | Page 19 of 28

AD5360/AD5361 MONITOR FUNCTION POWER-DOWN MODE The AD5360/AD5361 contain a channel monitor function The AD5360/AD5361 can be powered down by setting Bit 0 in that consists of an analog multiplexer addressed via the serial the control register to 1. This turns off the DACs, thus reducing interface, allowing any channel output to be routed to this pin the current consumption. The DAC outputs are connected to for monitoring using an external ADC. In addition, two monitor their respective SIGGND potentials. The power-down mode inputs, MON_IN0 and MON_IN1, are provided, which can also does not change the contents of the registers, and the DACs be routed to MON_OUT. The monitor function is controlled by return to their previous voltage when the power-down bit is the monitor register, which allows the monitor output to be cleared to 0. enabled or disabled, and selection of a DAC channel or one of THERMAL MONITORING FUNCTION the monitor pins. When disabled, the monitor output is high The AD5360/AD5361 can be programmed to power down the impedance, so several monitor outputs can be connected in DACs if the temperature on the die exceeds 130°C. Setting Bit 1 parallel and only one enabled at a time. Table 9 shows the in the control register to 1 (see Table 15) enables this function. control register settings relevant to the monitor function. If the die temperature exceeds 130°C, the AD5360/AD5361 Table 9. Control Register Monitor Functions enter a temperature power-down mode, which is equivalent to F5 F4 F3 F2 F1 F0 Function setting the power-down bit in the control register. To indicate 0 X X X X X MON_OUT disabled that the AD5360/AD5361 have entered temperature shutdown 1 X X X X X MON_OUT enabled mode, Bit 4 of the control register is set to 1. The AD5360/AD5361 1 0 0 0 0 0 MON_OUT = VOUT0 remain in temperature shutdown mode, even if the die tempera- 1 0 0 0 0 1 MON_OUT = VOUT1 ture falls, until Bit 1 in the control register is cleared to 0. 1 0 1 1 1 1 MON_OUT = VOUT15 TOGGLE MODE 1 1 0 0 0 0 MON_OUT = MON_IN0 The AD5360/AD5361 have two X2 registers per channel, X2A 1 1 0 0 0 1 MON_OUT = MON_IN1 and X2B, which can be used to switch the DAC output between The multiplexer is implemented as a series of analog switches. two levels with ease. This approach greatly reduces the overhead Because this could conceivably cause a large amount of current required by a microprocessor, which would otherwise have to to flow from the input of the multiplexer, that is, VOUTx or write to each channel individually. When the user writes to MON_INx to the output of the multiplexer, MON_OUT, care either the X1A, X2A, M, or C register, the calculation engine should taken to ensure that whatever is connected to the takes a certain amount of time to calculate the appropriate X2A MON_OUT pin is of high enough impedance to prevent the or X2B values. If the application only requires that the DAC continuous current limit specification from being exceeded. output switch between two levels, such as a data generator, any Because the MON_OUT pin is not buffered, the amount of method that reduces the amount of calculation time encoun- current drawn from this pin creates a voltage drop across the tered is advantageous. For the data generator example, the user switches, which in turn leads to an error in the voltage being should set the high and low levels for each channel once, by monitored. Where accuracy is important, it is recommended writing to the X1A and X1B registers. The values of X2A and that the MON_OUT pin be buffered. Figure 20 shows the X2B are calculated and stored in their respective registers. The typical error due to the MON_OUT current calculation delay, therefore, only happens during the setup GPIO PIN phase, that is, when programming the initial values. To toggle a The AD5360/AD5361 have a general-purpose I/O pin, GPIO. DAC output between the two levels, it is only required to write This can be configured as an input or an output and read back to the relevant A/B select register to set the MUX 2 register bit. or programmed (when configured as an output) via the serial Furthermore, because there are eight MUX 2 control bits per interface. Typical applications for this pin include monitoring register, it is possible to update eight channels with a single the status of a logic signal, monitoring a limit switch, or write. Table 17 shows the bits that correspond to each DAC controlling an external multiplexer. The GPIO pin is configured output. by writing to the GPIO register, which has the special function code of 001101 (see Table 14 and Table 15 ). When Bit F1 is set, the GPIO pin becomes an output and F0 determines whether the pin is high or low. The GPIO pin can be set as an input by writing 0 to both F1 and F0. The status of the GPIO pin can be determined by initiating a read operation using the appropriate bits in Table 16. The status of the pin is indicated by the LSB of the register read. Rev. A | Page 20 of 28

AD5360/AD5361 SERIAL INTERFACE The AD5360/AD5361 contain a high speed SPI operating at The serial interface works with both a continuous and a burst clock frequencies up to 50 MHz (20 MHz for read operations). (gated) serial clock. Serial data applied to SDI is clocked into To minimize both the power consumption of the device and the AD5360/AD5361 by clock pulses applied to SCLK. The first on-chip digital noise, the interface powers up fully only when falling edge of SYNC starts the write cycle. At least 24 falling the device is being written to, that is, on the falling edge of clock edges must be applied to SCLK to clock in 24 bits of data, SYNC. The serial interface is 2.5 V LVTTL-compatible when before SYNC is taken high again. If SYNC is taken high before operating from a 2.5 V to 3.6 V DVCC supply. It is controlled by the 24th falling clock edge, the write operation is aborted. four pins: SYNC (frame synchronization input), SDI (serial data If a continuous clock is used, SYNC must be taken high before input), SCLK (clocking of data in and out of the device), and the 25th falling clock edge. This inhibits the clock within the SDO (serial data output for data readback). AD5360/AD5361. If more than 24 falling clock edges are SPI WRITE MODE applied before SYNC is taken high again, the input data is The AD5360/AD5361 allow writing of data via the serial inter- corrupted. If an externally gated clock of exactly 24 pulses is face to every register directly accessible to the serial interface, used, SYNC may be taken high any time after the 24th falling which are all registers except the X2A, X2B, and DAC registers. clock edge. The X2A and X2B registers are updated when writing to the The input register addressed is updated on the rising edge of X1A, X1B, M, and C registers, and the DAC registers are SYNC. For another serial transfer to take place, SYNC must be updated by LDAC. The serial word (see Table 10 or Table 11) taken low again. is 24 bits long; 16 or 14 of these bits are data bits, six bits are address bits, and two bits are mode bits that determine what is done with the data. Two bits are reserved on the AD5361. Table 10. AD5360 Serial Word Bit Assignation I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 11. AD5361 Serial Word Bit Assignation I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I11 I01 M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 I1 and I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0. Rev. A | Page 21 of 28

AD5360/AD5361 SPI READBACK MODE PACKET ERROR CHECKING To verify that data has been received correctly in noisy environ- The AD5360/AD5361 allow data readback via the serial inter- ments, the AD5360/AD5361 offer the option of error checking face from every register directly accessible to the serial interface, based on an 8-bit (CRC-8) cyclic redundancy check. The device which is all registers except the X2A, X2B, and DAC data controlling the AD5360/AD5361 should generate an 8-bit registers. To read back a register, it is first necessary to tell the checksum using the polynomial C(x) = x8 + x2 + x1 +1. The AD5360/AD5361 which register is to be read. This is achieved checksum is added to the end of the data word, and 32 data bits by writing a word whose first two bits are the Special Function are sent to the AD5360/AD5361 before taking SYNC high. If Code 00 to the device. The remaining bits then determine if the operation is a readback and which register is to be read back, or the AD5360/AD5361 see a 32-bit data frame, they perform the if it is a write to of the special function registers, such as the error check when SYNC goes high. If the checksum is valid, the control register. data is written to the selected register. If the checksum is invalid, the data is ignored, the packet error check output (PEC) goes If a readback command is written to a special function register, low, and Bit 3 of the control register is set. After reading the data from the selected register is clocked out of the SDO pin control register, the error flag is cleared automatically and PEC during the next SPI operation. The SDO pin is normally three- goes high again. stated but becomes driven as soon as a read command is issued. The pin remains driven until the register’s data is clocked out. UPDATE ON SYNC HIGH See Figure 5 for the read timing diagram. Note that, due to the SYNC timing requirements of t (25 ns), the maximum speed of the 22 SPI interface during a read operation should not exceed 20 MHz. SCLK REGISTER UPDATE RATES MSB LSB D23 D0 The value of the X2A or X2B register is calculated each time the SDI 24-BIT DATA user writes new data to the corresponding X1, C, or M register. The calculation is performed by a three-stage process. The first 24-BIT DATA TRANSFER—NO ERROR CHECKING two stages take approximately 600 ns each, and the third stage takes approximately 300 ns. When the write to a X1, C, or M UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC register is complete, the calculation process begins. If the write operation involves the update of a single DAC channel, the user is free to write to another register provided that the write SCLK operation does not finish until the first stage calculation is MSB LSB D31 D8 D7 D0 complete, that is, 600 ns after the completion of the first write SDI 24-BIT DATA 8-BIT CHECKSUM operation. If a group of channels is being updated by a single write operation, the first stage calculation is repeated for each PEC GOES LOW IF cnhoat ncnoeml,p tlaektein tgh e6 0n0e xnts w preirt ec hoapnenraetli.o Inn uthnitsi lc tahsies, ttihme eu hseasr eslhaopuseldd . PEC 24-BIT DATA TRANSFER WITH EERRRROORR CCHHEECCKKI NFGAILS 05761-029 Figure 24. SPI Write with and Without Error Checking Rev. A | Page 22 of 28

AD5360/AD5361 CHANNEL ADDRESSING AND SPECIAL MODES device. Table 13 shows all these address modes. It shows which group(s) and which channel(s) is/are addressed for every If the mode bits are not 00, then the data word D15 to D0 combination of Address Bit A4 to Address Bit A0. (AD5360) or D13 to D0 (AD5361) is written to the device. Address Bit A4 to Address Bit A0 determine which channel or Table 12. Mode Bits channels is/are written to, while the mode bits determine to M1 M0 Action which register (X1A, X1B, C, or M) the data is written, as 1 1 Write DAC data (X) register shown in Table 10 and Table 11. Data is to be written to the 1 0 Write DAC offset (C) register X1A when the A/B bit in the control register is 0 or to the X1B 0 1 Write DAC gain (M) register register when the bit is 1. 0 0 Special function, used in combination with other The AD5360/AD5361 have very flexible addressing that allows bits of a word writing of data to a single channel, all channels in a group, the same channel in Group 0 and Group 1 or all channels in the Table 13. Group and Channel Addressing Address Bit A4 to Address Bit A3 Address Bit A2 to Address Bit A0 00 01 10 11 000 All groups, all channels Group 0, Channel 0 Group 1, Channel 0 Unused 001 Group 0, all channels Group 0, Channel 1 Group 1, Channel 1 Unused 010 Group 1, all channels Group 0, Channel 2 Group 1, Channel 2 Unused 011 Unused Group 0, Channel 3 Group 1, Channel 3 Unused 100 Unused Group 0, Channel 4 Group 1, Channel 4 Unused 101 Unused Group 0, Channel 5 Group 1, Channel 5 Unused 110 Unused Group 0, Channel 6 Group 1, Channel 6 Unused 111 Unused Group 0, Channel 7 Group 1, Channel 7 Unused Rev. A | Page 23 of 28

AD5360/AD5361 SPECIAL FUNCTION MODE data required for execution of the special function, for example If the mode bits are 00, then the special function mode is the channel address for data readback. selected, as shown in Table 14. Bits I21 to I16 of the serial data word select the special function, while the remaining bits are The codes for the special functions in Table 16 show the addresses for data readback. Table 14. Special Function Mode I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 Table 15. Special Function Codes Special Function Code S5 S4 S3 S2 S1 S0 Data (F15 to F0) Action 0 0 0 0 0 0 0000 0000 0000 0000 NOP. 0 0 0 0 0 1 XXXX XXXX XXXX X [F2:F0] Write control register. F4 = 1: temperature over 130°C. F4 = 0: temperature under 130°C. Read-only bit. This bit should be 0 when writing to the control register. F3 = 1: PEC error. F3 = 0: No PEC error. Reserved. Read-only bit. This bit should be 0 when writing to the control register. F2 = 1: select Register X1B for input. F2 = 0: select Register X1A for input. F1 = 1: enable temperature shutdown. F1 = 0: disable temperature shutdown. F0 = 1: soft power-down. F0 = 0: soft power-up. 0 0 0 0 1 0 XX [F13:F0] Write data in F13 to F0 to OFS0 register. 0 0 0 0 1 1 XX [F13:F0] Write data in F13 to F0 to OFS1 register. 0 0 0 1 0 0 Reserved 0 0 0 1 0 1 See Table 16 Select register for readback. 0 0 0 1 1 0 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 0. 0 0 0 1 1 1 XXXX XXXX [F7:F0] Write data in F7 to F0 to A/B Select Register 1. 0 0 1 0 0 0 Reserved 0 0 1 0 0 1 Reserved 0 0 1 0 1 0 Reserved 0 0 1 0 1 1 XXXX XXXX [F7:F0] Block write A/B select registers. F7 to F0 = 0: write all 0s (all channels use X2A register). F7 to F0 = 1: write all 1s (all channels use X2B register). 0 0 1 1 0 0 XXXX XXXX XX [F5:F0] F5 = 1: monitor enable. F5 = 0: monitor disable. F4 = 1: monitor input pin selected by F0. F4 = 0: monitor DAC channel selected by F3:F0 (0000 = DAC0; 1111 = DAC15). F3 = not used if F4 = 1. F2 = not used if F4 = 1. F1 = not used. F0 = 0: MON_IN0 selected for monitoring (if F4 and F5 = 1). F0 = 1: MON_IN1 selected for monitoring (if F4 and F5 = 1). 0 0 1 1 0 1 XXXX XXXX XXXX XX [F1:F0] GPIO configure and write. F1 = 1: GPIO is an output. Data to output is written to F0. F1 = 0: GPIO is an input. Data can be read from F0 on readback. Rev. A | Page 24 of 28

AD5360/AD5361 Table 16. Address Codes for Data Readback1 F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read 0 0 0 Bit F12 to Bit F7 select channel to be read back, X1A Register 0 0 1 Channel 0 = 001000 to Channel 15 = 010111 X1B Register 0 1 0 C Register 0 1 1 M Register 1 0 0 0 0 0 0 0 1 Control Register 1 0 0 0 0 0 0 1 0 OFS0 Data Register 1 0 0 0 0 0 0 1 1 OFS1 Data Register 1 0 0 0 0 0 1 0 0 Reserved 1 0 0 0 0 0 1 1 0 A/B Select Register 0 1 0 0 0 0 0 1 1 1 A/B Select Register 1 1 0 0 0 0 1 0 0 0 Reserved 1 0 0 0 0 1 0 0 1 Reserved 1 0 0 0 0 1 0 1 0 Reserved 1 0 0 0 0 1 0 1 1 GPIO Read (Data in F0)2 1 F6 to F0 are don’t cares for the data readback function. 2 F6 to F0 should be 0 for GPIO read. Table 17. DACs Selected by A/B Select Registers A/B Select Bits1 Register F7 F6 F5 F4 F3 F2 F1 F0 0 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0 1 DAC15 DAC14 DAC13 DAC12 DAC11 DAC10 DAC9 DAC8 1 If the bit is 0, Register X2A is selected. If the bit is 1, Register X2B is selected. POWER SUPPLY DECOUPLING supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the In any circuit where accuracy is important, careful considera- board and should never be run near the reference inputs. It is tion of the power supply and ground return layout helps to essential to minimize noise on all VREFx lines. ensure the rated performance. The printed circuit board on which the AD5360/AD5361 are mounted should be designed so Avoid crossover of digital and analog signals. Traces on that the analog and digital sections are separated and confined opposite sides of the board should run at right angles to each to certain areas of the board. If the AD5360/AD5361 are in a other. This reduces the effects of feedthrough through the system where multiple devices require an AGND-to-DGND board. A microstrip technique is by far the best, but this is not connection, the connection should be made at one point only. always possible with a double-sided board. In this technique, The star ground point should be established as close as possible the component side of the board is dedicated to the ground to the device. For supplies with multiple pins (V , V , DV ), plane, while signal traces are placed on the solder side. SS DD CC it is recommended to tie these pins together and to decouple As is the case for all thin packages, care must be taken to avoid each supply once. flexing the package and to avoid a point load on the surface of The AD5360/AD5361 should have ample supply decoupling of this package during the assembly process. 10 μF in parallel with 0.1 μF on each supply located as close to POWER SUPPLY SEQUENCING the package as possible, ideally right up against the device. The When the supplies are connected to the AD5360/AD5361, it is 10 μF capacitors are the tantalum bead type. The 0.1 μF capaci- important that the AGND and DGND pins be connected to the tor should have low effective series resistance (ESR) and effective relevant ground plane before the positive or negative supplies series inductance (ESI), such as the common ceramic types that are applied. In most applications, this is not an issue because the provide a low impedance path to ground at high frequencies, to ground pins for the power supplies are connected to the ground handle transient currents due to internal logic switching. pins of the AD5360/AD5361 via ground planes. Where the Digital lines running under the device should be avoided AD5360/AD5361 are used in a hot-swap card, care should be because these couple noise onto the device. The analog ground taken to ensure that the ground pins are connected to the plane should be allowed to run under the AD5360/AD5361 to supply grounds before the positive or negative supplies are avoid noise coupling. The power supply lines of the AD5360/ connected. This is required to prevent currents from flowing in AD5361 should use as large a trace as possible to provide low directions other than toward an analog or digital ground. impedance paths and reduce the effects of glitches on the power Rev. A | Page 25 of 28

AD5360/AD5361 INTERFACING EXAMPLES The Analog Devices ADSP-21065L is a floating-point DSP with The SPI interface of the AD5360 and AD5361 is designed to two serial ports (SPORTs). Figure 26 shows how one SPORT allow the parts to be easily connected to industry standard DSPs can be used to control the AD5360 or AD5361. In this example, and microcontrollers. Figure 25 shows how the AD5360/AD5361 the transmit frame synchronization (TFS) pin is connected can be connected to the Analog Devices, Inc., Blackfin® DSP. The to the receive frame synchronization (RFS) pin. Similarly, Blackfin has an integrated SPI port that can be connected directly the transmit and receive clocks (TCLK and RCLK) are also to the SPI pins of the AD5360 or AD5361, and programmable connected together. The user can write to the AD5360 or I/O pins that can be used to set or read the state of the digital AD5361 by writing to the transmit register. A read operation input or output pins associated with the interface. can be accomplished by first writing to the AD5360/AD5361 AD5360/ to tell the part that a read operation is required. A second write AD5361 SPISELx SYNC operation with a NOP instruction causes the data to be read SCK SCLK from the AD5360/AD5361. The DSPs receive interrupt can be MOSI SDI used to indicate when the read operation is complete. MISO SDO ADSP-21065L AD5360/ PF10 RESET TFSx AD5361 ADSP-BF531 PF9 LDAC RFSx SYNC TCLKx PF8 CLR RCLKx SCLK PF7 BUSY 05761-024 DDRTxxAA SSDDIO Figure 25. Interfacing to a Blackfin DSP FLAG0 RESET FLAG1 LDAC FFLLAAGG23 CBLURSY 05761-025 Figure 26. Interfacing to an ADSP-21065L DSP Rev. A | Page 26 of 28

AD5360/AD5361 OUTLINE DIMENSIONS 12.20 0.75 12.00 SQ 0.60 1.60 11.80 0.45 MAX 52 40 1 39 PIN 1 10.20 TOP VIEW 10.00 SQ (PINS DOWN) 9.80 1.45 0.20 1.40 0.09 1.35 7° 3.5° 13 27 0.15 0° 14 26 0.05 SPLEAANTEING 0C.O10PLANARITY VIEW A 0.65 0.38 BSC 0.32 LEAD PITCH 0.22 VIEW A ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BCC 051706-A Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP] (ST-52) Dimensions shown in millimeters 0.30 8.00 0.60 MAX 0.23 BSC SQ 0.60 MAX 0.18 PIN 1 INDICATOR 43 56 1 PIN 1 42 INDICATOR TOP 7.75 EXPOSED 6.25 VIEW BSC SQ PAD 6.10 SQ (BOTTOM VIEW) 5.95 0.50 0.40 29 0.30 28 15 14 0.25 MIN 6.50 1.00 12° MAX 0.80 MAX REF 0.85 0.65 TYP 0.80 0.05 MAX 0.02 NOM SEATING 0.50 BSC COPLANARITY PLANE 0.20 REF 0.08 COMPLIANTTO JEDEC STANDARDS MO-220-VLLD-2 112805-0 Figure 28. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 8 mm × 8 mm, Very Thin Quad (CP-56-1) Dimensions shown in millimeter ORDERING GUIDE Model Temperature Range Package Description Package Option AD5360BSTZ1 −40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52 AD5360BSTZ-REEL1 −40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52 AD5360BCPZ1 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1 AD5360BCPZ-REEL71 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1 AD5361BSTZ1 −40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52 AD5361BSTZ-REEL1 −40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52 AD5361BCPZ1 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1 AD5361BCPZ-REEL71 −40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1 EVAL-AD5360EBZ1 Evaluation Board EVAL-AD5361EBZ1 Evaluation Board 1 Z = RoHS Compliant Part. Rev. A | Page 27 of 28

AD5360/AD5361 NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05761-0-2/08(A) Rev. A | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5360BCPZ AD5360BCPZ-REEL7 AD5360BSTZ AD5361BCPZ AD5361BCPZ-REEL7 AD5361BSTZ EVAL- AD5360EBZ EVAL-AD5361EBZ