2.5 V to 5.5 V, 250 μA, 2-Wire Interface, Dual Voltage Output, 8-/10-/12-Bit DACs AD5337/AD5338/AD5339 FEATURES GENERAL DESCRIPTION AD5337 The AD5337/AD5338/AD5339 are dual 8-, 10-, and 12-bit 2 buffered 8-bit DACs in 8-lead MSOP buffered voltage output DACs, respectively. Each part is housed AD5338, AD5338-1 in an 8-lead MSOP package and operates from a single 2.5 V to 2 buffered 10-bit DACs in 8-lead MSOP 5.5 V supply, consuming 250 μA at 3 V. On-chip output amplifiers AD5339 allow rail-to-rail output swing with a slew rate of 0.7 V/μs. A 2- 2 buffered 12-bit DACs in 8-lead MSOP wire serial interface operates at clock rates up to 400 kHz. This Low power operation: 250 μA @ 3 V, 300 μA @ 5 V interface is SMBus compatible at V < 3.6 V. Multiple devices DD 2-wire (I2C-compatible) serial interface can be placed on the same bus. 2.5 V to 5.5 V power supply The references for the two DACs are derived from one reference Guaranteed monotonic by design over all codes pin. The outputs of all DACs can be updated simultaneously Power-down to 80 nA @ 3 V, 200 nA @ 5 V using the software LDAC function. The parts incorporate a 3 power-down modes power-on reset circuit to ensure that the DAC outputs power up Double-buffered input logic to 0 V and remain there until a valid write to the device takes Output range: 0 V to V REF place. A software clear function resets all input and DAC Power-on reset to 0 V registers to 0 V. A power-down feature reduces the current Simultaneous update of outputs (LDAC function) consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V). Software clear facility Data readback facility The low power consumption of these parts in normal operation On-chip rail-to-rail output buffer amplifiers makes them ideally suited to portable battery-operated equip- Temperature range: −40°C to +105°C ment. The power consumption is typically 1.5 mW at 5 V and 0.75 mW at 3 V, reducing to 1 μW in power-down mode. APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control FUNCTIONAL BLOCK DIAGRAM VDD REFIN LDAC SCL REINGPISUTTER REGDIASCTER SDTARCINAG BUFFER VOUTA INTERFACE SDA LOGIC REINGPISUTTER REGDIASCTER SDTARCINBG BUFFER VOUTB A0 POWER-DOWN LOGIC POWER-ON AD5337/AD5338/AD5339 RESET GND 03756-001 Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.

AD5337/AD5338/AD5339 TABLE OF CONTENTS Features..............................................................................................1 Output Amplifier........................................................................15 Applications.......................................................................................1 Power-on Reset...........................................................................15 General Description.........................................................................1 Serial Interface............................................................................16 Functional Block Diagram..............................................................1 Write Operation..........................................................................17 Revision History...............................................................................2 Read Operation...........................................................................18 Specifications.....................................................................................3 Double-Buffered Interface........................................................19 AC Characteristics........................................................................5 Power-Down Modes..................................................................19 Timing Characteristics................................................................6 Applications.....................................................................................20 Absolute Maximum Ratings............................................................7 Typical Application Circuit.......................................................20 ESD Caution..................................................................................7 Bipolar Operation.......................................................................20 Pin Configuration and Function Descriptions.............................8 Multiple Devices on One Bus...................................................20 Typical Performance Characteristics.............................................9 Product as a Digitally Programmable Window Detector.....21 Terminology....................................................................................13 Coarse and Fine Adjustment Capabilities...............................21 Theory of Operation......................................................................15 Power Supply Decoupling.........................................................21 Digital-to-Analog Converter Section......................................15 Outline Dimensions.......................................................................24 Resistor String.............................................................................15 Ordering Guide..........................................................................24 DAC Reference Inputs...............................................................15 REVISION HISTORY 9/07—Rev. B to Rev. C 10/04—Rev. 0 to Rev. A Changes to Features..........................................................................1 Updated Format..................................................................Universal Changes to Table 4............................................................................7 Added AD5338-1................................................................Universal Changes to Ordering Guide..........................................................25 Changes to Specifications.................................................................4 Updated Outline Dimensions.......................................................24 Changes to Ordering Guide..........................................................24 9/06—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Figure 31......................................................................16 11/03—Rev. 0: Initial Version Changes to Table 6..........................................................................16 Changes to Table 10........................................................................23 Changes to Ordering Guide..........................................................25 Rev. C | Page 2 of 28

AD5337/AD5338/AD5339 SPECIFICATIONS V = 2.5 V to 5.5 V; V = 2 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD REF L L MIN MAX Table 1. A Grade1 B Grade1 Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments DC PERFORMANCE3, 4 AD5337 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5338 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.50 LSB Guaranteed monotonic by design over all codes AD5339 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±8 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR Lower Deadband 20 60 20 60 mV Lower deadband exists only if offset error is negative Offset Error Drift5 −12 −12 ppm of FSR/°C Gain Error Drift5 −5 −5 ppm of FSR/°C Power Supply Rejection Ratio5 −60 −60 dB ∆V = ±10% DD DC Crosstalk5 200 200 μV R = 2 kΩ to GND or V L DD DAC REFERENCE INPUTS5 V Input Range 0.25 V 0.25 V V REF DD DD V Input Impedance 37 45 37 45 kΩ Normal operation REF >10 >10 MΩ Power-down mode Reference Feedthrough −90 −90 dB Frequency = 10 kHz OUTPUT CHARACTERISTICS5 Minimum Output Voltage6 0.001 0.001 V Measure of the minimum drive capabilities of the output amplifier Maximum Output Voltage6 V − V − V Measure of the maximum DD DD 0.001 0.001 drive capabilities of the output amplifier DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 25 25 mA V = 5 V DD 16 16 mA V = 3 V DD Power-Up Time 2.5 2.5 μs Coming out of power- down mode, V = 5 V DD 5 5 μs Coming out of power- down mode, V = 3 V DD Rev. C | Page 3 of 28

AD5337/AD5338/AD5339 A Grade1 B Grade1 Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments LOGIC INPUTS (A0)5 Input Current ±1 ±1 μA Input Low Voltage (V ) 0.8 0.8 V V = 5 V ± 10% IL DD 0.6 0.6 V V = 3 V ± 10% DD 0.5 0.5 V V = 2.5 V DD Input High Voltage (V ) 2.4 2.4 V V = 5 V ± 10% IH DD 2.1 2.1 V V = 3 V ± 10% DD 2.0 2.0 V V = 2.5 V DD Pin Capacitance 3 3 pF LOGIC INPUTS (SCL, SDA)5 Input High Voltage (V ) 0.7 × V + 0.7 × V + V SMBus compatible at IH DD DD V 0.3 V 0.3 V < 3.6 V DD DD DD Input Low Voltage (V ) −0.3 +0.3 –0.3 +0.3 V SMBus compatible at IL V V V < 3.6 V DD DD DD Input Leakage Current (I ) ±1 ±1 μA IN Input Hysteresis (V ) 0.05 × 0.05 × V HYST V V DD DD Input Capacitance (C ) 8 8 pF IN Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of less than 50 ns LOGIC OUTPUT (SDA)5 Output Low Voltage (V ) 0.4 0.4 V I = 3 mA OL SINK 0.6 0.6 V I = 6 mA SINK Three-State Leakage Current ±1 ±1 μA Three-State Output Capacitance 8 8 pF POWER REQUIREMENTS V 2.5 5.5 2.5 5.5 V DD I (Normal Mode)7 V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 300 375 300 375 μA DD V = 2.5 V to 3.6 V 250 350 250 350 μA DD I (Power-Down Mode) V = V and V = GND DD IH DD IL V = 4.5 V to 5.5 V 0.2 1.0 0.2 1.0 μA I = 4 μA (max) during 0 DD DD readback on SDA V = 2.5 V to 3.6 V 0.08 1.00 0.08 1.00 μA I = 1.5 μA (max) during 0 DD DD readback on SDA 1 Temperature range for A Version and B Version: −40°C to +105°C; typical at 25°C. 2 See the Terminology section for explanations of the specific parameters. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5337 (Code 8 to Code 248), AD5338, AD5338-1 (Code 28 to Code 995), AD5339 (Code 115 to Code 3981). 5 Guaranteed by design and characterization; not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. 7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents. Rev. C | Page 4 of 28

AD5337/AD5338/AD5339 AC CHARACTERISTICS V = 2.5 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD L L MIN MAX Table 2. A Version and B Version1 Parameter2, 3 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time V = V = 5 V REF DD AD5337 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) AD5338 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300) AD5339 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major Code Transition Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 1 nV-s Digital Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p REF Total Harmonic Distortion −70 dB V = 2.5 V ± 0.1 V p-p, frequency = 10 kHz REF 1 Temperature range for A version and B version: −40°C to +105°C; typical at 25°C. 2 Guaranteed by design and characterization; not production tested. 3 See the Terminology section for explanations of the specific parameters. Rev. C | Page 5 of 28

AD5337/AD5338/AD5339 TIMING CHARACTERISTICS V = 2.5 V to 5.5 V. All specifications T to T , unless otherwise noted. DD MIN MAX Table 3. Limit at T , T MIN MAX Parameter A Version and B Version Unit Conditions/Comments f 400 kHz max SCL clock frequency SCL t 2.5 μs min SCL cycle time 1 t 0.6 μs min t , SCL high time 2 HIGH t 1.3 μs min t , SCL low time 3 LOW t 0.6 μs min t , start/repeated start condition hold time 4 HD,STA t 100 ns min t , data setup time 5 SU,DAT t 1 0.9 μs max t , data hold time 6 HD,DAT 0 μs min t , data hold time HD,DAT t 0.6 μs min t , setup time for repeated start 7 SU,STA t 0.6 μs min t , stop condition setup time 8 SU,STO t 1.3 μs min t , bus free time between a stop and a start condition 9 BUF t 300 ns max t, rise time of SCL and SDA when receiving 10 R 0 ns min t, rise time of SCL and SDA when receiving (CMOS compatible) R t 250 ns max t, fall time of SDA when transmitting 11 F 0 ns min t, fall time of SDA when receiving (CMOS compatible) F 300 ns max t, fall time of SCL and SDA when receiving F 20 + 0.1 C 2 ns min t, fall time of SCL and SDA when transmitting B F C 400 pF max Capacitive load for each bus line B 1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge. 2 CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 VDD and 0.7 VDD. SDA t9 t3 t10 t11 t4 SCL t4 t6 t2 t1 t8 t t START 5 7 CONDITION CROESPNTEDAAIRTTITOEDN COSNTDOITPION 03756-002 Figure 2. 2-Wire Serial Interface Timing Diagram Rev. C | Page 6 of 28

AD5337/AD5338/AD5339 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute SCL, SDA to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect A0 to GND −0.3 V to V + 0.3 V DD device reliability. Reference Input Voltage to GND −0.3 V to V + 0.3 V DD V A to V B to GND −0.3 V to V + 0.3 V Transient currents of up to 100 mA do not cause SCR latch-up. OUT OUT DD Operating Temperature Range Industrial (B Version) −40°C to +105°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J MSOP Package Power Dissipation (T max − T ) θ J A JA θ Thermal Impedance 206°C/W JA θJC Thermal Impedance 44°C/W Lead Temperature JEDEC Industry Standard Soldering J-STD-020 Rev. C | Page 7 of 28

AD5337/AD5338/AD5339 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 AD5337/ 8 A0 VOUTA 2 AD5338/ 7 SCL VROEUFTIBN 34 (NAToODtPt5oV3SI3Eca9Wle) 65 SGDNAD 03756-003 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 V Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. DD 2 V A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 3 V B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 4 REFIN Reference Input Pin for the Two DACs. It has an input range from 0.25 V to V . DD 5 GND Ground Reference Point for All Circuitry on the Parts. 6 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift register. SDA is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift register. Clock rates of up to 400 kbps can be accommodated in the 2-wire interface. 8 A0 Address Input. Sets the least significant bit of the 7-bit slave address. Rev. C | Page 8 of 28

AD5337/AD5338/AD5339 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA=25°C TA=25°C VDD=5V VDD=5V 0.2 0.5 B) B) 0.1 R (LS R (LS RO 0 RO 0 R R INL E DNL E –0.1 –0.5 –0.2 –1.0 03756-006 –0.3 03756-009 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 4. AD5337 Typical INL Plot Figure 7. AD5337 Typical DNL Plot 3 0.6 TVADD==255°VC VTADD==255°VC 2 0.4 B) 1 B) 0.2 R (LS R (LS RO 0 RO 0 R R INL E –1 DNL E –0.2 –2 –0.4 –3 03756-007 –0.6 03756-010 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 5. AD5338 Typical INL Plot Figure 8. AD5338 Typical DNL Plot 12 1.0 TA=25°C TA=25°C VDD=5V VDD=5V 8 0.5 B) 4 B) R (LS R (LS RO 0 RO 0 R R INL E –4 DNL E –0.5 –8 –12 03756-008 –1.0 03756-011 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 6. AD5339 Typical INL Plot Figure 9. AD5339 Typical DNL Plot Rev. C | Page 9 of 28

AD5337/AD5338/AD5339 0.50 0.2 TA=25°C TA=25°C VDD=5V 0.1 VREF=2V GAINERROR 0.25 0 MAXDNL SB) MAX INL %) –0.1 R (L 0 OR ( –0.2 O R R MINDNL R ER E –0.3 –0.25 –0.4 MIN INL OFFSETERROR –0.50 03756-012 ––00..65 03756-015 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 4 5 6 VREF(V) VDD(V) Figure 10. AD5337 INL and DNL Error vs. VREF Figure 13. Offset Error and Gain Error vs. VDD 0.5 5 0.4 VDD=5V 5VSOURCE VREF=3V 0.3 4 0.2 MAX INL B) 0.1 3 3VSOURCE OR (LS 0 MAXDNL (V)OUT R MINDNL V R –0.1 2 E –0.2 –0.3 MIN INL 1 5VSINK ––00..54 03756-013 0 3VSINK 03756-016 –40 0 40 80 120 0 1 2 3 4 5 6 TEMPERATURE(°C) SINK/SOURCECURRENT(mA) Figure 11. AD5337 INL and DNL Error vs. Temperature Figure 14. VOUT Source and Sink Current Capability 1.0 300 VDD=5V VREF=2V 250 0.5 OFFSETERROR 200 RROR (%) 0 I (µA)DD 150 E GAINERROR 100 –0.5 50 TA=25°C –1.0 03756-014 0 VVDREDF==52VV 03756-017 –40 0 40 80 120 ZEROSCALE FULLSCALE TEMPERATURE(°C) CODE Figure 12. AD5337 Offset Error and Gain Error vs. Temperature Figure 15. Supply Current vs. Code Rev. C | Page 10 of 28

AD5337/AD5338/AD5339 300 TA=25°C –40°C VDD=5V VREF=5V 250 CH1 +25°C +105°C 200 VOUTA A) (µD 150 D I 100 SCL CH2 50 0 03756-018 CH11V,CH25V,TIMEBASE=1µs/DIV 03756-021 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD(V) Figure 16. Supply Current vs. Supply Voltage Figure 19. Midscale Settling (¼ to ¾ Scale Code Change) 0.5 TA=25°C VDD=5V VREF=2V 0.4 CH1 0.3 (µA)D –40°C VDD D I 0.2 +25°C CH2 VOUTA 0.1 0 +105°C 03756-019 CH12V,CH2200mV,TIMEBASE=200µs/DIV 03756-022 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD(V) Figure 17. Power-Down Current vs. Supply Voltage Figure 20. Power-On Reset to 0 V 400 TA=25°C 350 TA=25°C VDD=5V VVDRDEF==52VV 300 CH1 DECREASING 250 INCREASING A) VOUTA (µD 200 VDD=3V ID SCL 150 100 CH2 500 03756-020 03756-023 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CH1500mV,CH25V,TIMEBASE=1µs/DIV VLOGIC(V) Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Figure 21. Existing Power-Down to Midscale Increasing and Decreasing Rev. C | Page 11 of 28

AD5337/AD5338/AD5339 0.02 TA=25°C VDD=5V VDD=3V VDD=5V 0.01 V) R ( Y O FREQUENC SCALE ERR 0 L- L U F–0.01 150 200 250 300 03756-024 –0.02 03756-027 0 1 2 3 4 5 6 IDD(µA) VREF(V) Figure 22. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 25. Full-Scale Error vs. VREF 2.50 2.49 V) DIV (UT mV/ VO 1 2.48 2.47 03756-025 03756-028 1µs/DIV 50ns/DIV Figure 23. AD5339 Major Code Transition Glitch Energy Figure 26. DAC-to-DAC Crosstalk 10 0 –10 –20 B d –30 –40 –50 –60 03756-026 10 100 1k 10k 100k 1M 10M FREQUENCY(Hz) Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. C | Page 12 of 28

AD5337/AD5338/AD5339 TERMINOLOGY Relative Accuracy (Integral Nonlinearity, INL) Major Code Transition Glitch Energy For the DAC, relative accuracy, or integral nonlinearity (INL), The energy of the impulse injected into the analog output when is a measure, in LSBs, of the maximum deviation from a straight the code in the DAC register changes state. Normally specified line passing through the endpoints of the DAC transfer function. as the area of the glitch in nV-s, it is measured when the digital Typical INL vs. code plots can be seen in Figure 4, Figure 5, and code is changed by 1 LSB at the major carry transition (011...11 Figure 6. to 100...00 or 100...00 to 011...11). Differential Nonlinearity (DNL) Digital Feedthrough The difference between the measured change and the ideal A measure of the impulse injected into the analog output of the 1 LSB change between any two adjacent codes. A specified DAC from the digital input pins of the device when the DAC differential nonlinearity of ±1 LSB maximum ensures mono- output is not being updated. Specified in nV-s and measured tonicity. This DAC is guaranteed monotonic by design. Typical with a worst-case change on the digital input pins, such as DNL vs. code plots can be seen in Figure 7, Figure 8, and changing from all 0s to all 1s or vice-versa. Figure 9. Digital Crosstalk Offset Error The glitch impulse transferred to the output of one DAC at A measure of the offset error of the DAC and the output midscale in response to a full-scale code change (all 0s to all 1s, amplifier, expressed as a percentage of the full-scale range. or vice versa) in the input register of another DAC. It is expressed in nV-s. Gain Error A measure of the span error of the DAC. It is the deviation in DAC-to-DAC Crosstalk slope of the actual DAC transfer characteristic from the ideal, The glitch impulse transferred to the output of one DAC due to expressed as a percentage of the full-scale range. a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is Offset Error Drift measured by loading one of the DACs with a full-scale code A measure of the change in offset error with changes in change (all 0s to all 1s, or vice versa) with the LDAC bit set low temperature. It is expressed in (ppm of full-scale range)/°C. and monitoring the output of another DAC. The energy of the Gain Error Drift glitch is expressed in nV-s. A measure of the change in gain error with changes in Multiplying Bandwidth temperature. It is expressed in (ppm of full-scale range)/°C. The amplifiers within the DAC have a finite bandwidth. The Power Supply Rejection Ratio (PSRR) multiplying bandwidth is the frequency at which the output This indicates how the output of the DAC is affected by changes amplitude falls to 3 dB below the input. A sine wave on the in the supply voltage. PSRR is the ratio of the change in V to OUT reference (with full-scale code loaded to the DAC) appears on a change in V for full-scale output of the DAC. It is measured DD the output. in dB. V is held at 2 V and V is varied ±10%. REF DD Total Harmonic Distortion (THD) DC Crosstalk The difference between an ideal sine wave and its attenuated The dc change in the output level of one DAC at midscale in version using the DAC. The sine wave is used as the reference response to a full-scale code change (all 0s to all 1s and vice for the DAC, and the THD is a measure of the harmonic versa) and output change of another DAC. It is expressed in μV. distortion present in the DAC output. It is measured in dB. Reference Feedthrough The ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Rev. C | Page 13 of 28

AD5337/AD5338/AD5339 GAINERROR GAINERROR PLUS PLUS OFFSETERROR ACTUAL OFFSETERROR OUTPUT OUTPUT IDEAL VOLTAGE VOLTAGE ACTUAL IDEAL POSITIVE NOEEFGRFRASOTEIRVTE DACCODE OFFSET DACCODE 03756-005 Figure 28. Transfer Function with Positive Offset DEADBANDCODES AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR 03756-004 Figure 27. Transfer Function with Negative Offset Rev. C | Page 14 of 28

AD5337/AD5338/AD5339 THEORY OF OPERATION The AD5337/AD5338/AD5339 are dual resistor string DACs R fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each part contains two output buffer R amplifiers and is written to via a 2-wire serial interface. The TO OUTPUT DACs operate from single supplies of 2.5 V to 5.5 V, and the R AMPLIFIER output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. The two DACs share a single reference input pin. Each DAC has three programmable power-down modes that allow the output amplifier to be configured with R either a 1 kΩ load to ground, a 100 kΩ load to ground, or as aD hIGigIhT iAmLp-eTdOan-cAe NthAreLe-OstGat eC oOuNtpVutE. RTER SECTION R 03756-030 Figure 30. Resistor String The architecture of one DAC channel consists of a resistor- DAC REFERENCE INPUTS string DAC followed by an output buffer amplifier. The voltage at the REFIN pin provides the reference voltage for the DAC. There is a single reference input pin for the two DACs. The Figure 29 shows a block diagram of the DAC architecture. reference input is unbuffered. The user can have a reference Because the input coding to the DAC is straight binary, the ideal voltage as low as 0.25 V and as high as V , because there is no DD output voltage is given by restriction due to headroom and foot room of any reference amplifier. V ×D V = REF OUT 2N It is recommended to use a buffered reference in the external circuit, for example, REF192. The input impedance is typically where: 45 kΩ. D is the decimal equivalent of the binary code, which is loaded to the DAC register OUTPUT AMPLIFIER 0 to 255 for AD5337 (8 bits) The output buffer amplifier is capable of generating rail-to-rail 0 to 1023 for AD5338 and AD5338-1 (10 bits) voltages on its output, which gives an output range of 0 V to 0 to 4095 for AD5339 (12 bits) V when the reference is V . The amplifier is capable of driving DD DD N is the DAC resolution. a load of 2 kΩ to GND or V in parallel with 500 pF to GND DD REFIN or V . The source and sink capabilities of the output amplifier DD can be seen in the plot in Figure 14. The slew rate is 0.7 V/μs with a half-scale settling time to REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTA ±0.5 LSB (at 8 bits) of 6 μs. POWER-ON RESET OUTAPMUPTLIBFUIEFRFER 03756-029 The AD5337/AD5338/AD5339 power on in a defined state via a Figure 29. DAC Channel Architecture power-on reset function. The power-on state is normal operation, RESISTOR STRING with output voltage set to 0 V. The resistor string portion is shown in Figure 30. It is simply a Both input and DAC registers are filled with zeros until a valid string of resistors, each of value R. The digital code loaded to write sequence is made to the device. This is particularly useful the DAC register determines the node at which the voltage is in applications where it is important to know the state of the tapped off and fed into the output amplifier. The voltage is DAC outputs while the device is powering on. tapped off by closing one of the switches that connects the string to the amplifier. Because the DAC comprises a string of resistors, it is guaranteed to be monotonic. Rev. C | Page 15 of 28

AD5337/AD5338/AD5339 SERIAL INTERFACE Read/Write Sequence The AD5337/AD5338/AD5339 are controlled via an I2C®- For the AD5337/AD5338/AD5339, all write access sequences compatible serial bus. The DACs are connected to this bus as and most read sequences begin with the device address (with slave devices, that is, no clock is generated by the AD5337/ R/W = 0), followed by the pointer byte. This pointer byte specifies AD5338/AD5339 DACs. This interface is SMBus compatible which DAC is being accessed in the subsequent read/write at V < 3.6 V. operation (see Figure 31). In a write operation, the data follows DD immediately. In a read operation, the address is resent with The AD5337/AD5338/AD5339 have a 7-bit slave address. The R/W = 1, and then the data is read back. However, it is also six MSBs are 000110, and the LSB is determined by the state of possible to perform a read operation by sending only the the A0 pin. The facility of making hardwired changes to A0 allows the use of one or two of these devices on one bus. The address with R/W = 1. The previously loaded pointer settings AD5338-1 has a unique 7-bit slave address. The six MSBs are are then used for the readback operation. See Figure 32 for a 010001, and the LSB is determined by the state of the A0 pin. graphical explanation of the interface. Using a combination of AD5338 and AD5338-1 allows the user MSB LSB to accommodate four of these dual 10-bit devices (eight X X 0 0 0 0 DACB DACA 03756-031 channels) on the same bus. Figure 31. Pointer Byte The 2-wire serial bus protocol operates as follows: Table 6 explains the individual bits that make up the pointer byte. 1. The master initiates data transfer by establishing a start condition when a high-to-low transition on the SDA line Table 6. Pointer Byte Bits occurs while SCL is high. The following byte is the address Pointer Byte Bit Description byte, which consists of the 7-bit slave address, followed by X Don’t care bits. an R/W bit. (This bit determines whether data is read from 0 This bit is reserved and must be set to 0 or written to the slave device.) DACB 1: The following data bytes are for DAC B. DACA 1: The following data bytes are for DAC A. The slave with the address corresponding to the transmitted address responds by pulling SDA low during the ninth Input Shift Register clock pulse (this is termed the acknowledge bit). At this The input shift register is 16 bits wide. Data is loaded into the stage, all other devices on the bus remain idle while the device as two data bytes on the serial data line, SDA, under the selected device waits for data to be written to or read from control of the serial clock input, SCL. The timing diagram for this its shift register. operation is shown in Figure 2. The two data bytes consist of four 2. Data is transmitted over the serial bus in sequences of nine control bits followed by 8, 10, or 12 bits of DAC data, depending clock pulses (eight data bits, followed by an acknowledge on the device type. The first two bits loaded are Bit PD1 and bit). The transitions on the SDA line must occur during the Bit PD0, which control the mode of operation of the device. low period of SCL and remain stable during the high period See the Power-Down Modes section for a complete description. of SCL. Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are left- 3. When all data bits have been read from or written to, a stop justified DAC data bits, starting with the MSB (see Figure 32). condition is established. In write mode, the master pulls Table 7. Input Shift Register the SDA line high during the 10th clock pulse to establish a Register Setting Result stop condition. In read mode, the master issues a No CLR 0 All DAC registers and input registers are Acknowledge for the ninth clock pulse, that is, the SDA filled with 0s on completion of the write line remains high. The master then brings the SDA line low sequence. before the 10th clock pulse and high during the 10th clock 1 Normal operation. pulse to establish a stop condition. LDAC 0 The two DAC registers and, therefore, all DAC outputs, simultaneously updated on completion of the write sequence. 1 Addressed input register only is updated. There is no change in the contents of the DAC registers. Rev. C | Page 16 of 28

AD5337/AD5338/AD5339 Default Readback Condition Multiple DAC Read Back Sequence All pointer byte bits power up to 0. Therefore, if the user If the user attempts to read back data from more than one DAC initiates a readback without writing to the pointer byte first, no at a time, the part reads back the default, power-on reset single DAC channel has been specified. In this case, the default conditions, that is, all 0s except for CLR, which is 1. readback bits are all 0s, except for the CLR bit, which is 1. WRITE OPERATION Multiple DAC Write Sequence When writing to the AD5337/AD5338/AD5339 DACs, the user Because there are individual bits in the pointer byte for each must begin with an address byte (R/W = 0), after which the DAC, it is possible to write the same data and control bits to two DAC acknowledges that it is prepared to receive data by pulling DACs simultaneously by setting the relevant bits to 1. SDA low. This address byte is followed by the pointer byte, which is also acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 33. A stop condition follows. MOSTSIGNIFICANTDATABYTE LEASTSIGNIFICANTDATABYTE MSB 8-BITAD5337 LSB MSB 8-BITAD5337 LSB PD1 PD0 CLR LDAC D7 D6 D5 D4 D3 D2 D1 D0 X X X X MSB 10-BITAD5338 LSB MSB 10-BITAD5338 LSB PD1 PD0 CLR LDAC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X MPDS1B PD0 CLR 1L2D-BAICTADD513139 D10 D9 LDS8B MDS7B D6 D5 12D-B4ITADD53339 D2 D1 LDS0B 03756-032 Figure 32. Data Formats for Write and Read Back SCL SDA 0 0 0 1 1 0 A0 R/W X X LSB START ACK MSB ACK CONDITION BY BY BY ADDRESSBYTE AD533x POINTERBYTE AD533x MASTER SCL SDA MSB LSB MSB LSB ACK ACK STOP MOSTSIGNIFICANTDATABYTE ADB5Y33x LEASTSIGNIFICANTDATABYTE ADB5Y33x CMONABDSYTITEIORN 03756-033 Figure 33. Write Sequence Rev. C | Page 17 of 28

AD5337/AD5338/AD5339 READ OPERATION Note that in a read sequence, data bytes are the same as those in the write sequence, except that don’t cares are read back as 0s. When reading data back from the AD5337/AD5338/AD5339 However, if the master sends an ACK and continues clocking DACs, the user begins with an address byte (R/W = 0), after SCL (no stop is sent), the DAC retransmits the same two bytes which the DAC acknowledges that it is prepared to receive data of data on SDA. This allows continuous read back of data from by pulling SDA low. This address byte is usually followed by the the selected DAC register. Alternatively, the user can send a pointer byte, which is also acknowledged by the DAC. Then, the start followed by the address with R/W = 1. In this case, the master initiates another start condition (repeated start) and the previously loaded pointer settings are used and read back of address is resent with R/W = 1. This is acknowledged by the data can begin immediately. DAC indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC as shown in Figure 34. A stop condition follows. SCL SDA 0 0 0 1 1 0 A0 R/W X X LSB START ACK MSB ACK CONBDYITION ADDRESSBYTE ADB5Y33x POINTERBYTE ADB5Y33x MASTER SCL SDA 0 0 0 1 1 0 A0 R/W MSB LSB REPEATED ACK ACK START BY BY CONDITION ADDRESSBYTE AD533x DATABYTE MASTER BY MASTER SCL SDA MSB LSB NO STOP LEASTSIGNIFICANTDATABYTE MAABSCYTKER CMONABDSYTITEIORN 03756-034 Figure 34. Read Sequence Rev. C | Page 18 of 28

AD5337/AD5338/AD5339 DOUBLE-BUFFERED INTERFACE When both bits are 0, the DAC works with its normal power consumption of 300 μA at 5 V. However, for the three power- The AD5337/AD5338/AD5339 DACs have a double-buffered down modes, the supply current falls to 200 nA at 5 V (80 nA interface consisting of two banks of registers—an input register at 3 V). Not only does the supply current drop, but the output and a DAC register per channel. The input register is directly stage is also internally switched from the output of the amplifier connected to the input shift register, and the digital code is to a resistor network of known values. This is advantageous in transferred to the relevant input register upon completion of a that the output impedance of the part is known while the part is valid write sequence. The DAC register contains the digital code in power-down mode, which provides a defined input condition used by the resistor string. for whatever is connected to the output of the DAC amplifier. Access to the DAC register is controlled by the LDAC bit. There are three options. The output can be connected internally When the LDAC bit is set high, the DAC register is latched to GND through a 1 kΩ resistor, a 100 kΩ resistor, or can be left and therefore, the input register can change state without open-circuited (three-state). Resistor tolerance = ±20%. The affecting the DAC register. This is useful if the user requires output stage is illustrated in Figure 35. simultaneous updating of all DAC outputs. The user can write to three of the input registers individually; by setting the LDAC bit low when writing to the remaining DAC input register, all SRTERSINISGTDOARC AMPLIFIER VOUT outputs update simultaneously. These parts contain an extra feature whereby the DAC register is only updated if its input register has been updated since the POWER-DOWN CIRCUITRY RESISTOR luanstn teicmeses athryat d LigDiAtaCl c wroasss tbarloku. g ht low, thereby removing NETWORK 03756-035 Figure 35. Output Stage During Power-Down POWER-DOWN MODES The bias generator, output amplifiers, resistor string, and all The AD5337/AD5338/AD5339 have very low power consumption, other associated linear circuitry are shut down when power- typically dissipating 0.75 mW with a 3 V supply and 1.5 mW down mode is activated. However, the contents of the DAC with a 5 V supply. Power consumption can be further reduced registers remain unchanged when power-down mode is activated. when the DACs are not in use by putting them into one of three The time to exit power-down is typically 2.5 μs for V = 5 V DD power-down modes, which are selected by Bit 15 and Bit 14 and 5 μs when V = 3 V. This is the time from the rising edge DD (PD1 and PD0) of the data byte. Table 8 shows how the state of of the eighth SCL pulse to the time when the output voltage the bits corresponds to the mode of operation of the DAC. deviates from its power-down voltage (see Figure 21 for a plot). Table 8. PD1/PD0 Operating Modes PD1 PD0 Operating Mode 0 0 Normal operation 0 1 Power-down (1 kΩ load to GND) 1 0 Power-down (100 kΩ load to GND) 1 1 Power-down (three-state output) Rev. C | Page 19 of 28

AD5337/AD5338/AD5339 APPLICATIONS TYPICAL APPLICATION CIRCUIT BIPOLAR OPERATION The AD5337/AD5338/AD5339 can be used with a wide The AD5337/AD5338/AD5339 are designed for single-supply range of reference voltages for full, one-quadrant multiplying operation, but a bipolar output range is also possible using the capability over a reference range of 0 V to V . More typically, circuit in Figure 37. This circuit gives an output voltage range of DD these devices are used with a fixed precision reference voltage. ±5 V. Rail-to-rail operation at the amplifier output is achievable Suitable references for 5 V operation are the AD780, the REF192, using an AD820 or an OP295 as the output amplifier. and the ADR391 (2.5 V references). For 2.5 V operation, a R2=10kΩ suitable external reference would be the AD589 or AD1580, a +5V 1.23 V band gap reference. Figure 36 shows a typical setup for 6VTO12V R1=10kΩ the AD5337/AD5338/AD5339 when using an external reference. 10µF 0.1µF AD820/ ±5V +5V OP295 Note that A0 can be high or low. VDD VOUTA VDD=2.5VTO5.5V AD1585 AD5339 –5V VIN VOUT REFIN VOUTB 0.1µF 10µF GND 1µF AD5337/ AD5338/ AD5339 A0 VIN VOUTA GND SCL SDA VOUT REFIN ERXETF 1µF VOUTB ADW78IT0/HREVDFD19=2/5AVD ORR391 SSDCAL INTS2E-EWRRIFIRAAELCE 03756-037 AD589/AD1580WITH Figure 37. Bipolar Operation with the AD5339 VDD=2.5V A0 GND The output voltage for any input code can be calculated as INTSEERRFIAALCE 03756-036 follows: ⎡⎛ D ⎞ R1+R2 R2⎤ Figure 36. AD5337/AD5338/AD5339 Using External Reference V = ⎢⎜REFIN× ⎟× −REFIN× ⎥ OUT ⎣⎝ 2N ⎠ R1 R1⎦ If an output range of 0 V to V is required, the simplest DD solution is to connect the reference input to V . Because this where: DD supply can be inaccurate and noisy, the AD5337/AD5338/ D is the decimal equivalent of the code loaded to the DAC. AD5339 can be powered from a reference voltage, for example, N is the DAC resolution. using a 5 V reference such as the REF195, which provides a REFIN is the reference voltage input. steady output supply voltage. With no load on the DACs, the With REFIN = 5 V, R1 = R2 = 10 kΩ: REF195 is required to supply 600 μA supply current to the DAC V = (10 × D/2N) − 5 and 112 μA to the reference input. When the DAC outputs are OUT loaded, the REF195 also needs to supply the current to the loads; MULTIPLE DEVICES ON ONE BUS therefore, the total current required with a 10 kΩ load on each Figure 38 shows two AD5339 devices on the same serial bus. output is Each has a different slave address because the state of the A0 pin 712 μA + 2 × (5 V/10 kΩ) = 1.7 mA is different. This allows each of four DACs to be written to or read from independently. The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 3.4 ppm (17 μV) for the 1.7 mA VDD A0 AD5339 current drawn from it. This corresponds to a 0.0009 LSB error PULL-UP at 8 bits and a 0.014 LSB error at 12 bits. RESISTORS SDA SCL MICROCONTROLLER SDA SCL A0 AD5339 03756-038 Figure 38. Multiple AD5339 Devices on One Bus Rev. C | Page 20 of 28

AD5337/AD5338/AD5339 PRODUCT AS A DIGITALLY PROGRAMMABLE POWER SUPPLY DECOUPLING WINDOW DETECTOR In any circuit where accuracy is important, careful consideration Figure 39 shows a digitally programmable upper/lower limit of the power supply and ground return layout helps to ensure detector using the two DACs in the AD5337/AD5338/AD5339. the rated performance. The printed circuit board on which the The upper and lower limits for the test are loaded into DAC A AD5337/AD5338/AD5339 are mounted should be designed so and DAC B, which, in turn, set the limits on the CMP04. If the that the analog and digital sections are separated and confined signal at the V input is not within the programmed window, to certain areas of the board. If the AD5337/AD5338/AD5339 IN an LED indicates the fail condition. are in a system where multiple devices require an AGND-to- 5V DGND connection, the connection should be made at one 0.1µF 10µF VIN 1kΩ 1kΩ point only. The star ground point should be established as close as possible to the device. The AD5337/AD5338/AD5339 should FAIL PASS VREF REFIN VDD have ample supply bypassing of 10 μF in parallel with 0.1 μF on the supply located as close to the package as possible, ideally VOUTA right up against the device. The 10 μF capacitors are the tantalum AD5337/ AD5338/ 1/2 PASS/FAIL bead type. The 0.1 μF capacitor should have low effective series AD53391 CMP04 resistance (ESR) and low effective series inductance (ESI) to DIN SDA SCL SCL VOUTB 1/674HC05 provide a low impedance path to ground at high frequencies to GND handle transient currents due to internal logic switching. The 1ADDITIONALPINS OMITTEDFORCLARITY. 03756-039 paso wlaerrg es uap tprlayc eli naes sp oofs tshibel eA tDo5 p3r3o7v/iAdDe l5o3w3 8im/ApDe5d3a3n9c es hpoauthlds aunsde Figure 39. Window Detection reduce the effects of glitches on the power supply line. Fast COARSE AND FINE ADJUSTMENT CAPABILITIES switching signals such as clocks should be shielded with digital The two DACs in the AD5337/AD5338/AD5339 can be paired ground to avoid radiating noise to other parts of the board, and together to form a coarse and fine adjustment function, as they should never be run near the reference inputs. A ground shown in Figure 40. DAC A is used to provide the coarse line routed between the SDA and SCL lines helps to reduce adjustment while DAC B provides the fine adjustment. Varying crosstalk between them. This is not required on a multilayer the ratio of R1 and R2 changes the relative effect of the coarse board because there is a separate ground plane, but separating and fine adjustments. With the resistor values and external the lines does help. reference shown, the output amplifier has unity gain for the Avoid crossover of digital and analog signals. Traces on opposite DAC A output, thus, the output range is 0 V to 2.5 V − 1 LSB. sides of the board should run at right angles to each other. This For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B reduces the effects of feedthrough on the board. Using a microstrip a range equal to 19 mV. technique is the best solution, but its use is not always possible The circuit is shown with a 2.5 V reference, but reference with a double-sided board. In this technique, the component voltages up to V can be used. The op amps indicated allow side of the board is dedicated to the ground plane, while signal DD a rail-to-rail output swing. traces are placed on the solder side. VDD=5V R3 R4 51.2kΩ 390Ω 0.1µF 10µF 5V ERXETFVINVOUT REFIN VDD VOUTA AD820/ VOUT 1µF R1 OP295 GND AD5337/ 390Ω AD5338/ AD53391 AD780/REF192/ADR391 WITHVDD=5V VOUTB GND R2 51.2kΩ 1ADDITIONALPINS OMITTEDFORCLARITY. 03756-040 Figure 40. Coarse/Fine Adjustment Rev. C | Page 21 of 28

AD5337/AD5338/AD5339 Table 9. Overview of All AD53xx Serial Devices Part No. Resolution (Bits) No. of DACs DNL (LSBs) Interface Settling Time (μs) Package No. of Pins Single AD5300 8 1 ±0.25 SPI 4 SOT-23, MSOP 6, 8 AD5310 10 1 ±0.50 SPI 6 SOT-23, MSOP 6, 8 AD5320 12 1 ±1.00 SPI 8 SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-Wire 6 SOT-23, MSOP 6, 8 AD5311 10 1 ±0.50 2-Wire 7 SOT-23, MSOP 6, 8 AD5321 12 1 ±1.00 2-Wire 8 SOT-23, MSOP 6, 8 Dual AD5302 8 2 ±0.25 SPI 6 MSOP 8 AD5312 10 2 ±0.50 SPI 7 MSOP 8 AD5322 12 2 ±1.00 SPI 8 MSOP 8 AD5303 8 2 ±0.25 SPI 6 TSSOP 16 AD5313 10 2 ±0.50 SPI 7 TSSOP 16 AD5323 12 2 ±1.00 SPI 8 TSSOP 16 AD5337 8 2 ±0.25 2-Wire 6 MSOP 8 AD5338 10 2 ±0.50 2-Wire 7 MSOP 8 AD5338-1 10 2 ±0.50 2-Wire 7 MSOP 8 AD5339 12 2 ±1.00 2-Wire 8 MSOP 8 Quad AD5304 8 4 ±0.25 SPI 6 MSOP 10 AD5314 10 4 ±0.50 SPI 7 MSOP 10 AD5324 12 4 ±1.00 SPI 8 MSOP 10 AD5305 8 4 ±0.25 2-Wire 6 MSOP 10 AD5315 10 4 ±0.50 2-Wire 7 MSOP 10 AD5325 12 4 ±1.00 2-Wire 8 MSOP 10 AD5306 8 4 ±0.25 2-Wire 6 TSSOP 16 AD5316 10 4 ±0.50 2-Wire 7 TSSOP 16 AD5326 12 4 ±1.00 2-Wire 8 TSSOP 16 AD5307 8 4 ±0.25 SPI 6 TSSOP 16 AD5317 10 4 ±0.50 SPI 7 TSSOP 16 AD5327 12 4 ±1.00 SPI 8 TSSOP 16 Octal AD5308 8 8 ±0.25 SPI 6 TSSOP 16 AD5318 10 8 ±0.50 SPI 7 TSSOP 16 AD5328 12 8 ±1.00 SPI 8 TSSOP 16 Rev. C | Page 22 of 28

AD5337/AD5338/AD5339 Table 10. Overview of AD53xx Parallel Devices No. of Settling Additional Pin Functions Part No. Resolution (Bits) DNL (LSBs) V Pins Time (μs) BUF GAIN HBEN CLR Package No. of Pins REF Single AD5300 8 ±0.25 1 6 * * * TSSOP 20 AD5331 10 ±0.50 1 7 * * TSSOP 20 AD5340 12 ±1.00 1 8 * * * TSSOP 24 AD5341 12 ±1.00 1 8 * * * * TSSOP 20 Dual AD5332 8 ±0.25 2 6 * TSSOP 20 AD5333 10 ±0.50 2 7 * * * TSSOP 24 AD5342 12 ±1.00 2 8 * * * TSSOP 28 AD5343 12 ±1.00 1 8 * * TSSOP 20 Quad AD5334 8 ±0.25 2 6 * * TSSOP 24 AD5335 10 ±0.50 2 7 * * TSSOP 24 AD5336 10 ±0.50 4 7 * * TSSOP 28 AD5344 12 ±1.00 4 8 TSSOP 28 Octal AD5346 8 ±0.25 4 6 * * * TSSOP, LFCSP 38, 40 AD5347 10 ±0.50 4 7 * * * TSSOP, LFCSP 38, 40 AD5348 12 ±1.00 4 8 * * * TSSOP, LFCSP 38, 40 Rev. C | Page 23 of 28

AD5337/AD5338/AD5339 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 0.80 0.15 0.38 0.23 8° 0.60 0.00 0.22 0.08 0° 0.40 COPLANARITY SEATING 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 41. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD5337ARM −40°C to +105°C 8-Lead MSOP RM-8 D23 AD5337ARM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D23 AD5337ARMZ1 −40°C to +105°C 8-Lead MSOP RM-8 D23# AD5337ARMZ-REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D23# AD5337BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D20 AD5337BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D20 AD5337BRMZ1 −40°C to +105°C 8-Lead MSOP RM-8 D20# AD5337BRMZ-REEL1 −40°C to +105°C 8-Lead MSOP RM-8 D20# AD5337BRMZ-REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D20# AD5338ARM −40°C to +105°C 8-Lead MSOP RM-8 D24 AD5338ARMZ1 −40°C to +105°C 8-Lead MSOP RM-8 D5F AD5338ARMZ-REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D5F AD5338ARMZ-11 −40°C to +105°C 8-Lead MSOP RM-8 D57 AD5338ARMZ-1REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D57 AD5338BRM −40°C to +105°C 8-Lead MSOP RM-8 D21 AD5338BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D21 AD5338BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D21 AD5338BRMZ1 −40°C to +105°C 8-Lead MSOP RM-8 D5H AD5338BRMZ-11 −40°C to +105°C 8-Lead MSOP RM-8 D58 AD5338BRMZ-1REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D58 AD5339ARM −40°C to +105°C 8-Lead MSOP RM-8 D25 AD5339ARMZ1 −40°C to +105°C 8-Lead MSOP RM-8 D6P AD5339ARMZ-REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D6P AD5339BRM −40°C to +105°C 8-Lead MSOP RM-8 D22 AD5339BRM-REEL −40°C to +105°C 8-Lead MSOP RM-8 D22 AD5339BRM-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D22 AD5339BRMZ1 −40°C to +105°C 8-Lead MSOP RM-8 D6R AD5339BRMZ-REEL1 −40°C to +105°C 8-Lead MSOP RM-8 D6R AD5339BRMZ-REEL71 −40°C to +105°C 8-Lead MSOP RM-8 D6R 1 Z = RoHS Compliant Part. # denotes lead-free product may be top or bottom marked. Rev. C | Page 24 of 28

AD5337/AD5338/AD5339 NOTES Rev. C | Page 25 of 28

AD5337/AD5338/AD5339 NOTES Rev. C | Page 26 of 28

AD5337/AD5338/AD5339 NOTES Rev. C | Page 27 of 28

AD5337/AD5338/AD5339 NOTES Purchase of licensed I²C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification as defined by Philips. ©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03756-0-9/07(C) Rev. C | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5338ARMZ-1 AD5337ARM AD5338ARMZ AD5338ARM AD5337ARMZ AD5337BRMZ AD5338BRMZ-1 AD5337ARMZ-REEL7 AD5339ARMZ AD5337BRMZ-REEL7 AD5339BRMZ-REEL7 AD5339ARM AD5337BRMZ- REEL AD5338BRMZ AD5338BRMZ-1REEL7 AD5338ARMZ-REEL7 AD5339BRMZ AD5338ARMZ-1REEL7 AD5339ARMZ-REEL7