a (cid:1) 2.5 V to 5.5 V, 230 A, Parallel Interface Dual Voltage-Output 8-/10-/12-Bit DACs AD5332/AD5333/AD5342/AD5343* FEATURES GENERAL DESCRIPTION AD5332: Dual 8-Bit DAC in 20-Lead TSSOP The AD5332/AD5333/AD5342/AD5343 are dual 8-, 10-, and AD5333: Dual 10-Bit DAC in 24-Lead TSSOP 12-bit DACs. They operate from a 2.5V to 5.5V supply con- AD5342: Dual 12-Bit DAC in 28-Lead TSSOP suming just 230 µA at 3V, and feature a power-down pin, PD AD5343: Dual 12-Bit DAC in 20-Lead TSSOP that further reduces the current to 80 nA. These devices incor- Low Power Operation: 230 (cid:1)A @ 3V, 300 (cid:1)A @ 5V porate an on-chip output buffer that can drive the output to via PD Pin both supply rails, while the AD5333 and AD5342 allow a choice Power-Down to 80 nA @ 3V, 200 nA @ 5V of buffered or unbuffered reference input. 2.5V to 5.5V Power Supply The AD5332/AD5333/AD5342/AD5343 have a parallel interface. Double-Buffered Input Logic CS selects the device and data is loaded into the input registers Guaranteed Monotonic by Design Over All Codes on the rising edge of WR. Buffered/Unbuffered Reference Input Options Output Range: 0–V or 0–2V The GAIN pin on the AD5333 and AD5342 allows the output Power-On Reset to RZEFero VoltsREF range to be set at 0V to VREF or 0V to 2 × VREF. Simultaneous Update of DAC Outputs via LDAC Pin Input data to the DACs is double-buffered, allowing simultaneous Asynchronous CLR Facility update of multiple DACs in a system using the LDAC pin. Low Power Parallel Data Interface An asynchronous CLR input is also provided, which resets the On-Chip Rail-to-Rail Output Buffer Amplifiers contents of the Input Register and the DAC Register to all zeros. Temperature Range: –40(cid:2)C to +105(cid:2)C These devices also incorporate a power-on reset circuit that ensures APPLICATIONS that the DAC output powers on to 0V and remains there until Portable Battery-Powered Instruments valid data is written to the device. Digital Gain and Offset Adjustment The AD5332/AD5333/AD5342/AD5343 are available in Thin Programmable Voltage and Current Sources Shrink Small Outline Packages (TSSOP). Programmable Attenuators Industrial Process Control AD5332 FUNCTIONAL BLOCK DIAGRAM (Other Diagrams Inside) VREFA VDD POWER-ON AD5332 RESET DB...7 REINGPISUTTER REGDIASCTER 8D-BAICT BUFFER VOUTA DB0 INTER- FACE CS LOGIC INPUT DAC 8-BIT WR REGISTER REGISTER DAC BUFFER VOUTB A0 RESET POWER-DOWN CLR LOGIC LDAC VREFB PD GND *Protected by U.S. Patent Number 5,969,657. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD5332/AD5333/AD5342/AD5343–SPECIFICATIONS (V = 2.5V to 5.5V, V = 2V. R = 2 k(cid:3) to GND; C =200 pF to GND; all specifications T to T unless otherwise noted.) DD REF L L MIN MAX B Version2 Parameter1 Min Typ Max Unit Conditions/Comments DC PERFORMANCE3, 4 AD5332 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic By Design Over All Codes AD5333 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic By Design Over All Codes AD5342/AD5343 Resolution 12 Bits Relative Accuracy ±2 ±16 LSB Differential Nonlinearity ±0.2 ±1 LSB Guaranteed Monotonic By Design Over All Codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 % of FSR Lower Deadband5 10 60 mV Lower Deadband Exists Only if Offset Error Is Negative Upper Deadband 10 60 mV V = 5V. Upper Deadband Exists Only if V V DD REF = DD Offset Error Drift6 –12 ppm of FSR/°C Gain Error Drift6 –5 ppm of FSR/°C DC Power Supply Rejection Ratio6 –60 dB ∆V = ±10% DD DC Crosstalk6 200 µV R = 2 kΩ to GND, 2 kΩ to V ; C = 200 pF to GND; L DD L Gain = 0 DAC REFERENCE INPUT6 V Input Range 1 V V Buffered Reference (AD5333 and AD5342) REF DD 0.25 V V Unbuffered Reference DD V Input Impedance >10 MΩ Buffered Reference (AD5333 and AD5342) REF 180 kΩ Unbuffered Reference. Gain = 1, Input Impedance = R DAC 90 kΩ Unbuffered Reference. Gain = 2, Input Impedance = R DAC Reference Feedthrough –90 dB Frequency = 10 kHz Channel-to-Channel Isolation –90 dB Frequency = 10 kHz (AD5332, AD5333, and AD5342) OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 0.001 V min Rail-to-Rail Operation Maximum Output Voltage4, 7 V – 0.001 V max DD DC Output Impedance 0.5 Ω Short Circuit Current 25 mA V = 5V DD 16 mA V = 3V DD Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V = 5V DD 5 µs Coming Out of Power-Down Mode. V = 3V DD LOGIC INPUTS6 Input Current ±1 µA V , Input Low Voltage 0.8 V V = 5 V ± 10% IL DD 0.6 V V = 3 V ± 10% DD 0.5 V V = 2.5 V DD V , Input High Voltage 2.4 V V = 5 V ± 10% IH DD 2.1 V V = 3 V ± 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3.5 pF POWER REQUIREMENTS V 2.5 5.5 V DD I (Normal Mode) All DACs active and excluding load currents DD V = 4.5 V to 5.5 V 300 450 µA Unbuffered Reference. V = V , V = GND. DD IH DD IL V = 2.5 V to 3.6 V 230 350 µA I increases by 50 µA at V > V – 100 mV. DD DD REF DD In Buffered Mode extra current is (5 +V /R ) µA. REF DAC I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 µA DD V = 2.5 V to 3.6 V 0.08 1 µA DD NOTES 1See Terminology section. 2Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. 3Linearity is tested using a reduced code range: AD5332 (Code 8 to 255); AD5333 (Code 28 to 1023); AD5342/AD5343 (Code 115 to 4095). 4DC specifications tested with outputs unloaded. 5This corresponds to x codes. x = Deadband voltage/LSB size. 6Guaranteed by design and characterization, not production tested. 7In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V = V and REF DD “Offset plus Gain” Error must be positive. Specifications subject to change without notice. –2– REV. 0

AD5332/AD5333/AD5342/AD5343 (V = 2.5 V to 5.5 V. R = 2 k(cid:3) to GND; C = 200 pF to GND; all specifications T to T unless AC CHARACTERISTICS1 DD L L MIN MAX otherwise noted.) B Version3 Parameter2 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time V = 2 V. See Figure 20 REF AD5332 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H) AD5333 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5342 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) AD5343 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) Slew Rate 0.7 V/µs Major Code Transition Glitch Energy 6 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 3 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3.5 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p. Unbuffered Mode REF Total Harmonic Distortion –70 dB V = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz REF NOTES 1Guaranteed by design and characterization, not production tested. 2See Terminology section. 3Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C. Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2, 3 (V = 2.5V to 5.5V, All specifications T to T unless otherwise noted.) DD MIN MAX Parameter Limit at T , T Unit Condition/Comments MIN MAX t 0 ns min CS to WR Setup Time 1 t 0 ns min CS to WR Hold Time 2 t 20 ns min WR Pulsewidth 3 t 5 ns min Data, GAIN, BUF, HBEN Setup Time 4 t 4.5 ns min Data, GAIN, BUF, HBEN Hold Time 5 t 5 ns min Synchronous Mode. WR Falling to LDAC Falling 6 t 5 ns min Synchronous Mode. LDAC Falling to WR Rising 7 t 4.5 ns min Synchronous Mode. WR Rising to LDAC Rising 8 t 5 ns min Asynchronous Mode. LDAC Rising to WR Rising 9 t 4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling 10 t 20 ns min LDAC Pulsewidth 11 t 20 ns min CLR Pulsewidth 12 t 50 ns min Time Between WR Cycles 13 t 20 ns min A0 Setup Time 14 t 0 ns min A0 Hold Time 15 NOTES 1Guaranteed by design and characterization, not production tested. 2All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD t1 t2 IL IH 3See Figure 1. CS Specifications subject to change without notice. t3 t13 WR t4 t5 DATA, GAIN, BUF, HBEN t6 t7 t8 LDAC1 t t t 9 10 11 LDAC2 t CLR t14 t15 12 A0 1SYNCHRONOUS LDAC UPDATE MODE 2ASYNCHRONOUS LDAC UPDATE MODE Figure 1.Parallel Interface Timing Diagram REV. 0 –3–

AD5332/AD5333/AD5342/AD5343 ABSOLUTE MAXIMUM RATINGS* θ Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W JA (T = 25°C unless otherwise noted) θ Thermal Impedance (28-Lead TSSOP) . . . . 97.9°C/W A JA VDDigDi ttaol IGnNpuDt V .o .l t.a .g .e . t.o . G. .N . D. . .. .. .. .. .. .. .. . –. 0. ..3 . V. –to0 .V3D VD t+o 0+.37 VV θθJJCC TThheerrmmaall IImmppeeddaannccee ((2204--LLeeaadd TTSSSSOOPP)) .. .. .. .. .. .. 4452°°CC//WW Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V θJC Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W Reference Input Voltage to GND . . . . –0.3 V to V + 0.3 V Reflow Soldering V to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C OUT DD Operating Temperature Range Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C *Stresses above those listed under Absolute Maximum Ratings may cause perma- Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C nent damage to the device. This is a stress rating only; functional operation of the Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating TSSOP Package conditions for extended periods may affect device reliability. Power Dissipation . . . . . . . . . . . . . . . (T max – T )/θ mW J A JA θ Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W JA ORDERING GUIDE Package Model Temperature Range Package Description Option AD5332BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20 AD5333BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24 AD5342BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28 AD5343BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5332/AD5333/AD5342/AD5343 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –4– REV. 0

AD5332/AD5333/AD5342/AD5343 AD5332 FUNCTIONAL BLOCK DIAGRAM AD5332 PIN CONFIGURATION VREFA VDD VREFB 1 20 DB7 POWER-ON AD5332 VREFA 2 19 DB6 RESET VOUTA 3 18 DB5 VOUTB 4 17 DB4 DB...7 REINGPISUTTER REGDIASCTER 8D-BAICT BUFFER VOUTA GND 5 AD8-5B3IT32 16 DB3 DB0 CS 6 (NToOt Pto V SIEcaWle)15 DB2 INTER- WR 7 14 DB1 CS LFOAGCIEC A0 8 13 DB0 WR REINGPISUTTER REGDIASCTER 8D-BAICT BUFFER VOUTB CLR 9 12 VDD LDAC 10 11 PD A0 RESET POWER-DOWN CLR LOGIC LDAC VREFB PD GND AD5332 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 V B Unbuffered reference input for DAC B. REF 2 V A Unbuffered reference input for DAC A. REF 3 V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 4 V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 A0 Address pin for selecting which DAC A and DAC B. 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 12 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10(cid:1)F capacitor in parallel with a 0.1(cid:1)F capacitor to GND. 13–20 DB –DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 REV. 0 –5–

AD5332/AD5333/AD5342/AD5343 AD5333 FUNCTIONAL BLOCK DIAGRAM AD5333 PIN CONFIGURATION VREFA VDD GAIN 1 24 DB9 AD5333 BUF 2 23 DB8 POWER-ON VREFB 3 22 DB7 BUF RESET REGDIASCTER VVORUETFAA 45 A1D05-B3I3T3 2210 DDBB65 GDAB...IN9 REINGPISUTTER 1D0-ABCIT BUFFER VOUTA VOGUNTDB 67 (NToOt Pto V SIEcaWle) 1198 DDBB34 DB0 CS 8 17 DB2 INTER- FACE WR 9 16 DB1 WCRS LOGIC REINGPISUTTER 1D0-ABCIT BUFFER VOUTB CLAR0 1101 1154 DVBDD0 DAC LDAC 12 13 PD A0 REGISTER RESET POWER-DOWN CLR LOGIC LDAC VREFB PD GND AD5333 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V or 0–2 V . REF REF 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3 V B Reference input for DAC B. REF 4 V A Reference input for DAC A. REF 5 V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 6 V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 7 GND Ground reference point for all circuitry on the part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 A0 Address pin for selecting between DAC A and DAC B. 11 CLR Asynchronous active-low control input that clears all input registers and DAC registers to zeros. 12 LDAC Active-low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 14 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10(cid:1)F capacitor in parallel with a 0.1(cid:1)F capacitor to GND. 15–24 DB –DB 10 Parallel Data Inputs. DB is the MSB of these 10 bits. 0 9 9 –6– REV. 0

AD5332/AD5333/AD5342/AD5343 AD5342 FUNCTIONAL BLOCK DIAGRAM AD5342 PIN CONFIGURATION VREFA VDD GAIN 1 28 DB11 AD5342 BUF 2 27 DB10 POWER-ON VREFB 3 26 DB9 RESET REGDIASCTER VREFA 4 25 DB8 VOUTA 5 24 DB7 DB...11 REINGPISUTTER 1D2-ABCIT BUFFER VOUTA VOUNTBC 67 TAO1DP25- VB3IIE4T2W 2232 DDBB56 DB0 NC 8 (Not to Scale) 21 DB4 INTER- FACE GND 9 20 DB3 CS LOGIC INPUT 12-BIT CS 10 19 DB2 WR REGISTER DAC BUFFER VOUTB WR 11 18 DB1 A0 REGDIASCTER A0 12 17 DB0 CLR 13 16 VDD RESET POWER-DOWN LDAC 14 15 PD CLR LOGIC NC = NO CONNECT LDAC VREFB PD GND AD5342 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0-V or 0-2 V . REF REF 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3 V B Reference Input for DAC B. REF 4 V A Reference Input for DAC A. REF 5 V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 6 V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 7, 8 NC No Connect. 9 GND Ground reference point for all circuitry on the part. 10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 11 WR Active low Write Input. This is used in conjunction with CS to write data to the parallel interface. 12 A0 Address pin for selecting between DAC A and DAC B. 13 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros. 14 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 16 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10(cid:1)F capacitor in parallel with a 0.1(cid:1)F capacitor to GND. 17–28 DB –DB 12 Parallel Data Inputs. DB is the MSB of these 12 bits. 0 11 11 REV. 0 –7–

AD5332/AD5333/AD5342/AD5343 AD5343 FUNCTIONAL BLOCK DIAGRAM AD5343 PIN CONFIGURATION VREF VDD HBEN 1 20 DB7 POWER-ON VREF 2 19 DB6 RESET AD5343 VOUTA 3 18 DB5 HIGH BYTE VOUTB 4 17 DB4 REGISTER 12-BIT DB.....7 GNCDS 56 (NToAOtD Pto5 V 3SIE4c3aWle)1165 DDBB23 DB.0 LROEWGI SBTYETRE REGDIASCTER 1D2-ABCIT BUFFER VOUTA WR 7 14 DB1 A0 8 13 DB0 HBEN INTER- HIGH BYTE CLR 9 12 VDD CS LFOAGCIEC REGISTER LDAC 10 11 PD WR A0 LROEWGI SBTYETRE REGDIASCTER 1D2-ABCIT BUFFER VOUTB RESET CLR LDAC POWER-DOWN LOGIC PD GND AD5343 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 2 V Unbuffered reference input for both DACs. REF 3 V A Output of DAC A. Buffered output with rail-to-rail operation. OUT 4 V B Output of DAC B. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 A0 Address pin for selecting between DAC A and DAC B. 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zeros. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. This allows all DAC outputs to be simultaneously updated. 11 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode. 12 V Power Supply Pin. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10(cid:1)F capacitor in parallel with a 0.1(cid:1)F capacitor to GND. 13–20 DB –DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 –8– REV. 0

AD5332/AD5333/AD5342/AD5343 TERMINOLOGY GAIN ERROR RELATIVE ACCURACY AND For the DAC, Relative Accuracy or Integral Nonlinearity (INL) OFFSET ERROR is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer ACTUAL function. Typical INL versus Code plot can be seen in Figures 5, 6, and 7. OUTPUT VOLTAGE DIFFERENTIAL NONLINEARITY Differential Nonlinearity (DNL) is the difference between the IDEAL measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed mono- tonic by design. Typical DNL versus Code plot can be seen in Figures 8, 9, and 10. POSITIVE OFFSET OFFSET ERROR DAC CODE This is a measure of the offset error of the DAC and the output Figure 3.Positive Offset Error and Gain Error amplifier. It is expressed as a percentage of the full-scale range. If the offset voltage is positive, the output voltage will still be positive at zero input code. This is shown in Figure 3. Because the DACs operate from a single supply, a negative offset cannot GAIN ERROR appear at the output of the buffer amplifier. Instead, there will AND be a code close to zero at which the amplifier output saturates OFFSET ERROR (amplifier footroom). Below this code there will be a deadband IDEAL over which the output voltage will not change.This is illustrated OUTPUT in Figure 4. VOLTAGE GAIN ERROR ACTUAL This is a measure of the span error of the DAC (including any error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illus- trated in Figure 2. NEOGFAFTSIVEET DAC CODE POSITIVE GAIN ERROR NEGATIVE ACTUAL GAIN ERROR DEADBAND CODES AMPLIFIER FOOTROOM OUTPUT (~1mV) VOLTAGE IDEAL NEGATIVE OFFSET DAC CODE Figure 4.Negative Offset Error and Gain Error Figure 2.Gain Error REV. 0 –9–

AD5332/AD5333/AD5342/AD5343 OFFSET ERROR DRIFT DIGITAL CROSSTALK This is a measure of the change in Offset Error with changes in This is the glitch impulse transferred to the output of one DAC temperature. It is expressed in (ppm of full-scale range)/°C. at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of the other DAC. It is GAIN ERROR DRIFT expressed in nV-secs. This is a measure of the change in Gain Error with changes in tem- perature. It is expressed in (ppm of full-scale range)/°C. ANALOG CROSSTALK This is the glitch impulse transferred to the output of one DAC POWER-SUPPLY REJECTION RATIO (PSRR) due to a change in the output of the other DAC. It is measured This indicates how the output of the DAC is affected by changes in by loading one of the input registers with a full-scale code change the supply voltage. PSRR is the ratio of the change in V to a (all 0s to all 1s and vice versa) while keeping LDAC high. Then OUT change in V for full-scale output of the DAC. It is measured pulse LDAC low and monitor the output of the DAC whose DD in dBs. V is held at 2 V and V is varied ±10%. digital code was not changed. The area of the glitch is expressed REF DD in nV-secs. DC CROSSTALK This is the dc change in the output level of one DAC at mid- DAC-TO-DAC CROSSTALK scale in response to a full-scale code change (all 0s to all 1s and This is the glitch impulse transferred to the output of one DAC vice versa) and output change of the other DAC. It is expressed due to a digital code change and subsequent output change of in µV. the other DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code REFERENCE FEEDTHROUGH change (all 0s to all 1s and vice versa) with the LDAC pin set This is the ratio of the amplitude of the signal at the DAC output low and monitoring the output of the other DAC. The energy of to the reference input when the DAC output is not being updated the glitch is expressed in nV-secs. (i.e., LDAC is high). It is expressed in dBs. MULTIPLYING BANDWIDTH CHANNEL-TO-CHANNEL ISOLATION The amplifiers within the DAC have a finite bandwidth. The This is a ratio of the amplitude of the signal at the output of one Multiplying Bandwidth is a measure of this. A sine wave on the DAC to a sine wave on the reference input of the other DAC. It reference (with full-scale code loaded to the DAC) appears on is measured by grounding one V pin and applying a 10kHz, the output. The Multiplying Bandwidth is the frequency at which REF 4V peak-to-peak sine wave to the other V pin. It is expressed the output amplitude falls to 3 dB below the input. REF in dBs. TOTAL HARMONIC DISTORTION MAJOR-CODE TRANSITION GLITCH ENERGY This is the difference between an ideal sine wave and its attenuated Major-Code Transition Glitch Energy is the energy of the version using the DAC. The sine wave is used as the reference impulse injected into the analog output when the DAC changes for the DAC and the THD is a measure of the harmonics present state. It is normally specified as the area of the glitch in nV secs on the DAC output. It is measured in dBs. and is measured when the digital code is changed by 1 LSB at the major carry transition (011...11 to 100...00 or 100...00 to 011...11). DIGITAL FEEDTHROUGH Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device but is measured when the DAC is not being written to (CS held high). It is specified in nV secs and is measured with a full-scale change on the digital input pins, i.e. from all 0s to all 1s and vice versa. –10– REV. 0

Typical Performance Characteristics–AD5332/AD5333/AD5342/AD5343 1.0 3 12 TVAD D= =2 55(cid:2)VC 2 TVAD D= =2 55(cid:2)VC 8 TVAD D= =2 55(cid:2)VC 0.5 SBs SBs 1 SBs 4 OR – L 0 OR – L 0 OR – L 0 R R R R R R E E E NL NL –1 NL –4 I–0.5 I I –2 –8 –1.0 –3 –12 0 50 100 150 200 250 0 200 400 600 800 1000 0 1000 2000 3000 4000 CODE CODE CODE Figure 5.AD5332 Typical INL Plot Figure 6.AD5333 Typical INL Plot Figure 7.AD5342 Typical INL Plot 0.3 0.6 1.0 0.2 TVAD D= =2 55(cid:2)VC 0.4 TVAD D= =2 55(cid:2)VC TVAD D= =2 55(cid:2)VC 0.5 SBs 0.1 SBs 0.2 SBs L L L R – R – R – O 0 O 0 O 0 R R R R R R E E E NL –0.1 NL –0.2 NL D D D –0.5 –0.2 –0.4 –0.3 –0.6 –1 0 50 100 150 200 250 0 200 400 600 800 1000 0 1000 2000 3000 4000 CODE CODE CODE Figure 8.AD5332 Typical DNL Plot Figure 9.AD5333 Typical DNL Plot Figure 10.AD5342 Typical DNL Plot 1.00 1.00 1.0 0.75 VTAD D= =2 55(cid:2)VC 0.75 VVDRDEF = = 5 2VV VVDRDEF = = 5 2VV 0.50 0.50 0.5 MAX DNL MAX INL OR – LSBs 00..2050 MMMAAINXX D DINNNLLL OR – LSBs 0.205 ROR – %0.0 GAIN ERROR RR–0.25 MIN INL RR–0.25 ER E E MIN INL MIN DNL OFFSET ERROR –0.50 –0.50 –0.5 –0.75 –0.75 –1.00 –1.00 –1.0 2 3 4 5 –40 0 40 80 120 –40 0 40 80 120 VREF – V TEMPERATURE – (cid:2)C TEMPERATURE – (cid:2)C Figure 11.AD5332 INL and DNL Figure 12.AD5332 INL Error and Figure 13.AD5332 Offset Error Error vs. V DNL Error vs. Temperature and Gain Error vs. Temperature REF REV. 0 –11–

AD5332/AD5333/AD5342/AD5343 0.2 5 400 0.1 TVAR E=F 2=5 2(cid:1)CV 4 5V SOURCE 350 TVAR E=F 2=5 (cid:2)2CV VDD = 5.5V 0 GAIN ERROR 300 ROR – %––00..21 – VoltsUT 3 3V SOURCE (cid:1) – ADD220500 VDD = 3.6V ER–0.3 VO 2 I 150 –0.4 OFFSET ERROR 100 1 3V SINK –0.5 5V SINK 50 –0.6 0 0 0 1 2 3 4 5 6 0 1 2 3 4 5 6 ZERO-SCALE FULL-SCALE VDD – Volts SINK/SOURCE CURRENT – mA DAC CODE Figure 14.Offset Error and Gain Figure 15.VOUT Source and Sink Figure 16.Supply Current vs. DAC Error vs. V Current Capability Code DD 400 TA = 25(cid:2)C 0.5 TA = 25(cid:2)C 11640000 TA = 25(cid:2)C 0.4 1200 300 1000 (cid:1)I – ADD200 (cid:1)I – ADD 00..23 (cid:1)I – ADD 860000 400 VDD = 5V 100 0.1 200 VDD = 3V 0 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1 2 3 4 5 VDD – V VDD – V VLOGIC – V Figure 17.Supply Current vs. Supply Figure 18.Power-Down Current vs. Figure 19.Supply Current vs. Logic Voltage Supply Voltage Input Voltage VDD = 5V TA = 25(cid:1)C TA = 25(cid:1)C TA = 25(cid:2)C VDD = 5V VDD = 5V CH2 LDAC CH1 VREF = 2V VREF = 2V VDD CH1 VOUTA VOUT VOUTA PD CH2 CH2 CH1 CH1 2V, CH2 200mV, TIME BASE = 200(cid:1)s/DIV CH1 500mV, CH2 5V, TIME BASE = 1(cid:1)s/DIV CH1 1V, CH2 5V, TIME BASE = 5(cid:1)s/DIV Figure 20.Half-Scale Settling (1/4 to Figure 21.Power-On Reset to 0 V Figure 22.Exiting Power-Down to 3/4 Scale Code Change) Midscale –12– REV. 0

AD5332/AD5333/AD5342/AD5343 0.939 10 0.938 0 VDD = +5V 0.937 VDD = +3V 0.936 –10 NCY olts 0.935 –20 EQUE – VUT0.934 dB–30 R O0.933 F V 0.932 –40 0.931 –50 0.930 0 0.929 –60 100 150 200 250 300 350 400 500 ns/DIV 0.01 0.1 1 10 100 1k 10k IDD – (cid:1)A FREQUENCY – kHz Figure 23.I Histogram with V = 3 Figure 24.AD5342 Major-Code Tran- Figure 25.Multiplying Bandwidth DD DD V and V = 5 V sition Glitch Energy (Small-Signal Frequency Response) DD 0.2 TA = 25(cid:2)C R VREF = 2V S F % – 0 R O V ERR V/DI E m L 4 A SC–0.2 L- L U F –0.4 0 1 2 3 4 5 6 750ns/DIV VREF – V Figure 26.Full-Scale Error vs. V Figure 27.DAC-DAC Crosstalk REF FUNCTIONAL DESCRIPTION where: The AD5332/AD5333/AD5342/AD5343 are dual DACs fabri- D = decimal equivalent of the binary code which is loaded to cated on a CMOS process with resolutions of 8, 10, 12, and the DAC register: 12 bits, respectively. They are written to using a parallel inter- 0–255 for AD5332 (8 Bits) face. They operate from single supplies of 2.5V to 5.5V and 0–1023 for AD5333 (10 Bits) the output buffer amplifiers offer rail-to-rail output swing. The 0–4095 for AD5342/AD5343 (12 Bits) AD5333 and AD5342 have reference inputs that may be buff- ered to draw virtually no current from the reference source. N = DAC resolution Their output voltage range may be configured to be 0 to V REF Gain = Output Amplifier Gain (1 or 2) or 0 to 2V . The reference inputs of the AD5332 and AD5343 REF are unbuffered and their output range is 0 to V . The devices have a power-down feature that reduces current RcEoFnsumption to VREF only 80 nA @ 3V. Digital-to-Analog Section REFERENCE BUF The architecture of one DAC channel consists of a reference BUFFER buffer and a resistor-string DAC followed by an output buffer GAIN amplifier. The voltage at the V pin provides the reference REF INPUT DAC RESISTOR voltage for the DAC. Figure 28 shows a block diagram of the REGISTER REGISTER STRING VOUT DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by: OUTPUT BUFFER AMPLIFIER D Figure 28.Single DAC Channel Architecture V =V × ×Gain OUT REF 2N REV. 0 –13–

AD5332/AD5333/AD5342/AD5343 Resistor String PARALLEL INTERFACE The resistor string section is shown in Figure 29. It is simply a The AD5332, AD5333, and AD5342 load their data as a single string of resistors, each of value R. The digital code loaded to 8-, 10-, or 12-bit word, while the AD5343 loads data as a low the DAC register determines at what node on the string the byte of 8 bits and a high byte containing 4 bits. voltage is tapped off to be fed into the output amplifier. The Double-Buffered Interface voltage is tapped off by closing one of the switches connecting The AD5332/AD5333/AD5342/AD5343 DACs all have double- the string to the amplifier. Because it is a string of resistors, it buffered interfaces consisting of an input register and a DAC is guaranteed monotonic. register. DAC data, BUF, and GAIN inputs are written to the input register under control of the Chip Select (CS) and Write VREF (WR). R Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input R register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC TO OUTPUT R AMPLIFIER register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are only updated when LDAC is taken low. R This is useful if the user requires simultaneous updating of all DACs and peripherals. The user may write to both input regis- R ters individually and then, by pulsing the LDAC input low, both outputs will update simultaneously. Figure 29.Resistor String Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5343, because it allows the whole data DAC Reference Input word to be assembled in parallel before updating the DAC register. The DACs operate with an external reference. The AD5332, This prevents spurious outputs that could occur if the DAC AD5333, and AD5342 have separate reference inputs for each register were updated with only the high byte or the low byte. DAC, while the AD5343 has a single reference input for both DACs. The reference inputs on the AD5333 and AD5342 may These parts contain an extra feature whereby the DAC register be configured as buffered or unbuffered. The reference inputs is not updated unless its input register has been updated since of the AD5332 and AD5343 are unbuffered. The buffered/ the last time that LDAC was brought low. Normally, when unbuffered option is controlled by the BUF pin. LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5332/ In buffered mode (BUF = 1) the current drawn from an exter- AD5333/AD5342/AD5343, the part will only update the DAC nal reference voltage is virtually zero, as the impedance is at least 10 MΩ. The reference input range is 1V to V . register if the input register has been changed since the last DD time the DAC register was updated. This removes unnecessary In unbuffered mode (BUF = 0) the user can have a reference crosstalk. voltage as low as 0.25V and as high as V since there is no DD Clear Input (CLR) restriction due to headroom and footroom of the reference ampli- fier. The impedance is still large at typically 180 kΩ for 0–V CLR is an active low, asynchronous clear that resets the input and mode and 90 kΩ for 0–2V mode. REF DAC registers. REF Chip Select Input (CS) If using an external buffered reference (e.g., REF192) there is CS is an active low input that selects the device. no need to use the on-chip buffer. Write Input (WR) Output Amplifier WR is an active low input that controls writing of data to the The output buffer amplifier is capable of generating output volt- device. Data is latched into the input register on the rising edge ages to within 1 mV of either rail. Its actual range depends on of WR. V , GAIN, the load on V and offset error. REF OUT Load DAC Input (LDAC) If a gain of 1 is selected (GAIN = 0), the output range is 0.001V LDAC transfers data from the input register to the DAC register to V . REF (and hence updates the outputs). Use of the LDAC function enables If a gain of 2 is selected (GAIN = 1), on the AD5333 and AD5342 double buffering of the DAC data, GAIN and BUF. There are the output range is 0.001V to 2VREF. two LDAC modes: The output amplifier is capable of driving a load of 2 kΩ to Synchronous Mode: In this mode the DAC register is updated GND or VDD, in parallel with 500 pF to GND or VDD. The after new data is read in on the rising edge of the WR input. source and sink capabilities of the output amplifier can be seen LDAC can be tied permanently low or pulsed as in Figure 1. in Figure 15. Asynchronous Mode: In this mode the outputs are not updated The slew rate is 0.7V/µs with a half-scale settling time to ±0.5 LSB at the same time that the input register is written to. When LDAC (at 8 bits) of 6 µs with the output unloaded. See Figure 20. goes low the DAC register is updated with the contents of the input register. –14– REV. 0

AD5332/AD5333/AD5342/AD5343 High-Byte Enable Input (HBEN) POWER-DOWN MODE High-Byte Enable is a control input on the AD5343 only that The AD5332/AD5333/AD5342/AD5343 have low power con- determines if data is written to the high-byte input register or sumption, dissipating typically 0.69 mW with a 3V supply and the low-byte input register. 1.5 mW with a 5V supply. Power consumption can be further reduced when the DACs are not in use by putting them into The low data byte of the AD5343 consists of data bits 0 to 7 at power-down mode, which is selected by taking pin PD low. data inputs DB to DB , while the high byte consists of data 0 7 bits 8 to 11 at data inputs DB to DB . DB to DB are ignored When the PD pin is high, the DACs work normally with a typical 0 3 4 7 during a high byte write, but they may be used for data to power consumption of 300 µA at 5V (230 µA at 3V). In power- set up the reference input as buffered/unbuffered, and buffer down mode, however, the supply current falls to 200 nA at 5V amplifier gain. See Figure 32. (80 nA at 3V) when both DACs are powered down. Not only does the supply current drop, but the output stage is also internally HIGH BYTE switched from the output of the amplifier, making it open-circuit. X X X X DB11DB10DB9 DB8 This has the advantage that the outputs are three-state while the part is in power-down mode, and provides a defined input LOW BYTE condition for whatever is connected to the outputs of the DAC DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 amplifiers. The output stage is illustrated in Figure 31. X = UNUSED BIT Figure 30.Data Format for AD5343 POWER-ON RESET RESISTOR AMPLIFIER VOUT STRING DAC The AD5332/AD5333/AD5342/AD5343 are provided with a power-on reset function, so that they power up in a defined state. POWER-DOWN The power-on state is: CIRCUITRY • Normal operation Figure 31. Output Stage During Power-Down • Reference input unbuffered • 0 – V output range The bias generator, the output amplifier, the resistor string, and REF • Output voltage set to 0V all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the Both input and DAC registers are filled with zeros and remain registers are unaffected when in power-down. The time to exit so until a valid write sequence is made to the device. This is power-down is typically 2.5 µs for V = 5V and 5 µs when particularly useful in applications where it is important to know DD V = 3V. This is the time from a rising edge on the PD pin to the state of the DAC outputs while the device is powering up. DD when the output voltage deviates from its power-down voltage. See Figure 22. Table I. AD5332/AD5333/AD5342 Truth Table CLR LDAC CS WR A0 Function 1 1 1 X X No Data Transfer 1 1 X 1 X No Data Transfer 0 X X X X Clear All Registers 1 1 0 0➝1 0 Load DAC A Input Register 1 1 0 0➝1 1 Load DAC B Input Register 1 0 X X X Update DAC Registers X = don’t care. Table II. AD5343 Truth Table CLR LDAC CS WR A0 HBEN Function 1 1 1 X X X No Data Transfer 1 1 X 1 X X No Data Transfer 0 X X X X X Clear All Registers 1 1 0 0➝1 0 0 Load DAC A Low Byte Input Register 1 1 0 0➝1 0 1 Load DAC A High Byte Input Register 1 1 0 0➝1 1 0 Load DAC B Low Byte Input Register 1 1 0 0➝1 1 1 Load DAC B High Byte Input Register 1 0 X X X X Update DAC Registers X = don’t care. REV. 0 –15–

AD5332/AD5333/AD5342/AD5343 SUGGESTED DATABUS FORMATS Driving V from the Reference Voltage DD In most applications GAIN and BUF are hard-wired. However, If an output range of zero to V is required when the reference DD if more flexibility is required, they can be included in a databus. inputs are configured as unbuffered, the simplest solution is to This enables you to software program GAIN, giving the option connect the reference inputs to V .As this supply may not be DD of doubling the resolution in the lower half of the DAC range. very accurate, and may be noisy, the devices may be powered In a bused system GAIN and BUF may be treated as data inputs from the reference voltage, for example using a 5V reference since they are written to the device during a write operation and such as the ADM663 or ADM666, as shown in Figure 34. take effect when LDAC is taken low. This means that the refer- ence buffers and the output amplifier gain of multiple DAC 6V TO 16V devices can be controlled using common GAIN and BUF lines. The AD5333 and AD5342 databuses must be at least 10, and 0.1(cid:1)F 10(cid:1)F 12 bits wide respectively, and are best suited to a 16-bit data- bus system. VIN AD5332/AD5333/ Examples of data formats for putting GAIN and BUF on a 16- ADM663/ADM666 AD5342/AD5343 bit databus are shown in Figure 32. Note that any unused bits SENSE VDD above the actual DAC data may be used for BUF and GAIN. VOUT(2) VREF* VOUT* VSET GNDSHDN 0.1(cid:1)F AD5333 GND X X X X BUFGAIN DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1DB0 AD5342 X X BUF GAINDB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1DB0 *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Figure 34. Using an ADM663/ADM666 as Power and Refer- X = UNUSED BIT ence to AD5332/AD5333/AD5342/AD5343 Figure 32.GAIN and BUF Data on a 16-Bit Bus Bipolar Operation Using the AD5332/AD5333/AD5342/AD5343 APPLICATIONS INFORMATION The AD5332/AD5333/AD5342/AD5343 have been designed Typical Application Circuits for single supply operation, but bipolar operation is achievable The AD5332/AD5333/AD5342/AD5343 can be used with a using the circuit shown in Figure 35. The circuit shown has been wide range of reference voltages, especially if the reference inputs configured to achieve an output voltage range of –5V < VO < are configured to be unbuffered, in which case the devices offer +5V. Rail-to-rail operation at the amplifier output is achievable full, one-quadrant multiplying capability over a reference range using an AD820 or OP295 as the output amplifier. of 0.25V to VDD. More typically, these devices may be used with a The output voltage for any input code can be calculated as fixed, precision reference voltage. Figure 33 shows a typical follows: setup for the devices when using an external reference connected to V = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V × D/2N)] – R4 × V /R3 the unbuffered reference inputs. If the reference inputs are unbuf- O REF REF fered, the reference input range is from 0.25V to V , but if the where: DD on-chip reference buffers are used, the reference range is reduced. D is the decimal equivalent of the code loaded to the DAC, N is Suitable references for 5V operation are the AD780 and REF192. DAC resolution and V is the reference voltage input. REF For 2.5V operation, a suitable external reference would be the With: AD589, a 1.23V bandgap reference. V = 2.5V REF VDD = 2.5V TO 5.5V R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ and V = 5V. DD V = (10 × D/2N) – 5 0.1(cid:1)F 10(cid:1)F OUT VDD = 5V EXTVIN VDD 20Rk4(cid:3) REF VOUT VREF* 0.1(cid:1)F 10(cid:1)F VOUT* R3 +5V GND AD5332/AD5333/ 10k(cid:3) AD5342/AD5343 VIN (cid:4)5V AD780/REF192 EXT VDD WITH VDD = 5V REF VOUT VREF* OR GND 0.1(cid:1)F –5V AD589 WITH VDD = 2.5V GND AADD55333422//AADD55333433/ R1 10k(cid:3) *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN VOUT* AD780/REF192 Figure 33.AD5332/AD5333/AD5342/AD5343 Using WITH VDD = 5V GND R202k(cid:3) OR External Reference AD589 WITH VDD = 2.5V *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN Figure 35.Bipolar Operation using the AD5332/AD5333/ AD5342/AD5343 –16– REV. 0

AD5332/AD5333/AD5342/AD5343 Decoding Multiple AD5332/AD5333/AD5342/AD5343 Note that the AD5343 has only a single reference input. If using The CS pin on these devices can be used in applications to decode the AD5332, AD5333, or AD5342, both reference inputs must a number of DACs. In this application, all DACs in the system be connected. receive the same data and WR pulses, but only the CS to one of the DACs will be active at any one time, so data will only be 5V written to the DAC whose CS is low. If multiple AD5343s are 0.1(cid:1)F 10(cid:1)F 1k(cid:3) 1k(cid:3) being used, a common HBEN line will also be required to VIN FAIL PASS determine if the data is written to the high-byte or low-byte VREF VREFA* VDD register of the selected DAC. VOUT The 74HC139 is used as a 2- to 4-line decoder to address any VREFB* 1/2 PASS/ of the DACs in the system. To prevent timing errors from AD5332/AD5333/ CMP04 FAIL occurring, the enable input should be brought to its inactive AD5342 state while the coded address inputs are changing state. Figure 36 VOUTB 1/6 74HC05 shows a diagram of a typical setup for decoding multiple devices GND in a system. Once data has been written sequentially to all DACs in *NOT AD5343 a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to Figure 37.Programmable Window Detector reset all DAC outputs to zero. Programmable Current Source Figure 38 shows the AD5332/AD5333/AD5342/AD5343 used as the control element of a programmable current source. In this AD5332/AD5333/ AD5342/AD5343 example, the full-scale current is set to 1 mA. The output volt- A1 A0 age from the DAC is applied across the current setting resistor HBEN HBEN* of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, LDWACR WLDRAC INDPAUTTAS which gives an adjustment of about ±5%. Suitable transistors to CLR CLR place in the feedback loop of the amplifier include the BC107 CS and the 2N3904, which enable the current source to operate AD5332/AD5333/ from a minimum VSOURCE of 6V. The operating range is deter- AD5342/AD5343 mined by the operating characteristics of the transistor. Suitable A0 amplifiers include the AD820 and the OP295, both having rail- HBEN* WR DATA to-rail operation on their outputs. The current for any digital VDD LDAC INPUTS input code and resistor value can be calculated as follows: CLR S U CS B VCC A D ENABLE 1G 1Y0 AADD55333422//AADD55333433/ DAT I = G ×VREF ×(2N × R)mA CODED 1A 1Y1 A0 Where: ADDRESS 1B74HC1391Y2 HWBREN* DATA G is the gain of the buffer amplifier (1 or 2) 1Y3 LDAC INPUTS D is the digital equivalent of the digital input code CLR N is the DAC resolution (8, 10, or 12 bits) DGND CS R is the sum of the resistor plus adjustment potentiometer in kΩ AD5332/AD5333/ AD5342/AD5343 A0 VDD = 5V *AD5343 ONLY HBEN* WR DATA LDAC INPUTS 0.1(cid:1)F 10(cid:1)F CLR VSOURCE CS Figure 36.Decoding Multiple DAC Devices EXTVIN VDD 5V LOAD REF VOUT VREF* VOUT* 0.1(cid:1)F AD5332/AD5333/AD5342/AD5343 as a Digitally Program- GND AD5332/AD5333/ AD5342/AD5343 mable Window Detector A digitally programmable upper/lower limit detector using the AD780/REF192 two DACs in the AD5332/AD5333/AD5342 is shown in Figure WITH VDD = 5V 4.7k(cid:3) GND 37. The upper and lower limits for the test are loaded to DACs 470(cid:3) A and B which, in turn, set the limits on the CMP04. If a signal at the V input is not within the programmed window, an LED *ONLY ONE CHANNEL OF VREF AND VOUT SHOWN IN will indicate the fail condition. Figure 38.Programmable Current Source REV. 0 –17–

AD5332/AD5333/AD5342/AD5343 Coarse and Fine Adjustment Using the AD5332/AD5333/ Power Supply Bypassing and Grounding AD5342/AD5343 In any circuit where accuracy is important, careful consideration The DACs in the AD5332/AD5333/AD5342/AD5343 can be of the power supply and ground return layout helps to ensure paired together to form a coarse and fine adjustment function, the rated performance. The printed circuit board on which the as shown in Figure 39. DAC A is used to provide the coarse AD5332/AD5333/AD5342/AD5343 is mounted should be adjustment while DAC B provides the fine adjustment. Varying designed so that the analog and digital sections are separated, the ratio of R1 and R2 will change the relative effect of the coarse and confined to certain areas of the board. If the device is in a and fine adjustments. With the resistor values shown the output system where multiple devices require an AGND-to-DGND amplifier has unity gain for the DAC A output, so the output connection, the connection should be made at one point only. range is 0V to 2.5V – 1 LSB. For DAC B the amplifier has a gain The star ground point should be established as closely as pos- of 7.6 × 10–3, giving DAC B a range equal to 2 LSBs of DAC A. sible to the device. The AD5332/AD5333/AD5342/AD5343 should have ample supply bypassing of 10 µF in parallel with The circuit is shown with a 2.5V reference, but reference volt- 0.1µF on the supply located as close to the package as pos- ages up to V may be used. The op amps indicated will allow a DD sible, ideally right up against the device. The 10 µF capacitors rail-to-rail output swing. are the tantalum bead type. The 0.1 µF capacitor should have Note that the AD5343 has only a single reference input. If using low Effective Series Resistance (ESR) and Effective Series Induc- the AD5332, AD5333, or AD5342, both reference inputs must tance (ESI), like the common ceramic types that provide a low be connected. impedance path to ground at high frequencies to handle tran- sient currents due to internal logic switching. VDD = 5V R3 R4 The power supply lines of the device should use as large a trace 51.2k(cid:3) 390(cid:3) as possible to provide low impedance paths and reduce the effects 0.1(cid:1)F 10(cid:1)F +5V of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiat- REXETFVINVOUT VREFA* VDD VOUTA 39R01(cid:3) VOUT innega rn tohisee r teofe orethnecre pinaprtust os.f Athveo ibdo acrrods, saonvde rs hoof udlidg itnaelv aenr db ea nrau-n GND 0.1(cid:1)F AD5332/AD5333/ log signals. Traces on opposite sides of the board should run AD5342/AD5343 R2 51.2k(cid:3) at right angles to each other. This reduces the effects of feed- AD780/REF192 VOUTB through through the board. A microstrip technique is by far WITH VDD = 5V VREFB* the best, but not always possible with a double-sided board. In GND this technique, the component side of the board is dedicated to *NOT AD5343 ground plane while signal traces are placed on the solder side. Figure 39.Coarse and Fine Adjustment –18– REV. 0

AD5332/AD5333/AD5342/AD5343 Table III. Overview of AD53xx Parallel Devices Part No. Resolution DNL V Pins Settling Time Additional Pin Functions Package Pins REF SINGLES BUF GAIN HBEN CLR AD5330 8 ±0.25 1 6 µs (cid:2) (cid:2) (cid:2) TSSOP 20 AD5331 10 ±0.5 1 7 µs (cid:2) (cid:2) TSSOP 20 AD5340 12 ±1.0 1 8 µs (cid:2) (cid:2) (cid:2) TSSOP 24 AD5341 12 ±1.0 1 8 µs (cid:2) (cid:2) (cid:2) (cid:2) TSSOP 20 DUALS AD5332 8 ±0.25 2 6 µs (cid:2) TSSOP 20 AD5333 10 ±0.5 2 7 µs (cid:2) (cid:2) (cid:2) TSSOP 24 AD5342 12 ±1.0 2 8 µs (cid:2) (cid:2) (cid:2) TSSOP 28 AD5343 12 ±1.0 1 8 µs (cid:2) (cid:2) TSSOP 20 QUADS AD5334 8 ±0.25 2 6 µs (cid:2) (cid:2) TSSOP 24 AD5335 10 ±0.5 2 7 µs (cid:2) (cid:2) TSSOP 24 AD5336 10 ±0.5 4 7 µs (cid:2) (cid:2) TSSOP 28 AD5344 12 ±1.0 4 8 µs TSSOP 28 Table IV. Overview of AD53xx Serial Devices Part No. Resolution No. of DACS DNL Interface Settling Time Package Pins SINGLES AD5300 8 1 ±0.25 SPI 4 µs SOT-23, MicroSOIC 6, 8 AD5310 10 1 ±0.5 SPI 6 µs SOT-23, MicroSOIC 6, 8 AD5320 12 1 ±1.0 SPI 8 µs SOT-23, MicroSOIC 6, 8 AD5301 8 1 ±0.25 2-Wire 6 µs SOT-23, MicroSOIC 6, 8 AD5311 10 1 ±0.5 2-Wire 7 µs SOT-23, MicroSOIC 6, 8 AD5321 12 1 ±1.0 2-Wire 8 µs SOT-23, MicroSOIC 6, 8 DUALS AD5302 8 2 ±0.25 SPI 6 µs MicroSOIC 8 AD5312 10 2 ±0.5 SPI 7 µs MicroSOIC 8 AD5322 12 2 ±1.0 SPI 8 µs MicroSOIC 8 AD5303 8 2 ±0.25 SPI 6 µs TSSOP 16 AD5313 10 2 ±0.5 SPI 7 µs TSSOP 16 AD5323 12 2 ±1.0 SPI 8 µs TSSOP 16 QUADS AD5304 8 4 ±0.25 SPI 6 µs MicroSOIC 10 AD5314 10 4 ±0.5 SPI 7 µs MicroSOIC 10 AD5324 12 4 ±1.0 SPI 8 µs MicroSOIC 10 AD5305 8 4 ±0.25 2-Wire 6 µs MicroSOIC 10 AD5315 10 4 ±0.5 2-Wire 7 µs MicroSOIC 10 AD5325 12 4 ±1.0 2-Wire 8 µs MicroSOIC 10 AD5306 8 4 ±0.25 2-Wire 6 µs TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 µs TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 µs TSSOP 16 AD5307 8 4 ±0.25 SPI 6 µs TSSOP 16 AD5317 10 4 ±0.5 SPI 7 µs TSSOP 16 AD5327 12 4 ±1.0 SPI 8 µs TSSOP 16 Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html REV. 0 –19–

AD5332/AD5333/AD5342/AD5343 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Thin Shrink Small Outline Package TSSOP (RU-20) 0.260 (6.60) 0.252 (6.40) 0) v. e 20 11 0.177 (4.50) 0 (r 0.169 (4.30) 4/0 0.256 (6.50) 5– 0.246 (6.25) 2. – 1 10 9 2 8 PIN 1 3 C 0.006 (0.15) 0.0433 (1.10) 0.002 (0.05) MAX 8(cid:2) SEPALTAINNGE0.02B56S C(0.65) 00..00101785 ((00..3109)) 00.0.0003759 ( (00.0.2900))0(cid:2) 00..002280 ((00..7500)) 24-Lead Thin Shrink Small Outline Package TSSOP (RU-24) 0.311 (7.90) 0.303 (7.70) 24 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 12 PIN 1 0.006 (0.15) 0.0433 (1.10) 0.002 (0.05) MAX 8(cid:2) SEPALTAINNGE 0.02B56S C(0.65) 00..00101785 ((00..3109)) 00.0.0003759 ( (00.0.2900))0(cid:2) 00..002280 ((00..7500)) 28-Lead Thin Shrink Small Outline Package TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) A. 0.169 (4.30) S. 0.256 (6.50) U. 0.246 (6.25) N 1 14 D I E PIN 1 T N 0.006 (0.15) 0.0433 (1.10) RI 0.002 (0.05) MAX P 8(cid:2) SEPALTAINNGE 0.02B56S C(0.65) 00..00101785 ((00..3109)) 00.0.0003759 ( (00.0.2900))0(cid:2) 00..002280 ((00..7500)) –20– REV. 0