2.5 V to 5.5 V, 115 μA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs AD5330/AD5331/AD5340/AD5341 FEATURES GENERAL DESCRIPTION AD5330: single 8-bit DAC in 20-lead TSSOP The AD5330/AD5331/AD5340/AD53411 are single 8-/10-/12- AD5331: single 10-bit DAC in 20-lead TSSOP bit DACs. They operate from a 2.5 V to 5.5 V supply consuming AD5340: single 12-bit DAC in 24-lead TSSOP just 115 μA at 3 V and feature a power-down mode that further AD5341: single 12-bit DAC in 20-lead TSSOP reduces the current to 80 nA. The devices incorporate an on-chip Low power operation: 115 μA @ 3 V, 140 μA @ 5 V output buffer that can drive the output to both supply rails, but Power-down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin the AD5330, AD5340, and AD5341 allow a choice of buffered 2.5 V to 5.5 V power supply or unbuffered reference input. Double-buffered input logic The AD5330/AD5331/AD5340/AD5341 have a parallel Guaranteed monotonic by design over all codes interface. CS selects the device and data is loaded into the Buffered/unbuffered reference input options input registers on the rising edge of WR. Output range: 0 V to V or 0 V to 2 × V REF REF Power-on reset to 0 V The GAIN pin allows the output range to be set at 0 V to VREF or Simultaneous update of DAC outputs via LDAC pin 0 V to 2 × VREF. Asynchronous CLR facility Input data to the DACs is double-buffered, allowing simultane- Low power parallel data interface ous update of multiple DACs in a system using the LDAC pin. On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +105°C An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. APPLICATIONS These devices also incorporate a power-on reset circuit that Portable battery-powered instruments ensures that the DAC output powers on to 0 V and remains Digital gain and offset adjustment there until valid data is written to the device. Programmable voltage and current sources The AD5330/AD5331/AD5340/AD5341 are available in thin Programmable attenuators shrink small outline packages (TSSOP). Industrial process control 1 Protected by U.S. Patent Number 5,969,657. FUNCTIONAL BLOCK DIAGRAM VREF VDD 3 12 POWER-ON RESET AD5330 BUF 1 GAIN 8 INPUT DAC REGISTER REGISTER DDBB..701230 OGIC 8D-ABICT BUFFER 4 VOUT L CS 6 CE A F WR 7 ER CLR 9 INT RESET POWER-DOWN LOGIC LDAC 10 P11D GN5D 06852-001 Figure 1. AD5330 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2000–2008 Analog Devices, Inc. All rights reserved.

AD5330/AD5331/AD5340/AD5341 TABLE OF CONTENTS Features .............................................................................................. 1 Double-Buffered Interface ........................................................ 18 Applications ....................................................................................... 1 Clear Input (CLR) ...................................................................... 18 General Description ......................................................................... 1 Chip Select Input (CS) ............................................................... 18 Functional Block Diagram .............................................................. 1 Write Input (WR) ....................................................................... 18 Revision History ............................................................................... 2 Load DAC Input (LDAC) .......................................................... 18 Specifications ..................................................................................... 3 High-Byte Enable Input (HBEN) ............................................. 18 AC Characteristics ........................................................................ 4 Power-On Reset .......................................................................... 18 Timing Characteristics ................................................................ 5 Power-Down Mode ........................................................................ 19 Absolute Maximum Ratings ............................................................ 6 Suggested Databus Formats .......................................................... 20 ESD Caution .................................................................................. 6 Applications Information .............................................................. 21 Pin Configurations and Function Descriptions ........................... 7 Typical Application Circuits ..................................................... 21 Terminology .................................................................................... 11 Driving V From the Reference Voltage ............................... 21 DD Typical Performance Characteristics ........................................... 13 Bipolar Operation Using the AD5330/AD5331/ Theory of Operation ...................................................................... 17 AD5340/AD5341 ......................................................................... 21 Digital-to-Analog Section ......................................................... 17 Decoding Multiple AD5330/AD5331/ AD5340/AD5341 .... 21 Resistor String ............................................................................. 17 Programmable Current Source ................................................ 22 DAC Reference Input ................................................................. 17 Power Supply Bypassing and Grounding ................................ 22 Output Amplifier ........................................................................ 17 Outline Dimensions ....................................................................... 24 Parallel Interface ............................................................................. 18 Ordering Guide .......................................................................... 25 REVISION HISTORY 2/08—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Table 4 .......................................................................... 16 Replaced Driving V from the Reference Voltage Section ..... 21 DD Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 25 4/00—Revision 0: Initial Version Rev. A | Page 2 of 28

AD5330/AD5331/AD5340/AD5341 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 2 V, R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD REF L L MIN MAX Table 1. B Version2 Parameter1 Min Typ Max Unit Conditions/Comments DC PERFORMANCE3, 4 AD5330 Resolution 8 Bits Relative Accuracy ±0.15 ±1 LSB Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5331 Resolution 10 Bits Relative Accuracy ±0.5 ±4 LSB Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5340/AD5341 Resolution 12 Bits Relative Accuracy ±2 ±16 LSBs Differential Nonlinearity ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 % of FSR Gain Error ±0.15 ±1 % of FSR Lower Deadband5 10 60 mV Lower deadband exists only if offset error is negative Upper Deadband 10 60 mV V = 5 V; upper deadband exists only if V = V DD REF DD Offset Error Drift6 −12 ppm of FSR/°C Gain Error Drift6 −5 ppm of FSR/°C DC Power Supply Rejection Ratio6 −60 dB ΔV = ±10% DD DAC REFERENCE INPUT6 V Input Range 1 V V Buffered reference (AD5330, AD5340, and AD5341) REF DD 0.25 V V Unbuffered reference DD V Input Impedance >10 MΩ Buffered reference (AD5330, AD5340, and AD5341) REF 180 kΩ Unbuffered reference; gain = 1, input impedance = R DAC 90 kΩ Unbuffered reference; gain = 2, input impedance = R DAC Reference Feedthrough −90 dB Frequency = 10 kHz OUTPUT CHARACTERISTICS6 Minimum Output Voltage4, 7 0.001 V min Rail-to-rail operation Maximum Output Voltage4, 7 V − 0.001 V max DD DC Output Impedance 0.5 Ω Short-Circuit Current 25 mA V = 5 V DD 15 mA V = 3 V DD Power-Up Time 2.5 μs Coming out of power-down mode; V = 5 V DD 5 μs Coming out of power-down mode; V = 3 V DD LOGIC INPUTS6 Input Current ±1 μA Input Low Voltage, V 0.8 V V = 5 V ± 10% IL DD 0.6 V V = 3 V ± 10% DD 0.5 V V = 2.5 V DD Input High Voltage, V 2.4 V V = 5 V ± 10% IH DD 2.1 V V = 3 V ± 10% DD 2.0 V V = 2.5 V DD Pin Capacitance 3 pF Rev. A | Page 3 of 28

AD5330/AD5331/AD5340/AD5341 B Version2 Parameter1 Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS V 2.5 5.5 V DD I (Normal Mode) DACs active and excluding load currents. Unbuffered DD V = 4.5 V to 5.5 V 140 250 μA Reference, V = V , V = GND DD IH DD IL V = 2.5 V to 3.6 V 115 200 μA I increases by 50 μA at V > V − 100 mV. DD DD REF DD In buffered mode, extra current is (5 + V /R ) μA, REF DAC where R is the resistance of the resistor string. DAC I (Power-Down Mode) DD V = 4.5 V to 5.5 V 0.2 1 μA DD V = 2.5 V to 3.6 V 0.08 1 μA DD 1 See the Terminology section. 2 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. 3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095). 4 DC specifications tested with output unloaded. 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization, not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. AC CHARACTERISTICS1 V = 2.5 V to 5.5 V. R = 2 kΩ to GND, C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD L L MIN MAX Table 2. B Version3 Parameter2 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time V = 2 V; see Figure 29 REF AD5330 6 8 μs ¼ scale to ¾ scale change (0x40 to 0xC0) AD5331 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5340 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) AD5341 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major Code Transition Glitch Energy 6 nV/s 1 LSB change around major carry Digital Feedthrough 0.5 nV/s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p; unbuffered mode REF Total Harmonic Distortion −70 dB V = 2.5 V ± 0.1 V p-p; frequency = 10 kHz REF 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range: B Version: −40°C to +105°C; typical specifications are at 25°C. Rev. A | Page 4 of 28

AD5330/AD5331/AD5340/AD5341 TIMING CHARACTERISTICS1, 2, 3 V = 2.5 V to 5.5 V, all specifications T to T , unless otherwise noted. DD MIN MAX Table 3. Parameter Limit at T , T Unit Condition/Comments MIN MAX t 0 ns min CS to WR setup time. 1 t 0 ns min CS to WR hold time. 2 t 20 ns min WR pulse width. 3 t 5 ns min Data, GAIN, BUF, HBEN setup time. 4 t 4.5 ns min Data, GAIN, BUF, HBEN hold time. 5 t 5 ns min Synchronous mode; WR falling to LDAC falling. 6 t 5 ns min Synchronous mode; LDAC falling to WR rising. 7 t 4.5 ns min Synchronous mode; WR rising to LDAC rising. 8 t 5 ns min Asynchronous mode; LDAC rising to WR rising. 9 t 4.5 ns min Asynchronous mode; WR rising to LDAC falling. 10 t 20 ns min LDAC pulse width. 11 t 20 ns min CLR pulse width. 12 t 50 ns min Time between WR cycles. 13 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. t t 1 2 CS t t 3 13 WR t DATA, t4 5 GAIN, BUF, HBEN t t t 8 6 7 LDAC1 t9 t10 t11 LDAC2 t 12 CLR N12SAOYSTNYECNSHC:RHORONONOUSU SL DLADCA CU PUDPADTAET EM MOODEDE 06852-002 Figure 2. Parallel Interface Timing Diagram Rev. A | Page 5 of 28

AD5330/AD5331/AD5340/AD5341 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 4. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect Digital Output Voltage to GND −0.3 V to V + 0.3 V DD device reliability. Reference Input Voltage to GND −0.3 V to V + 0.3 V DD V to GND −0.3 V to V + 0.3 V OUT DD Operating Temperature Range ESD CAUTION Industrial (B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C TSSOP Package Power Dissipation (TJ max – TA)/θJA mW θJA Thermal Impedance (20-Lead TSSOP)1 85°C/W θ Thermal Impedance (24-Lead TSSOP)1 80°C/W JA Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec 1 Thermal resistance (JEDEC 4-layer (2S2P) board). Rev. A | Page 6 of 28

AD5330/AD5331/AD5340/AD5341 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VREF VDD 3 12 POWER-ON RESET AD5330 BUF 1 BUF 1 20 DB7 GAIN 8 INPUT DAC DDCBB..S70 12630 ACE LOGIC REGISTER REGISTER 8D-ABICT BUFFER 4 VOUT VVGORNNUECDFT 2345 TAOD8P-5B V3IITE3W0 11119876 DDDDBBBB6543 F (Not to Scale) WR 7 ER CS 6 15 DB2 CLR 9 INT RESET POWER-DOWN WR 7 14 DB1 LOGIC GAIN 8 13 DB0 LDAC 10 CLR 9 12 VDD P11D GN5D 06852-003 LDAC 10NC = NO CONNECT11 PD 06852-004 Figure 3. AD5330 Functional Block Diagram Figure 4. AD5330 Pin Configuration Table 5. AD5330 Pin Function Descriptions Pin No. Mnemonic Description 1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 2 NC No Connect. 3 V Reference Input. REF 4 V Output of DAC. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 V Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB to DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 Rev. A | Page 7 of 28

AD5330/AD5331/AD5340/AD5341 VREF VDD 3 12 POWER-ON RESET AD5331 DB8 1 DB9 2 GDAB..IN7280 OGIC REINGPISUTTER REGDIASCTER 1D0-ABCIT BUFFER 4 VOUT DDBB89 21 1290 DDBB76 DB013 CE L VREF 3 18 DB5 CS 6 RFA VOUT 4 A1D05-B3IT31 17 DB4 CWLRR 97 INTE RESET POWER-DOWN GNCDS 56 (NToOt Pto V SIEcaWle) 1165 DDBB32 LOGIC WR 7 14 DB1 LDAC 10 GAIN 8 13 DB0 P11D GN5D 06852-005 LDCALCR 190 1121 VPDDD 06852-006 Figure 5. AD5331 Functional Block Diagram Figure 6. AD5331 Pin Configuration Table 6. AD5331 Pin Function Descriptions Pin No. Mnemonic Description 1 DB Parallel Data Input. 8 2 DB Most Significant Bit of Parallel Data Input. 9 3 V Unbuffered Reference Input. REF 4 V Output of DAC. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 9 CLR Active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 V Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB to DB Eight Parallel Data Inputs. 0 7 Rev. A | Page 8 of 28

AD5330/AD5331/AD5340/AD5341 VREF VDD 4 14 POWER-ON RESET AD5340 DB10 1 GDBDDABCUBB..I1NSF190121823540 FACE LOGIC REINGPISUTTER REGDIASCTER 1D2-ABCIT BUFFER 5 VOUT VDDVBOBBRUUE11FFT01 12345 A1D25-B3IT40 2222243210 DDDDDBBBBB76589 ER NC 6 TOP VIEW 19 DB4 WR 9 INT RESET GND 7 (Not to Scale) 18 DB3 CLR11 POWER-DOWN CS 8 17 DB2 LOGIC LDAC 12 WR 9 16 DB1 GAIN 10 15 DB0 P13D GN7D 06852-007 LDCALCR 1112 1143 VPDDD 06852-008 Figure 7. AD5340 Functional Block Diagram Figure 8. AD5340 Pin Configuration Table 7. AD5340 Pin Function Descriptions Pin No. Mnemonic Description 1 DB Parallel Data Input. 10 2 DB Most Significant Bit of Parallel Data Input. 11 3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 4 V Reference Input. REF 5 V Output of DAC. Buffered output with rail-to-rail operation. OUT 6 NC No Connect. 7 GND Ground reference point for all circuitry on the part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 11 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 12 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 13 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 14 V Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 15 to 24 DB to DB Ten Parallel Data Inputs. 0 9 Rev. A | Page 9 of 28

AD5330/AD5331/AD5340/AD5341 VREF VDD 3 12 POWER-ON RESET AD5341 HIGH BYTE BUF 2 REGISTER R GDDABB..IN70 12830 LOGIC LROEWGI SBTYETRE DACREGISTE 1D2-ABCIT BUFFER 4 VOUT HVBBREUENFF 231 112980 DDDBBB765 HBEN 1 ACE VOUT 4 A1D05-B3IT41 17 DB4 WCRS 76 INTERF RESET POWER-DOWN GNCDS 56 (NToOt Pto V SIEcaWle) 1165 DDBB32 LOGIC WR 7 14 DB1 CLR 9 GAIN 8 13 DB0 LDAC 10 P11D GN5D 06852-009 LDCALCR 190 1121 VPDDD 06852-010 Figure 9. AD5341 Functional Block Diagram Figure 10. AD5341 Pin Configuration Table 8. AD5341 Pin Function Descriptions Pin No. Mnemonic Description 1 HBEN High Byte Enable Pin. This pin is used when writing to the device to determine if data is written to the high byte register or the low byte register. 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3 V Reference Input. REF 4 V Output of DAC. Buffered output with rail-to-rail operation. OUT 5 GND Ground reference point for all circuitry on the part. 6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0 V to V or 0 V to 2 × V . REF REF 9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 V Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a DD 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 13 to 20 DB to DB Eight Parallel Data Inputs. DB is the MSB of these eight bits. 0 7 7 Rev. A | Page 10 of 28

AD5330/AD5331/AD5340/AD5341 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) GAIN ERROR For the DAC, relative accuracy or INL is a measure of the AND OFFSET ERROR maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 14, Figure 15, and Figure 16. Differential Nonlinearity (DNL) OUTPUT VOLTAGE ACTUAL DNL is the difference between the measured change and the IDEAL ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures mono- tonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 17, Figure 18, and Figure 19. POSITIVE Gain Error OFFSET DAC CODE 06852-012 This is a measure of the span error of the DAC (including any Figure 12. Positive Offset Error and Gain Error error in the gain of the buffer amplifier). It is the deviation in slope of the actual DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range. This is illustrated in Figure 11. GAIN ERROR AND Offset Error OFFSET ERROR This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. OUTPUT VOLTAGE If the offset voltage is positive, the output voltage is still positive at zero input code. This is shown in Figure 12. Because the ACTUAL DACs operate from a single supply, a negative offset cannot IDEAL appear at the output of the buffer amplifier. Instead, there is a code close to zero at which the amplifier output saturates (amplifier footroom). Below this code, there is a deadband over NEGATIVE which the output voltage does not change. This is illustrated in OFFSET DAC CODE Figure 13. POSITIVE GAIN ERROR NEGATIVE GAIN ERROR DEADBAND CODES AMPLIFIER OUTPUT FOOTROOM VOLTAGE ACTUAL (~1mV) IDEAL NEGATIVE OFFSET DAC CODE 06852-011 Figure 13. Negative Offset Error and Gain Error 06852-013 Figure 11. Gain Error Rev. A | Page 11 of 28

AD5330/AD5331/AD5340/AD5341 Offset Error Drift Digital Feedthrough This is a measure of the change in offset error with changes in Digital Feedthrough is a measure of the impulse injected into temperature. It is expressed in (ppm of full-scale range)/°C. the analog output of the DAC from the digital input pins of the device; it is measured when the DAC is not being written to (CS Gain Error Drift This is a measure of the change in gain error with changes in held high). It is specified in nV/s and is measured with a full- temperature. It is expressed in (ppm of full-scale range)/°C. scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. Power-Supply Rejection Ratio (PSRR) Multiplying Bandwidth This indicates how the output of the DAC is affected by changes The amplifiers within the DAC have a finite bandwidth. The in the supply voltage. PSRR is the ratio of the change in V to OUT multiplying bandwidth is a measure of this. A sine wave on the a change in V for full-scale output of the DAC. It is measured DD in decibels. V is held at 2 V and V is varied ±10%. reference (with a full-scale code loaded to the DAC) appears on REF DD the output. The multiplying bandwidth is the frequency at Reference Feedthrough which the output amplitude falls to 3 dB below the input. This is the ratio of the amplitude of the signal at the DAC Total Harmonic Distortion (THD) output to the reference input when the DAC output is not being This is the difference between an ideal sine wave and its atte- updated (that is, LDAC is high). It is expressed in decibels. nuated version using the DAC. The sine wave is used as the Major-Code Transition Glitch Energy reference for the DAC and THD is a measure of the harmonics Major-code transition glitch energy is the energy of the impulse present on the DAC output. It is measured in decibels. injected into the analog output when the DAC changes state. It is normally specified as the area of the glitch in nV/s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 … 11 to 100 … 00 or 100 … 00 to 011 … 11). Rev. A | Page 12 of 28

AD5330/AD5331/AD5340/AD5341 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 VTAD D= =2 55°VC TVAD D= =2 55°VC 0.2 0.5 Bs) Bs) 0.1 R (LS R (LS O 0 O 0 R R R R INL E DNL E –0.1 –0.5 –0.2 –1.0 –0.3 0 50 100 CODE150 200 250 06852-015 0 50 100 CODE150 200 250 06852-018 Figure 14. AD5330 Typical INL Plot Figure 17. AD5330 Typical DNL Plot 3 0.6 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 2 0.4 Bs) 1 Bs) 0.2 S S R (L R (L O 0 O 0 R R R R E E INL –1 DNL –0.2 –2 –0.4 –30 200 400 CODE500 800 1000 06852-016 –0.60 200 400 CODE600 800 1000 06852-019 Figure 15. AD5331 Typical INL Plot Figure 18. AD5331 Typical DNL Plot 12 1.0 TA = 25°C VDD = 5V TA = 25°C 8 VDD = 5V 0.5 Bs) 4 Bs) S S R (L R (L O 0 O 0 R R R R E E INL –4 DNL –0.5 –8 –120 1000 2C0O0D0E 3000 4000 06852-017 –1.00 1000 2C0O0D0E 3000 4000 06852-020 Figure 16. AD5340/AD5341 Typical INL Plot Figure 19. AD5340/AD5341 Typical DNL Plot Rev. A | Page 13 of 28

AD5330/AD5331/AD5340/AD5341 1.00 0.2 TA = 25°C 0.75 VDD = 5V 0.1 TVAR E=F 2=5 °2CV 0.50 0 GAIN ERROR R (LSBs) 0.250 MMAAXX DINNLL OR (%) ––00..12 O MIN DNL R R R ER –0.25 MIN INL E –0.3 –0.50 –0.4 OFFSET ERROR –0.75 –0.5 –1.002 3 VREF (V) 4 5 06852-021 –0.60 1 2 VDD3 (V) 4 5 6 06852-024 Figure 20. AD5330 INL and DNL Error vs. VREF Figure 23. Offset Error and Gain Error vs. VDD 1.00 5 VDD = 5V VREF = 3V 0.75 5V SOURCE 4 0.50 MAX DNL MAX INL 3V SOURCE Bs) 0.25 3 R (LS 0 (V)UT O O R V ER –0.25 2 MIN INL MIN DNL –0.50 1 5V SINK 3V SINK –0.75 –1.00 0 –40 0 TEMPERA40TURE (°C) 80 120 06852-022 0 1 SINK2/SOURCE 3CURRENT4 (mA) 5 6 06852-025 Figure 21. AD5330 INL Error and DNL Error vs. Temperature Figure 24. VOUT Source and Sink Current Capability 1.0 300 VDD = 5V TA = 25°C VREF = 2V VREF = 2V 250 0.5 VDD = 5.5V 200 GAIN ERROR %) ERROR ( 0 I (µA)DD 150 VDD = 3.6V 100 OFFSET ERROR –0.5 50 –1.0–40 0 TEMPERA40TURE (°C) 80 120 06852-023 0ZERO-SCALE DAC CODE FULL-SCALE06852-026 Figure 22. AD5330 Offset Error and Gain Error vs. Temperature Figure 25. Supply Current vs. DAC Code Rev. A | Page 14 of 28

AD5330/AD5331/AD5340/AD5341 300 TA = 25°C TA = 25°C VDD = 5V CH2 200 5V CLK A) µ (D D I 100 VOUT CH1 1V 0 2.5 3.0 3.5 VD4D.0 (V) 4.5 5.0 5.5 06852-027 TIME BASE = 5µs/DIV 06852-030 Figure 26. Supply Current vs. Supply Voltage Figure 29. Half-Scale Settling (¼ to ¾ Scale Code Change) 0.5 TA = 25°C TA = 25°C 0.4 VDD = 5V VREF = 2V CH1 2V VDD 0.3 A) µ (D D I 0.2 VOUTA 0.1 CH2 200mV 0 2.5 3.0 3.5 VD4D.0 (V) 4.5 5.0 5.5 06852-028 TIME BASE = 200µs/DIV 06852-031 Figure 27. Power-Down Current vs. Supply Voltage Figure 30. Power-On Reset to 0 V 1800 TA = 25°C 1600 TA = 25°C VDD = 5V 1400 VREF = 2V CH1 1200 500mV VDD = 5V µA) 1000 VOUTA (D D 800 I 600 400 PD CH2 5V 200 VDD = 3V 0 0 1 2 VLOGIC3(V) 4 5 06852-029 TIME BASE = 1µs/DIV 06852-032 Figure 28. Supply Current vs. Logic Input Voltage Figure 31. Exiting Power-Down to Midscale Rev. A | Page 15 of 28

AD5330/AD5331/AD5340/AD5341 10 0 –10 VDD = 3V Y NC VDD = 5V –20 UE B) REQ (d –30 F –40 –50 80 90 100 110 120 130IDD1 (4µ0A)150 160 170 180 190 200 06852-033 –600.01 0.1 1FREQUE1N0CY (kHz1)00 1k 10k 06852-035 Figure 32. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 34. Multiplying Bandwidth (Small-Signal Frequency Response) 0.4 0.917 TA = 25°C 0.916 VDD = 5V 0.915 R) 0.914 S F 0.913 % 0.2 R ( 0.912 O R LTS 00..991101 E ER O L V 0.909 CA 0.908 L-S 0 L 0.907 FU 0.906 0.905 0.904 –0.2 0.903 250ns/DIV 06852-034 0 1 2 VREF (V) 3 4 5 06852-036 Figure 33. AD5340 Major-Code Transition Glitch Energy Figure 35. Full-Scale Error vs. VREF Rev. A | Page 16 of 28

AD5330/AD5331/AD5340/AD5341 THEORY OF OPERATION The AD5330/AD5331/AD5340/AD5341 are single resistor- VREF string DACs fabricated on a CMOS process with resolutions R of 8, 10, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to R 5.5 V and the output buffer amplifiers offer rail-to-rail output TO OUTPUT swing. The AD5330, AD5340, and AD5341 have a reference R AMPLIFIER input that can be buffered to draw virtually no current from the reference source. The reference input of the AD5331 is unbuffered. The devices have a power-down feature that R reduces current consumption to only 80 nA @ 3 V. DIGITAL-TO-ANALOG SECTION R The architecture of one DAC channel consists of a reference 06852-038 buffer and a resistor-string DAC followed by an output buffer Figure 37. Resistor String amplifier. The voltage at the V pin provides the reference REF DAC REFERENCE INPUT voltage for the DAC. Figure 36 shows a block diagram of the DAC architecture. Because the input coding to the DAC is There is a reference input pin for the DAC. The reference straight binary, the ideal output voltage is given by input is buffered on the AD5330, AD5340, and AD5341 but can be configured as unbuffered also. The reference input of D V =V × ×Gain the AD5331 is unbuffered. The buffered/unbuffered option is OUT REF 2N controlled by the BUF pin. where: In buffered mode (BUF = 1), the current drawn from an D is the decimal equivalent of the binary code, which is loaded external reference voltage is virtually zero because the to the DAC register: impedance is at least 10 MΩ. The reference input range is 0 to 255 for AD5330 (8 Bits) 1 V to 5 V with a 5 V supply. 0 to 1023 for AD5331 (10 Bits) In unbuffered mode (BUF = 0), the user can have a reference 0 to 4095 for AD5340/AD5341 (12 Bits) voltage as low as 0.25 V and as high as V because there is no DD N is the DAC resolution. restriction due to headroom and footroom of the reference Gain is the output amplifier gain (1 or 2). amplifier. The impedance is still large at typically 180 kΩ for VREF 0 V to VREF mode and 90 kΩ for 0 V to 2 × VREF mode. If there is an external buffered reference (for example, REF192), there is no need to use the on-chip buffer. REFERENCE BUF BUFFER OUTPUT AMPLIFIER GAIN The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends INPUT DAC RESISTOR REGISTER REGISTER STRING VOUT on V , GAIN, the load on V , and offset error. REF OUT BUFFEORU TAPMUPTLIFIER 06852-037 Itof aV gain. of 1 is selected (GAIN = 0), the output range is 0.001 V Figure 36. Single DAC Channel Architecture REF RESISTOR STRING If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 × V . However, because of clamping, the maximum REF The resistor-string section is shown in Figure 37. It is simply a output is limited to V – 0.001 V. DD string of resistors, each of value R. The digital code loaded to The output amplifier is capable of driving a load of 2 kΩ to the DAC register determines at what node on the string the GND or 2 kΩ to V in parallel with 500 pF to GND or 500 pF voltage is tapped off to be fed into the output amplifier. The DD to V . The source and sink capabilities of the output amplifier voltage is tapped off by closing one of the switches connecting DD can be seen in Figure 24. the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 μs with the output unloaded (see Figure 29). Rev. A | Page 17 of 28

AD5330/AD5331/AD5340/AD5341 PARALLEL INTERFACE LOAD DAC INPUT (LDAC) The AD5330, AD5331, and AD5340 load their data as a single 8-, 10-, or 12-bit word, while the AD5341 loads data as a low LDAC transfers data from the input register to the DAC register byte of eight bits and a high byte containing four bits. (and therefore updates the outputs). Use of the LDAC function DOUBLE-BUFFERED INTERFACE enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes: synchronous mode and The AD5330/AD5331/AD5340/AD5341 DACs all have double- asynchronous mode. buffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the In synchronous mode, the DAC register is updated after new input register under the control of chip select (CS) and write (WR). data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed, as shown in Figure 2. Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input In asynchronous mode, the outputs are not updated at the same register may change state without affecting the contents of the time that the input register is written to. When LDAC goes low, DAC register. However, when LDAC is brought low, the DAC the DAC register is updated with the contents of the input register becomes transparent and the contents of the input register. register are transferred to it. The gain and buffer control signals HIGH BYTE ENABLE INPUT (HBEN) are also double-buffered and are only updated when LDAC is High byte enable is a control input on the AD5341 only. It taken low. determines if data is written to the high byte input register Double-buffering is also useful where the DAC data is loaded or the low byte input register. in two bytes, as in the AD5341, because it allows the whole The low data byte of the AD5341 consists of Data Bits [0:7] data word to be assembled in parallel before updating the DAC at the data inputs DB to DB, whereas the high byte consists 0 7 register. This prevents spurious outputs that can occur if the DAC of Data Bits [8:11] at the data inputs DB to DB, as shown in 0 3 register is updated with only the high byte or the low byte. Figure 38. DB to DB are ignored during a high byte write, but 4 7 These parts contain an extra feature whereby the DAC register they can be used for data to set up the reference input as buffered/ is not updated unless its input register has been updated since unbuffered, and buffer amplifier gain (see Figure 42). the last time that LDAC was brought low. Normally, when HIGH BYTE LDAC is brought low, the DAC register is filled with the X X X X DB11 DB10 DB9 DB8 contents of the input register. In the case of the AD5330/ AD5331/AD5340/AD5341, the parts only update the DAC LOW BYTE rthege iDstAerC i fr ethgies tienrp wuat sr eugpidstaeter dh. aTsh bise ernem chovaensg uendn seincecses athrye clarosts sttiamlke. X =D UBN7USEDD BB6IT DB5 DB4 DB3 DB2 DB1 DB0 06852-039 Figure 38. Data Format for AD5341 CLEAR INPUT (CLR) POWER-ON RESET CLR is an active low, asynchronous clear that resets the input and DAC registers. The AD5330/AD5331/AD5340/AD5341 are provided with a power-on reset function, so that they power up in a defined CHIP SELECT INPUT (CS) state. The power-on state is CS is an active low input that selects the device. • Normal operation WRITE INPUT (WR) • Reference input unbuffered • 0 V to V output range WR is an active low input that controls writing of data to the REF • Output voltage set to 0 V device. Data is latched into the input register on the rising edge of WR. Both input and DAC registers are filled with zeros and remain as such until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Rev. A | Page 18 of 28

AD5330/AD5331/AD5340/AD5341 POWER-DOWN MODE The AD5330/AD5331/AD5340/AD5341 have low power consumption, dissipating only 0.35 mW with a 3 V supply and SRTERSINISGT DOARC AMPLIFIER VOUT 0.7 mW with a 5 V supply. Power consumption can be further reduced when the DAC is not in use by putting it into power- down mode, which is selected by taking Pin PD low. POCWIRECRU-IDTORWYN 06852-040 Figure 39. Output Stage During Power-Down When the PD pin is high, the DAC works normally with a typical power consumption of 140 μA at 5 V (115 μA at 3 V). The bias generator, the output amplifier, the resistor string, and In power-down mode, however, the supply current falls to all other associated linear circuitry are shut down when the 200 nA at 5 V (80 nA at 3 V) when the DAC is powered down. power-down mode is activated. However, the contents of the Not only does the supply current drop, but the output stage registers are unaffected when in power-down. The time to exit is also internally switched from the output of the amplifier, power-down is typically 2.5 μs for V = 5 V and 5 μs when DD making it open-circuit. This has the advantage that the output V = 3 V. This is the time from a rising edge on the PD pin to DD is three-state while the part is in power-down mode and provides when the output voltage deviates from its power-down voltage a defined input condition for whatever is connected to the (see Figure 31). output of the DAC amplifier. The output stage is illustrated in Figure 39. Table 9. AD5330/AD5331/AD5340 Truth Table1 CLR LDAC CS WR Function 1 1 1 X No data transfer 1 1 X 1 No data transfer 0 X X X Clear all registers 1 1 0 0→1 Load input register 1 0 0 0→1 Load input register and DAC register 1 0 X X Update DAC register 1 X = don’t care. Table 10. AD5341 Truth Table1 CLR LDAC CS WR HBEN Function 1 1 1 X X No data transfer 1 1 X 1 X No data transfer 0 X X X X Clear all registers 1 1 0 0→1 0 Load low byte input register 1 1 0 0→1 1 Load high byte input register 1 0 0 0→1 0 Load low byte input register and DAC register 1 0 0 0→1 1 Load high byte input register and DAC register 1 0 X X X Update DAC register 1 X = don’t care. Rev. A | Page 19 of 28

AD5330/AD5331/AD5340/AD5341 SUGGESTED DATABUS FORMATS The AD5341 is a 12-bit device that uses byte load, so only four In most applications, GAIN and BUF are hard-wired. However, bits of the high byte are actually used as data. Two of the unused if more flexibility is required, they can be included in a databus. bits can be used for GAIN and BUF data by connecting them to This enables the user to software program GAIN, giving the the GAIN and BUF inputs; for example, Bit 6 and Bit 7, as option of doubling the resolution in the lower half of the DAC shown in Figure 41 and Figure 42. range. In a bused system, GAIN and BUF can be treated as data inputs because they are written to the device during a write operation and take effect when LDAC is taken low. This means 8-BIT DATA that the reference buffers and the output amplifier gain of DATA BUS DB6 DB7 INPUTS multiple DAC devices can be controlled using common GAIN BUF AD5341 and BUF lines. GAIN LDAC In the case of the AD5330, this means that the databus must be CLR wider than eight bits. The AD5331 and AD5340 databuses must CS be at least 10 bits and 12 bits wide, respectively, and are best WR suited to a 16-bit databus system. HBEN 06852-042 Examples of data formats for putting GAIN and BUF on a Figure 41. AD5341 Data Format for Byte Load with GAIN and BUF Data on 8-Bit Bus 16-bit databus are shown in Figure 40. Note that any unused bits above the actual DAC data can be used for BUF and GAIN. DAC In this case, the low byte is written to first in a write operation devices can be controlled using common GAIN and BUF lines. with HBEN = 0. Bit 6 and Bit 7 of DAC data are written into AD5330 GAIN and BUF registers but have no effect. The high byte is BUFGAIN X X X X X X DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 then written to. Only the lower four bits of data are written into AD5331 the DAC high byte register, so Bit 6 and Bit 7 can be GAIN and BUFGAIN X X X X DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BUF data. AD5340 XB U= FUNGUASINED XBIT X DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 06852-041 LDAC is used to update theH IDGHA BCY,T GEAIN, and BUF values. Figure 40. GAIN and BUF Data on a 16-Bit Bus BUF GAIN X X DB11 DB10 DB9 DB8 LOW BYTE X =D UBN7USED DBBIT6 DB5 DB4 DB3 DB2 DB1 DB0 06852-043 Figure 42. AD5341 with GAIN and BUF Data on 8-Bit Bus Rev. A | Page 20 of 28

AD5330/AD5331/AD5340/AD5341 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUITS BIPOLAR OPERATION USING THE AD5330/AD5331/ AD5340/AD5341 The AD5330/AD5331/AD5340/AD5341 can be used with a wide range of reference voltages, especially if the reference The AD5330/AD5331/AD5340/AD5341 are designed for inputs are configured to be unbuffered, in which case the single-supply operation, but bipolar operation is achievable devices offer full, one-quadrant multiplying capability over a using the circuit shown in Figure 45. The circuit shown has reference range of 0.25 V to VDD. More typically, these devices been configured to achieve an output voltage range of –5 V < can be used with a fixed, precision reference voltage. Figure 43 V < +5 V. Rail-to-rail operation at the amplifier output is O shows a typical setup for the devices when using an external achievable using an AD820 or OP295 as the output amplifier. reference connected to the unbuffered reference inputs. If the The output voltage for any input code can be calculated as follows: reference inputs are unbuffered, the reference input range is V = [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V × D/2N)] – from 0.25 V to V , but if the on-chip reference buffers are O REF DD R4 × V /R3 used, the reference range is reduced. Suitable references for 5 V REF operation are the AD780 and REF192. For 2.5 V operation, a where: suitable external reference is the AD589, a 1.23 V band gap D is the decimal equivalent of the code loaded to the DAC. reference. N is the DAC resolution. VDD = 2.5V TO 5.5V VREF is the reference voltage input. + with: 0.1µF 10µF V = 2.5 V. REF VIN R1 = R3 = 10 kΩ. ERXETF VOUT VREF VDD VOUT RV2O == R(140 = × 2 D0 /k2ΩN) a−n 5d. VDD = 5 V. GND AD5330/AD5331/ AD5340/AD5341 VDD = 5V R4 20kΩ AD780/REF192 + WITH VDD = 5V 0.1µF 10µF FAiDg5u8r9e W 43ITO. HAR DVD5D3 3= 02/.5AVD5331/AD5340/AD5341 UGsNinDg External Referenc06852-044e ERXETF VINVOUT VDD 10Rk3Ω +5V VO = ±5V VREF DRIVING V FROM THE REFERENCE VOLTAGE GND 0.1µF AD5330/AD5331/ –5V DD AD5340/AD5341 R1 AD780/REF192 10kΩ If an output range of 0 V to VDD is required, the simplest WITH VDD = 5V VOUT OR R2 solution is to connect the reference inputs to VDD. Because this AD589 WITH VDD = 2.5V 20kΩ scuanpp bley pmoawye nreodt bfreo vmer tyh aec rceuferraeten caen dvo mltaagye b, efo nro eixsya,m thpele d uesviincges GND 06852-046 a 5 V reference such as the ADP667, as shown in Figure 44. Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341 6V TO 16V DECODING MULTIPLE AD5330/AD5331/ + AD5340/AD5341 0.1µF 10µF The CS pin on these devices can be used in applications to VIN decode a number of DACs. In this application, all DACs in the ADP667 system receive the same data and WR pulses, but only CS to one VDD of the DACs is active at any one time, so data is only written to VOUT VREF VOUT the DAC whose CS is low. If multiple AD5341s are being used, a VSETGND SHDN 0.1µF AD5330/AD5331/ AD5340/AD5341 common HBEN line is also required to determine if the data is written to the high byte or low byte register of the selected DAC. The 74HC139 is used as a 2-line to 4-line decoder to address GND 06852-045 aennyab olfe tihnep uDtA sChos uinld t bhee bsyrostuegmh.t Ttoo iptrse ivneanctt itvime sitnagte e wrrhoirlse, tthhee Figure 44. Using an ADP667 as Power and Reference to coded address inputs are changing state. Figure 46 shows a AD5330/AD5331/AD5340/AD5341 diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in Rev. A | Page 21 of 28

AD5330/AD5331/AD5340/AD5341 a system, all the DACs can be updated simultaneously using a VDD = 5V common LDAC line. A common CLR line can also be used to + reset all DAC outputs to zero. 0.1µF 10µF VSOURCE AD5330/AD5331/ VIN AD5340/AD5341 HBEN* HBEN* ERXETF VOUT VREF VDD VOUT 5V LOAD WR WR DATA GND 0.1µF AD820/ LDAC LDAC INPUTS AD5330/AD5331/ OP295 CLR CLR AD5340/AD5341 CS AD780/REF192 WITH VDD = 5V AD5330/AD5331/ 4.7kΩ AD5340/AD5341 GND HBEN* 470Ω VDD LCWDLRARC INDPAUTTAS S 06852-048 CS BU Figure 47. Programmable Current Source VCC TA ENABLE G1 74HC1391Y0 AD5330/AD5331/ DA POWER SUPPLY BYPASSING AND GROUNDING CODED A1 1Y1 AD5340/AD5341 In any circuit where accuracy is important, careful consid- ADDRESS B1 1Y2 HBEN* eration of the power supply and ground return layout helps WR DATA DGND 1Y3 LDAC INPUTS to ensure the rated performance. The printed circuit board on CLR CS which the AD5330/AD5331/AD5340/AD5341 are mounted should be designed so that the analog and digital sections are AD5330/AD5331/ AD5340/AD5341 separated and confined to certain areas of the board. If the device is in a system where multiple devices require an AGND- HBEN* WR DATA to-DGND connection, the connection should be made at one LDAC INPUTS CLR point only. The star ground point should be established as *AD5341 ONLY CS 06852-047 cAloDs5e3ly4 0as/A pDos5s3ib4l1e sthoo tuhled d heavviec ea. mTphlee AsuDp5p3ly3 0b/yApDas5s3in3g1 /o f Figure 46. Decoding Multiple DAC Devices 10 μF in parallel with 0.1 μF on the supply located as close to PROGRAMMABLE CURRENT SOURCE the package as possible, ideally right up against the device. Figure 47 shows the AD5330/AD5331/AD5340/AD5341 used The 10 μF capacitors are the tantalum bead type. The 0.1 μF as the control element of a programmable current source. In capacitor should have low effective series resistance (ESR) and this example, the full-scale current is set to 1 mA. The output effective series inductance (ESI), like the common ceramic voltage from the DAC is applied across the current setting types that provide a low impedance path to ground at high resistor of 4.7 kΩ in series with the 470 Ω adjustment poten- frequencies to handle transient currents due to internal logic switching. tiometer, which gives an adjustment of about ±5%. Suitable transistors to place in the feedback loop of the amplifier include The power supply lines of the device should use as large a trace the BC107 and the 2N3904, which enable the current source to as possible to provide low impedance paths and reduce the operate from a minimum VSOURCE of 6 V. The operating range is effects of glitches on the power supply line. Fast switching determined by the operating characteristics of the transistor. signals such as clocks should be shielded with digital ground Suitable amplifiers include the AD820 and the OP295, both to avoid radiating noise to other parts of the board, and should having rail-to-rail operation on their outputs. The current for never be run near the reference inputs. Avoid crossover of any digital input code and resistor value can be calculated as digital and analog signals. Traces on opposite sides of the board follows: should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by D I=G×V × mA REF (2N ×R) far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to where: the ground plane while signal traces are placed on the solder side. G is the gain of the buffer amplifier (1 or 2). D is the digital equivalent of the digital input code. N is the DAC resolution (8, 10, or 12 bits). R is the sum of the resistor plus adjustment potentiometer in kilo ohms. Rev. A | Page 22 of 28

AD5330/AD5331/AD5340/AD5341 Table 11. Overview of AD53xx Parallel Devices Additional Pin Functions Part No. Resolution Bits DNL No. of V Pins Settling Time BUF GAIN HBEN CLR Package No. of Pins REF Singles AD5330 8 ±0.25 1 6 μs BUF GAIN CLR TSSOP 20 AD5331 10 ±0.5 1 7 μs GAIN CLR TSSOP 20 AD5340 12 ±1.0 1 8 μs BUF GAIN CLR TSSOP 24 AD5341 12 ±1.0 1 8 μs BUF GAIN HBEN CLR TSSOP 20 Duals AD5332 8 ±0.25 2 6 μs CLR TSSOP 20 AD5333 10 ±0.5 2 7 μs BUF GAIN CLR TSSOP 24 AD5342 12 ±1.0 2 8 μs BUF GAIN CLR TSSOP 28 AD5343 12 ±1.0 1 8 μs HBEN CLR TSSOP 20 Quads AD5334 8 ±0.25 2 6 μs GAIN CLR TSSOP 24 AD5335 10 ±0.5 2 7 μs HBEN CLR TSSOP 24 AD5336 10 ±0.5 4 7 μs GAIN CLR TSSOP 28 AD5344 12 ±1.0 4 8 μs TSSOP 28 Table 12. Overview of AD53xx Serial Devices Part No. Resolution Bits No. of DACs DNL Interface Settling Time Package No of Pins Singles AD5300 8 1 ±0.25 SPI 4 μs SOT-23, MSOP 6, 8 AD5310 10 1 ±0.5 SPI 6 μs SOT-23, MSOP 6, 8 AD5320 12 1 ±1.0 SPI 8 μs SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-Wire 6 μs SOT-23, MSOP 6, 8 AD5311 10 1 ±0.5 2-Wire 7 μs SOT-23, MSOP 6, 8 AD5321 12 1 ±1.0 2-Wire 8 μs SOT-23, MSOP 6, 8 Duals AD5302 8 2 ±0.25 SPI 6 μs MSOP 10 AD5312 10 2 ±0.5 SPI 7 μs MSOP 10 AD5322 12 2 ±1.0 SPI 8 μs MSOP 10 AD5303 8 2 ±0.25 SPI 6 μs TSSOP 16 AD5313 10 2 ±0.5 SPI 7 μs TSSOP 16 AD5323 12 2 ±1.0 SPI 8 μs TSSOP 16 Quads AD5304 8 4 ±0.25 SPI 6 μs MSOP, LFCSP 10 AD5314 10 4 ±0.5 SPI 7 μs MSOP, LFCSP 10 AD5324 12 4 ±1.0 SPI 8 μs MSOP, LFCSP 10 AD5305 8 4 ±0.25 2-Wire 6 μs MSOP 10 AD5315 10 4 ±0.5 2-Wire 7 μs MSOP 10 AD5325 12 4 ±1.0 2-Wire 8 μs MSOP 10 AD5306 8 4 ±0.25 2-Wire 6 μs TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 μs TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 μs TSSOP 16 AD5307 8 4 ±0.25 SPI 6 μs TSSOP 16 AD5317 10 4 ±0.5 SPI 7 μs TSSOP 16 AD5327 12 4 ±1.0 SPI 8 μs TSSOP 16 Rev. A | Page 23 of 28

AD5330/AD5331/AD5340/AD5341 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 48. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 49. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters Rev. A | Page 24 of 28

AD5330/AD5331/AD5340/AD5341 ORDERING GUIDE Model Temperature Range Package Description Package Option AD5330BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRUZ1 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRUZ-REEL1 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5330BRUZ-REEL71 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRUZ1 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRUZ-REEL1 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5331BRUZ-REEL71 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5340BRU –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRU-REEL –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRU-REEL7 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRUZ1 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRUZ-REEL1 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5340BRUZ-REEL71 –40°C to +105°C 24-Lead Thin Shrink Small Outline Package [TSSOP] RU-24 AD5341BRU –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRU-REEL –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRU-REEL7 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRUZ1 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRUZ-REEL1 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 AD5341BRUZ-REEL71 –40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20 1 Z = RoHS Compliant Part. Rev. A | Page 25 of 28

AD5330/AD5331/AD5340/AD5341 NOTES Rev. A | Page 26 of 28

AD5330/AD5331/AD5340/AD5341 NOTES Rev. A | Page 27 of 28

AD5330/AD5331/AD5340/AD5341 NOTES ©2000–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06852-0-2/08(A) Rev. A | Page 28 of 28