2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail Voltage Output 10-/12-Bit DACs Data Sheet AD5313/AD5323 FEATURES GENERAL DESCRIPTION AD5313: 2 buffered 10-bit DACs in 1 package The AD5313/AD5323 are dual, 10-/12-bit buffered voltage output A version: ±4 LSB INL, B version: ±2 LSB INL DACs in a 16-lead TSSOP package that operate from a single AD5323: 2 buffered 12-bit DACs in 1 package 2.5 V to 5.5 V supply, consuming 230 μA at 3 V. Their on-chip A version: ±16 LSB INL, B version: ±8 LSB INL output amplifiers allow the outputs to swing rail to rail with a slew 16-lead TSSOP package rate of 0.7 V/μs. The AD5313/AD5323 utilize a versatile 3-wire Micropower operation: 300 μA at 5 V (including reference serial interface that operates at clock rates up to 30 MHz and is current) compatible with standard SPI, QSPI™, MICROWIRE™, and DSP Power-down to 200 nA at 5 V, 50 nA at 3 V interface standards. 2.5 V to 5.5 V power supply The references for the two DACs are derived from two reference Double-buffered input logic pins (one per DAC). These reference inputs can be configured Guaranteed monotonic by design over all codes as buffered or unbuffered inputs. The devices incorporate a power- Buffered/unbuffered reference input options on reset circuit, which ensures that the DAC outputs power up Output range: 0 V to V or 0 V to 2 V REF REF to 0 V and remain there until a valid write to the device takes Power-on reset to 0 V place. There is also an asynchronous active low CLR pin that SDO daisy-chaining option Simultaneous update of DAC outputs via LDAC pin clears both DACs to 0 V. The outputs of both DACs can be Asynchronous CLR facility updated simultaneously using the asynchronous LDAC input. Low power serial interface with Schmitt-triggered inputs The devices contain a power-down feature that reduces the On-chip rail-to-rail output buffer amplifiers current consumption of the devices to 200 nA at 5 V (50 nA at Qualified for automotive applications 3 V) and provides software-selectable output loads while in power- down mode. The devices can also be used in daisy-chaining APPLICATIONS applications using the SDO pin. Portable battery-powered instruments The low power consumption of these devices in normal operation Digital gain and offset adjustment makes them ideally suited to portable battery operated equipment. Programmable voltage and current sources The power consumption is 1.5 mW at 5 V and 0.7 mW at 3 V, Programmable attenuators reducing to 1 μW in power-down mode. FUNCTIONAL BLOCK DIAGRAM VDD BUF A VREFA AD5313/AD5323 POWER-ON RESET REINGPISUTTER REGDIASCTER STDRAICNG BUFFER VOUTA SYNC INTERFACE SCLK LOGIC POWLEORG-DICOWN NREETSWISOTORRK DIN REINGPISUTTER REGDIASCTER STDRAICNG BUFFER VOUTB SDO GAIN-SELECT RESISTOR LOGIC NETWORK DCEN LDACCLR PD BUF B VREFB GND 00472-001 Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©1999–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5313/AD5323 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Low Power Serial Interface ....................................................... 16 Applications ....................................................................................... 1 Double-Buffered Interface ........................................................ 16 General Description ......................................................................... 1 Power-Down Modes....................................................................... 18 Functional Block Diagram .............................................................. 1 Microprocesser Interfacing ........................................................... 19 Revision History ............................................................................... 2 AD5313/AD5323 to ADSP-2161 Interface ............................. 19 Specifications ..................................................................................... 3 AD5313/AD5323 to 68HC11/68L11 Interface....................... 19 AC Characteristics ........................................................................ 6 AD5313/AD5323 to 80C51/80L51 Interface .......................... 19 Timing Characteristics ................................................................ 6 AD5313/AD5323 to MICROWIRE Interface ........................ 19 Absolute Maximum Ratings ............................................................ 8 Applications Information .............................................................. 20 ESD Caution .................................................................................. 8 Typical Application Circuit ....................................................... 20 Pin Configuration and Function Descriptions ............................. 9 Bipolar Operation Using the AD5313/AD5323........................ 20 Terminology .................................................................................... 10 Opto-Isolated Interface for Process Control Applications ... 21 Typical Performance Characteristics ........................................... 11 Decoding Multiple AD5313/AD5323s .................................... 21 Theory of Operation ...................................................................... 14 AD5313/AD5323 as a Digitally Programmable Window Digital to Analog ........................................................................ 14 Detector ....................................................................................... 21 Resistor String ............................................................................. 14 Coarse and Fine Adjustment Using the AD5313/AD5323 ... 22 DAC Reference Inputs ............................................................... 14 Daisy-Chain Mode ..................................................................... 22 Output Amplifier ........................................................................ 14 Power Supply Bypassing and Grounding ................................ 23 Power-On Reset .............................................................................. 15 Outline Dimensions ....................................................................... 24 Clear Function (CLR) ................................................................ 15 Ordering Guide .......................................................................... 24 Automotive Products ................................................................. 24 Serial Interface ................................................................................ 16 Input Shift Register..................................................................... 16 REVISION HISTORY 5/15—Rev. B to Rev. C 8/03—Rev. 0 to Rev. A Deleted AD5303............................................................. Throughout Added A Version ................................................................ Universal Changes to Features Section............................................................ 1 Changes to Features .......................................................................... 1 Deleted Figure 7 and Figure 10; Renumbered Sequentially ..... 11 Changes to Specifications ................................................................. 2 Deleted Figure 13 and Figure 14 ................................................... 12 Changes to Absolute Maximum Ratings ........................................ 5 Changes to Output Amplifier Section ......................................... 14 Changes to Ordering Guide ............................................................. 5 Deleted Figure 31 ............................................................................ 18 Updated Outline Dimensions ....................................................... 18 Changed ADSP-2101 to ADSP-2161 ........................................... 19 Changes to Ordering Guide .......................................................... 24 4/99—Revision 0: Initial Version Added Automotive Products Section........................................... 24 6/07—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 4 ............................................................................ 8 Changes to the Ordering Guide .................................................... 25 Rev. C | Page 2 of 24

Data Sheet AD5313/AD5323 SPECIFICATIONS V = 2.5 V to 5.5 V; V = 2 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD REF L L MIN MAX Table 1. A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE3, 4 AD5313 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ± 0.5 ±2 LSB Differential Nonlinearity ±0.05 ±0.5 ± 0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5323 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±8 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 2 and Figure 3 Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 2 and Figure 3 Lower Dead Band 10 60 10 60 mV See Figure 2 and Figure 3 Offset Error Drift5 −12 −12 ppm of FSR/°C Gain Error Drift5 −5 −5 ppm of FSR/°C Power Supply Rejection −60 −60 dB ΔV = ±10% DD Ratio5 DC Crosstalk5 30 30 μV DAC REFERENCE INPUTS5 V Input Range 1 V 1 V V Buffered reference mode REF DD DD 0 V 0 V V Unbuffered reference mode DD DD V Input Impedance >10 >10 MΩ Buffered reference mode REF 180 180 kΩ Unbuffered reference mode 0 V to V output range, input REF impedance = R DAC 90 90 kΩ Unbuffered reference mode 0 V to 2 V output range, input REF impedance = R DAC Reference Feedthrough −90 −90 dB Frequency = 10 kHz Channel to Channel −80 −80 dB Frequency = 10 kHz Isolation OUTPUT CHARACTERISTICS5 Minimum Output Voltage6 0.001 0.001 V min This is a measure of the minimum Maximum Output Voltage6 V − V − V max and maximum drive capability of DD DD 0.001 0.001 the output amplifier DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 50 50 mA V = 5 V DD 20 20 mA V = 3 V DD Power-Up Time 2.5 2.5 μs Coming out of power-down mode; V = 5 V DD 5 5 μs Coming out of power-down mode; V = 3 V DD Rev. C | Page 3 of 24

AD5313/AD5323 Data Sheet A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS5 Input Current ±1 ±1 μA Input Low Voltage, V 0.8 0.8 V V = 5 V ± 10% IL DD 0.6 0.6 V V = 3 V ± 10% DD 0.5 0.5 V V = 2.5 V DD Input High Voltage, V 2.4 2.4 V V = 5 V ± 10% IH DD 2.1 2.1 V V = 3 V ± 10% DD 2.0 2.0 V V = 2.5 V DD Pin Capacitance 2 3.5 2 3.5 pF LOGIC OUTPUT (SDO)5 V = 5 V ± 10% DD Output Low Voltage 0.4 0.4 V I = 2 mA SINK Output High Voltage 4.0 4.0 V I = 2 mA SOURCE V = 3 V ± 10% DD Output Low Voltage 0.4 0.4 V I = 2 mA SINK Output High Voltage 2.4 2.4 V I = 2 mA SOURCE Floating State Leakage 1 1 μA DCEN = GND Current Floating State Output 3 3 pF DCEN = GND Capacitance POWER REQUIREMENTS V 2.5 5.5 2.5 5.5 V I specification is valid for all DAC DD DD codes I (Normal Mode) Both DACs active and excluding DD load currents V = 4.5 V to 5.5 V 300 450 300 450 μA Both DACs in unbuffered mode; DD VDD = 2.5 V to 3.6 V 230 350 230 350 μA VIH = VDD and VIL = GND; in buffered mode, extra current is typically x μA per DAC, where x = 5 μA + V /R REF DAC I (Full Power-Down) DD V = 4.5 V to 5.5 V 0.2 1 0.2 1 μA DD V = 2.5 V to 3.6 V 0.05 1 0.05 1 μA DD 1 Temperature range for Version A, Version B: −40°C to +105°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5313 (Code 28 to Code 995); AD5323 (Code 115 to Code 3981). 5 Guaranteed by design and characterization; not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. Rev. C | Page 4 of 24

Data Sheet AD5313/AD5323 GAIN ERROR PLUS GAIN ERROR OFFSET ERROR PLUS OFFSET ERROR OUTPUT OUTPUT ACTUAL VOLTAGE IDEAL VOLTAGE ACTUAL IDEAL POSITIVE POOESFRFIRTSIOVERET DAC CODE OEFRFRSOERT DAC CODE 00472-006 Figure 3. Transfer Function with Positive Offset DEAD BAND AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR 00472-005 Figure 2. Transfer Function with Negative Offset Rev. C | Page 5 of 24

AD5313/AD5323 Data Sheet AC CHARACTERISTICS V = 2.5 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD L L MIN MAX Table 2. A, B Version3 Parameter1, 2 Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time V = V = 5 V REF DD AD5313 7 9 μs ¼ scale to ¾ scale change (0x100 to 0x300) AD5323 8 10 μs ¼ scale to ¾ scale change (0x400 to 0xc00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-sec 1 LSB change around major carry (011 . . . 11 to 100 . . . 00) Digital Feedthrough 0.10 nV-sec Analog Crosstalk 0.01 nV-sec DAC to DAC Crosstalk 0.01 nV-sec Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p, unbuffered mode REF Total Harmonic Distortion −70 dB V = 2.5 V ± 0.1 V p-p, frequency = 10 kHz REF 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range for Version A and Version B: −40°C to +105°C. TIMING CHARACTERISTICS V = 2.5 V to 5.5 V; all specifications T to T , unless otherwise noted. DD MIN MAX Table 3. Limit at T T MIN, MAX Parameter1, 2, 3 (A, B Version) Unit Test Conditions/Comments t 33 ns min SCLK cycle time 1 t 13 ns min SCLK high time 2 t 13 ns min SCLK low time 3 t4 0 ns min SYNC to SCLK rising edge setup time t 5 ns min Data setup time 5 t 4.5 ns min Data hold time 6 t7 0 ns min SCLK falling edge to SYNC rising edge t8 100 ns min Minimum SYNC high time t9 20 ns min LDAC pulse width t10 20 ns min SCLK falling edge to LDAC rising edge t11 20 ns min CLR pulse width t 4, 5 5 ns min SCLK falling edge to SDO invalid 12 t 4, 5 20 ns max SCLK falling edge to SDO valid 13 t145 0 ns min SCLK falling edge to SYNC rising edge t155 10 ns min SYNC rising edge to SCLK rising edge 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 4 and Figure 5. 4 These are measured with the load circuit of Figure 4. 5 Daisy-chain mode only (see Figure 42). Rev. C | Page 6 of 24

Data Sheet AD5313/AD5323 2mA IOL TO OUTPUT 1.6V PIN CL 50pF 2mA IOH 00472-002 Figure 4. Load Circuit for Digital Output (SDO) Timing Specifications t1 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN* DB15 DB0 t9 LDAC t10 LDAC t11 *SCELER THE INPUT SHIFT REGISTER SECTION. 00472-003 Figure 5. Serial Interface Timing Diagram Rev. C | Page 7 of 24

AD5313/AD5323 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted.1 Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 4. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond Digital Input Voltage to GND −0.3 V to V + 0.3 V DD the maximum operating conditions for extended periods may Digital Output Voltage to GND −0.3 V to V + 0.3 V DD affect product reliability. Reference Input Voltage to GND −0.3 V to V + 0.3 V DD V A, V B to GND −0.3 V to V + 0.3 V OUT OUT DD Operating Temperature Range ESD CAUTION Industrial (A, B Version) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T Max) 150°C J 16-Lead TSSOP Package Power Dissipation (T max − T )/θ J A JA θ Thermal Impedance 160°C/W JA Lead Temperature JEDEC Industry Standard Soldering J-STD-020 1 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. C | Page 8 of 24

Data Sheet AD5313/AD5323 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLR 1 16 SDO LDAC 2 15 GND VDD 3 AD5313/ 14 DIN AD5323 VREFB 4 TOP VIEW 13 SCLK VREFA 5 (Not to Scale) 12 SYNC VOUTA 6 11 VOUTB BUF A 7 10 PD BUF B 8 9 DCEN 00472-004 Figure 6. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 CLR Active Low Control Input. Loads all zeros to both input and DAC registers. 2 LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data. This allows the simultaneous update of both DAC outputs. 3 V Power Supply Input. Operate the devices from 2.5 V to 5.5 V, and decouple the supply to GND. DD 4 V B Reference Input Pin for DAC B. It can be configured as a buffered or an unbuffered input, depending on the state REF of the BUF B pin. It has an input range from 0 V to V in unbuffered mode and from 1 V to V in buffered mode. DD DD 5 V A Reference Input Pin for DAC A. It can be configured as a buffered or an unbuffered input depending on the state REF of the BUF A pin. It has an input range from 0 V to V in unbuffered mode and from 1 V to V in buffered mode. DD DD 6 V A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 7 BUF A Control Pin. Controls whether the reference input for DAC A is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 8 BUF B Control Pin. Controls whether the reference input for DAC B is unbuffered or buffered. If this pin is tied low, the reference input is unbuffered. If it is tied high, the reference input is buffered. 9 DCEN This pin is used to enable the daisy-chaining option. Tie the pin high if the device is being used in a daisy chain. Tie the pin low if it is being used in standalone mode. 10 PD Active Low Control Input. Acts as a hardware power-down option. This pin overrides any software power-down option. Both DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the device drops to 200 nA at 5 V (50 nA at 3 V). 11 V B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 12 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 13 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 14 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 15 GND Ground Reference Point for All Circuitry on the Device. 16 SDO Serial Data Output. Can be used to daisy-chain a number of these devices together or to read back the data in the shift register for diagnostic purposes. The serial data output is valid on the falling edge of the clock. Rev. C | Page 9 of 24

AD5313/AD5323 Data Sheet TERMINOLOGY DAC to DAC Crosstalk Relative Accuracy or Integral Nonlinearity (INL) This is the glitch impulse transferred to the output of one DAC For the DAC, relative accuracy or integral nonlinearity is a measure due to a digital code change and subsequent output change of of the maximum deviation, in LSB, from a straight line passing the other DAC. This includes both digital and analog crosstalk. through the actual endpoints of the DAC transfer function. It is measured by loading one of the DACs with a full-scale code Figure 7 and Figure 8 show typical INL error vs. code plots. change (all 0s to all 1s and vice versa) while keeping LDAC low Differential Nonlinearity (DNL) and monitoring the output of the other DAC. The area of the Differential nonlinearity is the difference between the measured glitch is expressed in nV-sec. change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of ±1 LSB maximum ensures monotonic- DC Crosstalk ity. This DAC is guaranteed monotonic by design. A typical DNL This is the dc change in the output level of one DAC in response error vs. code plot can be seen in Figure 9 and Figure 10. to a change in the output of the other DAC. It is measured with a full-scale output change on one DAC while monitoring the other Offset Error DAC. It is expressed in microvolts. This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes Gain Error in the supply voltage. PSRR is the ratio of the change in V to OUT This is a measure of the span error of the DAC. It is the devia- a change in V for full-scale output of the DAC. It is measured DD tion in slope of the actual DAC transfer characteristic from the in decibels. V is held at 2 V and V is varied ±10%. REF DD ideal expressed as a percentage of the full-scale range. Reference Feedthrough Offset Error Drift This is the ratio of the amplitude of the signal at the DAC output to This is a measure of the change in offset error with changes in the reference input when the DAC output is not being updated temperature. It is expressed in ppm of full-scale range/°C. (that is, LDAC is high). It is expressed in decibels. Gain Error Drift Total Harmonic Distortion (THD) This is a measure of the change in gain error with changes in This is the difference between an ideal sine wave and its attenuated temperature. It is expressed in ppm of full-scale range/°C. version using the DAC. The sine wave is used as the reference Major-Code Transition Glitch Energy for the DAC and the THD is a measure of the harmonics present Major-code transition glitch energy is the energy of the impulse on the DAC output. It is measured in decibels. injected into the analog output when the code in the DAC register Multiplying Bandwidth changes state. It is normally specified as the area of the glitch in The amplifiers within the DAC have a finite bandwidth. The nV-sec and is measured when the digital code is changed by multiplying bandwidth is a measure of this. A sine wave on the 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or reference (with full-scale code loaded to the DAC) appears on 100 . . . 00 to 011 . . . 11). the output. The multiplying bandwidth is the frequency at which Digital Feedthrough the output amplitude falls to 3 dB below the input. Digital feedthrough is a measure of the impulse injected into Channel to Channel Isolation the analog output of the DAC from the digital input pins of the This is a ratio of the amplitude of the signal at the output of one device, but is measured when the DAC is not being written to DAC to a sine wave on the reference input of the other DAC. It (SYNC held high). It is specified in nV-sec and is measured is measured in decibels. with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa. Analog Crosstalk This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. Rev. C | Page 10 of 24

Data Sheet AD5313/AD5323 TYPICAL PERFORMANCE CHARACTERISTICS 3 1.0 VTAD D= =2 55°VC TVAD D= =2 55°VC 2 0.5 INL ERROR (LSB)–110 DNL ERROR (LSB) 0 –0.5 –2 –30 200 400 CODE 600 800 1000 00472-008 –1.00 1000 C20O0D0E 3000 4000 00472-012 Figure 7. AD5313 Typical INL Plot Figure 10. AD5323 Typical DNL Plot 12 1.0 TA = 25°C VDD = 5V VDD = 5V VREF =2V 8 0.5 B) 4 L ERROR (LS 0 ERROR (%) 0 GAIN ERROR N I –4 OFFSET ERROR –0.5 –8 –120 1000 C20O0D0E 3000 4000 00472-009 –1.0–40 0 TEMPERA4T0URE (°C) 80 120 00472-015 Figure 8. AD5323 Typical INL Plot Figure 11. Offset Error and Gain Error vs. Temperature 0.6 TA = 25°C VDD = 5V 0.4 VDD = 5V VDD = 3V R (LSB) 0.2 ENCY O U R 0 Q R E E R L F N D–0.2 –0.4 –0.60 200 400 CODE600 800 1000 00472-011 0100 150 200 IDD2 5(0µA) 300 350 400 00472-016 Figure 9. AD5313 Typical DNL Plot Figure 12. IDD Histogram with VDD = 3 V and VDD = 5 V Rev. C | Page 11 of 24

AD5313/AD5323 Data Sheet 5 1.0 BOTH DACS IN 5V SOURCE 0.9 THREE-STATE CONDITION 4 0.8 0.7 3 3V SOURCE 0.6 V) A) (OUT (µDD0.5 V 2 I 0.4 0.3 3V SINK –40°C +25°C 1 5V SINK 0.2 0.1 +105°C –00 1 SINK2/SOURCE 3CURRENT 4(mA) 5 6 00472-017 02.7 3.2 3.7 VDD (4V.2) 4.7 5.2 00472-020 Figure 13. Source and Sink Current Capability Figure 16. Power-Down Current vs. Supply Voltage 600 700 TA = 25°C TA = 25°C VDD = 5V 500 600 400 500 I(µA)DD300 I(µA)DD 400 VDD = 5V 300 200 200 VDD = 3V 100 0ZERO SCALE FULL SCALE 00472-018 1000 0.5 1.0 1.5 2.0VLO2G.5IC(V)3.0 3.5 4.0 4.5 5.0 00472-021 Figure 14. Supply Current vs. Code Figure 17. Supply Current vs. Logic Input Voltage 600 BOTH DACS IN GAIN-OF-TWO MODE VDD = 5V REFERENCE INPUTS BUFFERED TA = 25°C 500 CH2 CLK 400 –40°C A) (µ 300 D D I 200 +25°C +105°C CH1 VOUT 100 02.5 3.0 3.5 VD4D.0(V) 4.5 5.0 5.5 00472-019 CH1 1V, CH2 5V, TIME BASE = 5µs/DIV 00472-022 Figure 15. Supply Current vs. Supply Voltage Figure 18. Half-Scale Settling (¼ to ¾ Scale Code Change) Rev. C | Page 12 of 24

Data Sheet AD5313/AD5323 TA = 25°C 10 VDD 0 –10 –20 B) d ( –30 CH1 –40 VOUTA CH2 –50 CH1 1V, CH2 1V, TIME BASE = 20µs/DIV 00472-023 –6010 100 1kFREQU1E0NkCY(Hz)100k 1M 10M 00472-026 Figure 19. Power-On Reset to 0 V Figure 22. Multiplying Bandwidth (Small Signal Frequency Response) TA = 25°C VOUT V DI CH1 V/ m 2 CH3 CLK CH1 1V, CH3 5V, TIME BASE = 1µs/DIV 00472-024 500ns/DIV 00472-027 Figure 20. Exiting Power-Down to Midscale Figure 23. DAC to DAC Crosstalk 2.50 0.10 TA = 25°C VDD = 5V 2.49 V) 0.05 V) OR ( (UT RR O E V E 0 L A 2.48 C S L- L U F–0.05 2.47 1µs/DIV 00472-025 –0.100 1 2 VREF (V) 3 4 5 00472-028 Figure 21. AD5323 Major Code Transition Figure 24. Full-Scale Error vs. VREF (Buffered) Rev. C | Page 13 of 24

AD5313/AD5323 Data Sheet THEORY OF OPERATION The AD5313/AD5323 are dual resistor string DACs fabricated RESISTOR STRING on a CMOS process with resolutions of 10 bits and 12 bits, The resistor string section of the AD5313/AD5323 is shown in respectively. They contain reference buffers and output buffer Figure 26. It is simply a string of resistors, each of value R. The amplifiers, and are written to via a 3-wire serial interface. They digital code loaded to the DAC register determines at what node operate from single supplies of 2.5 V to 5.5 V and the output on the string the voltage is tapped off to be fed into the output buffer amplifiers provide rail-to-rail output swing with a slew amplifier. The voltage is tapped off by closing one of the switches rate of 0.7 V/μs. Each DAC is provided with a separate reference connecting the string to the amplifier. Because it is a string of input, which can be buffered to draw virtually no current from resistors, it is guaranteed monotonic. the reference source, or unbuffered to give a reference input range from GND to VDD. The devices have three programmable R power-down modes, in which one or both DACs can be turned R off completely with a high impedance output, or the output can R TO OUTPUT AMPLIFIER be pulled low by an on-chip resistor. DIGITAL TO ANALOG The architecture of one DAC channel consists of a reference R buffer and a resistor-string DAC followed by an output buffer R vamoltpalgifei efro. rT thhee vDoAltCag. eF aigt uthree 2V5R EsFhxo pwisn ap brolovcidke dsi tahger armef eorfe nthcee 00472-030 Figure 26. Resistor String DAC architecture. Because the input coding to the DAC is straight binary, the ideal output voltage is given by DAC REFERENCE INPUTS V D There is a reference input pin for each of the two DACs. The VOUT  RE2FN reference inputs are buffered, but can also be configured as unbuffered. The advantage with the buffered input is the high where: impedance it presents to the voltage source driving it. However, D is the decimal equivalent of the binary code, which is loaded if the unbuffered mode is used, the user can have a reference to the DAC register: 0 to 1023 for AD5313 (10 bits) and 0 to voltage as low as GND and as high as V because there is no DD 4095 for AD5323 (12 bits). restriction due to headroom and footroom of the reference N is the DAC resolution. amplifier. VREFA If there is a buffered reference in the circuit (for example, REF192), SWITCH there is no need to use the on-chip buffers of the AD5313/AD5323. CONTROLLED In unbuffered mode, the input impedance is still large at typically REFERENCE BY CONTROL BUFFER LOGIC 180 kΩ per reference input for 0 V to VREF mode and 90 kΩ for 0 V to 2 V mode. REF REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTA The buffered/unbuffered option is controlled by the BUF A OUTAPMUPTL IBFUIEFRFER 00472-029 aisn bdu BffUerFe dB; pifi ntise.d I fl oaw B, UitF is p uinn bisu tfifeedre hdi.g h, the reference input Figure 25. Single DAC Channel Architecture OUTPUT AMPLIFIER The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail, which gives an output range of 0.001 V to V − 0.001 V when the reference is V . DD DD It is capable of driving a load of 2 kΩ in parallel with 500 pF to GND and V . Figure 13 shows the source and sink capabilities DD of the output amplifier. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at 10 bits) of 7 μs. Rev. C | Page 14 of 24

Data Sheet AD5313/AD5323 POWER-ON RESET The AD5313/AD5323 are provided with a power-on reset function, CLEAR FUNCTION (CLR) so that they power up in a defined state. The power-on state is The CLR pin is an active low input that, when pulled low, loads with 0 V to V output range and the output set to 0 V. REF all zeros to both input registers and both DAC registers. This Both input and DAC registers are filled with zeros and remain enables both analog outputs to be cleared to 0 V. so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Rev. C | Page 15 of 24

AD5313/AD5323 Data Sheet SERIAL INTERFACE The AD5313/AD5323 are controlled over a versatile, 3-wire After the end of serial data transfer, data is automatically serial interface that operates at clock rates up to 30 MHz and is transferred from the input shift register to the input register compatible with SPI, QSPI, MICROWIRE, and DSP interface of the selected DAC. If SYNC is taken high before the 16th standards. falling edge of SCLK, the data transfer is aborted and the input INPUT SHIFT REGISTER registers are not updated. When data has been transferred into both input registers, the The input shift register is 16 bits wide. Data is loaded into the DAC registers of both DACs can be simultaneously updated, device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 5. by taking LDAC low. CLR is an active low, asynchronous clear The 16-bit word consists of four control bits followed by 10 bits that clears the input and DAC registers of both DACs to all 0s. to 12 bits of DAC data, depending on the device type. The first LOW POWER SERIAL INTERFACE bit loaded is the MSB (Bit 15), which determines whether the data To reduce the power consumption of the device even further, is for DAC A or DAC B. Bit 14 determines the output range (0 V to the interface only powers up fully when the device is being V or 0 V to 2 V ). Bit 13 and Bit 12 control the operating mode REF REF written to. As soon as the 16-bit control word is written to the of the DAC. device, the SCLK and DIN input buffers are powered down. Table 6. Control Bits They only power up again following a falling edge of SYNC. Power-On DOUBLE-BUFFERED INTERFACE Bit Name Function Default The DACs all have double-buffered interfaces consisting of two 15 A/B 0: data written to DAC A Not applicable banks of registers—input registers and DAC registers. The input 1: data written to DAC B register is connected directly to the input shift register and the 14 GAIN 0: output range of 0 V to V 0 REF digital code is transferred to the relevant input register on com- 1: output range of 0 V to 2 V REF pletion of a valid write sequence. The DAC register contains the 13 PD1 Mode bit 0 digital code used by the resistor string. 12 PD0 Mode bit 0 Access to the DAC register is controlled by the LDAC function. The remaining bits are DAC data bits, starting with the MSB When LDAC is high, the DAC register is latched and the input and ending with the LSB. The AD5323 uses all 12 bits of DAC register can change state without affecting the contents of the data; the AD5313 uses 10 bits and ignores the 2 LSBs. The data DAC register. However, when LDAC is brought low, the DAC format is straight binary, with all 0s corresponding to 0 V output, register becomes transparent and the contents of the input reg- and all 1s corresponding to full-scale output (V − 1 LSB). ister are transferred to it. REF The SYNC input is a level triggered input that acts as a frame This is useful if the user requires simultaneous updating of synchronization signal and chip enable. Data can be transferred both DAC outputs. The user can write to both input registers into the device only while SYNC is low. To start the serial data individually and then, by pulsing the LDAC input low, both transfer, take SYNC low, observing the minimum SYNC to outputs update simultaneously. SCLK rising edge setup time, t4. After SYNC goes low, serial These devices contain an extra feature whereby the DAC register is data is shifted into the input shift register of the device on the not updated unless its input register has been updated since the falling edges of SCLK for 16 clock pulses. Any data and clock last time that LDAC was brought low. Normally, when LDAC is pulses after the 16th are ignored, and no further serial data brought low, the DAC registers are filled with the contents of the transfer occurs until SYNC is taken high and low again. input registers. In the case of the AD5313/AD5323, the device only updates the DAC register if the input register has been SYNC can be taken high after the falling edge of the 16th SCLK changed since the last time the DAC register was updated, pulse, observing the minimum SCLK falling edge to SYNC thereby removing unnecessary digital crosstalk. rising edge time, t. 7 Rev. C | Page 16 of 24

Data Sheet AD5313/AD5323 DB15 (MSB) DB0 (LSB) A/B GAIN PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X DATA BITS 00472-032 Figure 27. AD5313 Input Shift Register Contents DB15 (MSB) DB0 (LSB) A/B GAIN PD1 PD0 D11 D10 D9 D8 D7 DADT6A BDIT5S D4 D3 D2 D1 D0 00472-033 Figure 28. AD5323 Input Shift Register Contents Rev. C | Page 17 of 24

AD5313/AD5323 Data Sheet POWER-DOWN MODES The AD5313/AD5323 have very low power consumption, power-down options. The output is connected internally to GND dissipating only 0.7 mW with a 3 V supply and 1.5 mW with a 5 V through either a 1 kΩ resistor or a 100 kΩ resistor, or it is left in supply. Power consumption can be further reduced when the a high impedance state (three-state). Figure 29 shows the output DACs are not in use by putting them into one of three power- stage. down modes, which are selected by Bit 13 and Bit 12 (PD1 and The bias generator, the output amplifier, the resistor string, and PD0) of the control word. Table 7 shows how the state of the all other associated linear circuitry are shut down when the power- bits corresponds to the mode of operation of that particular down mode is activated. However, the contents of the registers DAC. are unaffected when in power-down. The time to exit power- down is typically 2.5 μs for V = 5 V and 5 μs when V = 3 V Table 7. PD1/PD0 Operating Modes DD DD (see Figure 20). PD1 PD0 Operating Mode 0 0 Normal operation The software power-down modes programmed by PD0 and 0 1 Power-down (1 kΩ load to GND) PD1 are overridden by the PD pin. Taking this pin low puts 1 0 Power-down (100 kΩ load to GND) both DACs into power-down mode simultaneously and both 1 1 Power-down (high impedance output) outputs are put into a high impedance state. If PD is not used, tie the pin high. When both bits are set to 0, the DACs work normally with their AMPLIFIER normal power consumption of 300 μA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at SRTERSINISGT DOARC VOUT 5 V (50 nA at 3 V) when both DACs are powered down. Not only does the supply current drop, but the output stage is also internally sowf kitncohwedn fvraolmue st.h Teh oisu thpaus tt hoef tahdev aanmtapgleif tiehra tt oth ae roeustipstuotr i mneptewdoarnkc e POCWIRECRU-IDTORWYN RNEESTWISOTORRK 00472-034 Figure 29. Output Stage During Power-Down of the device is known while the device is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. There are three different Rev. C | Page 18 of 24

Data Sheet AD5313/AD5323 MICROPROCESSER INTERFACING AD5313/AD5323 TO ADSP-2161 INTERFACE AD5313/AD5323 TO 80C51/80L51 INTERFACE Figure 30 shows a serial interface between the AD5313/AD5323 Figure 32 shows a serial interface between the AD5313/AD5323 and the ADSP-2161. Set up the ADSP-2161 to operate in the and the 80C51/80L51 microcontroller. The setup for the interface is SPORT transmit alternate framing mode. The ADSP-2161 as follows: TXD of the 80C51/80L51 drives SCLK of the AD5313/ SPORT is programmed through the SPORT control register. AD5323, while RXD drives the serial data line of the device. Configure the ADSP-2161 as follows: internal clock operation, The SYNC signal is again derived from a bit programmable pin active-low framing, 16-bit word length. Transmission is initiated by on the port. In this case, port line P3.3 is used. When data is to writing a word to the Tx register after the SPORT has been be transmitted to the AD5313/AD5323, P3.3 is taken low. The enabled. 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to ADSP-2161 AD5313/ the DAC, P3.3 is left low after the first eight bits are transmitted AD5323* and a second write cycle is initiated to transmit the second byte TFS SYNC of data. P3.3 is taken high following the completion of this cycle. DT DIN The 80C51/ 80L51 output the serial data in a format that has the LSB first. The AD5313/AD5323 require data with MSB as the SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY 00472-035 ftihrisst ibnitto r eacceciovuendt. .T he 80C51/80L51 transmit routine must take Figure 30. AD5313/AD5323 to ADSP-2161 Interface 80C51/80L51* AD5313/ AD5313/AD5323 TO 68HC11/68L11 INTERFACE AD5323* Figure 31 shows a serial interface between the AD5313/AD5323 P3.3 SYNC and the 68HC11/68L11 microcontroller. SCK of the 68HC11/ TXD SCLK 68L11 drives the SCLK of the AD5313/AD5323, while the MOSI RXD DIN soiugtnpaul ti sd rdievreisv ethde f rsoemria al dpaotrat lliinnee ((DPICN7)) .o Tf hthee s eDtuApC c. oTnhdei tSiYonNsC *ADDITIONAL PINS OMITTED FOR CLARITY. 00472-037 for correct operation of this interface are as follows: configure the Figure 32. AD5313/AD5323 to 80C51/80L51 Interface 68HC11/68L11 so that its CPOL bit is a 0 and its CPHA bit is a 1. AD5313/AD5323 TO MICROWIRE INTERFACE When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as Figure 33 shows an interface between the AD5313/AD5323 and previously mentioned, data appearing on the MOSI output is any MICROWIRE-compatible device. Serial data is shifted out valid on the falling edge of SCK. Serial data from the 68HC11/ on the falling edge of the serial clock and is clocked into the 68L11 is transmitted in 8-bit bytes with only eight falling clock AD5313/AD5323 on the rising edge of the SK. edges occurring in the transmit cycle. Data is transmitted MSB MICROWIRE* AD5313/ first. To load data to the AD5313/AD5323, PC7 is left low after AD5323* the first eight bits are transferred and a second serial write operation is performed to the DAC; PC7 is taken high at the CS SYNC end of this procedure. SK SCLK SO DIN 68HC11/68L11* AADD55332133*/ *ADDITIONAL PINS OMITTED FOR CLARITY. 00472-038 PC7 SYNC Figure 33. AD5313/AD5323 to MICROWIRE Interface SCK SCLK MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY 630-27400 Figure 31. AD5313/AD5323 to 68HC11/68L11 Interface Rev. C | Page 19 of 24

AD5313/AD5323 Data Sheet APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT 15V The AD5313/AD5323 can be used with a wide range of VS 0.1µF 10µF reference voltages, especially if the reference inputs are con- REF195 figured to be unbuffered, in which case the devices offer a full, OUTPUT VDD one-quadrant multiplying capability over a reference range of GND 1µF VREFA VOUTA 0 V to V . VREFB DD AD5313/ Typically, the AD5313/AD5323 can be used with a fixed AD5323 SCLK precision reference voltage. Figure 34 shows a typical setup for DIN the AD5313/AD5323 when using an external reference. If the SYNC VOUTB reference inputs are unbuffered, the reference input range is GND BUF A BUF B tfhroem re 0fe Vre ntoc eV rDaDn, gbeu its i rf etdhue coend-.c Shuipit arbelfee rreenfecree bnuceffse rfos ra 5re V u sed, INTSEERRFIAALCE 00472-040 Figure 35. Using an REF195 as Power and Reference to the AD5313/AD5323 operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference is the REF191, a BIPOLAR OPERATION USING THE AD5313/AD5323 2.048 V reference. The AD5313/AD5323 are designed for single-supply operation, VDD = 2.5V to 5.5V but bipolar operation is also achievable using the circuit shown in Figure 36. The circuit shown has been configured to achieve VDD ERXETF VOUT VREFA VOUTA an output voltage range of −5 V < VOUT < +5 V. Rail-to-rail opera- 1µF VREFB tion at the amplifier output is achievable using an AD820 or AD780/REF192 WITH VDD = 5V AD5313/ OP295 as the output amplifier. OR REF191 WITH AD5323 VDD = 2.5V SCLK 6V to 16V R2 DSYINNC VOUTB 0.1µF 10µF VDD = 5V 10kΩ +5V GND BUF A BUF B R1 10kΩ INTSEERRFIAALCE 00472-039 REFVS195 VDD AD820/±5V Figure 34. AD5313/AD5323 Using External Reference OUTPUT VREFx OP295 –5V GND 1µF AD5313/ If an output range of 0 V to V is required when the reference DD AD5323 inputs are configured as unbuffered (for example, 0 V to 5 V), SCLK the simplest solution is to connect the reference inputs to V . DD DIN Because this supply may not be very accurate and may be noisy, SYNC VOUTx the AD5313/AD5323 can be powered from the reference voltage, GND BUF A BUF B fFoirg uexream 35p.l eT, huesi nRgE aF 159 V5 roeufetpreuntcs ea s sutceha days tshuep RplEyF v1o9l5ta, agse sfhoor wthne i n INTSEERRFIAALCE 00472-041 AD5313/AD5323. The supply current required from the REF195 is Figure 36. Bipolar Operation Using the AD5313/AD5323 300 μA and approximately 30 μA or 60 μA into each of the The output voltage for any input code can be calculated as follows: reference inputs (if unbuffered). This is with no load on the DAC V = ((V ) × (D/2N) × (R1 + R2)/R1 – V × (R2/R1)) outputs. When the DAC outputs are loaded, the REF195 also OUT REF REF needs to supply the current to the loads. The total current where: required (with a 10 kΩ load on each output) is D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. 360 μA + 2(5 V/10 kΩ) = 1.36 mA V is the reference voltage input, and gain bit = 0. REF The load regulation of the REF195 is typically 2 ppm/mA, which With V = 5 V, R1 = R2 = 10 kΩ, and V = 5 V, results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA current REF DD drawn from it. This corresponds to a 0.011 LSB error at 12 bits. VOUT = (10 × D/2N) − 5 V Rev. C | Page 20 of 24

Data Sheet AD5313/AD5323 OPTO-ISOLATED INTERFACE FOR PROCESS SCLK AD5313/ CONTROL APPLICATIONS SYNC AD5323 DIN DIN The AD5313/AD5323 has a versatile 3-wire serial interface VDD SCLK making it ideal for generating accurate voltages in process VCC control and industrial applications. Due to noise, safety ENABLE 1G 1Y0 AD5313/ 74HC139 requirements, or distance, it may be necessary to isolate the CODED 1A 1Y1 SYNC AD5323 AD5313/AD5323 from the controller. This can easily be ADDRESS 1B 1Y2 DSCINLK 1Y3 achieved by using opto-isolators, which provide isolation in DGND excess of 3 kV. The serial loading structure of the AD5313/ AD5313/ AD5323 makes it ideally suited for use in opto-isolated SYNC AD5323 applications. Figure 37 shows an opto-isolated interface to the DIN SCLK AD5313/AD5323 where DIN, SCLK, and SYNC are driven from opto-couplers. Use a transformer to isolate the power supply to the device. On the DAC side of the transformer, a AD5313/ 5 V regulator provides the 5 V supply required for the SYNC AD5323 AD5313/AD5323. DSCINLK 00472-043 5V Figure 38. Decoding Multiple AD5313/AD5323 Devices in a System REGULATOR POWER 10µF 0.1µF AD5313/AD5323 AS A DIGITALLY PROGRAMMABLE WINDOW DETECTOR VDD A digitally programmable upper/lower limit detector using 10kΩ the two DACs in the AD5313/AD5323 is shown in Figure 39. VDD SCLK SCLK VREFA The upper and lower limits for the test are loaded to DAC A VREFB and DAC B, which, in turn, set the limits on the CMP04. If the signal at the V input is not within the programmed window, AD5313/ IN VDD an LED indicates the fail condition. AD5323 10kΩ VOUTA 5V SYNC SYNC VOUTB 0.1µF 10µF VIN 1kΩ 1kΩ VDD FAIL PASS VDD VREF VVRREEFFBA VOUTA 10kΩ AD5313/ DIN DIN AD5323 1/2 PASS/FAIL SYNC SYNC CMP04 GND BUF A BUF B Figure 37. AD5313/AD5323 in an Opto-Isolated Interface 00472-042 SCDLINK SDCINLK GND VOUTB 1/6 74HC05 00472-044 DECODING MULTIPLE AD5313/AD5323s Figure 39. Window Detector Using AD5313/AD5323 The SYNC pin on the AD5313/AD5323 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but only the SYNC to one of the devices is active at any one time, allowing access to two channels in this 8-channel system. The 74HC139 acts as a two-line to four-line decoder to address any of the DACs in the system. To prevent timing errors from occurring, bring the enable input to its inactive state while the coded address inputs are changing state. Figure 38 shows a diagram of a typical setup for decoding multiple AD5313/AD5323 devices in a system. Rev. C | Page 21 of 24

AD5313/AD5323 Data Sheet COARSE AND FINE ADJUSTMENT USING THE A continuous SCLK source can be used if it can be arranged AD5313/AD5323 that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of The DACs in the AD5313/AD5323 can be paired together to form clock cycles can be used and SYNC can be taken high some a coarse and fine adjustment function, as shown in Figure 40. DAC A provides the coarse adjustment while DAC B provides time later. the fine adjustment. Varying the ratio of R1 and R2 changes the When the transfer to all input registers is complete, a common relative effect of the coarse and fine adjustments. With the resistor LDAC signal updates all DAC registers and all analog outputs values and external reference shown, the output amplifier has are updated simultaneously. unity gain for the DAC A output, so the output range is 0 V to 2.5 V − 1 LSB. For DAC B, the amplifier has a gain of 7.6 × 10–3, AD5313/ 68HC111 AD53231 giving DAC B a range equal to 19 mV. (DAC 1) MOSI DIN The circuit is shown with a 2.5 V reference, but reference voltages SCK SCLK up to V can be used. The op amps indicated allow a rail-to- DD PC7 SYNC rail output swing. PC6 LDAC MISO SDO VDD = 5V R3 R4 51.2kΩ 900Ω DIN 0.1µF 10µF +5V AD5313/ VIN AD53231 EXT 2.5V REF VDD R1 VOUT SCLK (DAC 2) GNDVOUT 1µF VREFA VOUTA 390Ω AODP822905/ SYNC AD5313/ LDAC SDO AD5323 AD780/REF192 WITH VDD = 5V R2 VREFB VOUTB DIN 51.2kΩ GND 00472-045 SCLK AA(DDDA55C33 21N33)1/ Figure 40. Coarse and Fine Adjustment SYNC DAISY-CHAIN MODE LDAC SDO Tdehvisic meso odne tihs eu rsiesdin fgo re dugped aotfi nSYg NseCri.a Flloyr c soynsnteemctse dth oart cstoanntdaianlo ne 1ADDITIONAL PINS OMITTED FOR CLARITY. 00472-046 several DACs, or to read back the DAC contents for diagnostic Figure 41. Daisy-Chain Mode purposes, the SDO pin can be used to daisy-chain several devices together and provide serial readback. By connecting the daisy-chain enable (DCEN) pin high, the daisy-chain mode is enabled. It is tied low in standalone mode. In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out after the falling edge of SCLK and is valid on the subsequent rising and falling edges. By connect- ing this line to the DIN input on the next DAC in the chain, a multiDAC interface is constructed. Sixteen clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N, where N is the total number of devices in the chain. When the serial transfer to all devices is complete, take SYNC high. This prevents any further data from being clocked into the input shift register. Rev. C | Page 22 of 24

Data Sheet AD5313/AD5323 t 1 SCLK t8 t t3 t2 t14 4 SYNC t6 t15 t 5 DIN DB15 DB0 DB15 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC (N + 1) SDO DB15 DB0 UNDEFINED INPUT WORD FOR DAC N SCLK t 13 SDO VIH tVIL 00472-047 12 Figure 42. Daisy-Chaining Timing Diagram POWER SUPPLY BYPASSING AND GROUNDING inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle In any circuit where accuracy is important, careful considera- transient currents due to internal logic switching. tion of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on The power supply lines of the AD5313/AD5323 must use as large which the AD5313/AD5323 are mounted must be designed so a trace as possible to provide low impedance paths and reduce that the analog and digital sections are separated and confined the effects of glitches on the power supply line. Fast switching to certain areas of the board. If the AD5313/AD5323 are in a signals such as clocks must be shielded with digital ground to system where multiple devices require an AGND to DGND avoid radiating noise to other areas of the board, and must never be connection, make the connection at one point only. Establish run near the reference inputs. Avoid crossover of digital and the star ground point as close as possible to the AD5313/AD5323. analog signals. Traces on opposite sides of the board must run at The AD5313/AD5323 must have ample supply bypassing of 10 μF right angles to each other. This reduces the effects of feedthrough in parallel with 0.1 μF on the supply located as close to the through the board. A microstrip technique is by far the best but package as possible, ideally right up against the device. Use 10 μF is not always possible with a double-sided board. In this technique, capacitors that are of the tantalum bead type. The 0.1 μF capacitor the component side of the board is dedicated to the ground plane has low effective series resistance (ESR) and effective series while signal traces are placed on the solder side. Rev. C | Page 23 of 24

AD5313/AD5323 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 43. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option AD5313ARUZ −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313ARUZ-REEL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313BRUZ −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313BRUZ-REEL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323ARUZ −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRU −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRU-REEL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRUZ −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRUZ-REEL −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5323BRUZ-REEL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5313WBRUZ-REEL7 −40°C to +105°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5313W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. ©1999–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00472-0-5/15(C) Rev. C | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5323BRUZ AD5313ARUZ-REEL7 AD5323ARUZ AD5313BRUZ-REEL7 AD5323BRU AD5323BRUZ-REEL AD5323BRU-REEL7 AD5313WBRUZ-REEL7 AD5323BRUZ-REEL7 AD5313BRUZ AD5313ARUZ