10-Bit nanoDAC with SPI/I2C Interface and 2 ppm/°C On-Chip Reference Data Sheet AD5310R/AD5311R FEATURES FUNCTIONAL BLOCK DIAGRAMS High relative accuracy (INL): ±0.5 LSB maximum VLOGIC VREF VDD Low drift 2.5 V reference: 2 ppm/°C typical Selectable span output: 2.5 V or 5 V LDAC PORWEESRE-TON 2R.E5VF AD5310R Total unadjusted error (TUE): 0.06% of FSR maximum Offset error: ±1.5 mV maximum REGDIASCTER REF10-BIT OBUUFTFPEURT VOUT Gain error: ±0.05% of FSR maximum RESET DAC Low glitch: 0.1 nV-sec High drive capability: 20 mA INPUT POWER-DOWN CONTROL LOGIC CONTROL LOGIC RESISTOR Low power: 1.2 mW at 3.3 V NETWORK Independent logic supply: 1.8 V logic compatible WRoidbeu sotp 4e kraVt iHnBgM te EmSpDe prarotuterec triaonng e: −40°C to +105°C SYNC SCLK SDI GND 11956-001 Figure 1. AD5310R APPLICATIONS VLOGIC VREF VDD Process controls Data acquisition systems Digital gain and offset adjustment LDAC PORWEESRE-TON 2R.E5VF AD5311R Programmable voltage sources REF Optical modules REGDIASCTER 10-BIT OBUUFTFPEURT VOUT RESET DAC GENERAL DESCRIPTION INPUT POWER-DOWN CONTROL LOGIC CONTROL LOGIC RESISTOR NETWORK The AD5310R/AD5311R, members of the nanoDAC® family, are low power, single-channel, 10-bit buffered voltage output DACs. Trehfeer denevceic, easn idn cplruodvei daens e2n papbmled/° bCy. dTehfea uolut tipnutet rsnpaaln 2 c.5a nV b e SDA SCL A0 GND 11956-002 Figure 2. AD5311R programmed to be 0 V to V or 0 V to 2 × V . All devices REF REF operate from a single 2.7 V to 5.5 V supply and are guaranteed Table 1. Related Devices monotonic by design. The devices are available in 10-lead Interface Reference 12-Bit 10-Bit MSOP packages. SPI External AD5681R AD53101 The internal power-on reset circuit of the AD5310R/AD5311R I2C External AD53111 ensures that the DAC register is written to zero scale at powerup 1 The AD5310R and AD5311R are not pin-to-pin or software compatible with when the internal output buffer is configured in normal mode. the AD5310 and AD5311, respectively. The devices contain a power-down mode that reduces the PRODUCT HIGHLIGHTS current consumption of the device to 2 µA at 5 V. The AD5310R/AD5311R use a versatile SPI or I2C interface, 1. High Relative Accuracy (INL): ±0.5 LSB maximum. 2. Low Drift 2.5 V On-Chip Reference: 5 ppm/°C maximum including an asynchronous RESET pin and a V pin that LOGIC temperature coefficient. provides 1.8 V compatibility. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5310R/AD5311R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Transfer Function ....................................................................... 17 Applications ....................................................................................... 1 DAC Architecture....................................................................... 17 General Description ......................................................................... 1 Serial Interface ................................................................................ 18 Functional Block Diagrams ............................................................. 1 AD5310R SPI Serial Data Interface ......................................... 18 Product Highlights ........................................................................... 1 Daisy-Chain Mode Compatibility ............................................ 18 Revision History ............................................................................... 2 AD5311R I2C Serial Data Interface.......................................... 19 Specifications ..................................................................................... 3 Commands .................................................................................. 21 AC Characteristics ........................................................................ 4 Load DAC (Hardware LDAC Pin) ........................................... 22 Timing Characteristics ................................................................ 5 Hardware RESET ........................................................................ 22 Absolute Maximum Ratings ............................................................ 8 AD5311R, I2C Read Operation ................................................ 22 Thermal Resistance ...................................................................... 8 Thermal Hysteresis .................................................................... 23 ESD Caution .................................................................................. 8 Power-Up Sequence ................................................................... 23 Pin Configurations and Function Descriptions ........................... 9 Layout Guidelines....................................................................... 23 Typical Performance Characteristics ........................................... 11 Outline Dimensions ....................................................................... 24 Terminology .................................................................................... 16 Ordering Guide .......................................................................... 24 Theory of Operation ...................................................................... 17 Digital-to-Analog Converter .................................................... 17 REVISION HISTORY 2/2017—Rev. A to Rev. B 1/2014—Rev. 0 to Rev. A Changes to Features Section and Table 1 ...................................... 1 Change to Features Section .............................................................. 1 Changed 1.8 V ≤ V ≤ 5.5 V (V = 1.8 V to 5.5 V) to Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6, LOGIC LOGIC 1.62 V ≤ V ≤ 5.5 V ...................................................................... 3 Table 2; Renumbered Sequentially .................................................. 3 LOGIC Changed 1.8 V ≤ V ≤ V to 1.62 V ≤ V ≤ 5.5 V ............ 4 Removed Endnote 3, Table 3............................................................ 4 LOGIC DD LOGIC Changes to V Parameter, Table 2 ............................................ 4 Removed Endnote 1, Table 4; Renumbered Sequentially ............ 5 LOGIC Changed V = 1.8 V to 5.5 V to 1.62 V ≤ V ≤ 5.5 V ........ 5 Changes to Table 6 ............................................................................. 8 LOGIC LOGIC Changes to Table 4 and Figure 3 ............................................................... 5 Removed Solder Heat Reflow Section and Figure 44; Changed V = 1.8 V to 5.5 V to 1.62 V ≤ V ≤ 5.5 V ........ 6 Renumbered Sequentially ............................................................. 23 LOGIC LOGIC Changes to Table 8 ............................................................................ 9 Changes to Table 9 .......................................................................... 10 1/2014—Revision 0: Initial Version Changes to Terminology Section.................................................. 16 Changes to Transfer Function Section ......................................... 17 Rev. B | Page 2 of 24

Data Sheet AD5310R/AD5311R SPECIFICATIONS V = 2.7 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V , 1.62 V ≤ V ≤ 5.5 V, −40°C < T < +105°C, unless DD L L REF DD LOGIC A otherwise noted. Table 2. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE1 Resolution 10 Bits Relative Accuracy, INL ±0.5 LSB Differential Nonlinearity, DNL ±0.5 LSB Zero-Code Error 1.25 mV All 0s loaded to DAC register Offset Error ±1.5 mV Full-Scale Error ±0.075 % of FSR All 1s loaded to DAC register Gain Error ±0.05 % of FSR Total Unadjusted Error, TUE ±0.16 % of FSR Internal reference, gain = 1 ±0.14 % of FSR Internal reference, gain = 2 ±0.075 % of FSR External reference, gain = 1 ±0.06 % of FSR External reference, gain = 2 Zero-Code Error Drift ±1 µV/°C Offset Error Drift ±1 µV/°C Gain Temperature Coefficient ±1 ppm/°C DC Power Supply Rejection 0.2 mV/V DAC code = midscale, V = 5 V ± 10% DD Ratio, PSRR OUTPUT CHARACTERISTICS Output Voltage Range 0 V V Gain = 1 REF 0 2 × V V Gain = 2 REF Capacitive Load Stability 2 nF R = ∞ L 10 nF R = 2 kΩ L Resistive Load 1 kΩ C = 0 µF L Load Regulation 10 µV/mA V = 5 V, DAC code = midscale; DD −30 mA ≤ I ≤ 30 mA OUT 10 µV/mA V = 3 V, DAC code = midscale; DD −20 mA ≤ I ≤ 20 mA OUT Short-Circuit Current 20 50 mA Load Impedance at Rails2 20 Ω REFERENCE OUTPUT Output Voltage 2.4975 2.5025 V At ambient temperature Voltage Reference TC3 2 5 ppm/°C See the Terminology section Output Impedance 0.05 Ω Output Voltage Noise 16.5 µV p-p 0.1 Hz to 10 Hz Output Voltage Noise Density 240 nV/√Hz At ambient temperature; f = 10 kHz, CL = 10 nF Capacitive Load Stability 5 µF R = 2 kΩ L Load Regulation, Sourcing 50 µV/mA At ambient temperature; VDD ≥ 3 V Load Regulation, Sinking 30 µV/mA At ambient temperature Output Current Load Capability ±5 mA VDD ≥ 3 V Line Regulation 80 µV/V At ambient temperature Thermal Hysteresis 125 ppm First cycle 25 ppm Additional cycles Rev. B | Page 3 of 24

AD5310R/AD5311R Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments LOGIC INPUTS Input Current, I ±1 µA Per pin IN ±4 µA SDA and SCL pins (AD5311R) Input Low Voltage, V 0.3 × V V INL LOGIC Input High Voltage, V 0.7 × V V INH LOGIC Pin Capacitance, C 2 pF IN LOGIC OUTPUT (SDA) AD5311R Output Low Voltage, VOL 0.4 V ISINK = 200 μA Output High Voltage, VOH VLOGIC − 0.4 V ISOURCE = 200 μA Pin Capacitance 4 pF POWER REQUIREMENTS V 1.62 5.5 V LOGIC I 0.25 3 µA V = V or V = GND LOGIC IH LOGIC IL V 2.7 5.5 V Gain = 1 DD V + 1.5 5.5 V Gain = 2 REF I V = V , V = GND DD IH DD IL Normal Mode4 350 500 µA Internal reference enabled 110 180 µA Internal reference disabled Power-Down Modes5 2 µA 1 Linearity is calculated using a reduced code range: Code 8 to Code 1024, output unloaded. 2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output devices; for example, when sinking 1 mA, the minimum output voltage with 20 Ω, 1 mA generates 20 mV. See Figure 29. 3 Reference temperature coefficient calculated as per the box method. See the Terminology section for more information. 4 Interface inactive. DAC active. Code = zero-scale, DAC output unloaded. 5 DAC powered down. AC CHARACTERISTICS V = 2.7 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V , 1.62 V ≤ V ≤ 5.5 V, −40°C < T < +105°C, unless DD L L REF DD LOGIC A otherwise noted.1 Table 3. Parameter2 Typ Max Unit Conditions/Comments Output Voltage Settling Time 5 7 µs Gain = 1, ¼ to ¾ scale settling to ±0.25 LSB Slew Rate 0.7 V/µs Digital-to-Analog Glitch Impulse 0.1 nV-sec ±1 LSB change around major carry, gain = 1 Digital Feedthrough 0.1 nV-sec Total Harmonic Distortion (THD) −83 dB V = 2 V ± 0.1 V p-p, f = 10 kHz REF Output Noise Spectral Density 200 nV/√Hz DAC code = midscale, f = 10 kHz Output Noise 6 µV p-p 0.1 Hz to 10 Hz; internal reference Signal-to-Noise Ratio (SNR) 90 dB At ambient temperature, BW = 20 kHz, V = 5 V, f = DD OUT 1 kHz Spurious-Free Dynamic Range (SFDR) 88 dB At ambient temperature, BW = 20 kHz, V = 5 V, f = DD OUT 1 kHz Signal-to-Noise-and Distortion (SINAD) Ratio 82 dB At ambient temperature, BW = 20 kHz, V = 5 V, f = DD OUT 1 kHz 1 Temperature range = −40°C to +105°C, typical at 25°C. 2 See the Terminology section. Rev. B | Page 4 of 24

Data Sheet AD5310R/AD5311R TIMING CHARACTERISTICS AD5310R V = 2.7 V to 5.5 V, 1.62 V ≤ V ≤ 5.5 V, −40°C < T < +105°C, unless otherwise noted. DD LOGIC A Table 4. 1.8 V ≤ V ≤ 2.7 V 2.7 V ≤ V 2 ≤ 5.5 V LOGIC LOGIC Parameter 1 Symbol Min Typ Max Min Typ Max Unit SCLK Cycle Time t 33 20 ns 1 SCLK High Time t 16 10 ns 2 SCLK Low Time t 16 10 ns 3 SYNC to SCLK Falling Edge Setup Time t4 15 10 ns Data Setup Time t 5 5 ns 5 Data Hold Time t 5 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t7 15 10 ns Minimum SYNC High Time t8 20 20 ns SYNC Falling Edge to SCLK Fall Ignore t9 16 10 ns SYNC Rising Edge to SCLK Falling Edge t10 ns SYNC Rising Edge to LDAC Falling Edge t11 25 25 ns LDAC Pulse Width Low t12 20 15 ns RESET Minimum Pulse Width Low t13 75 75 ns RESET Pulse Activation Time t14 150 150 ns SYNC Rising Edge to SYNC Rising Edge (DAC t15 1.9 1.7 µs Updates) LDAC Falling Edge to SYNC Rising Edge t16 1.8 1.65 µs Reference Power-Up3 t 4 600 600 µs REF_POWER_UP Exit Shutdown3 t 5 6 6 µs SHUTDOWN 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Substitute VDD for VLOGIC on devices that do not include a VLOGIC pin. 3 Not shown in Figure 3. 4 Same timing must be expected when powering up the device after VDD = 2.7 V. 5 Time required to exit power-down to normal mode of AD5310R/AD5311R operation; SYNC rising edge to 90% of DAC midscale value, with output unloaded. Timing and Circuit Diagrams t4 t9 t2 t1 t7 SCLK t8 t3 t10 SYNC t15 t5 t6 SDI DB23 DB22 DB21 DB20 DB2 DB1 DB0 t11 t12 LDAC t16 t13 RESET t14 VOUT 11956-003 Figure 3. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note) Rev. B | Page 5 of 24

AD5310R/AD5311R Data Sheet AD5311R VDD = 2.7 V to 5.5 V, 1.62 V ≤ VLOGIC ≤ 5.5 V, −40°C < TA < +105°C, unless otherwise noted. Table 5. Parameter1 Symbol Min Typ Max Unit Serial Clock Frequency (Not Shown in Figure 4 or Figure 5) f 2 400 kHz SCL SCL High Time, t t 0.6 µs HIGH 1 SCL Low Time, t t 1.3 µs LOW 2 Data Setup Time, t t 100 ns SU; DAT 3 Data Hold Time, t t 0 0.9 µs HD; DAT 4 Setup Time for a Repeated Start Condition, t t 0.6 µs SU; STA 5 Hold Time (Repeated) Start Condition, t t 0.6 µs HD; STA 6 Bus Free Time Between a Stop and a Start Condition, t t 1.3 µs BUF 7 Setup Time for a Stop Condition, t t 0.6 µs SU; STO 8 Rise Time of SDA Signal, t t 20 300 ns R 9 Fall Time of SDA Signal, t t 20 × (V /5.5 V) 300 ns F 10 DD Rise Time of SCL Signal, t t 20 300 ns R 11 Fall Time of SCL Signal, t t 20 × (V /5.5 V) 300 ns F 12 DD Pulse Width of Suppressed Spike (Not Shown in Figure 4 t 0 50 ns SP Figure 5) LDAC Falling Edge to SCL Falling Edge t13 400 ns LDAC Pulse Width (Synchronous Mode) t14 400 ns LDAC Pulse Width (Asynchronous Mode) t15 20 ns RESET Pulse Width t16 75 ns Reference Power-Up (Not Shown in Figure 4 or Figure 5) t 3 600 µs REF_POWER_UP Exit Shutdown (Not Shown in Figure 4 or Figure 5) t 4 6 µs SHUTDOWN 1 Maximum bus capacitance is limited to 400 pF. All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the device. 3 Same timing should be expected when powering the device after VDD = 2.7 V. 4 Time to exit power-down to normal mode of operation. t12 t11 t6 t8 t2 SCL t10 t9 t1 t5 t3 t4 SDA t7 START REPEATED START STOP REPCEOANTODERIDT ISOTNART CONDITION CONDITION 11956-004 Figure 4. I2C Serial Interface Timing Diagram Rev. B | Page 6 of 24

Data Sheet AD5310R/AD5311R SCL SDA ACK STOP CONDITION t14 t t15 13 LDAC SYNCHRONOUS ASYNCHRONOUS DAC UPDATE DAC UPDATE t16 RESET 11956-005 Figure 5. I2C, LDAC, and RESET Timing Rev. B | Page 7 of 24

AD5310R/AD5311R Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. THERMAL RESISTANCE A θ is defined by the JEDEC JESD51 standard, and the value is Table 6. JA dependent on the test board and test environment. Parameter Rating V to GND −0.3 V to +7 V DD Table 7. Thermal Resistance V to GND −0.3 V to +7 V LOGIC Package Type θ θ Unit JA JC V to GND −0.3 V to V + 0.3 V or +7 V OUT DD 10-Lead MSOP 1351 N/A2 °C/W (whichever is less) VREF to GND −0.3 V to VDD + 0.3 V or +7 V 1 JEDEC 2S2P test board, still air (0 m/sec airflow). (whichever is less) 2 N/A means not applicable. Digital Input Voltage to GND −0.3 V to VDD + 0.3 V or +7 V (whichever is less) ESD CAUTION Operating Temperature Range Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 135°C J Power Dissipation (T max − T )/θ J A JA ESD1 4 kV FICDM2 1.25 kV 1 Human body model (HBM) classification. 2 Field-induced charged-device model classification. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 8 of 24

Data Sheet AD5310R/AD5311R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 10 VOUT VLOGIC 2 AD5310R 9 VREF RESET 3 TOP VIEW 8 SDI LGDANCD 45 (Not to Scale) 76 SSCYNLKC 11956-006 Figure 6. Pin Configuration, AD5310R Table 8. AD5310R Pin Function Descriptions Pin No. Mnemonic Description 1 V Power Supply Input. This device can be operated from 2.7 V to 5.5 V. Decouple the supply to GND. DD 2 V Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND. LOGIC 3 RESET Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external pins are ignored. The input and DAC registers are loaded with zero-scale values, and the control register is loaded with default values. This pin can be tied to V if not used. LOGIC 4 LDAC Load DAC. LDAC can be operated in asynchronous mode (see Figure 3). Pulsing this pin low allows the DAC register to be updated if the input register has new data. This pin can be tied permanently low; in this case, the DAC register is automatically updated when new data is written to the input register. 5 GND Ground Reference. 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data is transferred at rates up to 50 MHz. 7 SYNC Synchronization Data Input. When SYNC goes low, it enables the SCLK and SDI buffers and the input shift register. 8 SDI Serial Data Input. Data is sampled on the falling edge of the SCLK. 9 V Reference Input/Output. By default, this pin is a reference output. It is recommended that this pin be REF decoupled with a 10 nF capacitor to GND. 10 V Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. OUT Rev. B | Page 9 of 24

AD5310R/AD5311R Data Sheet VDD 1 10 VOUT VLOGIC 2 AD5311R 9 VREF RESET 3 TOP VIEW 8 SDA LGDANCD 45 (Not to Scale) 76 SAC0L 11956-007 Figure 7. Pin Configuration, AD5311R Table 9. AD5311R Pin Function Descriptions Pin No. Mnemonic Description 1 V Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND. DD 2 V Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple the supply to GND. LOGIC 3 RESET Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and external pins are ignored. The input and DAC registers are loaded with zero-scale value, and the control register is loaded with default values. This pin can be tied to V if not used. LOGIC 4 LDAC Load DAC. Transfers the contents of the input register to the DAC register. It can be operated in two modes, asynchronously and synchronously, as shown in Figure 5. This pin can be tied permanently low; the DAC updates when new data is written to the input register. 5 GND Ground Reference. 6 A0 Programmable Address (ADDR1) for Multiple Package Decoding. The address pin can be updated on-the-fly. 7 SCL Serial Clock Line. 8 SDA Serial Data Input/Output. 9 V Reference Input/Output. The default for this pin is as a reference output. It is recommended to decouple this pin REF with a 10 nF capacitor to GND. 10 V Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation. OUT Rev. B | Page 10 of 24

Data Sheet AD5310R/AD5311R TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 B) 0.1 B) 0.1 NL (LS 0 NL (LS 0 I–0.1 D–0.1 –0.2 –0.2 –0.3 –0.3 –0.4 –0.4 –0.50 200 400 CODE600 800 1000 11956-011 –0.50 200 400 CODE600 800 1000 11956-008 Figure 8. INL Figure 11. DNL 0.5 0.06 U1_EXT VDD = 5V 0.4 U2_EXT GAIN = 1 UU31__EINXTT VREF = 2.5V 0.3 0.04 U2_INT U3_INT 0.2 R) 0.1 R)0.02 S S F F % 0 % E ( E ( TU–0.1 TU 0 –0.2 –0.3 –0.02 –0.4 –0.50 200 400 CODE600 800 1000 11956-013 –0.04 –40 0 TEMPERATUR40E (°C) 80 11956-014 Figure 9. TUE vs. Code Figure 12. TUE vs. Temperature 0.04 500 TA = 25°C VDD = 5V GAIN = 1 450 VREF = 2.5V 0.03 400 350 0.02 ZS INTERNAL REFERENCE, GAIN = 1 R) 300 FS EXTERNAL REFERENCE, GAIN = 2 FS A) FS INTERNAL REFERENCE, GAIN = 2 TUE (% 0.01 U1 INTERNAL REFERENCE I (µDD225000 ZFFSSS IIENNXTTTEEERRRNNNAAALLL RR REEEFFFEEERRREEENNNCCCEEE,, ,GG GAAAIINNIN == = 21 1 U2 INTERNAL REFERENCE 0 U3 INTERNAL REFERENCE 150 100 –0.01 U1 EXTERNAL REFERENCE U2 EXTERNAL REFERENCE 50 U3 EXTERNAL REFERENCE –0.02 2.70 3.30 3.75 VDD 4(V.2)5 4.75 5.25 11956-017 0 –40 –20 0 TEMP2E0RATU4R0E (°C)60 80 105 11956-033 Figure 10. TUE vs. Supply, Gain = 1 Figure 13. Supply Current vs. Temperature Rev. B | Page 11 of 24

AD5310R/AD5311R Data Sheet 350 500 VDD = 5V U1 INTERNAL REFERENCE TA = 25°C GAIN = 1 U2 INTERNAL REFERENCE GAIN = 1 300 VREF = 2.5V U3 INTERNAL REFERENCE VREF = 2.5V 400 U1 EXTERNAL REFERENCE U2 EXTERNAL REFERENCE 250 U3 EXTERNAL REFERENCE V) V) 300 R (µ 200 R (µ O O R R ER 150 ER 200 100 U1 INTERNAL REFERENCE U2 INTERNAL REFERENCE U3 INTERNAL REFERENCE 100 50 U1 EXTERNAL REFERENCE U2 EXTERNAL REFERENCE U3 EXTERNAL REFERENCE 0 –40 –20 0 TEMP2E0RATU4R0E (°C)60 80 105 11956-016 0 2.70 3.30 3.75 VD4D.2 5(V) 4.75 5.25 5.50 11956-019 Figure 14. Zero-Code Error and Offset Error vs. Temperature Figure 17. Zero-Code Error and Offset Error vs. Supply 0.03 0.030 TA = 25°C 0.025 GAIN = 1 0.02 VREF = 2.5V 0.020 0.01 0.015 R) R) 0.010 S S % F 0 % F 0.005 U1 INTERNAL REFERENCE ROR (–0.01 ROR ( 0 UU23 IINNTTEERRNNAALL RREEFFEERREENNCCEE ER ER–0.005 U1 EXTERNAL REFERENCE U2 EXTERNAL REFERENCE –0.02 U1 INTERNAL REFERENCE –0.010 U3 EXTERNAL REFERENCE U2 INTERNAL REFERENCE U3 INTERNAL REFERENCE –0.015 –0.03 U1 EXTERNAL REFERENCE VDD = 5V U2 EXTERNAL REFERENCE GAIN = 1 –0.020 U3 EXTERNAL REFERENCE VREF = 2.5V –0.04 –40 0 TEMPERATUR40E (°C) 80 11956-015 –0.025 2.70 3.30 3.75 VD4D.2 5(V) 4.75 5.25 5.50 11956-018 Figure 15. Gain Error and Full-Scale Error vs. Temperature Figure 18. Gain Error and Full-Scale Error vs. Supply 2.505 2.50015 U1 VDD = 5V TA = 25°C U2 U3 2.50010 2.503 2.50005 2.501 V (V)REF2.499 V (V)REF22..4590909050 2.49990 2.497 D11 2.49985 D12 2.495–40 1T0EMPERATURE (°C)60 11956-020 2.499802.5 D13 3.5 VDD (V) 4.5 5.5 11956-021 Figure 16. Internal Reference Voltage vs. Temperature Figure 19. Internal Reference Voltage vs. Supply Voltage Rev. B | Page 12 of 24

Data Sheet AD5310R/AD5311R 4.5 2.5009 VDD = 5V TA = 25°C 5.5V 4.0 TA = 25°C 5.0V GAIN = 1 2.5008 3.0V 2.7V 3.5 S 3.0 2.5007 T HI BER OF 22..50 V (V)REF 2.5006 M NU 1.5 2.5005 1.0 2.5004 0.5 02.500012.500042.500072.500102.500132.500162.500192.500222.500252.500282.500312.500342.500372.500402.50043V2.50046R2.50049EF2.50052 (2.50055V)2.500582.500612.500642.500672.500702.500732.500762.500792.500822.500852.500882.500912.500942.500972.50100 11956-023 2.500–30.005 –0.003 L–O0.A0D01 CURRE0N.T0 0(1A) 0.003 0.005 11956-024 Figure 20. Reference Output Spread Figure 23. Internal Reference Voltage vs. Load Current 1800 T TA = 25°C VDD = 5V VDD = 5V 1600 TA = 25°C Hz) V/√1400 n SD (1200 N E C1000 N 1 E R E 800 F E R L 600 A N ER 400 T N I 200 CH1 10µV M1.00s A CH1 2.00µV 11956-022 010 100 FR1kEQUENCY 1(H0kz) 100k 1M 11956-025 Figure 21. Internal Reference Noise, 0.1 Hz to 10 Hz Figure 24. Internal Reference Noise Spectral Density vs. Frequency T TA = 25°C T TA = 25°C VDD = 5V VDD = 5V 1 1 CH1 10µV M1.00s A CH1 2.00µV 11956-029 CH1 10µV M1.00s A CH1 2.00µV 11956-026 Figure 22. 0.1 Hz to 10 Hz Output Noise Plot, External Reference Figure 25. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference Rev. B | Page 13 of 24

AD5310R/AD5311R Data Sheet 1200 1.4 FMZUEIDRLSLOC-SSACCLAAELLEE VTGADA DI=N =2 =55 °V1C 1.0 SSIONUKRINCGIN, GV,D VD D=D 3 =V 5V TA = 25°C 1000 SINKING, VDD = 5V SOURCING, VDD = 3V 0.6 800 SD (nV/√Hz) 600 ΔV (V)OUT–00..22 N 400 –0.6 200 –1.0 010 100 FR1kEQUENCY 1(H0kz) 100k 1M 11956-027 –1.40 0.0L1OAD CURRENT (A0).02 0.03 11956-030 Figure 26. Noise Spectral Density, Gain = 1 Figure 29. Headroom/Footroom vs. Load Current 6 7 0x3FF VDD = 5V 0x3FF VDD = 5V 0x300 TA = 25°C 6 0x300 TA = 25°C 5 0x200 GAIN = 1 0x200 GAIN = 2 0x100 0x100 0x000 5 0x000 4 4 V) 3 V) 3 V (OUT 2 V (OUT 2 1 1 0 0 –1 –1–50 LOAD CUR0RENT (mA) 50 11956-028 –2–50 LOAD CUR0RENT (mA) 50 11956-031 Figure 27. Source and Sink Capability, Gain = 1 Figure 30. Source and Sink Capability, Gain = 2 4.5 2.5 CL = 0nF CL = 0nF 4.0 CL = 0.2nF CL = 0.2nF CL = 1nF CL = 1nF 3.5 CL = 4.7nF 2.0 CL = 4.7nF CL = 10nF CL = 10nF 3.0 1.5 V) 2.5 V) (UT (UT VO 2.0 VO 1.0 1.5 1.0 TVAD D= =2 55°VC 0.5 VTAD D= =2 55°VC GAIN = 2 GAIN = 1 0.5 RL = 2kΩ RL = 2kΩ INTERNAL REFERENCE = 2.5V INTERNAL REFERENCE = 2.5V 00 TIM0E.0 (1ms) 0.02 11956-037 00 TIM0E.0 (1ms) 0.02 11956-034 Figure 28. Settling Time vs. Capacitive Load, Gain = 2 Figure 31. Settling Time vs. Capacitive Load, Gain = 1 Rev. B | Page 14 of 24

Data Sheet AD5310R/AD5311R 0.0015 0 GAIN = 1 VDD = 5V GAIN = 2 0.0010 GAIN = 2 TA = 25°C –10 GAIN = 1 REFERENCE = 2.5V CODE = 0x7FFF TO 0x8000 0.0005 –20 B) 0 d –30 (V)OUT–0.0005 WIDTH ( –40 V D N –0.0010 A –50 B –0.0015 –60 VDD = 5V –0.0020 –70 TA = 25°C VOUT = MIDSCALE EXTERNAL REFERENCE = 2.5V, ±0.1V p-p –0.00250 1 2 3TIME (µs4) 5 6 7 11956-036 –801k 10k FREQU1E0N0kCY (Hz) 1M 10M 11956-040 Figure 32. Digital-to-Analog Glitch Impulse Figure 35. Multiplying Bandwidth, External Reference 2.5 V ± 0.1 V p-p, 10 kHz to 10 MHz 20 VTINADT D=E =R2 5N5°VACL REFERENCE = 2.5V 3 TVAD D= =2 55°VC MIDSCALE, GAIN = 2 V) B –30 d N ( O 2 TI R O V) C DIST –80 V (OUT SYNC MIDSCALE, GAIN = 1 NI MO 1 AR–130 H –1800 5 FREQUE1N0CY (kHz) 15 20 11956-038 0–5 0 TIME5 (µs) 10 15 11956-041 Figure 33. Total Harmonic Distortion at 1 kHz Figure 36. Exiting Power-Down to Midscale 6 0.06 5 0.05 4 0.04 VDD V (V)DD 32 00..0032 V (V)OUT 1 0.01 VOUT 0 0 –10 1 2 3 TIME4 (ms) 5 6 7 8–0.01 11956-039 Figure 34. Power-On, Reset to 0 V Rev. B | Page 15 of 24

AD5310R/AD5311R Data Sheet TERMINOLOGY Digital-to-Analog Glitch Impulse Relative Accuracy or Integral Nonlinearity (INL) Digital-to-analog glitch impulse is the impulse injected into the For the DAC, relative accuracy (or integral nonlinearity) is a analog output when the input code in the DAC register changes measurement of the maximum deviation, in LSBs, from a straight state. It is normally specified as the area of the glitch in nV-sec, line passing through the endpoints of the DAC transfer and is measured when the digital input code is changed by 1 LSB at function. See Figure 8 for a typical INL vs. code plot. a major carry transition (0x1FF to 0x200). Differential Nonlinearity (DNL) Digital Feedthrough Differential nonlinearity is the difference between the measured Digital feedthrough is a measure of the impulse injected into the change and the ideal 1 LSB change between any two adjacent analog output of the DAC from the digital inputs of the DAC, but it codes. A specified differential nonlinearity of ±1 LSB maximum is measured when the DAC output is not updated. Digital ensures monotonicity. This DAC is guaranteed monotonic by feedthrough is specified in nV-sec and is measured with a full- design. See Figure 11 for a typical DNL vs. code plot. scale code change on the data bus, that is, from all 0s to all 1s Zero Code Error and vice versa. Zero code error is a measurement of the output error when zero Output Noise Spectral Density code (0x000) is loaded to the DAC register. Ideally, the output Noise spectral density is a measurement of the internally generated should be 0 V. The zero code error of the input is always positive; random noise. Random noise is characterized as a spectral density the output of the DAC cannot fall below 0 V due to a combination (nV/√Hz). It is measured by loading the DAC to midscale and of the offset errors in the DAC and in the output amplifier. Zero measuring noise at the output. It is measured in nV/√Hz. See code error is expressed in mV. See Figure 14 and Figure 17 for plots Figure 22, Figure 25, and Figure 26 for plots of noise spectral of zero code error. density. See Figure 21 and Figure 24 for plots of the noise Full-Scale Error spectral density for the internal reference. Full-scale error is a measurement of the output error when full- Multiplying Bandwidth scale code (0x3FF) is loaded to the DAC register. The recom- The amplifiers within the DAC have a finite bandwidth. The mended output is V – 1 LSB or |2 × V | − 1 LSB. Full-scale REF REF multiplying bandwidth is a measure of this. A sine wave on the error is expressed in percent of full-scale range (% of FSR). See reference (with full-scale code loaded to the DAC) appears on Figure 15 and Figure 18 for plots of full-scale error. the output. The multiplying bandwidth is the frequency at Gain Error which the output amplitude falls to 3 dB below the input. Gain error is a measurement of the span error of the DAC. It is Total Harmonic Distortion (THD) the deviation in slope of the DAC transfer characteristic from THD is the difference between an ideal sine wave and its the ideal, expressed as % of FSR. attenuated version using the DAC. The sine wave is used as the Zero-Code Error Drift reference for the DAC, and the THD is a measurement of the Zero-code error drift is a measurement of the change in zero- harmonics present on the DAC output. It is measured in dB. code error with a change in temperature. It is expressed in µV/°C. Voltage Reference Temperature Coefficient (TC) Gain Temperature Coefficient Voltage reference TC is a measurement of the change in the Gain temperature coefficient is a measurement of the change in gain reference output voltage with a change in temperature. The error with changes in temperature. It is expressed in ppm of FSR/°C. reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a Offset Error given temperature range expressed in ppm/°C, as follows: Offset error is a measure of the difference between V (actual) OUT and VOUT (ideal) expressed in mV in the linear region of the transfer TC= VREFmax−VREFmin ×106 function. Offset error is measured with Code 4 loaded in the VREFnom×TempRange DAC register. It can be negative or positive. where: DC Power Supply Rejection Ratio (PSRR) V is the maximum reference output measured over the REFmax PSRR indicates how the output of the DAC is affected by changes total temperature range. in the supply voltage. PSRR is the ratio of the change in V to OUT V is the minimum reference output measured over the total REFmin a change in V for full-scale output of the DAC. It is measured DD temperature range. in dB. V is held at 2 V, and V varies by ±10%. REF DD V is the nominal reference output voltage, 2.5 V. REFnom Output Voltage Settling Time TempRange is the specified temperature range, −40°C to +105°C. Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change. Rev. B | Page 16 of 24

Data Sheet AD5310R/AD5311R THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER VREF The AD5310R/AD5311R are single-channel, 10-bit, serial input, R voltage output DACs with a 2.5 V internal reference. The devices operate from supply voltages of 2.7 V to 5.5 V. Data is written to R the AD5310R/AD5311R in a 24-bit word format via an I2C serial interface or SPI interface. R TO OUTPUT BUFFER The AD5310R/AD5311R incorporate a power-on reset circuit that ensures that the DAC output powers up to a zero scale. The devices also have a software power-down mode that reduces the typical current consumption to 2 μA maximum in specs. TRANSFER FUNCTION R The internal reference is on by default. The input coding to the DAC is straight binary, and the ideal output voltage is given by R the following equations: 11956-043 For the AD5310R, Figure 38. Simplified Resistor String Structure V (D)=Gain×V × D  Internal Reference OUT REF 1024 The AD5310R/AD5311R has a 2.5 V, 2 ppm/°C reference that For the AD5311R, provides a full-scale output of 2.5 V or 5 V, depending on the state of the gain bit, see Table 15.  D  V (D)=Gain×V × OUT REF 1024 The AD5310R/AD5311R on-chip reference is on at power-up but can be disabled via a write to the control register. where: The internal reference is available at the V pin. It is internally D is the decimal equivalent of the binary code that is loaded to REF buffered and capable of driving external loads of up to 50 mA. the DAC register. Gain is the gain of the output amplifier and is set to ×1 by External Reference default. The gain can also be set to 1 or 2 using the gain select The V pin can be configured as an input pin, allowing the use REF bit in the control register. of an external reference if the application requires it. The default DAC ARCHITECTURE condition of the on-chip reference is on at power-up. The DAC architecture implements a segmented string DAC Before connecting an external buffer to the pin, a write to the with an internal output buffer. Figure 37 shows the internal control register is required to disable the internal reference, see block diagram. the REF Bit section. VREF Output Buffer 2.5V The output buffer is designed as an input/output rail-to-rail REF buffer, which gives a maximum output voltage range of up to 0 REF (+) REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUT V to VDD. The gain bit sets the segmented string DAC gain to ×1 or ×2 as shown in Table 15. The output buffer voltage is REF (–) GND 11956-042 dTehtee romutipnuedt bbuyf fVerR EcFa, nth de rgivaein 1 b0int,F a cnadp tahceit aonffcsee tw ainthd ag a2i nk Ωer rors. Figure 37. DAC Channel Architecture Block Diagram resistor in parallel, as shown in Figure 34. If a higher capacitance The simplified segmented resistor string DAC structure is load is required, a shunt resistor must be connected between the shown in Figure 38. The code loaded to the DAC register output amplifier and the load. The slew rate is 0.7 V/µs with a ¼ determines the switch on the string that is connected to the to ¾ scale settling time of 5 µs. output buffer. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. Rev. B | Page 17 of 24

AD5310R/AD5311R Data Sheet SERIAL INTERFACE AD5310R SPI SERIAL DATA INTERFACE DAISY-CHAIN MODE COMPATIBILITY The AD5310R has a 3-wire serial interface (SYNC, SCLK, and The AD5310R can be operated in a daisy-chain configuration, SDI) that is compatible with serial peripheral interface (SPI), but cannot forward data because there is no SDO pin. To connect Mode 1 and Mode 2, and with completely synchronous interfaces the AD5310R in daisy-chain mode, it is possible to connect only such as SPORT. See Figure 3 for a timing diagram of a typical one device per chain, and the AD5310R should be connected write sequence. See the AN-1248 Application Note for more the last device. information about the SPI interface. Daisy-chaining minimizes the number of pins required from The write sequence begins by bringing the SYNC line low. Data the controlling IC. As shown in Figure 39, the SDO pin of one from the SDI line is sampled into the input shift register on the package must be tied to the SDI pin of the next package. The falling edge of SCLK. The SYNC pin must be held low until the clock period may need to be increased because of the propagation delay of the line between subsequent devices. By complete data-word (16 bits) is loaded from the SDI pin, as default, the daisy-chain configuration mode is disabled. To shown in Figure 3. When SYNC returns high, the serial data- enable it, the DCEN bit must be set in the control register, as word is decoded according to the instructions in Table 10. shown in Table 11. SYNC must be brought high for a minimum of 20 ns before the When the DCEN bit is enabled in the control register, the next write sequence such that a falling edge of SYNC can AD5310R accepts as a valid frame any data-word longer than 24 initiate the next write sequence. bits, and decodes the last 24 bits received, with the last 10 LSB If SYNC is brought high after 16 falling clock edges occur, it is as do not care bits. interpreted as a valid write and the first 16 bits are loaded to the AD5686 input shift register. CONTROLLER U1 MOSI SDIN If SYNC is brought high before 16 falling clock edges, the serial SCLK SCLK write is ignored and the write sequence is considered invalid. SS SYNC To minimize power consumption, it is recommended that all MISO SDO serial interface pins be operated close to the supply rails. SDI AD5310R U2 SCLK SYNC 11956-044 Figure 39. Daisy-Chain Connection SCLK 24 48 SYNC MOSI DB23 DB0 DB23 DB0 INPUT WORD FOR AD5310R INPUT WORD FOR AD5686 SDO_U1 DB23 DB0 UNDEFINED INPUT WORD FOR AD5310R 11956-045 Figure 40. Daisy-Chain Timing Diagram Rev. B | Page 18 of 24

Data Sheet AD5310R/AD5311R Table 10. SPI Command Operation Command Bits[DB15:DB12] Data Bits [DB11:DB0]1 C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 [DB1:DB0] Operation 0 0 0 0 X X X X X X X X X X XX NOP. Do nothing. 0 0 0 1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 XX Write input register. 0 0 1 0 X X X X X X X X X X XX Update DAC register (LDAC software). 0 0 1 1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 XX Write DAC and input register. 0 1 0 0 DB9 DB8 DB7 DB6 DB5 DB4 0 0 0 0 00 Write control register. 1 X = don’t care. I2C Address Table 11. Control Register Bits DB11 DB10 DB9 DB8 DB7 DB6 The AD5311R has a 7-bit slave address. The five MSBs are RESET PD1 PDO REF GAIN DCEN 10011. The second to the last bit, set by the state of the A0 address pin and the LSB, is 0. The ability to make hardwired AD5311R I2C SERIAL DATA INTERFACE changes to A0 lets the user have two of these devices on one bus, as outlined in Table 12. Additionally, the pin can be updated The AD5311R has a 2-wire, I2C-compatible serial interface. before starting the transmission, allowing multiples devices in the These devices can be connected to an I2C bus as a slave device, same bus by connecting the pin to a GPIO or a multiplexer. under the control of a master device. See Figure 4 for a timing diagram of a typical write sequence. Table 12. Device Address Selection The AD5311R supports standard (100 kHz) and fast (400 kHz) A0 Pin Connection A0 Bit I2C Address data transfer modes. Support is not provided for 10-bit GND 0 1001100 addressing and general call addressing. VLOGIC 1 1001110 The 2-wire serial bus protocol operates as follows: I2C Write Operation 1. The master initiates a data transfer by establishing a start When writing to the AD5311R, the user must begin with a start condition when a high to low transition on the SDA line condition followed by an address byte (R/W= 0), after which occurs while SCL is high. The following byte is the address the DAC acknowledges that it is prepared to receive data by byte, which consists of the 7-bit slave address. The slave pulling SDA low, as shown in Figure 41. The AD5311R requires address corresponding to the transmitted address responds a command byte that controls various DAC functions (see by pulling SDA low during the ninth clock pulse (this is Table 13) and two bytes of data for the DAC. All these data called the acknowledge bit). At this stage, all other devices bytes are acknowledged by the AD5311R. A stop condition on the bus remain idle while the selected device waits for follows. The write sequence is shown in Figure 41. data to be written to, or read from, its shift register. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all the data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then high during the tenth clock pulse to establish a stop condition. Rev. B | Page 19 of 24

AD5310R/AD5311R Data Sheet SCL SDA 1 0 0 1 1 A0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 START ADDRESS BYTE ACK MSB COMMAND BYTE ACK CONDITION BY BY BY AD5311R AD5311R MASTER SCL SDA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DATAHIGHBYTE ACK DATALOWBYTE ACK STOP AD5B3Y11R AD5B3Y11R CMONABDSYTITEIORN 11956-046 Figure 41. I2C Write Operation Table 13. I2C Command Table1 Command Byte Data High Byte Data Low Byte DB7 DB6 DB5 DB4 [DB3:DB0] [DB7:DB3] [DB2:DB0] [DB7:DB6] [DB5:DB0] Operation 0 0 0 0 XXXX XXXXX XXX XX XXXXX NOP: do nothing. 0 0 0 1 XXXX DB9:DB5 DB:DB2 DB1:DB0 XXXXX Write input register. 0 0 1 0 XXXX XXXXX XXX XX XXXXX Update DAC register (LDAC software). 0 0 1 1 XXXX DB9:DB5 DB4:DB2 DB1:DB0 XXXXX Write DAC and input registers. 0 1 0 0 XXXX DB9:DB5 000 00 00000 Write control register. 1 X = don’t care. Table 14. Control Register Bits DB9 DB8 DB7 DB6 DB5 RESET PD1 PDO REF GAIN Rev. B | Page 20 of 24

Data Sheet AD5310R/AD5311R COMMANDS PD0 and PD1 Bits Write Input Register The AD5310R/AD5311R provide two separate modes of The input register allows the preloading of a new value for the operation that are accessed by writing to the write control register. DAC register. The transfer from the input register to the DAC In normal mode, the output buffer is directly connected to the register can be triggered by hardware, by the LDAC pin, or by V pin. OUT software using Command 2. In power-down mode, the output buffer is internally disabled If new data is loaded into the DAC register, the DAC register and the V pin output impedance can be selected to a well- OUT automatically overwrites the input register. known value, as shown in Table 17. Update DAC Register Table 17. Operation Modes This command transfers the contents of the input register to the Operating Mode PD1 PD0 DAC register and, consequently, the V pin is updated. The OUT Normal Mode 0 0 data contained in the serial write is ignored. Power-Down Modes This operation is equivalent to a software LDAC. 1 kΩ Output Impedance 0 1 Write DAC Register 100 kΩ Output Impedance 1 0 Three-State Output Impedance 1 1 This command updates the DAC register on completion of the write operation. The input register is refreshed automatically In power-down mode, the part disables the output buffer, but with the DAC register value. does not disable the internal reference. To achieve maximum Write Control Register power saving, it is recommend that the REF bit be disabled. The write control register command is used to set the power- Disabling both the internal reference and the output buffer down and gain functions. It is also used to enable/disable the results in the supply current falling to 2 μA at 5 V. internal reference and perform a software reset. See Table 14 for The output stage is illustrated in Figure 42. the control register bits. Gain Bit The gain bit selects the gain of the output amplifier. Table 15 DAC AMPLIFIER VOUT shows how the output voltage range corresponds to the state of the gain bit. POWER-DOWN Table 15. Gain Bit CIRCUITRY RESISTOR Gain Output Voltage Range NETWORK 11956-047 0 0 V to V (default) REF Figure 42. Output Stage During Power-Down 1 0 V to 2 × V REF The output amplifier is shut down when the power-down mode is activated. However, unless the internal reference is powered REF Bit down, the bias generator, reference, and resistor string remain The on-chip reference is on at power-up by default. This reference on. The supply current falls to 2 μA at 5 V. The contents of the can be turned on or off by setting a software programmable bit, DAC register are unaffected in power-down mode, and the DAC DB6, in the control register. Table 16 shows how the state of the register can be updated while the device is in power-down mode. bit corresponds to the mode of operation. The time that is required to exit power-down is typically 4 µs for To reduce power consumption, it is recommended that the VDD = 5 V, or 600 µs if the reference is disabled. internal reference be disabled if the device is placed in power- Reset Bit down mode. The write control register of the AD5310R/AD5311R contains a Table 16. REF Bit software reset bits that resets the DAC registers to zero scale REF Reference Function and resets the input, the DAC, and the control registers to their 0 Reference enabled (default) default values. A software reset is initiated by setting the reset 1 Reference disabled bit in the control register to 1. When the software reset is completed, the reset bit is cleared to 0 automatically. Rev. B | Page 21 of 24

AD5310R/AD5311R Data Sheet LOAD DAC (HARDWARE LDAC PIN) HARDWARE RESET The AD5310R/AD5311R have a double buffered interface RESET is an active low signal that resets the DAC output to zero consisting of an input register and a DAC register. The LDAC scale and sets the input, DAC, and control registers to their default pin transfers data from the input register to the DAC register, values. It is necessary to keep RESET low for 75 ns to complete and the output is updated. the operation. When the RESET signal returns high, the output Synchronous DAC Update (AD5311R Only) remains at zero scale until a new value is programmed. While the RESET pin is low, the AD5310R/AD5311R ignore any new If the LDAC pin is held low while the input register is written, command. the DAC register, input register, and output are updated on the last SCL falling edge before the ACK bit, as shown in Figure 5. If RESET is held low at power-up, the internal reference is not Asynchronous DAC Update initialized correctly until the RESET pin is released. AD5311R, I2C READ OPERATION LDAC is held high while data is transmitted to the device. The DAC output is updated by taking LDAC low after the stop When reading the input register back from the AD5311R DAC, condition is generated. The output DAC is updated on the the user begins with an address byte (R/W = 1), after which the falling edge of the LDAC pin. DAC acknowledges that it is prepared to receive data by pulling SDA low. Two bytes of data containing the contents of the input If LDAC is pulsed while the device is accessed, the pulse is ignored. register are then read from the DAC, as shown in Figure 43. A NACK condition from the master followed by a stop condition completes the read sequence. 1 9 1 9 SCL SDA 1 0 0 1 1 A0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 START BY ACK. BY ACK. BY MASTER AD5311R MASTER FRAME 1 FRAME 2 SLAVE ADDRESS DATA HIGH BYTE 1 9 SCL (CONTINUED) SDA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (CONTINUED) DATFAR LAOMWE B3YTE NMAACSKT. EBRY SMTAOSPT EBRY 11956-048 Figure 43. I2C Read Operation Rev. B | Page 22 of 24

Data Sheet AD5310R/AD5311R THERMAL HYSTERESIS POWER-UP SEQUENCE Thermal hysteresis is the voltage difference induced on the Because diodes limit the voltage compliance at the digital and reference voltage by sweeping the temperature from ambient analog pins, it is important to power GND first before applying to cold, to hot, and then back to ambient. any voltage to V , V , and V . Otherwise, the diode is DD OUT LOGIC forward-biased such that V is powered unintentionally. The The thermal hysteresis data is shown in Figure 44. It is measured by DD ideal power-up sequence is GND, V , V , V , followed by sweeping the temperature from ambient +25°C to −40°C, then to DD LOGIC REF the digital inputs. +105°C, and finally returning to ambient +25°C. The V delta REF is next measured between the two ambient measurements and LAYOUT GUIDELINES shown in the solid lines in Figure 44. The same temperature In any circuit where accuracy is important, careful sweep and measurements are immediately repeated and the consideration of the power supply and ground return layout results are shown in the dashed lines in Figure 44. helps to ensure the rated performance. The PCB on which the 6 AD5310R/AD5311R are mounted should be designed such that FIRST TEMPERATURE SWEEP SUBSEQUENT… the AD5310R/AD5311Rare placed on the analog plane. 5 Ensure that the AD5310R/AD5311R have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, S 4 T HI located as close to the package as possible, ideally right up F O against the device. The 10 µF capacitors are the tantalum bead R 3 BE type. Use a 0.1 µF capacitor with low effective series resistance M NU 2 (ESR) and low effective series inductance (ESI), such as the common ceramic types, which provide a low impedance path to 1 ground at high frequencies to handle transient currents due to internal logic switching. –0100 –80 –60 D–4IS0TOR–T2IO0N (pp0m) 20 40 60 11956-050 Figure 44. Thermal Hysteresis Rev. B | Page 23 of 24

AD5310R/AD5311R Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 Resolution (Bits) Temperature Range Package Description Package Option Branding AD5310RBRMZ 10 −40°C to +105°C 10-Lead MSOP RM-10 DJZ AD5310RBRMZ-RL7 10 −40°C to +105°C 10-Lead MSOP RM-10 DJZ AD5311RBRMZ 10 −40°C to +105°C 10-Lead MSOP RM-10 DJX AD5311RBRMZ-RL7 10 −40°C to +105°C 10-Lead MSOP RM-10 DJX 1 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11956-0-2/17(B) Rev. B | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5311RBRMZ AD5310RBRMZ AD5310RBRMZ-RL7 AD5311RBRMZ-RL7 EVAL-AD5310RDBZ