2.5 V to 5.5 V, 400 μA, 2-Wire Interface, Quad Voltage Output, 8-/10-/12-Bit DACs AD5306/AD5316/AD5326 FEATURES FUNCTIONAL BLOCK DIAGRAM AD5306: 4 buffered, 8-bit DACs in 16-lead TSSOP VDD VREFAVREFB A version: ±1 LSB INL; B version: ±0.625 LSB INL AD5306/AD5316/AD5326 AD5316: 4 buffered, 10-bit DACs in 16-lead TSSOP LDAC A version: ±4 LSB INL; B version: ±2.5 LSB INL REINGPISUTTER REGDIASCTER SDTARCIN AG BUFFER VOUTA AD5326: 4 buffered, 12-bit DACs in 16-lead TSSOP A version: ±16 LSB INL; B version: ±10 LSB INL SCL REINGPISUTTER REGDIASCTER SDTARCIN BG BUFFER VOUTB Low power operation: 400 μA @ 3 V, 500 μA @ 5 V SDA INTERFACE A1 LOGIC 22.-5w Vir eto (I 52C.5® -Vc opmowpaetri bsulep)p sleyr ial interface LDAAC0 REINGPISUTTER REGDIASCTER SDTARCIN CG BUFFER VOUTC Guaranteed monotonic by design over all codes Power-down to 90 nA @ 3 V, 300 nA @ 5 V (PD pin or bit) REINGPISUTTER REGDIASCTER SDTARCIN DG BUFFER VOUTD Double-buffered input logic PORWEESRE-TON POWER-DOWN LOGIC BOuuftfpeuret dra/unngbeu: 0ff Ver teod V refe orre n0c Ve tion p2u Vt options VREFDVREFC PD GND 02066-001 REF REF Power-on reset to 0 V Figure 1. Simultaneous update of outputs (LDAC pin) Software clear facility GENERAL DESCRIPTION Data readback facility The AD5306/AD5316/AD53261 are quad 8-/10-/12-bit buffered On-chip rail-to-rail output buffer amplifiers voltage output DACs in 16-lead TSSOP packages that operate Temperature range −40°C to +105°C from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing APPLICATIONS with a slew rate of 0.7 V/μs. A 2-wire serial interface, which Portable battery-powered instruments operates at clock rates up to 400 kHz, is used. This interface is Digital gain and offset adjustment SMBus-compatible at V < 3.6 V. Multiple devices can be DD Programmable voltage and current sources placed on the same bus. Programmable attenuators Industrial process control Each DAC has a separate reference input that can be configured as buffered or unbuffered. The outputs of all DACs can be updated simultaneously using the asynchronous LDAC input. The parts incorporate a power-on reset circuit that ensures the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The software clear function clears all DACs to 0 V. The parts contain a power-down feature that reduces the current consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). All three parts have the same pinout, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. 1 Protected by U.S. Patent Numbers 5,969,657 and 5,684,481. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD5306/AD5316/AD5326 TABLE OF CONTENTS Specifications.....................................................................................3 Multiple DAC Write Sequence.................................................17 AC Characteristics........................................................................5 Multiple DAC Readback Sequence..........................................17 Timing Characteristics................................................................6 Write Operation..........................................................................18 Absolute Maximum Ratings............................................................7 Read Operation...........................................................................18 ESD Caution..................................................................................7 Double-Buffered Interface........................................................19 Pin Configuration and Function Descriptions.............................8 Load DAC Input LDAC.............................................................19 Terminology......................................................................................9 Power-Down Mode....................................................................19 Typical Performance Characteristics...........................................11 Applications.....................................................................................20 Functional Description..................................................................15 Typical Application Circuit.......................................................20 Digital-to-Analog Section.........................................................15 Driving V from the Reference Voltage................................20 DD Resistor String.............................................................................15 Bipolar Operation Using the AD5306/AD5316/AD5326.....20 DAC Reference Inputs...............................................................15 Multiple Devices on One Bus...................................................20 Output Amplifier........................................................................15 AD5306/AD5316/AD5326 as a Digitally Programmable Window Detector.......................................................................21 Power-On Reset..........................................................................16 Coarse and Fine Adjustment Using the Serial Interface............................................................................16 AD5306/AD5316/AD5326.......................................................21 Read/Write Sequence.................................................................16 Power Supply Decoupling.............................................................22 Pointer Byte Bits.........................................................................16 Outline Dimensions.......................................................................24 Input Shift Register.....................................................................16 Ordering Guide..........................................................................24 Default Readback Conditions...................................................17 REVISION HISTORY 8/05—Rev. E to Rev. F 8/03—Rev. B to Rev. C Replaced Figure 22.........................................................................13 Added A Version................................................................Universal Changes to Bipolar Operation Changes to FEATURES....................................................................1 Using the AD5306/AD5316/AD5326 Section........................20 Changes to SPECIFICATIONS.......................................................2 Changes to Ordering Guide..........................................................24 Changes to ABSOLUTE MAXIMUM RATINGS.........................5 Edits to ORDERING GUIDE..........................................................5 5/05—Rev. D to Rev. E Changes to TPC 21.........................................................................11 Changes to Table 1............................................................................3 Added OCTALS section to Table I...............................................18 11/04—Rev. C to Rev. D Updated OUTLINE DIMENSIONS............................................19 Change to Figure 31.......................................................................16 4/01—Rev. A to Rev. B Changes to Pointer Byte Section...................................................16 Edit to Figure 6...............................................................................13 Change to Figure 32.......................................................................17 Edits to RIGHT/LEFT section of Pointer Byte Bits section......13 Edits to Input Shift Register section............................................13 Edits to Figure 7..............................................................................13 Edits to Figure 8..............................................................................14 Edits to Figure 9..............................................................................14 Edit to Figure 12.............................................................................16 2/01—Rev. 0 to Rev. A 6/00—Revision 0: Initial Version Rev. F | Page 2 of 24

AD5306/AD5316/AD5326 SPECIFICATIONS V = 2.5 V to 5.5 V; V = 2 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD REF L L MIN MAX Table 1. A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments DC PERFORMANCE3, 4 AD5306 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.625 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes. AD5316 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2.5 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes. AD5326 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±10 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes. Offset Error ±5 ±60 ±5 ±60 mV VDD = 4.5 V, gain = 2; see Figure 4 and Figure 5. Gain Error ±0.3 ±1.25 ±0.3 ±1.25 % of FSR VDD = 4.5 V, gain = 2; see Figure 4 and Figure 5. Lower Deadband5 10 60 10 60 mV See Figure 4; lower deadband exists only if offset error is negative. Upper Deadband5 10 60 10 60 mV See Figure 5; upper deadband exists only if VREF = VDD and offset plus gain error is positive. Offset Error Drift6 −12 –12 ppm of FSR/°C Gain Error Drift6 –5 –5 ppm of FSR/°C DC Power Supply –60 –60 dB ΔVDD = ±10%. Rejection Ratio6 DC Crosstalk6 200 200 μV RL = 2 kΩ to GND or VDD. DAC REFERENCE INPUTS6 VREF Input Range 1 VDD 1 VDD V Buffered reference mode. 0.25 VDD 0.25 VDD V Unbuffered reference mode. VREF Input Impedance >10 >10 MΩ Buffered reference mode and power-down mode. 148 180 148 180 kΩ Unbuffered reference mode; 0 V to VREF output range. 74 90 74 90 kΩ Unbuffered reference mode; 0 V to 2 VREF output range. Reference Feedthrough −90 −90 dB Frequency = 10 kHz. Channel-to-Channel Isolation −75 −75 dB Frequency = 10 kHz. OUTPUT CHARACTERISTICS6 Minimum Output Voltage7 0.001 0.001 V This is a measure of the minimum and maximum drive capability of the output amplifier. Maximum Output Voltage7 VDD − 0.001 VDD − 0.001 V DC Output Impedance 0.5 0.5 Ω Rev. F | Page 3 of 24

AD5306/AD5316/AD5326 A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments Short-Circuit Current 25 25 mA VDD = 5 V. 16 16 mA VDD = 3 V. Power-Up Time 2.5 2.5 μs Coming out of power- down mode; VDD = 5 V. 5 5 μs Coming out of power- down mode; VDD = 3 V. LOGIC INPUTS (Excluding SCL, SDA)6 Input Current ±1 ±1 μA VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%. 0.6 0.6 V VDD = 3 V ± 10%. 0.5 0.5 V VDD = 2.5 V. VIH, Input High Voltage 1.7 1.7 V VDD = 2.5 V to 5.5 V; TTL and 1.8 V CMOS compatible. Pin Capacitance 3 3 pF LOGIC INPUTS (SCL, SDA)6 VIH, Input High Voltage 0.7 VDD VDD + 0.3 0.7 VDD VDD + 0.3 V SMBus compatible at VDD < 3.6 V. VIL, Input Low Voltage −0.3 +0.3 VDD −0.3 +0.3 VDD V SMBus compatible at VDD < 3.6 V. IIN, Input Leakage Current ±1 ±1 μA VHYST, Input Hysteresis 0.05 VDD 0.05 VDD V See Figure 20. CIN, Input Capacitance 8 8 pF Glitch Rejection 50 50 ns Input filtering suppresses noise spikes of less than 50 ns. LOGIC OUTPUT (SDA)6 VOL, Output Low Voltage 0.4 0.4 V ISINK = 3 mA. 0.6 0.6 V ISINK = 6 mA. Three-State Leakage Current ±1 ±1 μA Three-State Output 8 8 pF Capacitance POWER REQUIREMENTS VDD 2.5 5.5 2.5 5.5 V IDD (Normal Mode)8 VIH = VDD and VIL = GND; interface inactive. VDD = 4.5 V to 5.5 V 500 900 500 900 μA All DACs in unbuffered mode. Buffered mode, extra current is typically x mA per DAC, where x = 5 μA + VREF/RDAC. VDD = 2.5 V to 3.6 V 400 750 400 750 μA IDD (Power-Down Mode) VIH = VDD and VIL = GND; interface inactive. VDD = 4.5 V to 5.5 V 0.3 1 0.3 1 μA IDD = 3 μA (max) during readback on SDA. VDD = 2.5 V to 3.6 V 0.09 1 0.09 1 μA IDD = 1.5 μA (max) during readback on SDA. 1 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C. 2 See the Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5306 (Code 8 to 255); AD5316 (Code 28 to 1023); AD5326 (Code 115 to 4095). 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization; not production tested. 7 For the amplifier output to reach its minimum voltage, the offset error must be negative; for the amplifier output to reach its maximum voltage, VREF = VDD, the offset plus gain error must be positive. 8 Interface inactive; all DACs active. DAC outputs unloaded. Rev. F | Page 4 of 24

AD5306/AD5316/AD5326 AC CHARACTERISTICS V = 2.5 V to 5.5 V; R = 2 kΩ to GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted. DD L L MIN MAX Table 2. A, B Versions1, 2 Parameter3 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time V = V = 5 V REF DD AD5306 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) AD5316 7 9 μs 1/4 scale to 3/4 scale change (0x100 to 0x300) AD5326 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00) Slew Rate 0.7 V/μs Major-Code Change Glitch Energy 12 nV-s 1 LSB change around major carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 0.5 nV-s Analog Crosstalk 1 nV-s DAC-to-DAC Crosstalk 3 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p, unbuffered mode REF Total Harmonic Distortion −70 dB V = 2.5 V ± 0.1 V p-p, frequency = 10 kHz REF 1 Guaranteed by design and characterization; not production tested. 2 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C. 3 See the Terminology section. Rev. F | Page 5 of 24

AD5306/AD5316/AD5326 TIMING CHARACTERISTICS1 V = 2.5 V to 5.5 V; all specifications T to T , unless otherwise noted. DD MIN MAX Table 3. A, B Versions Parameter2 Limit at T , T Unit Conditions/Comments MIN MAX t 2.5 μs min SCL cycle time 1 t 0.6 μs min t , SCL high time 2 HIGH t 1.3 μs min t , SCL low time 3 LOW t 0.6 μs min t , start/repeated start condition hold time 4 HD,STA t 100 ns min t , data setup time 5 SU,DAT t 3 0.9 μs max t , data hold time 6 HD,DAT 0 μs min t 0.6 μs min t , setup time for repeated start 7 SU,STA t 0.6 μs min t , stop condition setup time 8 SU,STO t 1.3 μs min t , bus free time between a stop and a start condition 9 BUF t 300 ns max t, rise time of SCL and SDA when receiving 10 R 0 ns min t, rise time of SCL and SDA when receiving (CMOS compatible) R t 250 ns max t, fall time of SDA when transmitting 11 F 0 ns min t, fall time of SDA when receiving (CMOS compatible) F 300 ns max t, fall time of SCL and SDA when receiving F 20 + 0.1C 4 ns min t, fall time of SCL and SDA when transmitting B F t 20 ns min LDAC pulse width 12 t 400 ns min SCL rising edge to LDAC rising edge 13 C4 400 pF max Capacitive load for each bus line B 1 See Figure 2. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge. 4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD. START REPEATED START STOP CONDITION CONDITION CONDITION SDA t 9 t t t 10 11 4 t 3 SCL t4 t2 t1 t t t t 6 5 7 8 t 12 LDAC1 t13 t 12 LDAC2 12NASOYSTNYENCSCHHRROONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 02066-002 Figure 2. 2-Wire Serial Interface Timing Diagram Rev. F | Page 6 of 24

AD5306/AD5316/AD5326 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter1 Value may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V DD rating only; functional operation of the device at these or any SCL, SDA to GND −0.3 V to V + 0.3 V DD other conditions above those indicated in the operational A0, A1, LDAC, PD to GND −0.3 V to V + 0.3 V DD section of this specification is not implied. Exposure to absolute Reference Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect V A to V D to GND −0.3 V to V + 0.3 V OUT OUT DD device reliability. Operating Temperature Range Industrial (A, B Versions) −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (T max) 150°C J 16-Lead TSSOP Power Dissipation (T max − T )/θ J A JA θ Thermal Impedance 150.4°C/W JA Reflow Soldering Peak Temperature 220°C Time at Peak Temperature 10 sec to 40 sec 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. F | Page 7 of 24

AD5306/AD5316/AD5326 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 16 A1 VDD 2 15 A0 VOUTA 3 AD5306/ 14 SCL VOUTB 4 AD5316/ 13 SDA AD5326 VOUTC 5 TOP VIEW 12 GND VREFA 6 (Not to Scale) 11 VOUTD VREFB 7 10 PD VREFC 8 9 VREFD 02066-003 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. 2 V Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled DD with a10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 3 V A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 4 V B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 5 V C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 6 V A Reference Input Pin for DAC A. This pin can be configured as a buffered or an unbuffered input depending on REF the state of the BUF bit in the input word to DAC A. It has an input range from 0.25 V to V in unbuffered DD mode and from 1 V to V in buffered mode. DD 7 V B Reference Input Pin for DAC B. This pin can be configured as a buffered or an unbuffered input depending on REF the state of the BUF bit in the input word to DAC B. It has an input range from 0.25 V to V in unbuffered DD mode and from 1 V to V in buffered mode. DD 8 V C Reference Input Pin for DAC C. This pin can be configured as a buffered or an unbuffered input depending on REF the state of the BUF bit in the input word to DAC C. It has an input range from 0.25 V to V in unbuffered DD mode and from 1 V to V in buffered mode. DD 9 V D Reference Input Pin for DAC D. This pin can be configured as a buffered or an unbuffered input depending on REF the state of the BUF bit in the input word to DAC D. It has an input range from 0.25 V to V in unbuffered DD mode and from 1 V to V in buffered mode. DD 10 PD Active Low Control Input. Acts as a hardware power-down option. All DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state. The current consumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V). 11 V D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 12 GND Ground Reference Point for All Circuitry on the Part. 13 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 14 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit input shift register. Clock rates of up to 400 kbps can be accommodated in the I2C-compatible interface. 15 A0 Address Input. Sets the LSB of the 7-bit slave address. 16 A1 Address Input. Sets the second LSB of the 7-bit slave address. Rev. F | Page 8 of 24

AD5306/AD5316/AD5326 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) Major-Code Transition Glitch Energy For the DAC, it is a measure, in LSB, of the maximum deviation The energy of the impulse injected into the analog output when from a straight line passing through the endpoints of the DAC the code in the DAC register changes state. This energy is transfer function. Typical INL vs. code plots are shown in normally specified as the area of the glitch in nV-s and is Figure 6, Figure 7, and Figure 8. measured when the digital code is changed by 1 LSB at the major carry transition (011...11 to 100...00 or 100...00 to Differential Nonlinearity (DNL) 011...11). The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential Digital Feedthrough nonlinearity of 1 LSB maximum ensures monotonicity. This DAC A measure of the impulse injected into the analog output of a is guaranteed monotonic by design. Typical DNL vs. code plots DAC from the digital input pins of the device when the DAC are shown in Figure 9, Figure 10, and Figure 11. output is not being updated. Digital feedthrough is specified in Offset Error nV-s and is measured with a worst-case change on the digital A measure of the offset error of the DAC and the output ampli- input pins (that is, from all 0s to all 1s, and vice versa). fier. It can be positive or negative. See Figure 4 and Figure 5. Digital Crosstalk Offset error is expressed in mV. The glitch impulse transferred to the output of one DAC at Gain Error midscale in response to a full-scale code change (all 0s to all 1s, A measure of the span error of the DAC. It is the deviation in and vice versa) in the input register of another DAC. The slope of the actual DAC transfer characteristic from the ideal energy of the glitch is expressed in nV-s. expressed as a percentage of the full-scale range. Analog Crosstalk Offset Error Drift The glitch impulse transferred to the output of one DAC due to A measure of the change in offset error with changes in a change in the output of another DAC. Analog crosstalk is temperature. Offset error drift is expressed in (ppm of full-scale measured by loading one of the DACs with a full-scale code range)/°C. change (all 0s to all 1s, and vice versa) while keeping LDAC high and then pulsing LDAC low and monitoring the output of Gain Error Drift the DAC whose digital code has not changed. The energy of the A measure of the change in gain error with changes in glitch is expressed in nV-s. temperature. Gain error drift is expressed in (ppm of full-scale range)/°C. DAC-to-DAC Crosstalk The glitch impulse transferred to the output of one DAC due to DC Power Supply Rejection Ratio (PSRR) a digital code change and subsequent output change of another This indicates how the output of the DAC is affected by changes DAC. This includes both digital and analog crosstalk. Crosstalk in the supply voltage. PSRR is the ratio of the change in V to OUT is measured by loading one of the DACs with a full-scale code a change in V for full-scale output of the DAC. PSRR is DD measured in dB. V is held at 2 V and V is varied 10%. change (all 0s to all 1s, and vice versa) with LDAC low and then REF DD monitoring the output of another DAC. The energy of the glitch DC Crosstalk is expressed in nV-s. The dc change in the output level of one DAC at midscale in Multiplying Bandwidth response to a full-scale code change (all 0s to all 1s, and vice The amplifiers within the DAC have a finite bandwidth. The versa) and output change of another DAC. DC crosstalk is multiplying bandwidth is a measure of this. A sine wave on the expressed in μV. reference (with full-scale code loaded to the DAC) appears on Reference Feedthrough the output. The multiplying bandwidth is the frequency at The ratio of the amplitude of the signal at the DAC output to which the output amplitude falls to 3 dB below the input. the reference input when the DAC output is not being updated, Total Harmonic Distortion (THD) that is, when LDAC is high. Reference feedthrough is expressed The difference between an ideal sine wave and its attenuated in dB. version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics Channel-to-Channel Isolation present on the DAC output. THD is measured in dB. The ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. Channel-to-channel isolation is measured in dB. Rev. F | Page 9 of 24

AD5306/AD5316/AD5326 GAIN ERROR GAIN ERROR PLUS PLUS OFFSET ERROR OFFSET ERROR UPPER OUTPUT IDEAL OUTPUT ACTUAL DEADBAND VOLTAGE VOLTAGE CODES ACTUAL IDEAL NEGATIVE POSITIVE OEFRFRSOERT DAC CODE OEFRFRSOERT DAC CODE FULL SCALE 02066-005 Figure 5. Transfer Function with Positive Offset (VREF = VDD) LOWER DEADBAND CODES AMPLIFIER FOOTROOM NEGATIVE OFFSET ERROR 02066-004 Figure 4. Transfer Function with Negative Offset Rev. F | Page 10 of 24

AD5306/AD5316/AD5326 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 0.2 0.5 B) B) 0.1 R (LS R (LS RO 0 RO 0 R R INL E DNL E –0.1 –0.5 –0.2 –1.0 02066-006 –0.3 02066-009 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 6. AD5306 INL Figure 9. AD5306 DNL 3 0.6 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 2 0.4 INL ERROR (LSB) –011 DNL ERROR (LSB) –00..220 –2 –0.4 –3 02066-007 –0.6 02066-010 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 7. AD5316 INL Figure 10. AD5316 DNL 12 1.0 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 8 0.5 INL ERROR (LSB) –404 DNL ERROR (LSB) 0 –0.5 –8 –12 02066-008 –1.0 02066-011 0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000 CODE CODE Figure 8. AD5326 INL Figure 11. AD5326 DNL Rev. F | Page 11 of 24

AD5306/AD5316/AD5326 0.50 0.2 TA = 25°C TA = 25°C VDD = 5V 0.1 VREF = 2V GAIN ERROR 0.25 0 MAX DNL B) SR) –0.1 S MAX INL F ERROR (L 0 MIN DNL ERROR (% ––00..32 –0.25 –0.4 MIN INL OFFSET ERROR –0.50 02066-012 ––00..65 02066-015 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 2 3 4 5 6 VREF (V) VDD (V) Figure 12. AD5306 INL and DNL Error vs. VREF Figure 15. Offset Error and Gain Error vs. VDD 0.5 5 0.4 VDD = 5V 5V SOURCE VREF = 3V 0.3 4 0.2 MAX INL B) 0.1 3 3V SOURCE R (LS 0 MAX DNL (V)UT O O RR –0.1 MIN DNL V 2 E –0.2 –0.3 MIN INL 1 5V SINK ––00..54 02066-013 0 3V SINK 02066-016 –40 0 40 80 120 0 1 2 3 4 5 6 TEMPERATURE (°C) SINK/SOURCE CURRENT (mA) Figure 13. AD5306 INL and DNL Error vs. Temperature Figure 16. VOUT vs. Source and Sink Current Capability 1.0 300 VDD = 5V VREF = 2V 250 0.5 OFFSET ERROR 200 R) S ROR (% F 0 I (A)μDD 150 R GAIN ERROR E 100 –0.5 50 TA = 25°C –1.0 02066-014 0 VVDRDEF = = 5 2VV 02066-017 –40 0 40 80 120 ZERO SCALE FULL SCALE CODE TEMPERATURE (°C) Figure 14. AD5306 Offset Error and Gain Error vs. Temperature Figure 17. Supply Current vs. DAC Code Rev. F | Page 12 of 24

AD5306/AD5316/AD5326 600 TA = 25°C +25°C –40°C VDD = 5V 500 VREF = 5V CH1 400 +105°C VOUTA A) (μD 300 D I 200 SCL CH2 100 0 02066-018 02066-021 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CH1 1V, CH2 5V, TIME BASE = 1μs/DIV VDD (V) Figure 18. Supply Current vs. Supply Voltage Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change) 0.5 TA = 25°C VDD = 5V VREF = 2V 0.4 CH1 A) 0.3 VDD (μD –40°C D I 0.2 +25°C CH2 0.1 VOUTA 0 +105°C 02066-019 CH1 2V, CH2 200mV, TIME BASE = 200μs/DIV 02066-022 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Figure 19. Power-Down Current vs. Supply Voltage Figure 22. Power-On Reset to 0 V 400 TA = 25°C TA = 25°C VDD = 5V 350 VREF = 2V DECREASING INCREASING CH1 300 250 A) VDD = 5V VOUTA (μD 200 D I 150 DECREASING INCREASING 100 CH2 PD 5000 0V.5DD = 13.V0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.002066-020 CH1500mV,CH25V,TIMEBASE=1μs/DIV 02066-023 VLOGIC (V) Figure 20. Supply Current vs. Logic Input Voltage Figure 23. Exiting Power-Down to Midscale for SDA and SCL Voltage Increasing and Decreasing Rev. F | Page 13 of 24

AD5306/AD5316/AD5326 0.02 TA = 25°C VDD = 3V VDD = 5V VDD = 5V 0.01 V) QUENCY E ERROR ( 0 FRE SCAL L- L U F–0.01 350 400 450 500 550 600 02066-0-024 –0.02 02066-027 0 1 2 3 4 5 6 IDD (μA) VREF (V) Figure 24. IDD Histogram with VDD = 3 V and VDD = 5 V Figure 27. Full-Scale Error vs. VREF 2.50 2.49 V V) DI (UT mV/ O 1 V 2.48 2.47 02066-025 02066-028 50ns/DIV 1μs/DIV Figure 25. AD5326 Major Code Transition Glitch Energy Figure 28. DAC-to-DAC Crosstalk 10 0 –10 –20 B d –30 –40 –50 –60 02066-026 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 26. Multiplying Bandwidth (Small-Signal Frequency Response) Rev. F | Page 14 of 24

AD5306/AD5316/AD5326 FUNCTIONAL DESCRIPTION The AD5306/AD5316/AD5326 are quad resistor-string DACs DAC REFERENCE INPUTS fabricated on a CMOS process with resolutions of 8, 10, and Each of the four DACs has a reference pin. The reference 12 bits, respectively. Each contains four output buffer amplifiers inputs are buffered but can also be individually configured as and is written to via a 2-wire serial interface. They operate from unbuffered. The advantage with the buffered input is the high single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers impedance it presents to the voltage source driving it. However, provide rail-to-rail output swing with a slew rate of 0.7 V/μs. Each if the unbuffered mode is used, the user can have a reference DAC is provided with a separate reference input, which can be voltage as low as 0.25 V and as high as V , since there is no DD buffered to draw virtually no current from the reference source, restriction due to headroom and footroom of the reference or unbuffered to give a reference input range from 0.25 V to amplifier. V . The devices have a power-down mode in which all DACs DD can be turned off completely with a high impedance output. R DIGITAL-TO-ANALOG SECTION R The architecture of one DAC channel consists of a resistor-string TO OUTPUT DAC followed by an output buffer amplifier. The voltage at the R AMPLIFIER V pin provides the reference voltage for the corresponding REF DAC. Figure 29 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by R V ×D R VOUT = RE2FN 02066-030 where: Figure 30. Resistor String D is the decimal equivalent of the binary code that is loaded to If there is a buffered reference in the circuit (for example, the DAC register: REF192), there is no need to use the on-chip buffers of the AD5306/AD5316/AD5326. In unbuffered mode, the input 0 to 255 for AD5306 (8 bits) impedance is still large at typically 180 kΩ per reference input 0 to 1023 for AD5316 (10 bits) for 0 V to V mode and 90 kΩ for 0 V to 2 V mode. 0 to 4095 for AD5326 (12 bits) REF REF The buffered/unbuffered option is controlled by the BUF bit in N is the DAC resolution. the control byte. The BUF bit setting applies to whichever DAC VREFA is selected in the pointer byte. REFERENCE OUTPUT AMPLIFIER BUFFER BUF The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of V , GAIN, offset error, and gain error. If a gain REF REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTA of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. OUTAPMUPTL IBFUIEFRFER 02066-029 Itof a2 g VaiRnEF .o Bf 2ec iasu sseele ocft ecdla (mGpAinINg, =ho 1w),e tvheer, otuhtep muta rxainmguem is o0u.0tp01u tV is limited to V – 0.001 V. Figure 29. Single DAC Channel Architecture DD RESISTOR STRING The output amplifier is capable of driving a load of 2 kΩ to GND or V in parallel with 500 pF to GND or V . The source The resistor string section is shown in Figure 30. It is simply a DD DD and sink capabilities of the output amplifier can be seen in the string of resistors, each of value R. The digital code loaded to plot in Figure 16. the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The The slew rate is 0.7 V/μs with a half-scale settling time to voltage is tapped off by closing one of the switches connecting 0.5 LSB (at eight bits) of 6 μs. the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Rev. F | Page 15 of 24

AD5306/AD5316/AD5326 POWER-ON RESET SDA line remains high. The master then brings the SDA line low before the 10th clock pulse and then high during The AD5306/AD5316/AD5326 have a power-on reset function the 10th clock pulse to establish a stop condition. so that they power up in a defined state. The power-on state is READ/WRITE SEQUENCE • Normal operation For the AD5306/AD5316/AD5326, all write access sequences • Reference inputs unbuffered and most read sequences begin with the device address (with R/W = 0) followed by the pointer byte. This pointer byte speci- • 0 V to V output range REF fies the data format and determines that DAC is being accessed • Output voltage set to 0 V in the subsequent read/write operation (see Figure 1). In a write operation, the data follows immediately. In a read operation, the Both input and DAC registers are filled with 0s and remain so address is resent with R/W = 1, and the data is then read back. until a valid write sequence is made to the device. This is However, it is also possible to perform a read operation by particularly useful in applications where it is important to know sending only the address with R/W = 1. The previously loaded the state of the DAC outputs while the device is powering up. pointer settings are then used for the readback operation. SERIAL INTERFACE MSB LSB The AD5306/AD5316/AD5326 are controlled via an I2C- X X 0 0 DACD DACC DACB DACA 02066-031 compatible serial bus. These devices are connected to this bus as Figure 31. Pointer Byte slave devices; that is, no clock is generated by the AD5306/ POINTER BYTE BITS AD5316/AD5326 DACs. This interface is SMBus-compatible at VDD < 3.6 V. Table 6 describes the individual bits that make up the pointer byte. The AD5306/AD5316/AD5326 has a 7-bit slave address. The Table 6. Pointer Byte Bits five MSBs are 00011, and the two LSBs are determined by the Bit Description state of the A0 and A1 pins. The facility to make hardwired X Don’t care bits. changes to A0 and A1 allows the user to have up to four of these 0 Reserved bits. Must be set to 0. devices on one bus. DACD 1: The following data bytes are for DAC D. DACC 1: The following data bytes are for DAC C. The 2-wire serial bus protocol operates as follows: DACB 1: The following data bytes are for DAC B. DACA 1: The following data bytes are for DAC A. 1. The master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is INPUT SHIFT REGISTER the address byte, which consists of the 7-bit slave address The input shift register is 16 bits wide. Data is loaded into the followed by an R/W bit. This bit determines whether data device as two data bytes on the serial data line, SDA, under the is read from or written to the slave device. control of the serial clock input, SCL. The timing diagram for this operation is shown in Figure 2. The two data bytes consist The slave whose address corresponds to the transmitted of four control bits followed by 8, 10, or 12 bits of DAC data, address responds by pulling SDA low during the ninth depending on the device type. The first bits loaded are the clock pulse (this is termed the acknowledge bit). At this control bits: GAIN, BUF, CLR, and PD; the remaining bits are stage, all other devices on the bus remain idle while the left-justified DAC data bits, starting with the MSB (see Figure 32). selected device waits for data to be written to or read from its shift register. Table 7. Input Shift Register Control Bits 2. Data is transmitted over the serial bus in sequences of Bit Description nine clock pulses (eight data bits followed by an GAIN 0: Output range for that DAC set at 0 V to VREF. 1: Output range for that DAC set at 0 V to 2 V . acknowledge bit). The transitions on the SDA line must REF BUF 0: Reference input for that DAC is unbuffered. occur during the low period of SCL and remain stable 1: Reference input for that DAC is buffered. during the high period of SCL. CLR 0: All DAC registers and input registers are filled with 3. When all data bits have been read from or written to, a 0s on completion of the write sequence. 1: Normal operation. stop condition is established. In write mode, the master PD 0: On completion of the write sequence, all four DACs pulls the SDA line high during the 10th clock pulse to go into power-down mode. The DAC outputs enter a establish a stop condition. In read mode, the master issues high impedance state. a no acknowledge for the ninth clock pulse; that is, the 1: Normal operation. Rev. F | Page 16 of 24

AD5306/AD5316/AD5326 DEFAULT READBACK CONDITIONS MULTIPLE DAC READBACK SEQUENCE All pointer byte bits power up to 0. Therefore, if the user If the user attempts to read back data from more than one DAC initiates a readback without first writing to the pointer byte, no at a time, the part reads back the power-on condition of GAIN, single DAC channel has been specified. In this case, the default BUF, and data bits (all 0), and the current state of CLR and PD. readback bits are all 0 except for the CLR bit and the PD bit, which are 1. MULTIPLE DAC WRITE SEQUENCE Because there are individual bits in the pointer byte for each DAC, it is possible to write the same data and control bits to two, three, or four DACs simultaneously by setting the relevant bits to 1. MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE MSB 8-BIT AD5306 LSB MSB 8-BIT AD5306 LSB GAIN BUF CLR PD D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 MSB 10-BIT AD5316 LSB MSB 10-BIT AD5316 LSB GAIN BUF CLR PD D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 MSB 12-BIT AD5326 LSB MSB 12-BIT AD5326 LSB GAIN BUF CLR PD D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 02066-032 Figure 32. Data Formats for Write and Readback Rev. F | Page 17 of 24

AD5306/AD5316/AD5326 WRITE OPERATION READ OPERATION When writing to the AD5306/AD5316/AD5326 DACs, the user When reading data back from the AD5306/AD5316/AD5326 must begin with an address byte (R/W = 0), after which the DAC DACs, the user begins with an address byte (R/W = 0), after acknowledges that it is prepared to receive data by pulling SDA which the DAC acknowledges that it is prepared to receive data low. This address byte is followed by the pointer byte, which is by pulling SDA low. This address byte is usually followed by the also acknowledged by the DAC. Two bytes of data are then pointer byte, which is also acknowledged by the DAC. Following written to the DAC, as shown in Figure 33. A stop condition this, there is a repeated start condition by the master, and the follows. address is resent with R/W = 1. This is acknowledged by the DAC, indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 34. A stop condition follows. SCL SDA 0 0 0 1 1 A1 A0 R/W X X LSB START ACK MSB ACK CONDITION BY BY BY ADDRESS BYTE AD533x POINTER BYTE AD53x6 MASTER SCL SDA MSB LSB MSB LSB ACK ACK STOP MOSTSIGNIFICANTDATABYTE ADB5Y3x6 LEASTSIGNIFICANTDATABYTE ADB5Y3x6 CMONABDSYTITEIORN 02066-033 Figure 33. Write Sequence SCL SDA 0 0 0 1 1 A1 A0 R/W X X LSB START ACK MSB ACK CONDITION ADDRESS BYTE BY POINTERBYTE BY BY AD53x6 AD53x6 MASTER SCL SDA 0 0 0 1 1 A1 A0 R/W MSB LSB REPEATED ACK ACK COSNTDAIRTITON ADDRESS BYTE ADB5Y3x6 DATABYTE MABSYTER BY MASTER SCL SDA MSB LSB NO STOP LEASTSIGNIFICANTDATABYTE MAABSCYTKER CMONABDSYTITEIORN 02066-034 Figure 34. Readback Sequence Rev. F | Page 18 of 24

AD5306/AD5316/AD5326 In asynchronous mode, the outputs are not updated at the same However, if the master sends an ACK and continues clocking time the input registers are written to. When LDAC goes low, SCL (no stop is sent), the DAC retransmits the same two bytes of data on SDA. This allows continuous readback of data from the DAC registers are updated with the contents of the input the selected DAC register. registers. POWER-DOWN MODE Alternatively, the user can send a start followed by the address with R/W = 1. In this case, the previously loaded pointer The AD5306/AD5316/AD5326 have very low power consump- settings are used and readback of data can start immediately. tion, dissipating typically at 1.2 mW with a 3 V supply and 2.5 mW with a 5 V supply. Power consumption can be reduced DOUBLE-BUFFERED INTERFACE further when the DACs are not in use by putting them into The AD5306/AD5316/AD5326 DACs have double-buffered power-down mode, which is selected by setting the PD pin low interfaces consisting of two banks of registers: input registers or by setting Bit 12 (PD) of the data-word to 0. and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the When the PD pin is high and the PD bit is set to 1, all DACs work relevant input register on completion of a valid write sequence. normally with a typical power consumption of 500 μA at 5 V The DAC registers contain the digital code used by the resistor (400 μA at 3 V). In power-down mode, however, the supply strings. current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are powered down. Not only does the supply current drop, but each Access to the DAC registers is controlled by the LDAC pin. output stage is internally switched from the output of its ampli- When LDAC is high, the DAC registers are latched and the fier, making it open-circuit. This has the advantage that the input registers can change state without affecting the contents of outputs are three-state while the part is in power-down mode the DAC registers. When LDAC is low, however, the DAC and provides a defined input condition for whatever is connected registers become transparent and the contents of the input to the output of the DAC amplifiers. The output stage is shown registers are transferred to them. in Figure 35. Double-buffering is useful if the user requires simultaneous uinppduatt irnegg iostfe arlsl iDnAdiCvi douutaplluyt sa.n Tdh teh eunse, rb ym pauy lwsinrigte t htoe eLaDchA Cof the SRTERSINISGT DOARC AMPLIFIER VOUT input low, all outputs update simultaneously. These parts contain an extra feature whereby a DAC register is POCWIRECRU-IDTORWYN 02066-035 not updated unless its input register has been updated since the Figure 35. Output Stage During Power-Down last time that LDAC was low. Normally, when LDAC is low, the The bias generator, output amplifiers, resistor strings, and all DAC registers are filled with the contents of the input registers. other associated linear circuitry are shut down when power- In the AD5306/AD5316/AD5326, the part updates the DAC down mode is activated. However, the contents of the registers register only if the input register has been changed since the last are unaffected when in power-down. In fact, it is possible to time the DAC register was updated, thereby removing load new data into the input registers and DAC registers during unnecessary digital crosstalk. power-down. The DAC outputs update as soon as the PD pin LOAD DAC INPUT LDAC goes high or the PD bit is reset to 1. The time to exit power- LDAC transfers data from the input registers to the DAC down is typically 2.5 μs for VDD = 5 V and 5 μs for VDD = 3 V. registers and, therefore, updates the outputs. The LDAC This is the time from the rising edge of the eighth SCL pulse or from the rising edge of PD to when the output voltage deviates function enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes: synchronous mode and from its power-down voltage (see Figure 23). asynchronous mode. In synchronous mode, the DAC registers are updated after new data is read in on the rising edge of the eighth SCL pulse. LDAC can be tied permanently low or pulsed as in Figure 2. Rev. F | Page 19 of 24

AD5306/AD5316/AD5326 APPLICATIONS TYPICAL APPLICATION CIRCUIT BIPOLAR OPERATION USING THE AD5306/AD5316/AD5326 The AD5306/AD5316/AD5326 can be used with a wide range of reference voltages where the devices offer full one-quadrant The AD5306/AD5316/AD5326 are designed for single-supply multiplying capability over a reference range of 0 V to VDD. operation, but a bipolar output range is also possible using the More typically, these devices are used with a fixed precision- circuit in Figure 37. This circuit gives an output voltage range reference voltage. Suitable references for 5 V operation are the of ±5 V. Rail-to-rail operation at the amplifier output is AD780 and REF192 (2.5 V references). For 2.5 V operation, a achievable using an AD820 or an OP295 as the output amplifier. suitable external reference is the AD589, a 1.23 V band gap R2 reference. Figure 36 shows a typical setup for the AD5306/ 10kΩ AD5316/AD5326 when using an external reference. Note that +5V R1 +5V 6V TO 12V 10kΩ A0 and A1 can be high or low. 10μF 0.1μF AD820/ ±5V VDD = 2.5V TO 5.5V VDD VOUTA OP295 AD5306/ VIN AD5316/ –5V 0.1μF 10μF AD1585 AD5306/ AD5326 AD5316/ VOUT VREFA VIN AD5326 GND 1μF VVRREEFFCB VVOOUUTTCB VOUT 1μF VVRREEFFAB VVOOUUTTAB VAR1EFD VOUTD ERXETF VVRREEFFCD VVOOUUTTCD AG0ND SCL SDA AD780/REF192 OWRIV TADHDD V 5=9D 92D . W5=V I5TVH SSCDLAA0 GND A1 INTS2E-EWRRIFIRAAELCE 03756-A-037 INTSEERRFIAALCE 02066-036 The ouFitgpuuret v37o.l tBaipgoel afor rO apnerya tiinopnu wt itcho tdhee cAaDn5 3b0e6 c/AaDlc5u3l1a6te/AdD a5s3 f2o6l lows: Figure 36. AD5306/AD5316/AD5326 Using a 2.5 V External Reference ⎡(REFIN×D/2N)×(R1+R2)⎤ DRIVING VDD FROM THE REFERENCE VOLTAGE VOUT =⎢⎢ R1 ⎥⎥−REFIN×(R2/R1) ⎣ ⎦ If an output range of 0 V to V is required when the reference DD where: inputs are configured as unbuffered, the simplest solution is to connect the reference inputs to V . Because this supply may be DD D is the decimal equivalent of the code loaded to the DAC. noisy and somewhat inaccurate, the AD5306/AD5316/AD5326 N is the DAC resolution. may be powered from the reference voltage, for example, using REFIN is the reference voltage input. a 5 V reference such as the REF195. The REF195 outputs a steady supply voltage for the AD5306/AD5316/AD5326. The With REFIN = 5 V, R1 = R2 = 10 kΩ, typical current required from the REF195 is 500 μA supply V = (10 × D/2N) − 5 V current and approximately 112 μA to supply the reference OUT inputs, if unbuffered. This is with no load on the DAC outputs. MULTIPLE DEVICES ON ONE BUS When the DAC outputs are loaded, the REF195 also needs to Figure 38 shows four AD5306 devices on the same serial bus. supply the current to the loads. The total current required (with Each has a different slave address since the states of the A0 and a 10 kΩ load on each output) is A1 pins are different. This allows each of 16 DACs to be written to or read from independently. 612 μA + (5 V/10 kΩ) = 2.6 mA VDD VDD The load regulation of the REF195 is typically 2 ppm/mA, PULL-UP A1 AD5306 A1 AD5306 which results in an error of 5.2 ppm (26 μV) for the 2.6 mA RESISTORS A0 A0 SDA SCL SDA SCL current drawn from it. This corresponds to a 0.0013 LSB error at eight bits and a 0.021 LSB error at 12 bits. MASTER SDA SCL VDD SDA SCL A1 A1 A0 AD5306 A0 AD5306 02066-038 Figure 38. Multiple AD5306 Devices on One Bus Rev. F | Page 20 of 24

AD5306/AD5316/AD5326 AD5306/AD5316/AD5326 AS A DIGITALLY COARSE AND FINE ADJUSTMENT USING THE PROGRAMMABLE WINDOW DETECTOR AD5306/AD5316/AD5326 A digitally programmable upper/lower limit detector using two Two of the DACs in the AD5306/AD5316/AD5326 can be of the DACs in the AD5306/AD5316/AD5326 is shown in paired together to form a coarse and fine adjustment function, Figure 39. The upper and lower limits for the test are loaded to as shown in Figure 40. DAC A is used to provide the coarse DACs A and B, which, in turn, set the limits on the CMP04. If adjustment while DAC B provides the fine adjustment. Varying the signal at the VIN input is not within the programmed the ratio of R1 and R2 changes the relative effect of the coarse window, an LED indicates the fail condition. Similarly, DAC C and fine adjustments. With the resistor values and external and DAC D can be used for window detection on a second reference shown, the output amplifier has unity gain for the V signal. IN DAC A output; therefore, the output range is 0 V to 2.5 V − 1 LSB. For DAC B, the amplifier has a gain of 7.6 × 10−3, giving 5V 0.1μF 10μF VIN 1kΩ 1kΩ DAC B a range of 19 mV. Similarly, DAC C and DAC D can be paired together for coarse and fine adjustment. FAIL PASS VREF VREFA VDD The circuit in Figure 40 is shown with a 2.5 V reference, but VREFB 1/2 VOUTA reference voltages up to VDD may be used. The op amps AD5306/ indicated allow a rail-to-rail output swing. AD5316/ 1/2 PASS/FAIL AD53261 CMP04 R3 R4 DIN SDA VDD = 5V 51.2kΩ 390Ω SCL SCL VOUTB 1/6 74HC05 GND 5V 1ADDITIONAL PINS OMITTED FOR CLARITY 02066-039 0.1μF 10μF VDD VOUT Figure 39. Window Detection ERXETFVIVNOUT VREFA VOUTA 39R01Ω AODP822905/ 1μF GND VREFB 1/2 VOUTB R2 AD5306/ 51.2kΩ AD780/REF192 AD5316/ WITHVDD = 5V AD5326 GND 02066-040 Figure 40. Coarse/Fine Adjustment Rev. F | Page 21 of 24

AD5306/AD5316/AD5326 POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration The power supply lines of the AD5306/AD5316/AD5326 should of the power supply and ground return layout helps to ensure use as large a trace as possible to provide low impedance paths the rated performance. The printed circuit board on which the and reduce the effects of glitches on the power supply line. AD5306/AD5316/AD5326 is mounted should be designed so Components with fast-switching signals, such as clocks, should the analog and digital sections are separated and confined to be shielded with digital ground to avoid radiating noise to other certain areas of the board. parts of the board, and they should never be run near the reference inputs. A ground line routed between the SDA and If the AD5306/AD5316/AD5326 is in a system where multiple SCL lines helps to reduce crosstalk between them. Although a devices require an AGND-to-DGND connection, the connection ground line is not required on a multilayer board because there is should be made at one point only. The star ground point should a separate ground plane, separating the lines helps. be established as close as possible to the device. The AD5306/ AD5316/AD5326 should have ample supply bypassing of 10 μF Avoid crossover of digital and analog signals. Traces on opposite in parallel with 0.1 μF on the supply located as close to the sides of the board should run at right angles to each other. This package as possible, ideally right up against the device. The 10 μF reduces the effects of feedthrough through the board. A micro- capacitors are the tantalum bead type. The 0.1 μF capacitor should strip technique is the best method, but its use is not always have low effective series resistance (ESR) and low effective possible with a double-sided board. In this technique, the series inductance (ESI), like the common ceramic types that component side of the board is dedicated to ground plane while provide a low impedance path to ground at high frequencies to signal traces are placed on the solder side. handle transient currents due to internal logic switching. Table 8. Overview of AD53xx Serial Devices1 Part No. Resolution No. of DACs DNL Interface Settling Time (μs) Package Pins SINGLES AD5300 8 1 ±0.25 SPI 4 SOT-23, MSOP 6, 8 AD5310 10 1 ±0.5 SPI 6 SOT-23, MSOP 6, 8 AD5320 12 1 ±1.0 SPI 8 SOT-23, MSOP 6, 8 AD5301 8 1 ±0.25 2-wire 6 SOT-23, MSOP 6, 8 AD5311 10 1 ±0.5 2-wire 7 SOT-23, MSOP 6, 8 AD5321 12 1 ±1.0 2-wire 8 SOT-23, MSOP 6, 8 DUALS AD5302 8 2 ±0.25 SPI 6 MSOP 8 AD5312 10 2 ±0.5 SPI 7 MSOP 8 AD5322 12 2 ±1.0 SPI 8 MSOP 8 AD5303 8 2 ±0.25 SPI 6 TSSOP 16 AD5313 10 2 ±0.5 SPI 7 TSSOP 16 AD5323 12 2 ±1.0 SPI 8 TSSOP 16 QUADS AD5304 8 4 ±0.25 SPI 6 MSOP 10 AD5314 10 4 ±0.5 SPI 7 MSOP 10 AD5324 12 4 ±1.0 SPI 8 MSOP 10 AD5305 8 4 ±0.25 2-Wire 6 MSOP 10 AD5315 10 4 ±0.5 2-Wire 7 MSOP 10 AD5325 12 4 ±1.0 2-Wire 8 MSOP 10 AD5306 8 4 ±0.25 2-Wire 6 TSSOP 16 AD5316 10 4 ±0.5 2-Wire 7 TSSOP 16 AD5326 12 4 ±1.0 2-Wire 8 TSSOP 16 AD5307 8 4 ±0.25 SPI 6 TSSOP 16 AD5317 10 4 ±0.5 SPI 7 TSSOP 16 AD5327 12 4 ±1.0 SPI 8 TSSOP 16 OCTALS AD5308 8 8 ±0.25 SPI 6 TSSOP 16 AD5318 10 8 ±0.5 SPI 7 TSSOP 16 AD5328 12 8 ±1.0 SPI 8 TSSOP 16 1 Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information. Rev. F | Page 22 of 24

AD5306/AD5316/AD5326 Table 9. Overview of AD53xx Parallel Devices Part No. Resolution DNL V Pins Settling Time (μs) Additional Pin Functions Package Pins REF SINGLES BUF GAIN HBEN CLR AD5330 8 ±0.25 1 6 Yes Yes Yes TSSOP 20 AD5331 10 ±0.5 1 7 Yes Yes TSSOP 20 AD5340 12 ±1.0 1 8 Yes Yes Yes TSSOP 24 AD5341 12 ±1.0 1 8 Yes Yes Yes Yes TSSOP 20 DUALS AD5332 8 ±0.25 2 6 Yes TSSOP 20 AD5333 10 ±0.5 2 7 Yes Yes Yes TSSOP 24 AD5342 12 ±1.0 2 8 Yes Yes Yes TSSOP 28 AD5343 12 ±1.0 1 8 Yes Yes TSSOP 20 QUADS AD5334 8 ±0.25 2 6 Yes Yes TSSOP 24 AD5335 10 ±0.5 2 7 Yes Yes TSSOP 24 AD5336 10 ±0.5 4 7 Yes Yes TSSOP 28 AD5344 12 ±1.0 4 8 TSSOP 28 Rev. F | Page 23 of 24

AD5306/AD5316/AD5326 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0S.6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD5306ARU −40°C to +105°C 16-Lead TSSOP RU-16 AD5306ARU-REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 AD5306ARUZ1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5306ARUZ-REEL71 −40°C to +105°C 16-Lead TSSOP RU-16 AD5306BRU −40°C to +105°C 16-Lead TSSOP RU-16 AD5306BRU-REEL −40°C to +105°C 16-Lead TSSOP RU-16 AD5306BRU-REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 AD5306BRUZ1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5306BRUZ-REEL1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5306BRUZ-REEL71 −40°C to +105°C 16-Lead TSSOP RU-16 AD5316ARU −40°C to +105°C 16-Lead TSSOP RU-16 AD5316ARU-REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 AD5316ARUZ1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5316BRU −40°C to +105°C 16-Lead TSSOP RU-16 AD5316BRU-REEL −40°C to +105°C 16-Lead TSSOP RU-16 AD5316BRU-REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 AD5316BRUZ1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5316BRUZ-REEL1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5316BRUZ-REEL71 −40°C to +105°C 16-Lead TSSOP RU-16 AD5326ARU −40°C to +105°C 16-Lead TSSOP RU-16 AD5326ARU-REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 AD5326ARUZ1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5326BRU −40°C to +105°C 16-Lead TSSOP RU-16 AD5326BRU-REEL −40°C to +105°C 16-Lead TSSOP RU-16 AD5326BRU-REEL7 −40°C to +105°C 16-Lead TSSOP RU-16 AD5326BRUZ1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5326BRUZ-REEL1 −40°C to +105°C 16-Lead TSSOP RU-16 AD5326BRUZ-REEL71 −40°C to +105°C 16-Lead TSSOP RU-16 1 Z = Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02066–0–8/05(F) Rev. F | Page 24 of 24