2.5 V to 5.5 V, 230 μA, Dual Rail-to-Rail, Voltage Output 8-/10-/12-Bit DACs AD5302/AD5312/AD5322 FEATURES GENERAL DESCRIPTION AD5302: Two 8-bit buffered DACs in 1 package The AD5302/AD5312/AD5322 are dual 8-, 10-, and 12-bit A version: ±1 LSB INL, B version: ±0.5 LSB INL buffered voltage output DACs in a 10-lead MSOP that operate AD5312: Two 10-bit buffered DACs in 1 package from a single 2.5 V to 5.5 V supply, consuming 230 μA at 3 V. A version: ±4 LSB INL, B version: ±2 LSB INL Their on-chip output amplifiers allow the outputs to swing rail- AD5322: Two 12-bit buffered DACs in 1 package to-rail with a slew rate of 0.7 V/μs. The AD5302/AD5312/AD5322 A version: ±16 LSB INL, B version: ±8 LSB INL utilize a versatile 3-wire serial interface that operates at clock 10-lead MSOP rates up to 30 MHz and is compatible with standard SPI®, Micropower operation: 300 μA @ 5 V (including QSPI™, MICROWIRE™, and DSP interface standards. reference current) Power-down to 200 nA @ 5 V, 50 nA @ 3 V The references for the two DACs are derived from two reference 2.5 V to 5.5 V power supply pins (one per DAC). The reference inputs can be configured as Double-buffered input logic buffered or unbuffered inputs. The outputs of both DACs can be Guaranteed monotonic by design over all codes updated simultaneously using the asynchronous LDAC input. Buffered/Unbuffered reference input options The parts incorporate a power-on reset circuit, which ensures 0 V to V output voltage that the DAC outputs power-up to 0 V and remain there until a REF Power-on-reset to 0 V valid write takes place to the device. The parts contain a power- Simultaneous update of DAC outputs via LDAC down feature that reduces the current consumption of the Low power serial interface with Schmitt-triggered inputs devices to 200 nA at 5 V (50 nA at 3 V) and provides software- On-chip rail-to-rail output buffer amplifiers selectable output loads while in power-down mode. Qualified for automotive applications The low power consumption of these parts in normal operation APPLICATIONS makes them ideally suited for portable battery-operated equipment. The power consumption is 1.5 mW at 5 V, 0.7 mW Portable battery-powered instruments at 3 V, reducing to 1 μW in power-down mode. Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators FUNCTIONAL BLOCK DIAGRAM VDD VREFA POWER-ON AD5302/AD5312/AD5322 RESET INPUT DAC STRING REGISTER REGISTER DAC BUFFER VVOOUUTTAA SYNC INTERFACE LOGIC POWER-DOWN RESISTOR SCLK LOGIC NETWORK DIN REINGPISUTTER REGDIASCTER STDRAICNG BUFFER VVOOUUTTBB RESISTOR NETWORK LDAC VREFB GND 00928-001 Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2006-2011 Analog Devices, Inc. All rights reserved.

AD5302/AD5312/AD5322 TABLE OF CONTENTS Features..............................................................................................1  Low Power Serial Interface.......................................................15  Applications.......................................................................................1  Double-Buffered Interface........................................................15  General Description.........................................................................1  Power-Down Modes......................................................................16  Functional Block Diagram..............................................................1  Microprocessor Interfacing...........................................................17  Revision History...............................................................................2  AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface.......................................................................................17  Specifications.....................................................................................3  AD5302/AD5312/AD5322 to 68HC11/68L11 Interface......17  AC Specifications..........................................................................4  AD5302/AD5312/AD5322 to 80C51/80L51 Interface..........17  Timing Characteristics................................................................5  AD5302/AD5312/AD5322 to MICROWIRE Interface........17  Absolute Maximum Ratings............................................................7  Applications Information..............................................................18  ESD Caution..................................................................................7  Typical Application Circuit.......................................................18  Pin Configuration and Function Descriptions.............................8  Bipolar Operation Using the AD5302/AD5312/AD5322.....18  Terminology......................................................................................9  Opto-Isolated Interface for Process Control Applications...19  Typical Performance Characteristics...........................................10  Decoding Multiple AD5302/AD5312/AD5322s....................19  Functional Description..................................................................14  AD5302/AD5312/AD5322 as a Digitally Programmable Digital-to-Analog Section.........................................................14  Window Detector.......................................................................19  Resistor String.............................................................................14  Coarse and Fine Adjustment Using the DAC Reference Inputs...............................................................14  AD5302/AD5312/AD5322.......................................................20  Output Amplifier........................................................................14  Power Supply Bypassing and Grounding................................20  Power-On Reset..........................................................................14  Outline Dimensions.......................................................................21  Serial Interface................................................................................15  Ordering Guide..........................................................................22  Input Shift Register.....................................................................15  REVISION HISTORY 5/11—Rev. C to Rev. D Updated Outline Dimensions.......................................................21 Added Automotive Products Information.................Throughout Changes to Ordering Guide..........................................................21 Updated Outline Dimensions.......................................................21 8/03—Rev. 0 to Rev. A Changes to Ordering Guide..........................................................22 Changes to Features..........................................................................1 Changes to Specifications.................................................................2 4/06—Rev. B to Rev. C Changes to Absolute Maximum Ratings........................................4 Updated Format..................................................................Universal Changes to Ordering Guide.............................................................4 Updated Outline Dimensions.......................................................21 Updated Outline Dimensions.......................................................16 Changes to Ordering Guide..........................................................21 12/05—Rev. A to Rev. B Updated Format..................................................................Universal Rev. D | Page 2 of 24

AD5302/AD5312/AD5322 SPECIFICATIONS V = 2.5 V to 5.5 V, V = 2 V, R = 2 kΩ to GND, C = 200 pF to GND, all specifications T to T , unless otherwise noted. DD REF L L MIN MAX Table 1. A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments DC PERFORMANCE3, 4 AD5302 Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.5 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by design over all codes AD5312 Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±2 LSB Differential Nonlinearity ±0.05 ±0.5 ±0.05 ±0.5 LSB Guaranteed monotonic by design over all codes AD5322 Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±8 LSB Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Guaranteed monotonic by design over all codes Offset Error ±0.4 ±3 ±0.4 ±3 % of FSR See Figure 3 and Figure 4 Gain Error ±0.15 ±1 ±0.15 ±1 % of FSR See Figure 3 and Figure 4 Lower Deadband 10 60 10 60 mV See Figure 3 and Figure 4 Offset Error Drift5 −12 −12 ppm of FSR/°C Gain Error Drift5 −5 −5 ppm of FSR/°C Power Supply Rejection −60 −60 dB ∆V = ±10% DD Ratio5 DC Crosstalk5 30 30 μV DAC REFERENCE INPUTS5 V Input Range 1 V 1 V V Buffered reference mode REF DD DD 0 V 0 V V Unbuffered reference mode DD DD V Input Impedance >10 >10 MΩ Buffered reference mode REF 180 180 kΩ Unbuffered reference mode, input impedance = R DAC Reference Feedthrough −90 −90 dB Frequency = 10 kHz Channel-to-Channel −80 −80 dB Frequency = 10 kHz Isolation OUTPUT CHARACTERISTICS5 Minimum Output Voltage6 0.001 0.001 V min A measure of the minimum drive capability of the output amplifier Maximum Output Voltage6 V − V − V max A measure of the maximum drive capability of DD DD 0.001 0.001 the output amplifier DC Output Impedance 0.5 0.5 Ω Short-Circuit Current 50 50 mA V = 5 V DD 20 20 mA V = 3 V DD Power-Up Time 2.5 2.5 μs Coming out of power-down mode, V = 5 V DD 5 5 μs Coming out of power-down mode, V = 3 V DD LOGIC INPUTS5 Input Current ±1 ±1 μA V , Input Low Voltage 0.8 0.8 V V = 5 V ± 10% IL DD 0.6 0.6 V V = 3 V ± 10% DD 0.5 0.5 V V = 2.5 V DD V , Input High Voltage 2.4 2.4 V V = 5 V ± 10% IH DD 2.1 2.1 V V = 3 V ± 10% DD 2.0 2.0 V V = 2.5 V DD Pin Capacitance 2 3.5 2 3.5 pF Rev. D | Page 3 of 24

AD5302/AD5312/AD5322 A Version1 B Version1 Parameter2 Min Typ Max Min Typ Max Unit Test Conditions/Comments POWER REQUIREMENTS V 2.5 5.5 2.5 5.5 V I specification is valid for all DAC codes DD DD I (Normal Mode) Both DACs active and excluding load currents DD V = 4.5 V to 5.5 V 300 450 300 450 μA Both DACs in unbuffered mode, V = V and DD IH DD V = 2.5 V to 3.6 V 230 350 230 350 μA V = GND; in buffered mode, extra current is DD IL typically × μA per DAC where x = 5 μA + V /R REF DAC I (Full Power-Down) DD V = 4.5 V to 5.5 V 0.2 1 0.2 1 μA DD V = 2.5 V to 3.6 V 0.05 1 0.05 1 μA DD 1 Temperature range: A, B version: –40°C to +105°C. 2 See Terminology section. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5302 (Code 8 to 248); AD5312 (Code 28 to 995); AD5322 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 In order for the amplifier output to reach its minimum voltage, offset error must be negative. In order for the amplifier output to reach its maximum voltage, VREF = VDD and offset plus gain error must be positive. AC SPECIFICATIONS V = 2.5 V to 5.5 V, R = 2 kΩ to GND, C = 200 pF to GND, all specifications T to T , unless otherwise noted.1 DD L L MIN MAX Table 2. A, B Version2 Parameter3 Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time V = V = 5 V REF DD AD5302 6 8 μs ¼ Scale to ¾ Scale Change (0 × 40 to 0 × C0) AD5312 7 9 μs ¼ Scale to ¾ Scale Change (0 × 100 to 0 × C300) AD5322 8 10 μs ¼ Scale to ¾ Scale Change (0 × 400 to 0 × C00) Slew Rate 0.7 V/μs Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry (011…11 to 100…00) Digital Feedthrough 0.10 nV-s Analog Crosstalk 0.01 nV-s DAC-to-DAC Crosstalk 0.01 nV-s Multiplying Bandwidth 200 kHz V = 2 V ± 0.1 V p-p, Unbuffered Mode REF Total Harmonic Distortion −70 dB V = 2.5 V ± 0.1 V p-p, Frequency = 10 kHz REF 1 Guaranteed by design and characterization, not production tested. 2 Temperature range: A, B version: −40°C to +105°C. 3 See Terminology section. Rev. D | Page 4 of 24

AD5302/AD5312/AD5322 TIMING CHARACTERISTICS V = 2.5 V to 5.5 V, all specifications T to T , unless otherwise noted.1, 2, 3 DD MIN MAX Table 3. Parameter Limit at T , T (A, B Version) Unit Conditions/Comments MIN MAX t 33 ns min SCLK Cycle Time 1 t 13 ns min SCLK High Time 2 t 13 ns min SCLK Low Time 3 t 0 ns min SYNC to SCLK Active Edge Setup Time 4 t 5 ns min Data Setup Time 5 t 4.5 ns min Data Hold Time 6 t 0 ns min SCLK Falling Edge to SYNC Rising Edge 7 t 100 ns min Minimum SYNC High Time 8 t 20 ns min LDAC Pulse Width 9 t 20 ns min SCLK Falling Edge to LDAC Rising Edge 10 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 3 See Figure 2. t 1 SCLK t t8 t t3 2 t7 4 SYNC t 6 t 5 DIN1 DB15 DB0 t 9 LDAC t 10 LDAC 1SEE INPUT SHIFT REGISTER SECTION. 00928-002 Figure 2. Serial Interface Timing Diagram Rev. D | Page 5 of 24

AD5302/AD5312/AD5322 GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE IDEAL ACTUAL POSITIVE OFFSET DAC CODE ERROR DEADBAND AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR 02928-004 Figure 3. Transfer Function with Negative Offset GAIN ERROR PLUS OFFSET ERROR OUTPUT ACTUAL VOLTAGE IDEAL POSITIVE OEFRFRSOERT DAC CODE 00928-005 Figure 4. Transfer Function with Positive Offset Rev. D | Page 6 of 24

AD5302/AD5312/AD5322 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted.1 A Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VDD to GND –0.3 V to +7 V rating only; functional operation of the device at these or any Digital Input Voltage to GND –0.3 V to VDD + 0.3 V other conditions above those indicated in the operational Reference Input Voltage to –0.3 V to VDD + 0.3 V section of this specification is not implied. Exposure to absolute GND maximum rating conditions for extended periods may affect V A, V B to GND –0.3 V to V + 0.3 V OUT OUT DD device reliability. Operating Temperature Range Industrial (A, B Version) –40°C to +105°C Storage Temperature Range –65°C to +150°C Junction Temperature (T max) +150°C J 10-Lead MSOP Power Dissipation (T max – T )/θ J A JA θ Thermal Impedance 206°C/W JA θ Thermal Impedance 44°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C 1 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 7 of 24

AD5302/AD5312/AD5322 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 10 GND AD5302/ VDD 2 AD5312/ 9 DIN VREFB 3 AD5322 8 SCLK VVORUEFTAA 45 (NToOt Pto V SIEcWale) 76 SVYONUTCB 00928-003 Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Active Low Control Input. This pin transfers the contents of the input registers to their respective DAC registers. Pulsing LDAC low allows either or both DAC registers to be updated if the input registers have new data. This allows simultaneous updating of both DAC outputs. 2 V Power Supply Input. The parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND. DD 3 V B Reference Input Pin for DAC B. This is the reference for DAC B. It can be configured as a buffered or an REF unbuffered input, depending on the BUF bit in the control word of DAC B. It has an input range of 0 V to V in DD unbuffered mode and 1 V to V in buffered mode. DD 4 V A Reference Input Pin for DAC A. This is the reference for DAC A. It can be configured as a buffered or an REF unbuffered input depending on the BUF bit in the control word of DAC A. It has an input range of 0 V to V in DD unbuffered mode and 1 V to V in buffered mode. DD 5 V A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 6 V B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 7 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. 9 DIN Serial Data Input. This device has a 16-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. 10 GND Ground Reference Point for All Circuitry on the Part. Rev. D | Page 8 of 24

AD5302/AD5312/AD5322 TERMINOLOGY change (all 0s to all 1s and vice versa) while keeping LDAC Relative Accuracy For the DAC, relative accuracy or integral nonlinearity (INL) is high, then pulsing LDAC low, and monitoring the output of the a measure of the maximum deviation, in LSB, from a straight DAC whose digital code is not changed. The area of the glitch is line passing through the actual endpoints of the DAC transfer expressed in nV-sec. function. A typical INL vs. code plot can be seen in Figure 6. DAC-to-DAC Crosstalk Differential Nonlinearity This is the glitch impulse transferred to the output of one DAC Differential nonlinearity (DNL) is the difference between the due to a digital code change and subsequent output change of measured change and the ideal 1 LSB change between any two the other DAC. This includes both digital and analog crosstalk. adjacent codes. A specified differential nonlinearity of ±1 LSB It is measured by loading one of the DACs with a full-scale code maximum ensures monotonicity. This DAC is guaranteed change (all 0s to all 1s and vice versa) while keeping LDAC low monotonic by design. A typical DNL vs. code plot can be seen and monitoring the output of the other DAC. The area of the in Figure 9. glitch is expressed in nV-sec. Offset Error DC Crosstalk This is a measure of the offset error of the DAC and the output This is the dc change in the output level of one DAC in response amplifier. It is expressed as a percentage of the full-scale range. to a change in the output of the other DAC. It is measured with a full-scale output change on one DAC while monitoring the Gain Error other DAC. It is expressed in μV. This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from Power Supply Rejection Ratio (PSRR) the ideal expressed as a percentage of the full-scale range. This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to OUT Offset Error Drift a change in V for full-scale output of the DAC. It is measured DD This is a measure of the change in offset error with changes in in dB. V is held at 2 V and V is varied ±10%. REF DD temperature. It is expressed in (ppm of full-scale range)/°C. Reference Feedthrough Gain Error Drift This is the ratio of the amplitude of the signal at the DAC This is a measure of the change in gain error with changes in output to the reference input when the DAC output is not being temperature. It is expressed in (ppm of full-scale range)/°C. updated (that is, LDAC is high). It is expressed in dB. Major-Code Transition Glitch Energy Total Harmonic Distortion (THD) Major-code transition glitch energy is the energy of the impulse This is the difference between an ideal sine wave and its injected into the analog output when the code in the DAC attenuated version using the DAC. The sine wave is used as the register changes state. It is normally specified as the area of the reference for the DAC and the THD is a measure of the glitch in nV-sec and is measured when the digital code is harmonics present on the DAC output. It is measured in dB. changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The Digital Feedthrough multiplying bandwidth is a measure of this. A sine wave on the Digital feedthrough is a measure of the impulse injected into reference (with full-scale code loaded to the DAC) appears on the analog output of the DAC from the digital input pins of the the output. The multiplying bandwidth is the frequency at device, but is measured when the DAC is not being written to which the output amplitude falls to 3 dB below the input. (SYNC held high). It is specified in nV-sec and is measured with a full-scale change on the digital input pins, that is, from Channel-to-Channel Isolation Definition all 0s to all 1s and vice versa. This is a ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of the other DAC. It Analog Crosstalk is measured in dB. This is the glitch impulse transferred to the output of one DAC due to a change in the output of the other DAC. It is measured by loading one of the input registers with a full-scale code Rev. D | Page 9 of 24

AD5302/AD5312/AD5322 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.3 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 0.2 0.5 B) B) 0.1 R (LS R (LS RO 0 RO 0 R R INL E DNL E–0.1 –0.5 –0.2 –1.0 00928-006 –0.3 00928-009 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE Figure 6. AD5302 Typical INL Plot Figure 9. AD5302 Typical DNL Plot 3 0.6 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 2 0.4 B) 1 B) 0.2 R (LS R (LS RO 0 RO 0 R R INL E –1 DNL E–0.2 –2 –0.4 –3 00928-007 –0.6 00928-010 0 200 400 600 800 1000 0 200 400 600 800 1000 CODE CODE Figure 7. AD5312 Typical INL Plot Figure 10. AD5312 Typical DNL Plot 3 1.0 TA = 25°C TA = 25°C VDD = 5V VDD = 5V 2 0.5 B) 1 B) R (LS R (LS RO 0 RO 0 R R INL E –4 DNL E –0.5 –8 –12 00928-008 –1.0 00928-011 0 1000 2000 3000 4000 0 1000 2000 3000 4000 CODE CODE Figure 8. AD5322 Typical INL Plot Figure 11. AD5322 Typical DNL Plot Rev. D | Page 10 of 24

AD5302/AD5312/AD5322 1.00 TA = 25°C 0.75 VDD = 5V VDD = 5V 0.50 VDD = 3V B)0.25 MAX INL CY S N R (L 0 MAX DNL QUE RO MIN DNL RE ER–0.25 MIN INL F –0.50 ––01..7050 00928-012 0100 150 200 250 300 350 40000928-015 2 3 4 5 VREF(V) IDD(µA) Figure 12. AD5302 INL and DNL Error vs. VREF Figure 15. IDD Histogram with VDD = 3 V and VDD = 5 V 1.00 5 VDD = 5V VREF = 3V 5V SOURCE 0.75 4 0.50 MAX DNL MAX INL B)0.25 3 3V SOURCE LS V) R ( 0 (UT O O R V R 2 E–0.25 –0.50 MIN INL MIN DNL 3V SINK 1 5V SINK ––01..7050 00928-013 –0 00928-016 –40 0 40 80 120 0 1 2 3 4 5 6 TEMPERATURE(°C) SINK/SOURCE CURRENT(mA) Figure 13. AD5302 INL Error and DNL Error vs. Temperature Figure 16. Source and Sink Current Capability 1.0 VVDRDEF = = 52VV 600 TVAD D= =2 55°VC 500 0.5 400 %) A) RROR ( 0 GAIN ERROR I(µDD 300 E 200 –0.5 OFFSET ERROR 100 –1.0–40 0 40 80 12000928-014 0ZERO SCALE FULL SCALE 00928-017 TEMPERATURE(°C) Figure 14. Offset Error and Gain Error vs. Temperature Figure 17. Supply Current vs. Code Rev. D | Page 11 of 24

AD5302/AD5312/AD5322 600 BOTH DACS IN GAIN-OF-TWO MODE VDD = 5V REFERENCE INPUTS BUFFERED TA = 25°C 500 CH2 CLK 400 –40°C +25°C A) (µD 300 D I +105°C 200 CH1 VOUT 100 0 00928-018 00928-021 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CH1 1V, CH2 5V, TIME BASE = 5µs/DIV VDD(V) Figure 18. Supply Current vs. Supply Voltage Figure 21. Half-Scale Setting (¼ to ¾ Scale Code Change) 1.0 BOTH DACS IN TA = 25°C THREE-STATE CONDITION 0.8 VDD 0.6 A) µ ( D D I 0.4 –40°C +25°C CH1 0.2 VOUTA 02.7 3.2 3.7 4.2 4.7 +105°5C.2 00928-019 CH2 CH1 1V, CH2 1V, TIME BASE = 20µs/DIV 00928-022 VDD(V) Figure 19. Power-Down Current vs. Supply Voltage Figure 22. Power-On Reset to 0 V 700 TA = 25°C TA = 25°C 600 500 VOUT A) µ 400 CH1 ( IDD VDD = 5V 300 CH3 200 VDD = 3V CLK 100 00928-020 00928-023 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 CH1 1V, CH3 5V, TIME BASE = 1µs/DIV VLOGIC(V) Figure 20. Supply vs. Logic Input Voltage Figure 23. Existing Power-Down to Midscale Rev. D | Page 12 of 24

AD5302/AD5312/AD5322 2.50 2.49 V(V)OUT 2mV/DIV 2.48 2.47 00928-024 00928-026 500ns/DIV 1µs/DIV Figure 24. AD5322 Major-Code Transition Figure 26. DAC-to-DAC Crosstalk 10 1.0 TA = 25°C VDD = 5V 0 0.5 –10 V) R ( O R –20 R E B E 0 d L –30 CA S L L –40 U F–0.5 –50 –60 00928-025 –1.0 00928-027 10 100 1k 10k 100k 1M 10M 0 1 2 3 4 5 FREQUENCY(Hz) VREF (V) Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response) Figure 27. Full-Scale Error vs. VREF (Buffered) Rev. D | Page 13 of 24

AD5302/AD5312/AD5322 FUNCTIONAL DESCRIPTION The AD5302/AD5312/AD5322 are dual resistor-string DACs R fabricated on a CMOS process with resolutions of 8, 10, and 12 R bits, respectively. They contain reference buffers and output TO OUTPUT R buffer amplifiers, and are written to via a 3-wire serial interface. AMPLIFIER They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/μs. Each DAC is provided with a separate R rceufrerreenntc fer oinmp utht,e w rhefiecrhe cnacne sboeu bruceff,e orre du ntob udfrfaewre vdi rtotu gailvlye na o R 00928-029 reference input range from GND to V . The devices have three DD Figure 29. Resistor String programmable power-down modes, in which one or both DACs can be turned off completely with a high impedance output, or DAC REFERENCE INPUTS the output can be pulled low by an on-chip resistor. There is a reference input pin for each of the two DACs. The DIGITAL-TO-ANALOG SECTION reference inputs are buffered but can also be configured as unbuffered. The advantage of the buffered input is the high The architecture of one DAC channel consists of a reference impedance it presents to the voltage source driving it. buffer and a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference However, if the unbuffered mode is used, the user can have a voltage for the DAC. Figure 28 shows a block diagram of the reference voltage as low as GND and as high as V because DD DAC architecture. Because the input coding to the DAC is there is no restriction due to headroom and footroom of the straight binary, the ideal output voltage is given by reference amplifier. If there is a buffered reference in the circuit V ×D (for example, REF192), there is no need to use the on-chip V = REF OUT 2N buffers of the AD5302/AD5312/AD5322. In unbuffered mode, the impedance is still large (180 kΩ per reference input). where: The buffered/unbuffered option is controlled by the BUF bit in D = decimal equivalent of the binary code that is loaded to the the control word (see the Serial Interface section for a DAC register: description of the register contents). 0 to 255 for AD5302 (8 bits) 0 to 1023 for AD5312 (10 bits) OUTPUT AMPLIFIER 0 to 4095 for AD5322 (12 bits) The output buffer amplifier is capable of generating output N = DAC resolution. voltages to within 1 mV of either rail, which gives an output VREFA range of 0.001 V to VDD – 0.001 V when the reference is VDD. It is capable of driving a load of 2 kΩ in parallel with 500 pF to SWITCH CONTROLLED GND and VDD. The source and sink capabilities of the output REFERENCE BY CONTROL BUFFER LOGIC amplifier can be seen in Figure 16. The slew rate is 0.7 V/μs with a half-scale settling time to REINGPISUTTER REGDIASCTER RSETSRISINTOGR VOUTA ±0.5 LSB (at eight bits) of 6 μs. See Figure 21. OUTAPMUPTL IBFUIEFRFER 00928-028 POWER-ON RESET Figure 28. Single DAC Channel Architecture The AD5302/AD5312/AD5322 are provided with a power-on RESISTOR STRING reset function to power them up in a defined state. The power- on state is The resistor-string section is shown in Figure 29. It is simply a string of resistors, each of value R. The digital code loaded to • Normal operation the DAC register determines at what node on the string the • Reference inputs unbuffered voltage is tapped off to be fed into the output amplifier. The • Output voltage set to 0 V voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is Both input and DAC registers are filled with zeros and remain guaranteed monotonic. so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. Rev. D | Page 14 of 24

AD5302/AD5312/AD5322 SERIAL INTERFACE falling edges of SCLK for 16 clock pulses. Any data and clock The AD5302/AD5312/AD5322 are controlled over a versatile, pulses after the 16th are ignored, and no further serial data 3-wire serial interface, which operates at clock rates up to 30 MHz transfers occur until SYNC is taken high and low again. and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. SYNC can be taken high after the falling edge of the 16th SCLK INPUT SHIFT REGISTER pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t. The input shift register is 16 bits wide (see Figure 30 to Figure 32). 7 Data is loaded into the device as a 16-bit word under the control After the end of serial data transfer, data is automatically of a serial clock input, SCLK. The timing diagram for this transferred from the input shift register to the input register of operation is shown in Figure 2. The 16-bit word consists of four the selected DAC. If SYNC is taken high before the 16th falling control bits followed by 8, 10, or 12 bits of DAC data, depending edge of SCLK, the data transfer is aborted and the input on the device type. The first bit loaded is the MSB (Bit 15), registers are not updated. which determines whether the data is for DAC A or DAC B. Bit 14 determines if the reference input is buffered or unbuffered. When data has been transferred into both input registers, the Bit 13 and Bit 12 control the operating mode of the DAC. DAC registers of both DACs can be simultaneously updated by Table 6. Control Bits taking LDAC low. Bit Name Function Power-On Default LOW POWER SERIAL INTERFACE 15 A/B 0: Data Written to DAC A N/A To reduce the power consumption of the device even further, 1: Data Written to DAC B the interface only powers up fully when the device is being 14 BUF 0: Reference Is Unbuffered 0 written to. As soon as the 16-bit control word has been written 1: Reference Is Buffered to the part, the SCLK and DIN input buffers are powered down. 13 PD1 Mode Bit 0 They only power up again following a falling edge of SYNC. 12 PD0 Mode Bit 0 DOUBLE-BUFFERED INTERFACE BIT 15 BIT 0 (MSB) (LSB) The AD5302/AD5312/AD5322 DACs all have double-buffered A/B BUF PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X interfaces consisting of two banks of registers—input registers and DATA BITS 00928-030 DAC registers. The input register is connected directly to the input Figure 30. AD5302 Input Shift Register Contents shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC BIT 15 BIT 0 (MSB) (LSB) register contains the digital code used by the resistor string. A/B BUF PD1 FPiDg0ureD 391. AD8D53D172 InDp6uDt ADST5hAi fBtDI TR4SegiDs3ter CD2ontDe1nts D0 X X 00928-031 AWchceenss LtoD AthCe Dis AhCig hre, gthisete Dr AisC c ornegtriostlelerd is b lya ttchhee LdD anAdC t fhuen icntpiount . register can change state without affecting the contents of the BIT 15 BIT 0 (MSB) (LSB) DAC register. However, when LDAC is brought low, the DAC A/B BUF PD1 PD0 D11 D10 D9 D8 D7 DADT6A BDIT5S D4 D3 D2 D1 D0 00928-032 rreeggiisstteerr bareec otrmanessf terrarnesdp taor eitn. t and the contents of the input Figure 32. AD5322 Input Shift Register Contents This is useful if the user requires simultaneous updating of both The remaining bits are DAC data bits, starting with the MSB and DAC outputs. The user can write to both input registers ending with the LSB. The AD5322 uses all 12 bits of DAC data, individually and then, by pulsing the LDAC input low, both the AD5312 uses 10 bits and ignores the 2 LSB. The AD5302 uses outputs update simultaneously. eight bits and ignores the last four bits. The data format is straight These parts contain an extra feature whereby the DAC register binary, with all 0s corresponding to 0 V output, and all 1s is not updated unless its input register has been updated since corresponding to full-scale output (VREF – 1 LSB). the last time that LDAC was brought low. Normally, when The SYNC input is a level-triggered input that acts as a frame LDAC is brought low, the DAC registers are filled with the synchronization signal and chip enable. Data can only be contents of the input registers. In the case of the AD5302/ transferred into the device while SYNC is low. To start the serial AD5312/AD5322, the part only updates the DAC register if data transfer, SYNC should be taken low observing the minimum the input register has been changed since the last time the SYNC to SCLK active edge setup time, t. After SYNC goes low, DAC register was updated, thereby removing unnecessary 4 serial data is shifted into the device’s input shift register on the digital crosstalk. Rev. D | Page 15 of 24

AD5302/AD5312/AD5322 POWER-DOWN MODES The AD5302/AD5312/AD5322 have very low power consump- • The output is connected internally to GND through a tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW 1 kΩ resistor, with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three • The output is connected internally to GND through a power-down modes, which are selected by Bit 13 and Bit 12 100 kΩ resistor, or (PD1 and PD0) of the control word. Table 7 shows how the • The output is left open-circuited (three-state). state of the bits corresponds to the mode of operation of that particular DAC. The output stage is illustrated in Figure 33. Table 7. PD1/PD0 Operating Modes The bias generator, the output amplifier, the resistor string, PD1 PDO Operating Mode and all other associated linear circuitry are shut down when 0 0 Normal Operation the power-down mode is activated. However, the contents of 0 1 Power-Down (1 kΩ Load to GND) the registers are unaffected when in power-down. The time to 1 0 Power-Down (100 kΩ Load to GND) exit power-down is typically 2.5 μs for V = 5 V and 5 μs when DD 1 1 Power-Down (High Impedance Output) V = 3 V. See Figure 23 for a plot. DD When both bits are set to 0, the DACs work normally with AMPLIFIER their normal power consumption of 300 μA at 5 V. However, RESISTOR- for the three power-down modes, the supply current falls to STRING DAC VOUT 200 nA at 5 V (50 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the oTuhtips uhta os ft hthee a admvapnlitfaigeer ttoh aat rtehsei sotourt pnuett wimoprke doaf nkcneo owf nth vea pluaerst. is POCWIRECRU-IDTORWYN RNEETSWISOTORRK 00928-033 Figure 33. Output Stage During Power-Down known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. There are three different options. Rev. D | Page 16 of 24

AD5302/AD5312/AD5322 MICROPROCESSOR INTERFACING AD5302/AD5312/AD5322 TO ADSP-2101/ADSP- AD5302/AD5312/AD5322 TO 80C51/80L51 2103 INTERFACE INTERFACE Figure 34 shows a serial interface between the AD5302/AD5312/ Figure 36 shows a serial interface between the AD5302/AD5312/ AD5322 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP- AD5322 and the 80C51/80L51 microcontroller. The setup for 2103 should be set up to operate in the SPORT transmit alternate the interface is as follows: TXD of the 80C51/80L51 drives framing mode. The ADSP-2101/ADSP-2103 sport is programmed SCLK of the AD5302/AD5312/AD5322, while RXD drives the through the SPORT control register and should be configured serial data line of the part. The SYNC signal is again derived as follows: internal clock operation, active low framing, 16-bit from a bit programmable pin on the port. In this case, port line word length. Transmission is initiated by writing a word to the P3.3 is used. When data is to be transmitted to the AD5302/ Tx register after the SPORT has been enabled. The data is clocked AD5312/AD5322, P3.3 is taken low. The 80C51/80L51 transmit out on each falling edge of the DSP’s serial clock and clocked into data in 8-bit bytes only; thus only eight falling clock edges occur the AD5302/AD5312/AD5322 on the rising edge of the DSP’s serial in the transmit cycle. To load data to the DAC, P3.3 is left low clock. This corresponds to the falling edge of the DAC’s SCLK. after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken ADSP-2101/ AD5302/ high following the completion of this cycle. The 80C51/80L51 ADSP-21031 AD5312/ AD53221 output the serial data in a format that has the LSB first. The AD5302/AD5312/AD5322 require their data with the MSB as TFS SYNC the first bit received. The 80C51/80L51 transmit routine should DT DIN take this into account. SCLK SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY 00928-034 80C51/80L511 AADD55330122// Figure 34. AD5302/AD5312/AD5322 to ADSP-2101/ADSP-2103 Interface AD53221 AD5302/AD5312/AD5322 TO 68HC11/68L11 P3.3 SYNC INTERFACE TXD SCLK RXD DIN FAiDgu5r3e2 325 a nshdo twhse a6 s8eHriCal1 i1n/t6e8rfLa1c1e mbeitcwroeecno nthtreo AlleDr.5 S3C02K/ AoDf t5h3e1 2/ 1ADDITIONAL PINS OMITTED FOR CLARITY 00928-036 68HC11/68L11 drives the SCLK of the AD5302/AD5312/AD5322, Figure 36. AD5302/AD5312/AD5322 to 80C51/80L51 Interface while the MOSI output drives the serial data line of the DAC. AD5302/AD5312/AD5322 TO MICROWIRE The SYNC signal is derived from a port line (PC7). The setup INTERFACE conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit = 0 Figure 37 shows an interface between the AD5302/AD5312/ and its CPHA bit = 1. When data is being transmitted to the AD5322 and any MICROWIRE-compatible device. Serial data is DAC, the SYNC line is taken low (PC7). When the 68HC11/ shifted out on the falling edge of the serial clock and is clocked 68L11 are configured as above, data appearing on the MOSI into the AD5302/AD5312/AD5322 on the rising edge of the SK. output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight MICROWIRE1 AD5302/ AD5312/ falling clock edges occurring in the transmit cycle. Data is AD53221 transmitted MSB first. In order to load data to the CS SYNC AD5302/AD5312/AD5322, PC7 is left low after the first eight SK SCLK bits are transferred and a second serial write operation is SO DIN ppreorfcoerdmureed. to the DAC; PC7 is taken high at the end of this 1ADDITIONAL PINS OMITTED FOR CLARITY 00928-037 Figure 37. AD5302/AD5312/AD5322 to MICROWIRE Interface 68HC11/68L111 AD5302/ AD5312/ AD53221 PC7 SYNC SCK SCLK MOSI DIN 1ADDITIONAL PINS OMITTED FOR CLARITY 359280-00 Figure 35. AD5302/AD5312/AD5322 to 68HC11/68L11 Interface Rev. D | Page 17 of 24

AD5302/AD5312/AD5322 APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT 6V to 16V The AD5302/AD5312/AD5322 can be used with a wide range VIN 0.1µF 10µF of reference voltages, especially if the reference inputs are REF195 configured to be unbuffered, in which case the devices offer full, VOUT VDD one-quadrant multiplying capability over a reference range of GND 1µF VREFA VOUTA 0 V to V . More typically, the AD5302/AD5312/AD5322 can VREFB DD AD5302/AD5312/ be used with a fixed, precision reference voltage. Figure 38 AD5322 shows a typical setup for the AD5302/AD5312/AD5322 SCLK when using an external reference. If the reference inputs are DIN VOUTB SYNC unbuffered, the reference input range is from 0 V to V , but if DD GND trhede uocne-dc.h Sipu irteafbelree rnecfee rbeunfcfeesr sf oarr e5 uVse odp, etrhaet iroenfe areren cthe er aAnDge7 8is0 INTSEERRFIAALCE 00928-039 and REF192 (2.5 V references). For 2.5 V operation, a suitable Figure 39. Using a REF195 as Power and Reference to the external reference would be the REF191, a 2.048 V reference. AD5302/AD5312/AD5322 VDD = 2.5V to 5.5V BIPOLAR OPERATION USING THE AD5302/AD5312/AD5322 VDD ERXETF VOUT VREFA VOUTA The AD5302/AD5312/AD5322 are designed for single-supply 1µF VREFB operation, but bipolar operation is also achievable using the AD780/REF192 WITH VDD = 5V AD5302/AD5312/ circuit shown in Figure 40. This circuit is configured to achieve OR REF191 WITH AD5322 an output voltage range of –5 V < V < +5 V. Rail-to-rail VDD = 2.5V SCLK OUT DIN operation at the amplifier output is achievable using an AD820 SYNC VOUTB or OP295 as the output amplifier. GND INTSEERRFIAALCE 00928-038 6V to 16V VDD = 5V 10Rk2Ω Figure 38. AD5302/AD5312/AD5322 Using External Reference 0.1µF 10µF +5V R1 10kΩ If an output range of 0 V to V is required when the reference VIN DD ±5V inputs are configured as unbuffered (for example, 0 V to 5 V), REF195 VDD AD820/ the simplest solution is to connect the reference inputs to VDD. GNDVOUT 1µF VREFA/B –5V OP295 As this supply cannot be very accurate and can be noisy, the AD5302/AD5312/ AD5322 AD5302/AD5312/AD5322 can be powered from the reference SCLK voltage, for example, a 5 V reference such as the REF195, as DIN SYNC VOUTA/B shown in Figure 39. The REF195 outputs a steady supply GND vfroolmtag teh efo Rr EthFe1 9A5D is5 330020/ AμAD 5su3p1p2/lyA cDu5r3re2n2t. aTnhde acpuprrreonxtim reaqtueliyr ed INTSEERRFIAALCE 00928-040 30 μA into each reference input. This is with no load on the Figure 40. Bipolar Operation Using the AD5302/AD5312/AD5322 DAC outputs. When the DAC outputs are loaded, the REF195 The output voltage for any input code can be calculated as also needs to supply the current to the loads. The total current follows: required (with a 10 kΩ load on each output) is ( ) ⎡V ×D/2N ×(R1+R2)⎤ ⎛ 5V ⎞ V =⎢ REF ⎥−V ×(R2/R1) 360μA+2⎜⎜10kΩ⎟⎟=1.36 mA OUT ⎣ R1 ⎦ REF ⎝ ⎠ where: The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 2.7 ppm (13.5 μV) for the 1.36 mA D is the decimal equivalent of the code loaded to the DAC. current drawn from it. This corresponds to a 0.0007 LSB error N is the DAC resolution. at eight bits and a 0.011 LSB error at 12 bits. V is the reference voltage input. REF If V = 5 V, R1 = R2 = 1 kΩ, and V = 5 V: REF DD ( ) V = 10×D/2N −5V OUT Rev. D | Page 18 of 24

AD5302/AD5312/AD5322 OPTO-ISOLATED INTERFACE FOR PROCESS The 74HC139 is used as a 2-to-4 line decoder to address any of CONTROL APPLICATIONS the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the Each AD5302/AD5312/AD5322 has a versatile 3-wire serial coded address inputs are changing state. Figure 42 shows a interface, making them ideal for generating accurate voltages in diagram of a typical setup for decoding multiple AD5302/ process control and industrial applications. Due to noise, safety AD5312/AD5322 devices in a system. requirements, or distance, it can be necessary to isolate the AD5302/AD5312/AD5322 from the controller. This can easily SCLK AD5302/AD5312/AD5322 be achieved by using opto-isolators, which provide isolation in SYNC DIN DIN excess of 3 kV. The serial loading structure of the AD5302/ VDD SCLK AD5312/AD5322 makes them ideally suited for use in opto- VCC isolated applications. Figure 41 shows an opto-isolated interface ENABLE 1G 74HC1391Y0 AD5302/AD5312/AD5322 to the AD5302/AD5312/AD5322 where DIN, SCLK, and SYNC CODED 1A 1Y1 SYNC are driven from opto-couplers. The power supply to the part ADDRESS 1B 11YY23 DSCINLK DGND also needs to be isolated by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply AD5302/AD5312/AD5322 SYNC required for the AD5302/AD5312/AD5322. DIN SCLK 5V REGULATOR AD5302/AD5312/AD5322 POWER 10µF 0.1µF SYNC DSCINLK 00928-042 VDD Figure 42. Decoding Multiple AD5302/AD5312/AD5322 Devices in a System 10kΩ VDD AD5302/AD5312/AD5322 AS A DIGITALLY SCLK SCLK VREFA PROGRAMMABLE WINDOW DETECTOR VREFB Figure 43 shows a digitally programmable upper-/lower-limit AD5302/AD5312/ VDD AD5322 detector using the two DACs in the AD5302/AD5312/AD5322. 10kΩ VOUTA The upper and lower limits for the test are loaded to DAC A SYNC SYNC VOUTB and DAC B, which, in turn, set the limits on the CMP04. If the signal at the V input is not within the programmed window, IN an LED indicates the fail condition. VDD 5V 10kΩ DIN DIN 0.1µF 10µF VIN 1kΩ 1kΩ GND 00928-041 VREF VVRREEFFAB VVDODUTA FAIL PASS Figure 41. AD5302/AD5312/AD5322 in an Opto-Isolated Interface AD5302/AD5312/ AD5322 1/2 PASS/FAIL DECODING MULTIPLE AD5302/AD5312/AD5322s SYNC SYNC CMP04 DIN DIN The SYNC pin on the AD5302/AD5312/AD5322 can be used in SCLK SCLK VOUTB 1/6 74HC05 aapll pthliec aDtiAonCss tion dtheec osdyset eam n uremcbeievre otfh De sAaCmse. Isner tihali sc laopcpkl iacnadti osenr,i al GND 00928-043 Figure 43. Window Detector Using AD5302/AD5312/AD5322 data, but only the SYNC to one of the devices is active at any one time, allowing access to two channels in this eight-channel system. Rev. D | Page 19 of 24

AD5302/AD5312/AD5322 COARSE AND FINE ADJUSTMENT USING THE POWER SUPPLY BYPASSING AND GROUNDING AD5302/AD5312/AD5322 In any circuit where accuracy is important, careful considera- tion of the power supply and ground return layout helps to The DACs in the AD5302/AD5312/AD5322 can be paired ensure the rated performance. The printed circuit board on together to form a coarse and fine adjustment function, as which the AD5302/AD5312/AD5322 is mounted should be shown in Figure 44. DAC A is used to provide the coarse designed so that the analog and digital sections are separated adjustment while DAC B provides the fine adjustment. Varying and confined to certain areas of the board. If the AD5302/ the ratio of R1 and R2 changes the relative effect of the coarse AD5312/AD5322 are in a system where multiple devices require and fine adjustments. With the resistor values and external an AGND-to-DGND connection, the connection should be reference shown, the output amplifier has unity gain for the made at one point only. The star ground point should be DAC A output, so the output range is 0 V to 2.5 V − 1 LSB. For established as close as possible to the AD5302/AD5312/ DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B a AD5322. The part should have ample supply bypassing of 10 μF range equal to 19 mV. in parallel with 0.1 μF on the supply located as close as possible The circuit is shown with a 2.5 V reference, but reference to the package, ideally right up against the device. The 10 μF voltages up to VDD can be used. The op amps indicated allow a capacitors are the tantalum bead type. The 0.1 μF capacitor rail-to-rail output swing. should have low effective series resistance (ESR) and effective series inductance (ESI), similar to the common ceramic types VDD = 5V R3 R4 that provide a low impedance path to ground at high frequencies 51.2kΩ 900Ω that handle transient currents due to internal logic switching. 0.1µF 10µF +5V VIN ERXETF VOUT VREFA VDD VOUTA R1 AD820/ VOUT Tshhoeu pldo wuseer asus plaprlgye l ian tersa ocef tahse p AosDsi5b3l0e 2t/oA pDro5v3i1d2e/ AloDw5 i3m2p2e dance GND 1µF 390Ω OP295 paths and reduce the effects of glitches on the power supply line. AD5302/AD5312/ Fast switching signals such as clocks should be shielded with AD5322 digital ground to avoid radiating noise to other parts of the board, RR22 VREFB VOUTB and should never be run near the reference inputs. Avoid crossover 5511..22kkΩΩ GND of digital and analog signals. Traces on opposite sides of the 00928-044 board should run at right angles to each other. This reduces the Figure 44. Coarse/Fine Adjustment effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedi- cated to ground while signal traces are placed on the solder side. Rev. D | Page 20 of 24

AD5302/AD5312/AD5322 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. D | Page 21 of 24

AD5302/AD5312/AD5322 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding AD5302ARM −40°C to +105°C 10-Lead MSOP RM-10 D5A AD5302ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5A AD5302ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D5A# AD5302ARMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5A# AD5302ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5A# AD5302BRM −40°C to +105°C 10-Lead MSOP RM-10 D5B AD5302BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5B AD5302BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5B AD5302BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D5B# AD5302BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D5B# AD5302BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D5B# AD5312ARM −40°C to +105°C 10-Lead MSOP RM-10 D6A AD5312ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D6A# AD5312ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6A# AD5312BRM −40°C to +105°C 10-Lead MSOP RM-10 D6B AD5312BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6B AD5312BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6B AD5312BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D6B# AD5312BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D6B# AD5312BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6B# AD5322ARM −40°C to +105°C 10-Lead MSOP RM-10 D7A AD5322ARM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7A AD5322ARMZ −40°C to +105°C 10-Lead MSOP RM-10 D6T AD5322ARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6T AD5322BRM −40°C to +105°C 10-Lead MSOP RM-10 D7B AD5322BRM-REEL −40°C to +105°C 10-Lead MSOP RM-10 D7B AD5322BRM-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7B AD5322BRMZ −40°C to +105°C 10-Lead MSOP RM-10 D7B# AD5322BRMZ-REEL −40°C to +105°C 10-Lead MSOP RM-10 D7B# AD5322BRMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D7B# AD5312WARMZ-REEL7 −40°C to +105°C 10-Lead MSOP RM-10 D6A# 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5312WARMZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model. Rev. D | Page 22 of 24

AD5302/AD5312/AD5322 NOTES Rev. D | Page 23 of 24

AD5302/AD5312/AD5322 NOTES ©2006-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00928-0-5/11(D) Rev. D | Page 24 of 24