2.7 V to 5.5 V, 140 μA, Rail-to-Rail Output 8-Bit DAC in a SOT-23 AD5300 FEATURES FUNCTIONAL BLOCK DIAGRAM Single 8-Bit DAC VDD GND 6-Lead SOT-23 and 8-Lead MSOP Packages POWER-ON Micropower Operation: 140 μA @ 5 V AD5300 RESET Power-Down to 200 nA @ 5 V, 50 nA @ 3 V REF (+)REF (–) 2G.u7a Vra tnot 5e.e5d V M Poonwoetro Snuicp bpyly D esign REGDIASCTER 8D-ABICT OBUUFTFPEURT VOUT Reference Derived from Power Supply Power-On Reset to 0 V INPUT 3 Power-Down Functions CONTROL CPOONWTREORL-D LOOWGNIC RESISTOR LOGIC NETWORK Low Power Serial Interface with Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier, Rail-to-Rail Operation QSYuNaClif Iinetde frorur patu Ftoamciloittyiv e applications SYNC SCLK DIN 00471-001 APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5300 is a single, 8-bit buffered voltage output DAC that 1. Available in 6-lead SOT-23 and 8-lead MSOP packages. operates from a single 2.7 V to 5.5 V supply, consuming 115 μA 2. Low power, single-supply operation. This part operates from a at 3 V. Its on-chip precision output amplifier allows rail-to-rail single 2.7 V to 5.5 V supply and typically consumes 0.35 mW output swing to be achieved. The AD5300 uses a versatile 3-wire at 3 V and 0.7 mW at 5 V, making it ideal for battery-powered serial interface that operates at clock rates up to 30 MHz and is applications. compatible with standard SPI®, QSPI™, MICROWIRE™, and 3. The on-chip output buffer amplifier allows the output of DSP interface standards. the DAC to swing rail-to-rail with a slew rate of 1 V/μs. 4. Reference derived from the power supply. The reference for the AD53001 is derived from the power supply 5. High speed serial interface with clock speeds up to 30 MHz. inputs and thus gives the widest dynamic output range. The part Designed for very low power consumption. The interface incorporates a power-on reset circuit that ensures that the DAC powers up only during a write cycle. output powers up to 0 V and remains there until a valid write takes 6. Power-down capability. When powered down, the DAC place to the device. The part contains a power-down feature that typically consumes 50 nA at 3 V and 200 nA at 5 V. reduces the current consumption of the device to 200 nA at 5 V and provides software selectable output loads while in power- down mode. The part is put into power-down mode over the serial interface. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 0.7 mW at 5 V, reducing to 1 μW in power-down mode. The AD5300 is one of a family of pin-compatible DACs. The AD5310 is the 10-bit version, and the AD5320 is the 12-bit version. The AD5300/AD5310/AD5320 are available in 6-lead SOT-23 packages and 8-lead MSOP packages. 1 Patent pending; protected by U.S. Patent No. 5684481. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.

AD5300–SPECIFICATIONS (VDD = 2.7 V to 5.5 V; RL = 2 k(cid:2) to GND; CL = 500 pF to GND; all specifications T to T , unless otherwise noted.) MIN MAX B Version1 Parameter Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 Resolution 8 Bits Relative Accuracy ±1 LSB See Figure 2. Differential Nonlinearity ±0.25 LSB Guaranteed Monotonic by Design. See Figure 3. Zero-Code Error +0.5 +3.5 LSB All Zeros Loaded to DAC Register. See Figure 6. Full-Scale Error –0.5 –3.5 LSB All Ones Loaded to DAC Register. See Figure 6. Gain Error ±1.25 % of FSR Zero-Code Error Drift –20 µV/°C Gain Temperature Coefficient –5 ppm of FSR/°C OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V V DD Output Voltage Settling Time 4 6 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex). R = 2 kΩ; 0 pF < C < 500 pF. See Figure 16. L L Slew Rate 1 V/µs ∞ Capacitive Load Stability 470 pF R = . L 1000 pF R = 2 kΩ. L Digital-to-Analog Glitch Impulse 20 nV-s 1 LSB Change Around Major Carry. See Figure 19. Digital Feedthrough 0.5 nV-s DC Output Impedance 1 Ω Short-Circuit Current 50 mA V = 5 V. DD 20 mA V = 3 V. DD Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V = 5V. DD 5 µs Coming Out of Power-Down Mode. V = 3V. DD LOGIC INPUTS3 Input Current ±1 µA V , Input Low Voltage 0.8 V V = 5 V. INL DD V , Input Low Voltage 0.6 V V = 3V. INL DD V , Input High Voltage 2.4 V V = 5 V. INH DD V , Input High Voltage 2.1 V V = 3 V. INH DD Pin Capacitance 3 pF POWER REQUIREMENTS V 2.7 5.5 V DD I (Normal Mode) DAC Active and Excluding Load Current. DD V = 4.5 V to 5.5 V 140 250 µA V = V and V = GND. DD IH DD IL V = 2.7 V to 3.6 V 115 200 µA V = V and V = GND. DD IH DD IL I (All Power-Down Modes) DD V = 4.5 V to 5.5 V 0.2 1 µA V = V and V = GND. DD IH DD IL V = 2.7 V to 3.6 V 0.05 1 µA V = V and V = GND. DD IH DD IL POWER EFFICIENCY I /I 93 % I = 2 mA. V = 5 V. OUT DD LOAD DD NOTES 1Temperature range as follows: B Version: –40°C to +105°C. 2Linearity calculated using a reduced code range of 4 to 251. Output unloaded. 3Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. –2– REV. D

AD5300 TIMING CHARACTERISTICS1, 2 (V = 2.7 V to 5.5 V; all specifications T to T , unless otherwise noted.) DD MIN MAX Limit at T , T MIN MAX Parameter V = 2.7 V to 3.6 V V = 3.6 V to 5.5 V Unit Conditions/Comments DD DD t 3 50 33 ns min SCLK Cycle Time 1 t 13 13 ns min SCLK High Time 2 t 22.5 13 ns min SCLK Low Time 3 t 13 13 ns min SYNC to SCLK Falling Edge Setup Time 4 t 5 5 ns min Data Setup Time 5 t 4.5 4.5 ns min Data Hold Time 6 t 0 0 ns min SCLK Falling Edge to SYNC Rising Edge 7 t 50 33 ns min Minimum SYNC High Time 8 NOTES 1All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2. DD IL IH 2See Figure 1. 3Maximum SCLK frequency is 30 MHz at V = 3.6 V to 5.5 V and 20 MHz at V = 2.7 V to 3.6 V. DD DD Specifications subject to change without notice. t1 SCLK t 8 t t t3 2 t7 4 SYNC t 6 t 5 DIN DB15 DB0 Figure 1.Serial Write Operation ABSOLUTE MAXIMUM RATINGS* *Stresses above those listed under Absolute Maximum Ratings may cause perma- (T = 25°C, unless otherwise noted.) nent damage to the device. This is a stress rating only; functional operation of the A device at these or any other conditions above those listed in the operational sections V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DD of this specification is not implied. Exposure to absolute maximum rating condi- Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V tions for extended periods may affect device reliability. V to GND . . . . . . . . . . . . . . . . . . . –0.3 V to V + 0.3 V OUT DD Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (T max) . . . . . . . . . . . . . . . . . . .150°C J SOT-23 Package Power Dissipation . . . . . . . . . . . . . . . . . . . (T max–T )/θ J A JA θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 240°C/W JA Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .220°C MSOP Package Power Dissipation . . . . . . . . . . . . . . . . . . . (T max–T )/θ J A JA θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W JA θ Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W JC Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . .215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .220°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5300 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. D –3–

AD5300 PIN CONFIGURATIONS SOT-23 MSOP VOUT 1 6 SYNC VDD 1 8 GND GND 2 AD5300 5 SCLK NC 2 AD5300 7 DIN TOP VIEW VDD 3 (Not to Scale) 4 DIN NC 3 TOP VIEW 6 SCLK (Not to Scale) VOUT 4 5 SYNC NC = NO CONNECT PIN FUNCTION DESCRIPTIONS SOT-23 MSOP Pin No. Pin No. Mnemonic Function 1 4 V Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. OUT 2 8 GND Ground Reference Point for All Circuitry on the Part. 3 1 V Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and V should be decoupled DD DD to GND. 4 7 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 5 6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 5 SYNC Level Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC. NC 2, 3 NC No Connect. –4– REV. D

AD5300 TERMINOLOGY Gain Error Relative Accuracy This is a measure of the span error of the DAC. It is the devia- For the DAC, relative accuracy or integral nonlinearity (INL) is tion in slope of the DAC transfer characteristic from ideal a measure of the maximum deviation, in LSBs, from a straight line expressed as a percent of the full-scale range. passing through the endpoints of the DAC transfer function. A Total Unadjusted Error typical INL vs. code plot can be seen in Figure 2. Total unadjusted error (TUE) is a measure of the output error Differential Nonlinearity taking into account all the various errors. A typical TUE vs. Differential nonlinearity (DNL) is the difference between the code plot can be seen in Figure 4. measured change and the ideal 1 LSB change between any two Zero-Code Error Drift adjacent codes. A specified differential nonlinearity of ±1 LSB This is a measure of the change in zero-code error with a maximum ensures monotonicity. This DAC is guaranteed change in temperature. It is expressed in µV/°C. monotonic by design. A typical DNL vs. code plot can be seen in Figure 3. Gain Error Drift This is a measure of the change in gain error with changes in Zero-Code Error temperature. It is expressed in (ppm of full-scale range)/°C. Zero-code error is a measure of the output error when zero code (00 Hex) is loaded to the DAC register. Ideally, the output Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the should be 0 V. The zero-code error is always positive in the analog output when the input code in the DAC register changes AD5300 because the output of the DAC cannot go below 0 V. state. It is normally specified as the area of the glitch in nV-secs This is due to a combination of the offset errors in the DAC and is measured when the digital input code is changed by and output amplifier. Zero-code error is expressed in LSBs. A 1 LSB at the major carry transition (7F Hex to 80 Hex). See plot of zero-code error vs. temperature can be seen in Figure 6. Figure 19. Full-Scale Error Full-scale error is a measure of the output error when full- Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the scale code (FF Hex) is loaded to the DAC register. Ideally, analog output of the DAC from the digital inputs of the DAC the output should be V – 1LSB. Full-scale error is expressed DD but is measured when the DAC output is not updated. It is in LSBs. A plot of full-scale error vs. temperature can be specified in nV-secs and is measured with a full-scale code seen in Figure 6. change on the data bus, i.e., from all 0s to all 1s, and vice versa. REV. D –5–

AD5300–Typical Performance Characteristics 1.0 0.5 1.0 TA = 25(cid:3)C 0.4 TUE @ 3V TA = 25(cid:3)C 0.3 INL ERROR – LSBs 0.50 INLI N@L 3 @V 5V DNL ERROR – LSBs––0000....12120 DDNNLL @ @ 3 5VV TUE – LSBs0.50 TUE @ 5V –0.5 –0.5 –0.3 TA = 25(cid:3)C –0.4 –1.0 –0.5 –1.0 0 50 100 150 200 250 0 50 100 150 200 250 0 50 100 150 200 250 CODE CODE CODE Figure 2.Typical INL Plot Figure 3.Typical DNL Plot Figure 4.Typical Total Unadjusted Error Plot 1.0 3 2500 VDD = 5V 2 VDD = 5V VDD = 5V 2000 ERROR – LSBs0.50 MMMAIANXX D DINNNLLL ERROR – LSBs –011 ZFSS EERRRROORR FREQUENCY 11500000 VDD = 3V MIN INL –0.5 500 –2 –1.0–40 0 40 80 120 –3–40 0 40 80 120 050 60 70 80 90100110120130140150160170180190 TEMPERATURE – (cid:3)C TEMPERATURE – (cid:3)C IDD – (cid:1)A Figure 5.INL Error and DNL Error Figure 6.Zero-Scale Error and Figure 7.IDD Histogram with vs. Temperature Full-Scale Error vs. Temperature VDD = 3V and VDD = 5V 3 5 500 TA = 25(cid:3)C DAC LOADED WITH FF HEX 4 400 DAC LOADED WITH FF HEX 2 – VUT – VOUT3 TA = 25(cid:3)C (cid:1) – AD300 VO V 2 ID200 1 VDD = 5V DAC LOADED WITH 00 HEX 1 100 DAC LOADED WITH 00 HEX VDD = 3V 00 5 10 15 00 5 10 15 00 50 100 150 200 250 ISOURCE/SINK – mA ISOURCE/SINK – mA CODE Figure 8.Source and Sink Current Figure 9.Source and Sink Current Figure 10.Supply Current vs. Code Capability with VDD = 3 V Capability with VDD = 5 V –6– REV. D

AD5300 300 300 1.0 VDD = 5V 0.9 THREE–STATE CONDITION 250 250 0.8 200 200 0.7 (cid:1)I – ADD150 (cid:1)I – ADD150 (cid:1)I – ADD000...465 +105(cid:3)C 100 100 0.3 +25(cid:3)C –40(cid:3)C 50 50 0.2 0.1 0 0 0 –40 0 40 80 120 2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 TEMPERATURE – (cid:3)C VDD – V VDD – V Figure 11.Supply Current vs. Figure 12.Supply Current vs. Figure 13.Power-Down Current vs. Temperature Supply Voltage Supply Voltage 800 TA = 25(cid:3)C 600 CH2 CH2 CLK CLK A (cid:1) – 400 I DD VOUT VOUT 200 VDD = 5V CH1 VF T UAD DL = L0 =20- 5S5 H(cid:3)VCCEAXL E– FCFO HDEEX CHANGE CH1 VH T ADA D L= 4 F=20- 55S H(cid:3)VCCEAXL –E CC0O HDEEX CHANGE OUTPUT LOADED WITH OUTPUT LOADED WITH VDD = 3V 2k(cid:2) AND 200pF TO GND 2k(cid:2) AND 200pF TO GND 0 CH1 1V, CH2 5V, TIME BASE = 1(cid:1)s/DIV CH1 1V, CH2 5V, TIME BASE = 1(cid:1)s/DIV 0 1 2 3 4 5 VLOGIC – V Figure 14.Supply Current vs. Logic Figure 15.Full-Scale Settling Time Figure 16.Half-Scale Settling Time Input Voltage 2.54 LOADED WITH 2k(cid:2) 2k(cid:2) LOAD VDD = 5V AND 200pF TO GND TO VDD CH2 CLK 2.52 CODE CHANGE: 80 HEX TO 7F HEX VDD – V T2.50 CH1 U O V VOUT CH2 VOUT 2.48 CH1 CH1 1V, CH2 1V, TIME BASE = 20(cid:1)s/DIV CH1 1V, CH2 5V, TIME BASE = 5(cid:1)s/DIV 2.46 500ns/DIV Figure 17.Power-On Reset to 0 V Figure 18.Exiting Power-Down Figure 19.Digital-to-Analog Glitch (7F Hex Loaded) Impulse REV. D –7–

AD5300 GENERAL DESCRIPTION D/A Section Output Amplifier The AD5300 DAC is fabricated on a CMOS process. The archi- The output buffer amplifier is capable of generating rail-to-rail tecture consists of a string DAC followed by an output buffer voltages on its output, which gives an output range of 0 V to amplifier. Since there is no reference input pin, the power V . It is capable of driving a load of 2 kΩ in parallel with supply (V ) acts as the reference. Figure 20 shows a block DD DD 1000 pF to GND. The source and sink capabilities of the output diagram of the DAC architecture. amplifier can be seen in Figures 8 and 9. The slew rate is 1V/µs with a half-scale settling time of 4 µs with the output loaded. VDD REF (+) SERIAL INTERFACE The AD5300 has a 3-wire serial interface (SYNC, SCLK, and RESISTOR DAC REGISTER STRING VOUT DIN), which is compatible with SPI, QSPI, and MICROWIRE REF (–) OUTPUT interface standards as well as most DSPs. See Figure 1 for a AMPLIFIER timing diagram of a typical write sequence. GND The write sequence begins by bringing the SYNC line low. Data Figure 20.DAC Architecture from the DIN line is clocked into the 16-bit shift register on the Since the input coding to the DAC is straight binary, the ideal falling edge of SCLK. The serial clock frequency can be as high output voltage is given by as 30 MHz, making the AD5300 compatible with high speed DSPs. On the 16th falling clock edge, the last data bit is clocked  D  V =V ×  in and the programmed function is executed (i.e., a change in OUT DD 256 DAC register contents and/or a change in the mode of operation). At this stage, the SYNC line may be kept low or be brought where D = decimal equivalent of the binary code that is loaded high. In either case, it must be brought high for a minimum of to the DAC register; D can range from 0 to 255. 33 ns (V = 3.6 V to 5.5 V) or 50 ns (V = 2.7 V to 3.6 V) DD DD Resistor String before the next write sequence so that a falling edge of SYNC The resistor string section is shown in Figure 21. It is simply a can initiate the next write sequence. Since the SYNC buffer string of resistors, each of value R. The code loaded to the draws more current when V = 2.4 V than it does when V = IN IN DAC register determines at which node on the string the voltage 0.8 V, SYNC should be idled low between write sequences for is tapped off to be fed into the output amplifier. The voltage is even lower power operation of the part. As previously men- tapped off by closing one of the switches connecting the string tioned, however, it must be brought high again just before the to the amplifier. Because it is a string of resistors, it is guaran- next write sequence. teed monotonic. Input Shift Register The input shift register is 16 bits wide (see Figure 22). The first R two bits are Don’t Cares. The next two are control bits that control which mode of operation the part is in (normal mode or R any one of three power-down modes). There is a more complete description of the various modes in the Power-Down Modes TO OUTPUT R AMPLIFIER section. The next eight bits are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK. Finally, the last four bits are Don’t Cares. R R Figure 21.Resistor String DB15 (MSB) DB0 (LSB) X X PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS 0 0 NORMAL OPERATION 0 1 1k(cid:2) TO GND 1 0 100k(cid:2) TO GND POWER-DOWN MODES 1 1 THREE-STATE Figure 22.Input Register Contents –8– REV. D

AD5300 SCLK SYNC DIN DB15 DB0 DB15 DB0 INVALID WRITE SEQUENCE: VALID WRITE SEQUENCE, OUTPUT UPDATES SYNC HIGH BEFORE 16TH FALLING EDGE ON THE 16TH FALLING EDGE Figure 23.SYNC Interrupt Facility SYNC Interrupt In a normal write sequence, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the SRTERSINISGT DOARC AMPLIFIER VOUT 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence. The shift register is reset and the write sequence is seen as invalid; neither an update of the DAC register contents or a POWER-DOWN CIRCUITRY RESISTOR change in the operating mode occurs—see Figure 23. NETWORK Power-On Reset The AD5300 contains a power-on reset circuit that controls the Figure 24.Output Stage During Power-Down output voltage during power-up. The DAC register is filled with The bias generator, the output amplifier, the resistor string, and zeros and the output voltage is 0 V. It remains there until other associated linear circuitry are all shut down when the a valid write sequence is made to the DAC. This is useful in power-down mode is activated. However, the contents of the applications where it is important to know the state of the out- DAC register are unaffected when in power-down. The time to put of the DAC while it is in the process of powering up. exit power-down is typically 2.5 µs for V = 5 V and 5 µs for DD Power-Down Modes V = 3V (see Figure 18). DD The AD5300 contains four separate modes of operation. These modes are software programmable by setting two bits (DB13 MICROPROCESSOR INTERFACING and DB12) in the control register. Table I shows how the state AD5300 to ADSP-2101/ADSP-2103 Interface of the bits corresponds to the mode of operation of the device. Figure 25 shows a serial interface between the AD5300 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should Table I. Modes of Operation for the AD5300 be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed DB13 DB12 Operating Mode through the SPORT control register and should be configured 0 0 Normal Operation as follows: internal clock operation, active low framing, 16-bit Power-Down Modes word length. Transmission is initiated by writing a word to the 0 1 1 kΩ to GND Tx register after the SPORT has been enabled. 1 0 100 kΩ to GND 1 1 Three-State ADSP-2101/ AD5300* ADSP-2103* When both bits are set to 0, the part works normally with its normal power consumption of 140 µA at 5 V. However, for the TFS SYNC three power-down modes, the supply current falls to 200 nA at DT DIN 5 V (50 nA at 3 V). Not only does the supply current fall but SCLK SCLK the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has an *ADDITIONAL PINS OMITTED FOR CLARITY advantage: the output impedance of the part is known while the Figure 25.AD5300 to ADSP-2101/ADSP-2103 Interface part is in power-down mode. There are three different options. The output is connected internally to GND through a 1 kΩ resis- tor or a 100 kΩ resistor, or it is left open-circuited (three-stated). The output stage is illustrated in Figure 24. REV. D –9–

AD5300 AD5300 to 68HC11/68L11 Interface Figure 26 shows a serial interface between the AD5300 and the MICROWIRE* AD5300* 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5300, while the MOSI output drives CS SYNC the serial data line of the DAC. The SYNC signal is derived SK SCLK from a port line (PC7). The setup conditions for correct opera- tion of this interface are as follows: the 68HC11/68L11 should SO DIN be configured so that its CPOL bit is a 0 and its CPHA bit is a *ADDITIONAL PINS OMITTED FOR CLARITY 1. When data is being transmitted to the DAC, the SYNC line is Figure 28.AD5300 to MICROWIRE Interface taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling APPLICATIONS edge of SCK. Serial data from the 68HC11/68L11 is transmit- Using REF19x as a Power Supply for AD5300 ted in 8-bit bytes with only eight falling clock edges occurring in Because the supply current required by the AD5300 is extremely the transmit cycle. Data is transmitted MSB first. In order to low, an alternative option is to use a REF19x voltage reference load data to the AD5300, PC7 is left low after the first eight bits (REF195 for 5 V or REF193 for 3 V) to supply the required are transferred, and a second serial write operation is performed voltage to the part—see Figure 29. This is especially useful if to the DAC and PC7 is taken high at the end of this procedure. your power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V (e.g., 15 V). The REF19x will output a steady supply voltage for the AD5300. If the low 68HC11/68L11* AD5300* dropout REF195 is used, the current it needs to supply to the PC7 SYNC AD5300 is 140 µA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs to SCK SCLK supply the current to the load. The total current required (with MOSI DIN a 5 kΩ load on the DAC output) is 140 µA + (5 V/5 kΩ) = 1.14 mA *ADDITIONAL PINS OMITTED FOR CLARITY Figure 26.AD5300 to 68HC11/68L11 Interface The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 2.3 ppm (11.5 µV) for the 1.14 mA AD5300 to 80C51/80L51 Interface current drawn from it. This corresponds to a 0.0006 LSB error. Figure 27 shows a serial interface between the AD5300 and the 80C51/80L51 microcontroller. The setup for the interface is as 15V follows: TXD of the 80C51/80L51 drives SCLK of the AD5300, 5V while RXD drives the serial data line of the part. The SYNC REF195 signal is again derived from a bit programmable pin on the port. 140(cid:1)A In this case, port line P3.3 is used. When data is to be transmitted to the AD5300, P3.3 is taken low. The 80C51/80L51 transmits 3-WIRE SYNC VOUT = 0V TO 5V data only in 8-bit bytes; thus, only eight falling clock edges SERIAL SCLK AD5300 INTERFACE DIN occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken Figure 29.REF195 as Power Supply to AD5300 high following the completion of this cycle. The 80C51/80L51 Bipolar Operation Using the AD5300 outputs the serial data in a format that has the LSB first. The The AD5300 has been designed for single-supply operation, AD5300 requires its data with the MSB as the first bit received. but a bipolar output range is also possible using the circuit in The 80C51/80L51 transmit routine takes this into account. Figure 30. The circuit in Figure 30 will give an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. 80C51/80L51* AD5300* The output voltage for any input code can be calculated as P3.3 SYNC   D  R1+R2 R2 TXD SCLK V =V × × –V ×  O  DD 256  R1  DD R1 RXD DIN where D represents the input code in decimal (0 to 255). *ADDITIONAL PINS OMITTED FOR CLARITY With V = 5 V, R1 = R2 = 10 kΩ, DD Figure 27.AD5300 to 80C51/80L51 Interface AD5300 to MICROWIRE Interface 10×D V = –5V Figure 28 shows an interface between the AD5300 and any O  256  MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5300 on This is an output voltage range of ±5 V with 00 Hex corresponding the rising edge of the SK. to a –5 V output and FF Hex corresponding to a 5 V output. –10– REV. D

AD5300 R2 = 10k(cid:2) 5V +5V POWER REGULATOR 10(cid:1)F 0.1(cid:1)F +5V R1 = 10k(cid:2) AD820/ (cid:4)5V VDD VDD VOUT OP295 SCLK 10k(cid:2) SCLK VDD 10(cid:1)F 0.1(cid:1)F AD5300 –5V VDD AD5300 10k(cid:2) 3-WIRE SYNC SYNC VOUT SERIAL INTERFACE VDD Figure 30.Bipolar Operation with the AD5300 10k(cid:2) Two 8-Bit AD5300s Together Make One 15-Bit DAC DATA DIN GND By using the configuration in Figure 31, it can be seen that one 15-bit DAC can be made with two 8-bit AD5300s. Because of the low supply current the AD5300 requires, the output of one DAC may be directed into the supply pin of the second DAC. Figure 32.AD5300 with an Opto-Isolated Interface The first DAC has no problem sourcing the required 140 µA Power Supply Bypassing and Grounding of current for the second DAC. When accuracy is important in a circuit, it is helpful to carefully Since the AD5300 works on any supply voltage between 2.5 V consider the power supply and ground return layout on the and 5.5 V, the output of the first DAC can be anywhere above board. The printed circuit board containing the AD5300 should 2.5 V. For a V of 5 V, this allows the first DAC to use half of have separate analog and digital sections, each having its own DD its output range (2.5 V to 5 V), which gives 7-bit resolution on area of the board. If the AD5300 is in a system where other the output voltage. This output then becomes the supply and devices require an AGND to DGND connection, the connec- reference for the second DAC. The second DAC has 8-bit reso- tion should be made at one point only. This ground point should lution on the output range, which gives an overall resolution for be as close as possible to the AD5300. the system of 15 bits. The power supply to the AD5300 should be bypassed with A level-shifter is required to ensure that the logic input voltages 10 µF and 0.1 µF capacitors. The capacitors should be physi- do not exceed the supply voltage of the part. The microcontroller cally as close as possible to the device with the 0.1 µF capacitor outputs 5 V signals, which need to be level shifted down to 2.5 V ideally right up against the device. The 10 µF capacitors are the in the case of the second DAC having a supply of only 2.5 V. tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and effective series 5V inductance (ESI), e.g., common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for SYNC VDD VOUT = 2.5V TO 5V high frequencies caused by transient currents due to internal SCLK AD5300 logic switching. DIN The power supply line itself should have as large a trace as pos- MICRO- CONTROLLER sible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other fast switching digital signals SYNC VDD should be shielded from other parts of the board by digital LEVEL SHIFTER SCLK AD5300 VOUT = 0V TO 5V ground. Avoid crossover of digital and analog signals if possible. DIN 15-BIT RESOLUTION When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is Figure 31. 15-Bit DAC Using Two AD5300s the microstrip technique where the component side of the board Using AD5300 with an Opto-Isolated Interface is dedicated to the ground plane only and the signal traces are In process-control applications in industrial environments, it is placed on the solder side. However, this is not always possible often necessary to use an opto-isolated interface to protect and with a 2-layer board. isolate the controlling circuitry from any hazardous common- mode voltages that may occur in the area where the DAC is functioning. Opto-isolators provide isolation in excess of 3 kV. Because the AD5300 uses a 3-wire serial logic interface, it requires only three opto-isolators to provide the required isola- tion (see Figure 32). The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5300. REV. D –11–

AD5300 OUTLINE DIMENSIONS 3.00 2.90 2.80 1.70 6 5 4 3.00 1.60 2.80 1.50 2.60 1 2 3 PIN1 INDICATOR 0.95BSC 1.90 BSC 1.30 1.15 0.90 1.45MAX 0.20MAX 0.95MIN 0.08MIN 0.55 0.15MAX 10° 0.45 0.05MIN 0.50MAX SPLEAATNIENG 4° B0S.6C0 0.35 0.30MIN 0° COMPLIANTTOJEDECSTANDARDSMO-178-AB 12-16-2008-A Figure 33. 6-Lead Small Outline Transistor Package (SOT-23) (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 8 5 5.15 3.20 4.90 3.00 4.65 2.80 1 4 PIN1 IDENTIFIER 0.65BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.80 0.15 0.40 6° 0.23 0.55 CO0P.0L50A.1N0ARICTOYMPLIANT0.T25OJEDECSTA0°NDARDS0M.0O9-187-AA 0.40 10-07-2009-B Figure 34. 8-Lead Mini Small Outline Package (MSOP) (RM-8) Dimensions shown in millimeters Rev. D | Page 12 of 13

AD5300 ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option Branding AD5300BRM −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRMZ −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRMZ-REEL −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRMZ-REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2B AD5300BRT-500RL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRT-REEL −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRT-REEL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRTZ-500RL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRTZ-REEL −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300BRTZ-REEL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 D2B AD5300WBRTZ-RL7 −40°C to +105°C 6-Lead SOT-23 RJ-6 DG5 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5300WBRTZ-RL7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for this model. REVISION HISTORY 12/10—Rev. C to Rev. D Change to Features Section .............................................................. 1 Updated Outline Dimensions ........................................................ 12 Moved Ordering Guide; Changes to Ordering Guide ................ 13 Added Automotive Products Section ........................................... 13 11/03—Rev. B to Rev. C Changes to Ordering Guide ............................................................. 3 Changes to Pin Function Descriptions Section ............................ 4 Updated Outline Dimensions ........................................................ 12 ©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00471-0-12/10(D) Rev. D | Page 13 of 13