256-/1024-Position, Digital Potentiometers with Maximum ±1% R-Tolerance Error and 20-TP Memory Data Sheet AD5291/AD5292 FEATURES FUNCTIONAL BLOCK DIAGRAM Single-channel, 256-/1024-position resolution VDD RESET 20 kΩ, 50 kΩ, and 100 kΩ nominal resistance POWER-ON Maximum ±1% nominal resistor tolerance error (resistor RESET AD5291/ AD5292 performance mode) 20-times programmable wiper memory VLOGIC Rheostat mode temperature coefficient: 35 ppm/°C RDAC Voltage divider temperature coefficient: 5 ppm/°C SCLK REGISTER A SERIAL DATA +9 V to +33 V single-supply operation SYNC INTERFACE W ±9 V to ±16.5 V dual-supply operation OTP SPI-compatible serial interface DIN MEMORY BLOCK B Wiper setting readback SDO Power-on refreshed from 20-TP memory RDY AMPecPhLaInCicAaTl pIOotNenSt iometer replacement VSS EXT_CAP GND 07674-001 Figure 1. Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The AD5291 and AD5292 are single-channel, 256-/1024- The AD5291 and AD5292 device wiper settings are controllable position digital potentiometers1 that combine industry leading through the SPI digital interface. Unlimited adjustments are variable resistor performance with nonvolatile memory (NVM) allowed before programming the resistance value into the in a compact package. These devices are capable of operating 20-TP memory. The AD5291 and AD5292 do not require any across a wide voltage range, supporting both dual supply operation external voltage supply to facilitate fuse blow, and there are 20 at ±10.5 V to ±16.5 V and single supply operation at +21 V to opportunities for permanent programming. During 20-TP +33 V, while ensuring less than 1% end-to-end resistor tolerance activation, a permanent blow fuse command freezes the wiper error and offering 20-time programmable (20-TP) memory. position (analogous to placing epoxy on a mechanical trimmer). The guaranteed industry leading low resistor tolerance error The AD5291 and AD5292 are available in a compact 14-lead feature simplifies open-loop applications as well as precision TSSOP package. The part is guaranteed to operate over the calibration and tolerance matching applications. extended industrial temperature range of −40°C to +105°C. 1 The terms digital potentiometer and RDAC are used interchangeably. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5291/AD5292 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 20-TP Memory ........................................................................... 23 Applications ....................................................................................... 1 Write Protection ......................................................................... 23 Functional Block Diagram .............................................................. 1 Basic Operation .......................................................................... 24 General Description ......................................................................... 1 20-TP Readback and Spare Memory Status ........................... 24 Revision History ............................................................................... 2 Shutdown Mode ......................................................................... 24 Specifications ..................................................................................... 3 Resistor Performance Mode ...................................................... 25 Electrical Characteristics—AD5291 .......................................... 3 Reset ............................................................................................. 25 Resistor Performance Mode Code Range ................................. 4 SDO Pin and Daisy-Chain Operation ..................................... 25 Electrical Characteristics—AD5292 .......................................... 6 RDAC Architecture .................................................................... 25 Resistor Performance Mode Code Range ................................. 7 Programming the Variable Resistor ......................................... 26 Interface Timing Specifications .................................................. 8 Programming the Potentiometer Divider ............................... 26 Absolute Maximum Ratings .......................................................... 10 EXT_CAP Capacitor .................................................................. 27 Thermal Resistance .................................................................... 10 Terminal Voltage Operating Range ......................................... 27 ESD Caution ................................................................................ 10 Applications Information .............................................................. 28 Pin Configuration and Function Descriptions ........................... 11 High Voltage DAC ...................................................................... 28 Typical Performance Characteristics ........................................... 12 Programmable Voltage Source with Boosted Output ........... 28 Test Circuits ..................................................................................... 21 High Accuracy DAC .................................................................. 28 Theory of Operation ...................................................................... 22 Variable Gain Instrumentation Amplifier .............................. 28 Serial Data Interface ................................................................... 22 Audio Volume Control .............................................................. 29 Shift Register ............................................................................... 22 Outline Dimensions ....................................................................... 30 RDAC Register ............................................................................ 22 Ordering Guide .......................................................................... 30 REVISION HISTORY 11/2019—Rev. E to Rev. F 12/2009—Rev. 0 to Rev. A Change to Ordering Guide ............................................................ 30 Added 50 kΩ and 100 kΩ specifications ......................... Universal Changes to Features Section ............................................................ 1 12/2014—Rev. D to Rev. E Changes to Table 1 ............................................................................. 3 Changes to Shift Register Section and Table 11 ......................... 22 Changes to Table 2 ............................................................................. 4 Added Table 3 .................................................................................... 5 9/2010—Rev. C to Rev. D Changes to Table 4 ............................................................................. 6 Changes to SDO Pin and Daisy-Chain Operation Section ....... 25 Changes to Table 5 ............................................................................. 7 Added Table 6 .................................................................................... 8 3/2010—Rev. B to Rev. C Change to Table 7 .............................................................................. 8 Changes to Revision History ........................................................... 2 Changes to Absolute Maximum Rating Section ........................ 10 Changes to Figure 3 and Figure 4 Captions .................................. 9 Changes Table 9 .............................................................................. 11 Changes to Typical Performance Characteristics Section ........ 12 3/2010—Rev. A to Rev. B Changes to Ordering Guide .......................................................... 30 Changes to Data Sheet Title ............................................................ 1 Changes to General Description Section ...................................... 1 4/2009—Revision 0: Initial Version Changes to Theory of Operation Section .................................... 22 Rev. F | Page 2 of 30

Data Sheet AD5291/AD5292 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5291 V = 21 V to 33 V, V = 0 V; V = 10.5 V to 16.5 V, V = −10.5 V to −16.5 V; V = 2.7 V to 5.5 V, V = V , V = V , DD SS DD SS LOGIC A DD B SS −40°C < T < +105°C, unless otherwise noted. A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 8 Bits Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 +1 LSB Resistor Integral Nonlinearity2 R-INL −1 +1 LSB Nominal Resistor Tolerance (R-Perf Mode)3 ∆RAB/RAB See Table 2, Table 3 −1 ±0.5 +1 % Nominal Resistor Tolerance (Normal Mode) ∆RAB/RAB ±7 % Resistance Temperature Coefficient4 (∆RAB/RAB)/∆T × 106 Code = full-scale; See Figure 38 35 ppm/°C Wiper Resistance RW Code= zero scale 60 100 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity5 DNL −0.5 +0.5 LSB Integral Nonlinearity5 INL −0.5 +0.5 LSB Voltage Divider Temperature Coefficient4 (∆VW/VW)/∆T × 106 Code = half-scale; See Figure 41 1.5 ppm/°C Full-Scale Error VWFSE Code = full scale −2 +0.25 LSB Zero-Scale Error VWZSE Code = zero scale 0 2 LSB RESISTOR TERMINALS Terminal Voltage Range6 VA, VB, VW VSS VDD V Capacitance A, Capacitance B4 CA, CB f = 1 MHz, measured to GND, 85 pF code = half-scale Capacitance W4 CW f = 1 MHz, measured to GND, 65 pF code = half-scale Common-Mode Leakage Current4 ICM VA = VB = VW ±1 nA DIGITAL INPUTS JEDEC compliant Input Logic High4 VIH VLOGIC = 2.7 V to 5.5 V 2.0 V Input Logic Low4 VIL VLOGIC = 2.7 V to 5.5 V 0.8 V Input Current IIL VIN = 0 V or VLOGIC ±1 μA Input Capacitance4 CIL 5 pF DIGITAL OUTPUTS (SDO and RDY) Output High Voltage4 VOH RPULL_UP = 2.2 kΩ to VLOGIC VLOGIC − 0.4 V Output Low Voltage4 VOL RPULL_UP = 2.2 kΩ to VLOGIC GND + 0.4 V V Three-State Leakage Current −1 +1 μA Output Capacitance4 COL 5 pF POWER SUPPLIES Single-Supply Power Range VDD VSS = 0 V 9 33 V Dual-Supply Power Range VDD/VSS ±9 ±16.5 V Positive Supply Current IDD VDD/VSS = ±16.5 V 0.1 2 μA Negative Supply Current ISS VDD/VSS = ±16.5 V −2 −0.1 μA Logic Supply Range VLOGIC 2.7 5.5 V Logic Supply Current ILOGIC VLOGIC = 5 V; VIH = 5 V or VIL = GND 1 10 μA OTP Store Current4, 7 ILOGIC_PROG VIH = 5 V or VIL = GND 25 mA OTP Read Current4, 8 ILOGIC_FUSE_READ VIH = 5 V or VIL = GND 25 mA Power Dissipation9 PDISS VIH = 5 V or VIL = GND 8 110 μW Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = ±15 V ± 10% %/% RAB = 20 kΩ 0.103 RAB = 50 kΩ 0.039 RAB = 100 kΩ 0.021 Rev. F | Page 3 of 30

AD5291/AD5292 Data Sheet Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS5, 10 Bandwidth BW −3 dB, code = half-scale kHz RAB = 20 kΩ 520 RAB = 50 kΩ 210 RAB = 100 kΩ 105 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz dB RAB = 20 kΩ −93 RAB = 50 kΩ −101 RAB = 100 kΩ −106 VW Settling Time tS VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale, board capacitance = 170 pF Code = full-scale, normal mode 750 ns Code = full-scale, R-Perf mode 2.5 μs Code = half-scale, normal mode μs RAB = 20 kΩ 2.5 RAB = 50 kΩ 7 RAB = 100 kΩ 14 Code = half-scale, R-Perf mode μs RAB = 20 kΩ 5 RAB = 50 kΩ 9 RAB = 100 kΩ 16 Resistor Noise Density eN_WB Code = half-scale, TA = 25°C, 0 kHz nV/√Hz to 200 kHz RAB = 20 kΩ 10 RAB = 50 kΩ 18 RAB = 100 kΩ 27 1 Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x02 to code 0xFF or between RWA at code 0xFD to code 0x00. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. 3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design and characterization, not subject to production test. 5 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground- referenced bipolar signal adjustment. 7 Different from operating current; supply current for fuse program lasts approximately 550 μs. 8 Different from operating current; supply current for fuse read lasts approximately 550 μs. 9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC). 10 All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. RESISTOR PERFORMANCE MODE CODE RANGE Table 2. R = 20 kΩ Resistor AB Tolerance per |VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V Code R R R R R R R R WB WA WB WA WB WA WB WA 1% R-Tolerance From 0x5A From 0x00 From 0x7D From 0x00 From 0x7D From 0x00 N/A N/A to 0xFF to 0xA5 to 0xFF to 0x82 to 0xFF to 0x82 2% R-Tolerance From 0x23 From 0x00 From 0x2D From 0x00 From 0x23 From 0x00 From 0x23 From 0x00 to 0xFF to 0xDC to 0xFF to 0xD2 to 0xFF to 0xDC to 0xFF to 0xDC 3% R-Tolerance From 0x1E From 0x00 From 0x19 From 0x00 From 0x17 From 0x00 From 0x17 From 0x00 to 0xFF to 0xE1 to 0xFF to 0xE6 to 0xFF to 0xE8 to 0xFF to 0xE8 Rev. F | Page 4 of 30

Data Sheet AD5291/AD5292 Table 3. R = 50 kΩ R = 100 kΩ AB AB Resistor Tolerance |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V per Code R R R R R R R R WB WA WB WA WB WA WB WA 1% R-Tolerance From 0x2A From 0x00 From 0x37 From 0x00 From 0x1E From 0x00 From 0x14 From 0x00 to 0xFF to 0xD5 to 0xFF to 0xC8 to 0xFF to 0xE1 to 0xFF to 0xEB 2% R-Tolerance From 0x11 From 0x00 From 0x16 From 0x00 From 0x0A From 0x00 From 0x0A From 0x00 to 0xFF to 0xEE to 0xFF to 0xE9 to 0xFF to 0xF5 to 0xFF to 0xF5 3% R-Tolerance From 0x0A From 0x00 From 0x0D From 0x00 From 0x07 From 0x00 From 0x07 From 0x00 to 0xFF to 0xF5 to 0xFF to 0xF2 to 0xFF to 0xF8 to 0xFF to 0xF8 Rev. F | Page 5 of 30

AD5291/AD5292 Data Sheet ELECTRICAL CHARACTERISTICS—AD5291 V = 21 V to 33 V, V = 0 V; V = 10.5 V to 16.5 V, V = −10.5 V to −16.5 V; V = 2.7 V to 5.5 V, V = V , V = V , DD SS DD SS LOGIC A DD B SS −40°C < T < +105°C, unless otherwise noted. A Table 4. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution N 10 Bits Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC −1 +1 LSB Resistor Integral Nonlinearity2 R-INL RAB =50 kΩ, 100 kΩ −2 +2 LSB R-INL RAB =20 kΩ , |VDD − VSS| = 26 V to 33 V −2 +2 LSB R-INL RAB =20 kΩ , |VDD − VSS| = 21 V to 26 V −3 +3 LSB Nominal Resistor Tolerance (R-Perf Mode)3 ∆RAB/RAB See Table 5 and Table 6 −1 ±0.5 +1 % Nominal Resistor Tolerance (Normal ∆RAB/RAB ±7 % Mode)4 Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 Code = full scale; See Figure 38 35 ppm/°C Wiper Resistance RW Code= zero scale 60 100 Ω DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N 10 Bits Differential Nonlinearity5 DNL −1 +1 LSB Integral Nonlinearity5 INL −1.5 +1.5 LSB Voltage Divider Temperature Coefficient4 (∆VW/VW)/∆T × 106 Code = half scale; See Figure 41 5 ppm/°C Full-Scale Error VWFSE Code = full scale −8 +1 LSB Zero-Scale Error VWZSE Code = zero scale 0 8 LSB RESISTOR TERMINALS Terminal Voltage Range4 VA, VB, VW VSS VDD V Capacitance A, Capacitance B6 CA, CB f = 1 MHz, measured to GND, 85 pF code = half scale Capacitance W5 CW f = 1 MHz, measured to GND, 65 pF code = half scale Common-Mode Leakage Current4 ICM VA = VB = VW ±1 nA DIGITAL INPUTS JEDEC compliant Input Logic High4 VIH VLOGIC = 2.7 V to 5.5 V 2.0 V Input Logic Low4 VIL VLOGIC = 2.7 V to 5.5 V 0.8 V Input Current IIL VIN = 0 V or VLOGIC ±1 μA Input Capacitance4 CIL 5 pF DIGITAL OUTPUTS (SDO and RDY) Output High Voltage4 VOH RPULL_UP = 2.2 kΩ to VLOGIC VLOGIC − 0.4 V Output Low Voltage4 VOL RPULL_UP = 2.2 kΩ to VLOGIC GND + 0.4 V Three-State Leakage Current −1 +1 μA Output Capacitance4 COL 5 pF POWER SUPPLIES Single-Supply Power Range VDD VSS = 0 V 9 33 V Dual-Supply Power Range VDD/VSS ±9 ±16.5 V Positive Supply Current IDD VDD/VSS = ±16.5 V 0.1 2 μA Negative Supply Current ISS VDD/VSS = ±16.5 V −2 −0.1 μA Logic Supply Range VLOGIC 2.7 5.5 V Logic Supply Current ILOGIC VLOGIC = 5 V; VIH = 5 V or VIL = GND 1 10 μA OTP Store Current6, 7 ILOGIC_PROG VIH = 5 V or VIL = GND 25 mA OTP Read Current6, 8 ILOGIC_FUSE_READ VIH = 5 V or VIL = GND 25 mA Power Dissipation9 PDISS VIH = 5 V or VIL = GND 8 110 μW Power Supply Rejection Ratio6 PSSR ∆VDD/∆VSS = ±15 V ± 10% %/% RAB = 20 kΩ 0.103 RAB = 50 kΩ 0.039 RAB = 100 kΩ 0.021 Rev. F | Page 6 of 30

Data Sheet AD5291/AD5292 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS5, 10 Bandwidth BW −3dB kHz RAB = 20 kΩ 520 RAB = 50 kΩ 210 RAB = 100 kΩ 105 Total Harmonic Distortion THDW VA = 1 V rms, VB = 0 V, f = 1 kHz dB RAB = 20 kΩ −93 RAB = 50 kΩ −101 RAB = 100 kΩ −106 VW Settling Time tS VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale, board capacitance = 170 pF Code = full-scale, normal mode 750 ns Code = full-scale, R-Perf mode 2.5 μs Code = half-scale, normal mode μs RAB = 20 kΩ 2.5 RAB = 50 kΩ 7 RAB = 100 kΩ 14 Code = half-scale, R-Perf mode μs RAB = 20 kΩ 5 RAB = 50 kΩ 9 RAB = 100 kΩ 16 Resistor Noise Density eN_WB Code = half-scale, TA = 25°C, 0 kHz to nV/√Hz 200 kHz RAB = 20 kΩ 10 RAB = 50 kΩ 18 RAB = 100 kΩ 27 1 Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between the RWB at code 0x00B to code 0x3FF or between RWA at code 0x3F3 to code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. 3 Resistor performance mode (see the Resistor Performance Mode section). The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design and characterization, not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground- referenced bipolar signal adjustment. 7 Different from operating current; supply current for fuse program lasts approximately 550 μs. 8 Different from operating current; supply current for fuse read lasts approximately 550 μs. 9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC). 10 All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. RESISTOR PERFORMANCE MODE CODE RANGE Table 5. R = 20 kΩ Resistor AB Tolerance per |VDD − VSS| = 30 V to 33 V |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V |VDD − VSS| = 21 V to 22 V Code R R R R R R R R WB WA WB WA WB WA WB WA 1% R-Tolerance From 0x15E From 0x000 From 0x1F4 From 0x000 From 0x1F4 From 0x000 N/A N/A to 0x3FF to 0x2A1 to 0x3FF to 0x20B to 0x3FF to 0x20B 2% R-Tolerance From 0x8C From 0x000 From 0xB4 From 0x000 From 0xFA From 0x000 From 0xFA From 0x000 to 0x3FF to 0x373 to 0x3FF to 0x34B to 0x3FF to 0x305 to 0x3FF to 0x305 3% R-Tolerance From 0x5A From 0x000 From 0x64 From 0x000 From 0x78 From 0x000 From 0x78 From 0x000 to 0x3FF to 0x3A5 to 0x3FF to 0x39B to 0x3FF to 0x387 to 0x3FF to 0x387 Rev. F | Page 7 of 30

AD5291/AD5292 Data Sheet Table 6. R = 50 kΩ R = 100 kΩ Resistor AB AB Tolerance per |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V |VDD − VSS| = 26 V to 33 V |VDD − VSS| = 21 V to 26 V Code R R R R R R R R WB WA WB WA WB WA WB WA 1% R-Tolerance From 0x08C From 0x000 From 0x0B4 From 0x000 From 0x04B From 0x000 From 0x064 From 0x000 to 0x3FF to 0x35F to 0x3FF to 0x31E to 0x3FF to 0x3B4 to 0x3FF to 0x39B 2% R-Tolerance From 0X03C From 0x000 From 0x050 From 0x000 From 0x028 From 0x000 From 0x028 From 0x000 to 0x3FF to 0x3C3 to 0x3FF to 0x3AF to 0x3FF to 0x3D7 to 0x3FF to 0x3D7 3% R-Tolerance From 0X028 From 0x000 From 0x032 From 0x000 From 0x019 From 0x000 From 0x019 From 0x000 to 0x3FF to 0x3D7 to 0x3FF to 0x3CD to 0x3FF to 0x3E6 to 0x3FF to 0x3E6 INTERFACE TIMING SPECIFICATIONS V /V = ±15 V, V = 2.7 V to 5.5 V, −40°C < T < +105°C. All specifications T to T , unless otherwise noted. DD SS LOGIC A MIN MAX Table 7. Parameter Limit1 Unit Description t2 20 ns min SCLK cycle time 1 t 10 ns min SCLK high time 2 t 10 ns min SCLK low time 3 t 10 ns min SYNC to SCLK falling edge setup time 4 t 5 ns min Data setup time 5 t 5 ns min Data hold time 6 t 1 ns min SCLK falling edge to SYNC rising edge 7 t 4003 ns min Minimum SYNC high time 8 t 14 ns min SYNC rising edge to next SCLK fall ignore 9 t 4 1 ns min RDY rising edge to SYNC falling edge 10 t114 40 ns max SYNC rising edge to RDY fall time t124 2.4 μs max RDY low time, RDAC register write command execute time (R-Perf mode) t124 410 ns max RDY low time, RDAC register write command execute time (normal mode) t124 8 ms max RDY low time, memory program execute time t124 1.5 ms min Software/hardware reset t134 450 ns max RDY low time, RDAC register readback execute time t134 1.3 ms max RDY low time, memory readback execute time t144 450 ns max SCLK rising edge to SDO valid t 20 ns min Minimum RESET pulse width (asynchronous) RESET t 5 2 ms max Power-on OTP restore time POWER-UP 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Maximum SCLK frequency is 50 MHz. 3 Refer to t12 and t13 for RDAC register and memory commands operations. 4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF. 5 Maximum time after VLOGIC is equal to 2.5 V. DB9 (MSB) DB0 (LSB) 0 0 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS DATA BITS 07674-003 Figure 2. Shift Register Content Rev. F | Page 8 of 30

Data Sheet AD5291/AD5292 Timing Diagrams t4 t2 t1 t7 SCLK t8 t3 t9 SYNC t5 t6 DIN X X C3 C2 D7 D6 D2 D1 D0 SDO t10 t11 t12 RDY RESET tRESET 07674-004 Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1 SCLK t 9 SYNC DIN X X C3 D0 D0 X X C3 D1 D0 t 14 SDO X X C3 D1 D0 t 11 RDY t13 07674-005 Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1 Rev. F | Page 9 of 30

AD5291/AD5292 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 8. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a V to GND −0.3 V to +35 V stress rating only; functional operation of the product at these DD V to GND +0.3 V to − 25 V or any other conditions above those indicated in the operational SS V to GND −0.3 V to + 7 V section of this specification is not implied. Operation beyond LOGIC V to V 35V the maximum operating conditions for extended periods may DD SS V , V , V to GND V − 0.3 V, V + 0.3 V affect product reliability. A B W SS DD Digital Input and Output Voltage to GND −0.3 V to VLOGIC + 0.3 V THERMAL RESISTANCE EXT_CAP Voltage to GND −0.3 V to +7 V θ is defined by JEDEC specification JESD-51 and the value is I , I , I JA A B W dependent on the test board and test environment. Continuous RAB = 20 kΩ ±3 mA Table 9. Thermal Resistance R = 50 kΩ, 100 kΩ ±2mA AB Package Type θ θ Unit JA JC Pulsed1 14-Lead TSSOP 931 20 °C/W Frequency > 10 kHz MCC2/d3 Frequency ≤ 10 kHz MCC2/√d3 1 JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec airflow). Operating Temperature Range4 −40°C to +105°C Maximum Junction Temperature (T max) 150°C J ESD CAUTION Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (T max − T )/θ J A JA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Maximum continuous current. 3 Pulse duty factor. 4 Includes programming of OTP memory. Rev. F | Page 10 of 30

Data Sheet AD5291/AD5292 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 14 RDY VSS 2 AD5291/ 13 SDO A 3 AD5292 12 SYNC W 4 TOP VIEW 11 SCLK B 5 Not to Scale 10 DIN EXT_CVADPD 67 98 GVLNODGIC 07674-006 Figure 5. Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the logic high transition. Tie RESET to V if not used. LOGIC 2 V Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF SS ceramic capacitors and 10 μF capacitors. 3 A Terminal A of RDAC. V ≤ V ≤ V . SS A DD 4 W Wiper Terminal of RDAC. V ≤ V ≤ V . SS W DD 5 B Terminal B of RDAC. V ≤ V ≤ V . SS B DD 6 V Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. DD 7 EXT_CAP External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V. 8 V Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF LOGIC capacitors. 9 GND Ground Pin, Logic Ground Reference. 10 DIN Serial Data Input. The AD5291 and AD5292 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 11 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. 12 SYNC Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. 13 SDO Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in daisy-chain mode or in readback mode. 14 RDY Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from the RDAC register or memory. Rev. F | Page 11 of 30

AD5291/AD5292 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 –40°C 20kΩ TEMPERATURE = 25°C 0.8 +25°C 0.8 50kΩ 100kΩ +105°C 0.6 0.6 0.4 0.4 0.2 0.2 B) B) S S L (L 0 L (L 0 N N I –0.2 I –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 RAB = 20kΩ –1.0 –1.0 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-106 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-215 Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5292) Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292) 0.6 0.6 RAB = 20kΩ TEMPERATURE = 25°C 0.5 0.5 0.4 0.4 0.3 0.3 SB) 0.2 SB) 0.2 L L NL ( 0.1 NL ( 0.1 D D 0 0 –0.1 –0.1 –0.2 –0.2 20kΩ 50kΩ –40°C +25°C +105°C 100kΩ –0.3 –0.3 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-007 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-211 Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5292) Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292) 1.0 1.0 RAB = 20kΩ 2500kkΩΩ TEMPERATURE = 25°C 0.8 0.8 100kΩ 0.6 0.6 0.4 SB) B) 0.4 INL (L 0.02 NL (LS 0.2 I 0 –0.2 –0.2 –0.4 –40°C +25°C +105°C –0.4 –0.6 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-010 –0.60 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-216 Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5292) Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292) Rev. F | Page 12 of 30

Data Sheet AD5291/AD5292 0.15 0.15 RAB = 20kΩ 2500kkΩΩ TEMPERATURE = 25°C 100kΩ 0.10 0.10 0.05 0.05 B) 0 B) 0 S S L L L ( L ( N–0.05 N–0.05 D D –0.10 –0.10 –0.15 –0.15 –40°C +25°C +105°C –0.200 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-011 –0.200 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-213 Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5292) Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292) 1.5 0.8 RAB = 20kΩ TEMPERATURE = 25°C 1.0 0.6 0.5 0.2 B) B) S S L (L 0 L (L 0 N N I I –0.5 –0.2 –1.0 –0.6 20kΩ 50kΩ –40°C +25°C +105°C 100kΩ –1.50 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-014 –0.80 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-207 Figure 13. INL in R-Perf Mode vs. Code vs. Temperature (AD5292) Figure 16. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292) 0.6 0.6 RAB = 20kΩ TEMPERATURE = 25°C 0.5 0.5 0.4 0.4 0.3 0.3 SB) SB) 0.2 NL (L 0.2 NL (L 0.1 D D 0.1 0 0 –0.1 –0.1 –0.2 20kΩ 50kΩ –40°C +25°C +105°C 100kΩ –0.20 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-015 –0.30 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-203 Figure 14. DNL in R-Perf Mode vs. Code vs. Temperature (AD5292) Figure 17. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5292) Rev. F | Page 13 of 30

AD5291/AD5292 Data Sheet 0.8 0.8 RAB = 20kΩ +–4205°°CC 2500kkΩΩ TEMPERATURE = 25°C 0.6 0.6 100kΩ +105°C 0.4 0.4 0.2 0.2 B) B) S S L (L 0 L (L 0 N N I I –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-018 0 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-209 Figure 18. INL in Normal Mode vs. Code vs. Temperature (AD5292) Figure 21. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5292) 0.10 0.08 –40°C 20kΩ +25°C 50kΩ 100kΩ 0.05 +105°C 0.04 0 0 B) B) S S L (L–0.05 L (L–0.04 N N D D –0.10 –0.08 –0.15 –0.12 TEMPERATURE = 25°C RAB = 20kΩ –0.200 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-019 –0.160 128 256 38C4ODE 5(D12ecima6l4)0 768 896 1023 07674-205 Figure 19. DNL in Normal Mode vs. Code vs. Temperature (AD5292) Figure 22. DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5292) 0.30 0.30 –40°C +25°C +105°C 20kΩ TEMPERATURE = 25°C 0.25 0.25 5100k0kΩΩ 0.20 0.20 0.15 0.15 B) 0.10 B) 0.10 S S L (L 0.05 L (L 0.05 N N I 0 I 0 –0.05 –0.05 –0.10 –0.10 –0.15 –0.15 RAB = 20kΩ –0.200 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-008 –0.200 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-218 Figure 20. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5291) Figure 23. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291) Rev. F | Page 14 of 30

Data Sheet AD5291/AD5292 0.14 0.14 RAB = 20kΩ TEMPERATURE = 25°C 0.12 0.12 0.10 0.10 0.08 0.08 B) 0.06 B) 0.06 S S L (L 0.04 L (L 0.04 N N D 0.02 D 0.02 0 0 –0.02 –0.02 20kΩ –0.04 –0.04 50kΩ –40°C +25°C +105°C 100kΩ –0.060 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-009 –0.060 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-212 Figure 24. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5291) Figure 27. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291) 0.25 0.25 –40°C +25°C +105°C 20kΩ TEMPERATURE = 25°C 50kΩ 100kΩ 0.20 0.20 0.15 0.15 B) 0.10 B) 0.10 S S NL (L 0.05 NL (L 0.05 I I 0 0 –0.05 –0.05 RAB = 20kΩ –0.10 –0.10 0 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-012 0 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-217 Figure 25. R-INL in Normal Mode vs. Code vs. Temperature (AD5291) Figure 28. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291) 0.03 0.03 –40°C +25°C +105°C TEMPERATURE = 25°C 20kΩ 50kΩ 0.02 0.02 100kΩ 0.01 0.01 0 0 B) B) S S L (L–0.01 L (L–0.01 N N D D –0.02 –0.02 –0.03 –0.03 –0.04 –0.04 RAB = 20kΩ –0.050 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-013 –0.050 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-214 Figure 26. R-DNL in Normal Mode vs. Code vs. Temperature (AD5291) Figure 29. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5291) Rev. F | Page 15 of 30

AD5291/AD5292 Data Sheet 0.25 0.25 –40°C +25°C +105°C TEMPERATURE = 25°C 0.20 0.20 0.15 0.15 0.10 0.10 B) 0.05 B) 0.05 S S L (L 0 L (L 0 N N I–0.05 I–0.05 –0.10 –0.10 –0.15 –0.15 20kΩ –0.20 –0.20 50kΩ RAB = 20kΩ 100kΩ –0.250 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-016 –0.250 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-208 Figure 30. INL in R-Perf Mode vs. Code vs. Temperature (AD5291) Figure 33. INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291) 0.14 0.14 –40°C +25°C +105°C TEMPERATURE = 25°C 0.12 0.12 0.10 0.10 0.08 0.08 B) 0.06 B) 0.06 S S L (L 0.04 L (L 0.04 N N D 0.02 D 0.02 0 0 –0.02 –0.02 20kΩ –0.04 –0.04 50kΩ RAB = 20kΩ 100kΩ –0.060 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-017 –0.060 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-204 Figure 31. DNL in R-Perf Mode vs. Code vs. Temperature (AD5291) Figure 34. DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5291) 0.20 0.20 –40°C +25°C +105°C 20kΩ TEMPERATURE = 25°C 50kΩ 0.15 0.15 100kΩ 0.10 0.10 0.05 0.05 B) B) S S NL (L 0 NL (L 0 I–0.05 I–0.05 –0.10 –0.10 –0.15 –0.15 –0.200 32 64 9C6ODE 1(D28ecima1l6)0 192 224 256 07674-020 –0.200 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-210 Figure 32. INL in Normal Mode vs. Code vs. Temperature (AD5291) Figure 35. INL in Normal Mode vs. Code vs. Nominal Resistance (AD5291) Rev. F | Page 16 of 30

Data Sheet AD5291/AD5292 0.03 0.03 –40°C +25°C +105°C TEMPERATURE = 25°C 0.02 0.02 0.01 0.01 0 0 B) B) S S L (L–0.01 L (L–0.01 N N D D –0.02 –0.02 –0.03 –0.03 –0.04 –0.04 20kΩ 50kΩ RAB = 20kΩ 100kΩ –0.05 –0.05 0 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-021 0 32 64 9C6ODE 1(D28ecima1l6)0 192 224 255 07674-206 Figure 36. DNL in Normal Mode vs. Code vs. Temperature (AD5291) Figure 39. DNL in Normal Mode vs. Code vs. Temperature (AD5291) 450 0.20 VDD/VSS = ±15V VDD = ±15V 400 VLOGIC = +5V 0.18 350 A) 0.16 ILOGIC m URRENT (nA) 322050000 RENT I (LOGIC 00..011.241 C R LY 150 CU 0.08 SUPP 100 IDD UPPLY 0.06 50 S 0.04 0 0.02 ISS –50–40–30–20–10 0 1T0EM2P0ER3A0TU4R0E 5(°0C)60 70 80 90 100 07674-022 00 0.5 1.0 D1I.G5ITA2L. 0INPU2T.5 VOL3T.0AGE3 (.V5) 4.0 4.5 5.0 07674-031 Figure 37. Supply Current (IDD, ISS, ILOGIC) vs. Temperature Figure 40. Supply Current ILOGIC vs. Digital Input Voltage 700 700 ODE TEMPCO (ppm/°C) 654300000000 VVDSSD= = 012 53V00000kkVkΩΩ,Ω R MODE TEMPCO (ppm/°C) 654300000000 VVDSSD= = 0 5213V0000kk0VkΩΩΩ M E OSTAT 200 TIOMET 200 E N RH 100 TE 100 O P 000 26546 CODE 15(D2182ecimal) 179628 1205253 AADD55229921 07674-024 000 26546 CODE 15(D2182ecimal) 179628 1205253 AADD55229921 07674-023 Figure 38. Rheostat Mode Tempco ΔRWB/ΔT vs. Code Figure 41. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code Rev. F | Page 17 of 30

AD5291/AD5292 Data Sheet 0 0 AD5292 (AD5291) –5 0x200 (0x80) AD5292 (AD5291) –5 0x200 (0x80) –10 0x100 (0x40) –10 0x100 (0x40) –15 0x080 (0x20) –15 –20 0x080 (0x20) 0x040 (0x10) –25 dB) –20 0x040 (0x10) dB) –30 0x020 ( 0x08) N ( –25 N ( –35 0x010 (0x04) GAI –30 0x020 ( 0x08) GAI –40 0x008 (0x02) 0x010 (0x04) –45 0x004 (0x01) –35 0x008 (0x02) –50 0x002 –40 –55 0x001 –45 0x004 (0x01) –60 0x002 0x001 –65 –5010 100 FR1kEQUENCY 1(H0kz) 100k 1M 07674-025 –67.51 10 100FREQUE1NkCY (Hz)10k 100k 1M 07674-201 Figure 42. 20 kΩ Gain vs. Frequency vs. Code Figure 45. 100 kΩ Gain vs. Frequency vs. Code 0 0 AD5292 (AD5291) 100kΩ 0x200 (0x80) 20kΩ 50kΩ –10 –10 0x100 (0x40) 0x080 (0x20) –20 –20 0x040 (0x10) B) B)–30 N (d –30 0x020 ( 0x08) R (d GAI 0x010 (0x04) PSR–40 –40 0x008 (0x02) –50 0x004 (0x01) –50 –60 0x002 0x001 –60 –70 10 100 FR1kEQUENCY 1(H0kz) 100k 1M 07674-200 100 1k FREQU1E0NkCY (Hz) 100k 1M 07674-026 Figure 43. 50 kΩ Gain vs. Frequency vs. Code Figure 46. Power Supply Rejection Ratio vs. Frequency 0 0 VDD/VSS = ±15V VDD/VSS = ±15V, CODE = HALF SCALE CODE = HALF SCALE –15 VNIoNi s=e 1 BVW rm =s 22kHz –20 fNINO I=S 1Ek BHWz = 22kHz 20kΩ 20kΩ –30 –40 50kΩ 50kΩ 100kΩ 100kΩ dB) –45 N (dB) –60 + N ( –60 HD + –80 D T H T –75 –100 –90 –120 –105 –140 –120100 1k FREQUENC1Y0 (kHz) 100k 07674-027 0.001 0.01 AMPLITU0D.1E (V rms) 1 10 07674-220 Figure 44. THD + Noise vs. Frequency Figure 47. THD + Noise vs. Amplitude Rev. F | Page 18 of 30

Data Sheet AD5291/AD5292 1,000,000 8 2200kk –– 07p5pFF 5500kk –– 125500ppFF VDD/VSS = 30V/0V 900,000 2200kk –– 125500ppFF 110000kk –– 07p5pFF 7 VVAB == VVDSSD 800,000 50k – 0pF 100k – 150pF 50k – 75pF 100k – 250pF mA) 6 H (Hz)670000,,000000 (B_MAX 5 T W WID500,000 AL I 4 BAND400,000 RETIC 3 20kΩ 300,000 O E 50kΩ H 2 200,000 T 100,000 1 100kΩ 000 8 8 16 C1O63D2E (Deci6m43a2l) 128 64256 511228 AADD55229921 07674-222 000 26546 CODE 51(D1228ecimal) 716982 1205253 AADD55229921 07674-029 Figure 48. Bandwidth vs. Code vs Net Capacitance Figure 51. Theoretical Maximum Current vs. Code 35 1.2 30 1.0 VVDLODG/VICS S= =+ 5±V15V VA = VDD A) 25 0.8 VB = VSS m RENT I (DD 2105 E (V) 00..46 521000kk0kΩΩΩ R G U A 0.2 C T PLY 10 VOL 0 P SU 5 –0.2 0 –0.4 –0.6 –5–0.4 –0.2 0 0.2 TIM0E. 4(ms) 0.6 0.8 1.0 1.2 07674-034 –0.8–2 0 2 4 6TIME (µ8s) 10 12 14 16 07674-035 Figure 49. IDD Waveform While Blowing/Reading Fuse Figure 52. Maximum Transition Glitch 35 40 VWB, CODE: FULL SCALE, VDD/VSS = ±15V NORMAL MODE 32 VA= VDD 30 VB= VSS VDD/VSS = 30V/0V 24 CODE = HALF CODE 25 VLOGIC = 5V VA = VDD 16 VB = VSS VOLTAGE (V) 112050 VWB, CODE:R F-PUELRLF S MCAOLDEE, VOLTAGE (μV) –808 SYNC –16 5 VWB, CODE: HALF-SCALE, 2500kkΩΩ –24 NORMAL MODE 100kΩ 0 VWB, CODE: HALF-SCALE, 2500kkΩΩ –32 R-PERF MODE 100kΩ –5–2 –1 0 1 2 3 4 5 T6IME7 (µ8s) 9 10 11 12 13 14 15 07674-033 –40–0.5 0 5 10 15TIM2E0 (µs)25 30 35 40 45 07674-032 Figure 50. 20 kΩ Large-Signal Settling Time from Code Zero Scale Figure 53. Digital Feedthrough Rev. F | Page 19 of 30

AD5291/AD5292 Data Sheet 6 75.0 300 VDD/VSS = ±15V VDD/VSS= ±15V VLOGIC = +5V 20kΩ 5 62.5 50kΩ 250 1) 100kΩ 2) 9 9 4 52 52 AD 50.0 200 AD LTAGE (V) 23 F CODES ( 37.5 150 F CODES ( O O O V R R E 25.0 100 E 1 MB MB U U N N 12.5 50 0 –1–1.0 –0.4 0.2 0.8 1.4 2.0 2.6 3.2TIM3.8E (m4.4s)5.0 5.6 6.2 6.8 7.4 8.0 8.6 07674-036 0–40–30–20–10 0 1T0EM2P0ER3A0TU4R0E 5(°0C)60 70 80 90 100 0 07674-056 Figure 54. VEXT_CAP Waveform While Reading Fuse or Calibration Figure 56. Code Range > 1% R-Tolerance Error vs. Temperature 8 20.0 80 VDD/VSS = ±15V 20kΩ VA = VDD VLOGIC = +5V 17.5 50kΩ VTEB M=P VESRSATURE = 25°C 70 100kΩ 6 D5291)15.0 60 D5292) VOLTAGE (V) 23 R OF CODES (A11027...055 345000 R OF CODES (A BE BE UM 5.0 20 UM 0 N N 2.5 10 –2–2.0 –0.8 0.4 1.6 2.8 4.0 5.2 6.4TIM7.6E (8.8ms)10.0 11.2 12.4 13.6 14.8 16.0 17.2 07674-037 021 26VOLTAGE VDD/VSS30 330 07674-219 Figure 55. VEXT_CAP Waveform While Writing Fuse Figure 57. Code Range > 1% R-Tolerance Error vs. Voltage Rev. F | Page 20 of 30

Data Sheet AD5291/AD5292 TEST CIRCUITS Figure 58 to Figure 63 define the test conditions used in the Specifications section. NC DUT A IW VA W V+ = VDD ± 10% B NC = NO CVOMNSNECT 07674-041 V+ ~ VDD BA W VMS PPSSSR R(% (d/%B)) == ∆∆20VV MDloDSg%%∆∆VVMDDS 07674-044 Figure 58. Resistor Position Nonlinearity Error Figure 61. Power Supply Sensitivity (PSS, PSRR) (Rheostat Operation; R-INL, R-DNL) A +15V ADUT V1L+S =B V =D DV+/2N VIN DUT W V+ W OFFSET B OP42 VOUT GND B VMS 07674-042 2.5V –15V 07674-047 Figure 59. Potentiometer Divider Nonlinearity Error Figure 62. Gain vs. Frequency (INL, DNL) +15V –15V NC GND 0.1V GND DUT RWB= IWB DVDUDT A W ICM +15V W CODE = 0x00 + RW = RW2B VSS GND B –15V B IWB –0.1V GND A = NC VSS TO VDD 07674-043 NC+15V –15VGND NC = NO CONNECT 07674-048 Figure 60. Wiper Resistance Figure 63. Common-Mode Leakage Current Rev. F | Page 21 of 30

AD5291/AD5292 Data Sheet THEORY OF OPERATION The AD5291 and AD5292 digital potentiometers are designed the lower two RDAC data bits are don’t cares if the RDAC register to operate as true variable resistors for analog signals that is read from or written to. Data is loaded MSB first (Bit DB15). remain within the terminal voltage range of VSS < VTERM < The four control bits determine the function of the software VDD. The patented ±1% resistor tolerance feature helps to command (see Table 11). Figure 3 shows a timing diagram of a minimize the total RDAC resistance error, which reduces the typical AD5291 and AD5292 write sequence. overall system error by offering better absolute matching and The write sequence begins by bringing the SYNC line low. The improved open-loop performance. The digital potentiometer SYNC pin must be held low until the complete data-word is wiper position is determined by the RDAC register contents. loaded from the DIN pin. When SYNC returns high, the serial The RDAC register acts as a scratchpad register, allowing as data-word is decoded according to the commands in Table 11. many value changes as necessary to place the potentiometer The command bits (Cx) control the operation of the digital wiper in the correct position. The RDAC register can be potentiometer. The data bits (Dx) are the values that are loaded programmed with any position setting using the standard SPI into the decoded register. The AD5291 and AD5292 have an interface by loading the 16-bit data-word. Once a desirable internal counter that counts a multiple of 16 bits (a frame) for position is found, this value can be stored in a 20-TP memory proper operation. For example, AD5291 and AD5292 work with register. Thereafter, the wiper position is always restored to that a 32-bit word but does not work properly with a 31-bit or 33-bit position for subsequent power-up. The storing of 20-TP data word. The AD5291 and AD5292 do not require a continuous takes approximately 6 ms; during this time, the shift register is SCLK, when SYNC is high, and all serial interface pins should locked, preventing any changes from taking place. The RDY pin be operated at close to the VLOGIC supply rails to minimize identifies the completion of this 20-TP storage. power consumption in the digital input buffers. SERIAL DATA INTERFACE RDAC REGISTER The AD5291 and AD5292 contain a serial interface (SYNC, The RDAC register directly controls the position of the digital SCLK, DIN and SDO) that is compatible with SPI interface potentiometer wiper. For example, when the RDAC register is standards, as well as most DSPs. The part allows writing of data loaded with all zeros, the wiper is connected to Terminal B of via the serial interface to every register. the variable resistor. The RDAC register is a standard logic SHIFT REGISTER register; there is no restriction on the number of changes allowed. The AD5291 and AD5292 shift register is 16 bits wide (see Figure 2). The 16-bit input word consists of two zeros, followed by four control bits, and 10 RDAC data bits. For the AD5291, Table 11. Command Operation Truth Table Command Bits[DB13:DB10] Data Bits[DB9:DB0]1 Command DB15 DB14 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 0 0 X X X X X X X X X X NOP command: do nothing. 1 0 0 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D12 D02 Write contents of serial data to RDAC. 2 0 0 0 0 1 0 X X X X X X X X X X Read RDAC wiper setting from the SDO output in the next frame. 3 0 0 0 0 1 1 X X X X X X X X X X Store wiper setting: store RDAC setting to 20-TP memory. 4 0 0 0 1 0 0 X X X X X X X X X X Reset: refresh RDAC with 20-TP stored value. 5 0 0 0 1 0 1 X X X X X D4 D3 D2 D1 D0 Read contents of 20-TP memory, or status of 20-TP memory, from the SDO output in the next frame. 6 0 0 0 1 1 0 X X X X X X D3 D2 D1 D0 Write contents of serial data to control register. 7 0 0 0 1 1 1 X X X X X X X X X X Read control register from the SDO output in the next frame. 8 0 0 1 0 0 0 X X X X X X X X X D0 Software shutdown. D0 = 0 (normal mode). D0 = 1 (device placed in shutdown mode). 1 X = don’t care. 2 In the AD5291, this bit is a don’t care. Rev. F | Page 22 of 30

Data Sheet AD5291/AD5292 20-TP MEMORY WRITE PROTECTION Once a desirable wiper position is found, the contents of the On power-up, the shift register write commands for both the RDAC register can be saved into a 20-TP memory register RDAC register and the 20-TP memory register are disabled. (see Table 12). Thereafter, the wiper position is always set at that The RDAC write protect bit, C1 of the control register (see position for any future on-off-on power supply sequence. The Table 13 and Table 14), is set to 0 by default. This disables any AD5291 and AD5292 have an array of 20 one-time programmable change of the RDAC register content regardless of the software (OTP) memory registers. When the desired word is programmed commands, except that the RDAC register can be refreshed to 20-TP memory, the device automatically verifies that the from the 20-TP memory using the software reset command program command was successful. The verification process (Command 4) or through hardware by the RESET pin. To enable includes margin testing. Bit C3 of the control register can be programming of the variable resistor wiper position (program- polled to verify that the fuse program command was successful. ming the RDAC register), the write protect bit, C1 of the control Programming data to 20-TP memory consumes approximately register, must first be programmed. This is accomplished by 25 mA for 550 μs and takes approximately 8 ms to complete. loading the shift register with Command 6 (see Table 11). To During this time, the shift register is locked, preventing any enable programming of the 20-TP memory block bit, C0 of the changes from taking place. The RDY pin can be used to monitor control register (set to 0 by default) must first be set to 1. the completion of the 20-TP memory program and verification. No change in supply voltage is required to program the 20-TP memory. However, a 1 μF capacitor on the EXT_CAP pin is required (see Figure 68). Prior to 20-TP activation, the AD5291 and AD5292 preset to midscale on power-up. Table 12. Write and Read to RDAC and 20-TP Memory DIN SDO Action 0x1803 0xXXXX Enable update of wiper position and 20-TP memory contents through digital interface. 0x0500 0x1803 Write 0x100 to the RDAC register; wiper moves to ¼ full-scale position. 0x0800 0x0500 Prepare data read from the RDAC register. 0x0C00 0x0100 Stores RDAC register content into 20-TP memory. The 16-bit word appears out of SDO, where the last 10 bits contain the contents of the RDAC register (0x100). 0x1C00 0x0C00 Prepare data read from the control register. 0x0000 0x000X NOP Instruction 0 sends 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, the fuse program command is successful. Table 13. Control Register Bit Map1 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X C3 C2 C1 C0 1 X = don’t care. Table 14. Control Register Function Bit Name Description C0 20-TP program enable 0 = 20-TP program disabled (default) 1 = enable device for 20-TP program C1 RDAC register write protect 0 = wiper position frozen to value in memory (default)1 1 = allow update of wiper position through digital Interface C2 Calibration enable 0 = resistor performance mode enabled (default) 1 = normal mode enabled C3 20-TP memory program success 0 = fuse program command unsuccessful (default) 1 = fuse program command successful 1 Wiper position frozen to value last programmed in 20-TP memory. Wiper is frozen to midscale if 20-TP memory has not been previously programmed. Rev. F | Page 23 of 30

AD5291/AD5292 Data Sheet BASIC OPERATION read-only Memory Address 0x14 and Memory Address 0x15 using Command 5. The data bytes read back from Memory The basic mode of setting the variable resistor wiper position Address 0x014 and Memory Address 0x015 are thermometer (programming the RDAC register) is accomplished by loading encoded versions of the address of the last programmed the shift register with Command 1 (see Table 11) and the desired memory location. wiper position data. When the desired wiper position is deter- mined, the user can load the shift register with Command 3 For the example outlined in Table 15, the address of the last (see Table 11), which stores the wiper position data in the 20-TP programmed location is calculated as memory register. After 6 ms, the wiper position is permanently (Number of Bits = 1 in Memory Address 0x14) + (Number stored in the 20-TP memory. The RDY pin can be used to moni- of Bits = 1 in Memory Address 0x15) − 1 = 10 + 8 − 1 = 17 tor the completion of this 20-TP program. Table 12 provides a (0x10) programming example, listing the sequence of serial data input If no memory location has been programmed, then the address (DIN) words with the serial data output appearing at the SDO pin generated is −1. in hexadecimal format. SHUTDOWN MODE 20-TP READBACK AND SPARE MEMORY STATUS The AD5291 and AD5292 can be placed in shutdown mode by It is possible to read back the contents of any of the 20-TP executing the software shutdown command, Command 8 (see memory registers through SDO by using Command 5 (see Table 11), and setting the LSB, D0, to 1. This feature places the Table 11). The lower five LSB bits (D0 to D4) of the data byte RDAC in a special state in which Terminal A is open-circuited, select which memory location is to be read back (see Table 16). and Wiper W is connected to Terminal B. The contents of the Data from the selected memory location are clocked out of the RDAC register are unchanged by entering shutdown mode. SDO pin during the next SPI operation, where the last 10 bits However, all commands listed in Table 11 are supported while contain the contents of the specified memory location. in shutdown mode. Execute Command 8 (see Table 11), and set It is also possible to calculate the address of the most recently the LSB, D0, to 0 to exit shutdown mode. programmed memory location by reading back the contents of Table 15. Example 20-TP Memory Readback DIN SDO Action 0x1414 0xXXXX Prepares data read from Memory Address 0x14. 0x1415 0x03FF Prepares data read from Memory Address 0x15. Sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x14. 0x0000 0x00FF NOP Command 0 sends 16-bit word out of SDO, where last 10-bits contain the contents of Memory Address 0x15. 0x1410 0x0000 Prepares data read from memory location 0x10. 0x0000 0xXXXX NOP Instruction 0 sends 16-bit word out of SDO, where the last 10 bits contain the contents of Memory Address 0x10 (17). Table 16. Memory Map of Command 5 Data Bits[DB9:DB0]1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Register Contents X X X X X 0 0 0 0 0 1st programmed wiper location (0x00) X X X X X 0 0 0 0 1 2nd programmed wiper location (0x01) X X X X X 0 0 0 1 0 3rd programmed wiper location (0x02) X X X X X 0 0 0 1 1 4th programmed wiper location (0x03) X X X X X 0 0 1 0 0 5th programmed wiper location (0x04) … … … … … … … … … … … X X X X X 0 1 0 0 1 10th programmed wiper location (0x09) X X X X X 0 1 1 1 0 15th programmed wiper location (0x0E) X X X X X 1 0 0 1 1 20th programmed wiper location (0x13) X X X X X 1 0 1 0 0 Programmed memory status (thermometer encoded)2 (0x14) X X X X X 1 0 1 0 1 Programmed memory status (thermometer encoded)2 (0x15) 1 X = don’t care. 2 Allows the user to calculate the remaining spare memory locations. Rev. F | Page 24 of 30

Data Sheet AD5291/AD5292 RESISTOR PERFORMANCE MODE Keep the SYNC pin low until all 32 bits are clocked into their This mode activates a new, patented 1% end-to-end resistor respective serial registers. The SYNC pin is then pulled high to tolerance that ensures a ±1% resistor tolerance on each code, complete the operation. that is, code = half scale, RWB = 10 kΩ ± 100 Ω. See Table 2 VLOGIC (AD5291) or Table 5 (AD5292) to check which codes achieve ±1% resistor tolerance. The resistor performance mode is AADD55229912/ 2R.P2kΩ AADD55229912/ activated by programming Bit C2 of the control register (see MOSI DIN U1 SDO DIN U2 SDO MICRO- CONTROLLER Table 13 and Table 14). The typical settling time is shown in SCLK SS Figure 50. SYNC SCLK SYNC SCLK RESET 07674-050 A low-to-high transition of the hardware RESET pin loads the Figure 64. Daisy-Chain Configuration Using SDO RDAC register with the contents of the most recently programmed RDAC ARCHITECTURE 20-TP memory location. The AD5291 and AD5292 can also be To achieve optimum performance, Analog Devices has patented reset through software by executing Command 4 (see Table 11). the RDAC segmentation architecture for all the digital If no 20-TP memory location is programmed, then the RDAC potentiometers. In particular, the AD5291 and AD5292 employ register loads with midscale upon reset. The control register is a three-stage segmentation approach, as shown in Figure 65. restored with default bits; see Table 14. The AD5291 and AD5292 wiper switches are designed with the SDO PIN AND DAISY-CHAIN OPERATION transmission gate CMOS topology and with the gate voltages The serial data output pin (SDO) serves two purposes: it can be derived from VDD and VSS. used to read the contents of the wiper setting, 50-TP values and A control register using Command 2, Command 5 and Command 7, respectively (see Table 11) or the SDO pin can be used in daisy- RL chain mode. Data is clocked out of SDO on the rising edge of SCLK. The SDO pin contains an open-drain N-channel FET that requires a pull-up resistor if this pin is used. To place the RL RM pin in high impedance and minimize the power dissipation when the pin is used, the 0x8001 data word followed by RM SW Command 0 should be sent to the part. Table 17 provides a RW sample listing for the sequence of the serial data input (DIN). W Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 64, users need to RW 8-/10-BIT tie the SDO pin of one package to the DIN pin of the next DAEDCDORDESESR RM package. Users may need to increase the clock period, because RL the pull-up resistor and the capacitive loading at the SDO-to- RM DIN interface may require additional time delay between RL subsequent devices. When two AD5291 and AD5292 devices are daisy-chained, 32 B bits of data are required. The first 16 bits go to U2, and the aserec ocnlodc 1k6ed b iitnst ogo t htoei rU r1e.s Hpeocltdiv teh esh SiYftN reCg ipsitner lso. wT huen StiYl aNllC 3 p2 ibni tiss 07674-051 then pulled high to complete the operation. Figure 65. Simplified RDAC Circuit Table 17. Minimize Power Dissipation at SDO Pin DIN SDO1 Action 0xXXXX 0xXXXX Last user command sent to the digipot 0x8001 0xXXXX Prepares the SDO pin to be placed in high impedance mode 0x0000 High impedance The SDO pin is placed in high impedance 1 X is don’t care. Rev. F | Page 25 of 30

AD5291/AD5292 Data Sheet PROGRAMMING THE VARIABLE RESISTOR where: Rheostat Operation—1% Resistor Tolerance D is the decimal equivalent of the binary code loaded in the 8-/10-bit RDAC register. The AD5291 and AD5292 operate in rheostat mode when only R is the end-to-end resistance. AB two terminals are used as a variable resistor. The unused terminal can be left floating or tied to the W terminal, as shown in In the zero-scale condition, a finite total wiper resistance of 120 Ω Figure 66. is present. Regardless of which setting the part is operating in, take care to limit the current between Terminal A and Terminal B, A A A between Terminal W and Terminal A, and between Terminal W W W W B B B 07674-052 aton dth Tee prumlsien caul Brr, etnot t shpee mciafixeidm iunm T caobnlet i8n.u Oouths ecruwrriesne,t doef g±r3a dmaAti oonr Figure 66. Rheostat Mode Configuration or possible destruction of the internal resistors may occur. The nominal resistance between Terminal A and Terminal B, PROGRAMMING THE POTENTIOMETER DIVIDER RAB, is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 256 or 1024 Voltage Output Operation tap points accessed by the wiper terminal. The 8-/10-bit data in The digital potentiometer easily generates a voltage divider at the RDAC latch is decoded to select one of the 256/1024 the wiper to B and at the wiper to A that is proportional to the possible wiper settings. The AD5291 and AD5292 contain an input voltage at A to B, as shown in Figure 67. Unlike the polarity internal ±1% resistor performance mode that can be disabled or of V to GND, which must be positive, voltage across A to B, enabled (this is enabled by default), by programming Bit C2 of DD W to A, and W to B can be at either polarity. the control register (see Table 13 and Table 14). The digitally programmed output resistance between the W terminal and the VIN A A terminal, R , and between the W terminal and B terminal, WA W R , is internally calibrated to give a maximum of ±1% absolute VOUT WB rgeesnisetraanl ceeq uerartoiorn asc froors sd ae twerimdei ncoindge trhaen dgeig. iAtasl lay rpersougltr,a tmhem ed B 07674-053 Figure 67. Potentiometer Mode Configuration output resistance between the W terminal and B terminal are If ignoring the effect of the wiper resistance for simplicity, con- AD5291: necting the A terminal to 30 V and the B terminal to ground R (D) D R (1) produces an output voltage at the Wiper W to Terminal B WB 256 AB ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is AD5292: equal to the voltage applied across Terminal A and Terminal B, divided by the 256/1024 positions of the potentiometer divider. D R (D) R (2) The general equations defining the output voltage at V with WB 1024 AB W respect to ground for any valid input voltage applied to Terminal A where: and Terminal B are D is the decimal equivalent of the binary code loaded in the AD5291: 8-/10-bit RDAC register. R is the end-to-end resistance. D 256D AB V (D) V  V (5) W 256 A 256 B Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a AD5292: digitally controlled complementary resistance, RWA. RWA is also D 1024D calibrated to give a maximum of 1% absolute resistance error. VW(D)1024VA 1024 VB (6) R starts at the maximum resistance value and decreases as the WA If using the AD5291 and AD5292 in voltage divider mode as data loaded into the latch increases. The general equations for shown in Figure 67, then the ±1% resistor tolerance calibration this operation are feature reduces the error when matching with discrete resistors. AD5291: However, it is recommended to disable the internal ±1% resistor 256D tolerance calibration feature by programming Bit C2 of the R (D) R (3) WA 256 AB control register (see Table 13 and Table 14) to optimize wiper position update rate. In this configuration, the RDAC is ratiome- AD5292: tric and resistor tolerance error does not affect performance. 1024D R (D) R (4) WA 1024 AB Rev. F | Page 26 of 30

Data Sheet AD5291/AD5292 Operation of the digital potentiometer in the voltage divider The ground pins of the AD5291 and AD5292 devices are mode results in a more accurate operation over temperature. primarily used as a digital ground reference. To minimize the Unlike the rheostat mode, the output voltage is dependent digital ground bounce, the AD5291 and AD5292 ground mainly on the ratio of the internal resistors, R and R , and terminals should be joined remotely to the common ground. WA WB not the absolute values. Therefore, the temperature drift reduces The digital input control signals to the AD5291 and AD5292 to 5 ppm/°C. must be referenced to the device ground pin (GND), and satisfy the logic level defined in the Specifications section. EXT_CAP CAPACITOR Power-Up Sequence A 1 μF capacitor to GND must be connected to the EXT_CAP pin (see Figure 68) on power-up and throughout the operation of To ensure that the AD5291 and AD5292 power up correctly, a the AD5291 and AD5292. 1 μF capacitor must be connected to the EXT_CAP pin. Because there are diodes to limit the voltage compliance at Terminal A, AD5291/ Terminal B, and Terminal W (see Figure 69), it is important to AD5292 power V and V first before applying any voltage to Terminal A, EXT_CAP OTP DD SS MEMORY Terminal B, and Terminal W. Otherwise, the diode is forward- C1 BLOCK 1µF biased such that V and V are powered up unintentionally. DD SS The ideal power-up sequence is GND, V , V and V , the GND SS LOGIC DD 07674-054 udpig iVtaAl, iVnBp,u VtsW, ,a anndd t htheen dVigAi,t ValB i,n apnudt sV iWs .n Toht eim oprdoerrt aonft p aosw loenrign ags Figure 68. Hardware Setup for EXT_CAP Pin they are powered after V , V , and V . DD SS LOGIC TERMINAL VOLTAGE OPERATING RANGE Regardless of the power-up sequence and the ramp rates of the The positive VDD and negative VSS power supplies of the power supplies, after VLOGIC is powered, the power-on preset AD5291 and AD5292 define the boundary conditions for activates, restoring the 20-TP memory value to the RDAC register. proper 3-terminal digital potentiometer operation. Supply signals present on Terminal A, Terminal B, and Terminal W that exceed V or V are clamped by the internal forward- DD SS biased diodes (see Figure 69). VDD A W B VSS 07674-055 Figure 69. Maximum Terminal Voltages Set by VDD and V SS Rev. F | Page 27 of 30

AD5291/AD5292 Data Sheet APPLICATIONS INFORMATION HIGH VOLTAGE DAC HIGH ACCURACY DAC The AD5292 can be configured as a high voltage DAC, with It is possible to configure the AD5292 as a high accuracy DAC output voltage as high as 33 V. The circuit is shown in Figure 70. by optimizing the resolution of the device over a specific The output is reduced voltage range. This is achieved by placing external resistors on either side of the RDAC, as shown in Figure 72. D   R  VOUT(D)10241.2V 1R12 (7) Terhreo ri maspsroocviaetde d± 1w%it hR -mToatlcehrainngce t osp deicsicfriectaet iroens igstroerast.l y reduces where D is the decimal code from 0 to 1023. R (D R )V V (D) 3 1024 AB DD (8) VDD OUT R  ((1024D) )R R 1 1024 AB 3 RBIAS VDD VDD U1A U2 R1 U1 V+ AD5292 ADR512 D1 ADV8–512 20kΩ U1B AD5292 VDD B AD8512 VOUT 20kRΩ2 ±1% VU+2 VOUT B OP1177 R1 R2 07674-153 FigRu3re 72. OptimizinVg– Resolution 07674-154 Figure 70. High Voltage DAC VARIABLE GAIN INSTRUMENTATION AMPLIFIER PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT The AD8221 in conjunction with the AD5291 and AD5292 and the ADG1207, as shown in Figure 73, make an excellent For applications that require high current adjustments such as a instrumentation amplifier for use in data acquisition systems. laser diode or tunable laser, a boosted voltage source can be The data acquisition system’s low distortion and low noise considered; see Figure 71. enable it to condition signals in front of a variety of ADCs. U3 2N7002 VIN VOUT ADG1207 VDD U1 AD5292 CC RBIAS +VIN1 BA WOP184U2 SIGNLADL IL +–VVIINN41 AD5292 AD8221 VOUT Figure 71. Programmable Boosted Voltage Source 07674-155 –VIN4 VSS 07674-156 Figure 73. Data Acquisition System In this circuit, the inverting input of the op amp forces V to OUT be equal to the wiper voltage set by the digital potentiometer. The gain can be calculated by using Equation 9. The load current is then delivered by the supply via the N-channel 49.4kΩ FET (U3). The N-Channel FET power handling must be adequate G(D)1   (9) D1024 R to dissipate (V − V ) × I power. This circuit can source a AB IN OUT L maximum of 100 mA with a 33 V supply. Rev. F | Page 28 of 30

Data Sheet AD5291/AD5292 AUDIO VOLUME CONTROL The configuration to reduce zipper noise is shown in Figure 74, and the results of using this configuration is shown in Figure 75. The excellent THD performance and high voltage capability The input is ac-coupled by C1 and attenuated down before feeding make the AD5291 and AD5292 ideal for a digital volume into the window comparator formed by U2, U3, and U4B. U6 is control as an audio attenuator or gain amplifier. A typical used to establish the signal zero reference. The upper limit of problem in these systems is that a large step change in the the comparator is set above its offset and, therefore, the output volume level at any arbitrary time can lead to an abrupt pulses high whenever the input falls between 2.502 V and 2.497 V discontinuity of the audio signal causing an audible zipper (or 0.005 V window) in this example. This output is AND’ed noise. To prevent this, a zero-crossing window detector can be with the SYNC signal such that the AD5291 and AD5292 inserted to the SYNC line to delay the device update until the updates whenever the signal crosses the window. To avoid a audio signal crosses the window. Because the input signal can constant update of the device, the SYNC signal should be operate on top of any dc level rather than absolute zero volt programmed as two pulses, rather than as one. level, zero-crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. In Figure 75, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. C1 VIN 1µF 5V U1 AD5292 100kRΩ1 +5V +15V VDD C3 A U2 0.1µF VCC C2 R904kΩ 200RΩ2 ADGCNMDP371 U4B 0.–11µ5FV VSS W +15UV5 +5V 4 7408 6 1 U4A 20kΩ V+ VOUT R105kΩ 5V ADVCCMCPU3371 5 2 7S4C0L8K SSYCNLKC B V– U6 GND SDIN SDIN –15V ADV85+41 R3 SYNC GND V– 100kΩ 07674-157 Figure 74. Audio Volume Control with Zipper Noise Reduction T 1 2 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p CH1 500mV BW CH2 500mV BW MT 2 05µ0.s0%A CH2 210mV 07674-158 Figure 75. Zipper Noise Detector Rev. F | Page 29 of 30

AD5291/AD5292 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.2A0X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPELAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model12 R (kΩ) Resolution Memory Temperature Range Package Description Package Option AB AD5291BRUZ-20 20 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5291BRUZ-20-RL7 20 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5291BRUZ-50 50 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5291BRUZ-100 100 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5291BRUZ-100-RL7 100 256 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5292BRUZ-20 20 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5292BRUZ-20-RL7 20 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5292BRUZ-50 50 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5292BRUZ-50-RL7 50 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5292BRUZ-100 100 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 AD5292BRUZ-100-RL7 100 1,024 20-TP −40°C to +105°C 14-Lead TSSOP RU-14 EVAL-AD5292DBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The EVAL-AD5292DBZ is also used to test the AD5291. ©2009–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07674-0-11/19(F) Rev. F | Page 30 of 30

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5291BRUZ-20 AD5292BRUZ-20 AD5292BRUZ-50 AD5292BRUZ-100-RL7 AD5292BRUZ-100 AD5292BRUZ- 50-RL7 AD5292BRUZ-20-RL7