Single/Dual, +15 V/±5 V, 256-Position, I2C-Compatible Digital Potentiometer AD5280/AD5282 FEATURES logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. AD5280: 1 channel AD5282: 2 channels The AD5280/AD5282 are available in thin, surface-mounted 256 positions 14-lead TSSOP and 16-lead TSSOP. All parts are guaranteed to +10 V to +15 V single supply; ±5.5 V dual-supply operation operate over the extended industrial temperature range of Fixed terminal resistance: 20 kΩ, 50 kΩ, 200 kΩ −40°C to +85°C. For 3-wire SPI-compatible interface applica- Low temperature coefficient: 30 ppm/°C tions, see the AD5260/AD5262 product information on Power-on midscale preset1 www.analog.com. Programmable reset FUNCTIONAL BLOCK DIAGRAMS Operating temperature: −40oC to +85oC I2C-compatible interface A W B O1 O2 APPLICATIONS SHDN Multimedia, video, and audio VDD Communications VL Mechanical potentiometer replacement VSS RDAC REGISTER OUTPUT REGISTER Instrumentation: gain, offset adjustment ADDRESS Programmable voltage source CODE PWR ON Programmable current source 8 RESET Line impedance matching SCL SERIAL INPUT REGISTER SDA GThEeN AEDR5A28L0 D/AEDS5C2R82I ParTeI sOinNgl e-channel and dual-channel, GND AD5280 02929-070 256-position, digitally controlled variable resistors (VRs)2. AD0 AD1 The devices perform the same electronic adjustment function Figure 1. AD5280 as a potentiometer, trimmer, or variable resistor. Each VR offers A1 W1 B1 A2 W2 B2 O1 a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The OUTPUT SHDN REGISTER fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has VVDDDD a 1% channel-to-channel matching tolerance. The nominal VL temperature coefficient of both parts is 30 parts per million/ VSS RDAC1 REGISTER RDAC2 REGISTER degrees centigrade (ppm/°C). Another key feature is that the parts can operate up to +15 V or ±5 V. ADDRESS CODE PWR ON 8 RESET Wiper position programming defaults to midscale at system SCL power-on. When powered, the VR wiper position is programmed SERIAL INPUT REGISTER SDA by an I2C-compatible, 2-wire serial data interface. The AD5280/ AlevDe5l 2o8f 2p rfeeasteut rien spleoewpe mr-uopd ea nprdo igsr aanm amltaebrnilaittyiv. eT htois a a cllooswtlsy any GND AD5282 02929-001 AD0 AD1 EEPROM solution. Both parts have additional programmable Figure 2. AD5282 1 Assert shutdown and program the device during power-up, then deassert the shutdown to achieve the desired preset level. 2 The terms digital potentiometer, VR, and RDAC are used interchangeably. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.

AD5280/AD5282 TABLE OF CONTENTS Features .............................................................................................. 1  Multiple Devices on One Bus ................................................... 17  Applications ....................................................................................... 1  Level Shift for Bidirectional Interface ...................................... 18  General Description ......................................................................... 1  Level Shift for Negative Voltage Operation ............................ 18  Functional Block Diagrams ............................................................. 1  ESD Protection ........................................................................... 18  Revision History ............................................................................... 2  Terminal Voltage Operating Range ......................................... 18  Specifications ..................................................................................... 3  Power-Up Sequence ................................................................... 18  Electrical Characteristics ............................................................. 3  Layout and Power Supply Bypassing ....................................... 19  Absolute Maximum Ratings ............................................................ 5  Applications Information .............................................................. 20  Thermal Resistance ...................................................................... 5  Bipolar DC or AC Operation from Dual Supplies ................. 20  ESD Caution .................................................................................. 5  Gain Control Compensation .................................................... 20  Pin Configurations and Function Descriptions ........................... 6  15 V, 8-Bit I2C DAC .................................................................... 20  Typical Performance Characteristics ............................................. 7  8-Bit Bipolar DAC ...................................................................... 21  Test Circuits ..................................................................................... 12  Bipolar Programmable Gain Amplifier ................................... 21  Theory of Operation ...................................................................... 14  Programmable Voltage Source with Boosted Output ........... 21  Rheostat Operation .................................................................... 14  Programmable Current Source ................................................ 22  Potentiometer Operation........................................................... 14  Programmable Bidirectional Current Source ......................... 22  Digital Interface .............................................................................. 16  Programmable Low-Pass Filter ................................................ 23  2-Wire Serial Bus ........................................................................ 16  Programmable Oscillator .......................................................... 23  Readback RDAC Value .............................................................. 17  RDAC Circuit Simulation Model ............................................. 24  Additional Programmable Logic Output ................................ 17  Macro Model Net List for RDAC ............................................. 24  Self-Contained Shutdown Function and Programmable Outline Dimensions ....................................................................... 25  Preset ............................................................................................ 17  Ordering Guide .......................................................................... 26  REVISION HISTORY 7/09—Rev. B to Rev. C Changes to Features Section............................................................ 1 Updated Outline Dimensions, RU-14 ......................................... 25 Changes to Ordering Guide .......................................................... 26 8/07—Rev. A to Rev. B Updated Operating Temperature Range Throughout ................... 1 Changes to the Features Section ....................................................... 1 Changes to the General Description Section .................................. 1 Changes to Table 2 .............................................................................. 3 Added the Thermal Resistance Section ........................................... 5 Changes to the Ordering Guide ...................................................... 26 11/05—Rev. 0 to Rev. A Updated Format ................................................................... Universal Updated Outline Dimensions ......................................................... 26 Changes to Ordering Guide ............................................................ 27 10/02—Revision 0: Initial Version Rev. C | Page 2 of 28

AD5280/AD5282 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = +15 V, V = 0 V or V = +5 V, V = −5 V; V = 5 V, V = +V , V = 0 V; −40°C < T < +85°C, unless otherwise noted. DD SS DD SS LOGIC A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS–RHEOSTAT MODE Resistor Differential NL2 R-DNL R , V = NC −1 ±1/4 +1 LSB WB A Resistor Nonlinearity2 R-INL R , V = NC −1 ±1/4 +1 LSB WB A Nominal Resistor Tolerance3 ΔR T = 25°C −30 +30 % AB A Resistance Temperature (∆R /R )/∆T x 106 V = V , wiper = no connect 30 ppm/°C AB AB AB DD Coefficient Wiper Resistance R I = V /R, V = 3 V or 5 V 60 150 Ω W W DD DD DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE (specifications apply to all VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −1 ±1/4 +1 LSB Differential Nonlinearity4 DNL −1 ±1/4 +1 LSB Voltage Divider Temperature (∆V /V )/∆T x 106 Code = 0x80 5 ppm/°C W W Coefficient Full-Scale Error V Code = 0xFF −2 −1 0 LSB WFSE Zero-Scale Error V Code = 0x00 0 +1 +2 LSB WZSE RESISTOR TERMINALS Voltage Range5 V , V , V V V V A B W SS DD Capacitance A, B6 C , C f = 5 MHz, measured to GND, 25 pF A B Code = 0x80 Capacitance W6 C f = 1 MHz, measured to GND, 55 pF W Code = 0x80 Common-Mode Leakage I V = V = V 1 nA CM A B W Shutdown Current I 5 μA SHDN DIGITAL INPUTS AND OUTPUTS Input Logic High V 0.7 × V V + 0.5 V IH L L Input Logic Low V 0 0.3 × V V IL L Output Logic High (O, O) V 4.9 V 1 2 IH Output Logic Low (O, O) V 0.4 V 1 2 IL Input Current I V = 0 V or 5 V ±1 μA IL IN Input Capacitance6 C 5 pF IL POWER SUPPLIES Logic Supply V 2.7 V V LOGIC DD Power Single-Supply Range V V = 0 V 4.5 16.5 V DD RANGE SS Power Dual-Supply Range V ±4.5 ±5.5 V DD/SS RANGE Logic Supply Current I V = 5 V 60 μA LOGIC LOGIC Positive Supply Current I V = 5 V or V = 0 V 0.1 1 μA DD IH IL Negative Supply Current I 0.1 1 μA SS Power Dissipation7 P V = 5 V or V = 0 V, V = +5 V, V = −5 0.2 0.3 mW DISS IH IL DD SS V Power Supply Sensitivity PSS 0.002 0.01 %/% DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth −3 dB BW_20K R = 20 kΩ, Code = 0x80 310 kHz AB BW_50K R = 50 kΩ, Code = 0x80 150 kHz AB BW_200K R = 200 kΩ, Code = 0x80 35 kHz AB Rev. C | Page 3 of 28

AD5280/AD5282 Parameter Symbol Conditions Min Typ1 Max Unit Total Harmonic Distortion THD V = 1 V rms, R = 20 kΩ 0.014 % W A AB V = 0 V dc, f = 1 kHz B V Settling Time t V = 5 V, V = 5 V, ±1 LSB error band 5 μs W S A B Crosstalk CT V = V , V = 0 V, measure V with 15 nV-s A DD B W1 adjacent RDAC making full-scale code change Analog Crosstalk CTA Measure V with V = 5 V p-p @ f = −62 dB W1 W2 10 kHz Resistor Noise Voltage e R = 20 kΩ, f = 1 kHz 18 nV/√Hz N_WB WB INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11 SCL Clock Frequency f 0 400 kHz SCL t Bus Free Time Between t 1.3 μs BUF 1 Stop and Start t Hold Time (Repeated t After this period, the first clock pulse 0.6 μs HD:STA 2 Start) is generated tLOW Low Period of SCL Clock t3 1.3 μs tHIGH High Period of SCL Clock t4 0.6 μs tSU:STA Setup Time for Start t5 0.6 μs Condition tHD:DAT Data Hold Time t6 0 0.9 μs tSU:DAT Data Setup Time t7 100 ns tF Fall Time of Both SDA and t8 300 ns SCL Signals tR Rise Time of Both SDA and t9 300 ns SCL Signals tSU:STO Setup Time for STOP t10 0.6 μs Condition 1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use VDD = 5 V. 10 See timing diagram (Figure 3) for location of measured values. 11 Standard I2C mode operation is guaranteed by design. t8 t6 t9 t2 SCL t2 t3 t4 t7 t5 t10 t t 9 8 SDA P t1 S S P 02929-042 Figure 3. Detailed Timing Diagram Rev. C | Page 4 of 28

AD5280/AD5282 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 2. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +16.5 V DD section of this specification is not implied. Exposure to absolute V to GND 0 V to −7 V SS maximum rating conditions for extended periods may affect V to V 16.5 V DD SS device reliability. VA, VB, VW to GND VSS to VDD AX to BX, AX to WX, BX to WX THERMAL RESISTANCE Intermittent1 ±20 mA θ is specified for the worst-case conditions, that is, a device JA Continuous ±5 mA soldered in a circuit board for surface-mount packages. Package VLOGIC to GND 0 V to 7 V power dissipation = (T − T )/ θ JMAX A JA . Output Voltage to GND 0 V to 7 V Operating Temperature Range −40°C to +85°C Table 3. Thermal Resistance Maximum Junction Temperature (TJMAX) 150°C Package Type θJA Unit Storage Temperature Range −65°C to +150°C TSSOP-14 206 °C/W Reflow Soldering TSSOP-16 150 °C/W Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec ESD CAUTION 1 Maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. Rev. C | Page 5 of 28

AD5280/AD5282 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A 1 14 O1 O1 1 16 A2 W 2 13 VL A1 2 15 W2 B 3 AD5280 12 O2 W1 3 AD5282 14 B2 TOP VIEW VDD 4 11 VSS B1 4 TOP VIEW 13 VL SHDN 5 10 GND VDD 5 12 VSS SSDCAL 67 98 AADD01 02929-002 SHSSDDCNAL 678 11910 GAADDN10D 02929-003 Figure 4. AD5280 Pin Configuration Figure 5. AD5282 Pin Configuration Table 4. AD5280 Pin Function Descriptions Table 5. AD5282 Pin Function Descriptions Pin No. Mnemonic Description Pin No. Mnemonic Description 1 A Resistor Terminal A. 1 O1 Logic Output Terminal O1. 2 W Wiper Terminal W. 2 A1 Resistor Terminal A1. 3 B Resistor Terminal B. 3 W1 Wiper Terminal W1. 4 VDD Positive Power Supply. Specified for 4 B1 Resistor Terminal B1. operation from 5 V to 15 V (sum of |VDD| 5 VDD Positive Power Supply. Specified for + |V | ≤ 15 V). operation from 5 V to 15 V (sum of |V | SS DD 5 SHDN Active Low, Asynchronous Connection + |VSS| ≤ 15 V). of Wiper W to Terminal B and Open 6 SHDN Active Low, Asynchronous Connection Circuit of Terminal A. RDAC register of Wiper W to Terminal B and Open contents unchanged. SHDN should tie Circuit of Terminal A. RDAC register to V if not used. Can also be used as a contents unchanged. SHDN should tie L programmable preset in power-up. to V if not used. Can be also used as a L 6 SCL Serial Clock Input. programmable preset in power-up. 7 SDA Serial Data Input/Output. 7 SCL Serial Clock Input. 8 AD0 Programmable Address Bit 0 for 8 SDA Serial Data Input/Output. Multiple Package Decoding. Bit AD0 9 AD0 Programmable Address Bit 0 for and Bit AD1 provide four possible Multiple Package Decoding. Bit AD0 addresses. and Bit AD1 provide four possible 9 AD1 Programmable Address Bit 1 for addresses. Multiple Package Decoding. Bit AD0 10 AD1 Programmable Address Bit 1 for and Bit AD1 provide four possible Multiple Package Decoding. Bit AD0 addresses. and Bit AD1 provide four possible 10 GND Common Ground. addresses. 11 VSS Negative Power Supply. Specified for 11 GND Common Ground. operation from 0 V to −5 V (sum of |VDD| 12 VSS Negative Power Supply. Specified for + |V | ≤ 15 V). operation from 0 V to −5 V (sum of |V | SS DD 12 O2 Logic Output Terminal O2. + |VSS| ≤ 15 V). 13 VL Logic Supply Voltage. Needs to be less 13 VL Logic Supply Voltage. Needs to be less than or equal to VDD and at the same than or equal to VDD and at the same voltage as the digital logic controlling voltage as the digital logic controlling the AD5280. the AD5282. 14 O1 Logic Output Terminal O1. 14 B2 Resistor Terminal B2. 15 W2 Wiper Terminal W2. 16 A2 Resistor Terminal A2. Rev. C | Page 6 of 28

AD5280/AD5282 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.5 0.8 RAB = 20kΩ 0.4 RAB = 20kΩ TA = 25°C B) L (LSB) 00..64 +5V DNL (LS 00..32 TA = –40°C TA = +85°C ODE R-IN 0.20 R MODE 0.10 M E T –0.2 ET –0.1 A M OST –0.4 ±5V TIO –0.2 E N H +15V E R –0.6 T –0.3 O P TA = +25°C ––10..08 02929-004 ––00..45 02929-007 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 6. R-INL vs. Code vs. Supply Voltages Figure 9. DNL vs. Code, VDD/VSS = ±5 V 0.5 1.0 B) 00..43 RTAAB == 2250°kCΩ SB) 00..86 RTAA B= =2 52°0CkΩ R-DNL (LS 00..21 ±5V +15V ODE INL (L 00..42 ±5V +5V +15V E M OD 0 ER 0 M T AT –0.1 ME –0.2 T O OS –0.2 NTI –0.4 RHE –0.3 +5V OTE –0.6 P ––00..85 02929-005 ––01..80 02929-008 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 7. R-DNL vs. Code vs. Supply Voltages Figure 10. INL vs. Code vs. Supply Voltages 1.0 0.5 0.8 RAB = 20kΩ 0.4 RAB = 20kΩ TA = 25°C SB) 0.6 SB) 0.3 NL (L 0.4 TA = +85°C NL (L 0.2 +5V E I E I ±5V +15V D 0.2 D 0.1 O O M M R 0 R 0 E E T T E –0.2 E –0.1 M M TIO –0.4 TA = –40°C TIO –0.2 N N OTE –0.6 TA = +25°C OTE –0.3 P P ––01..08 02929-006 ––00..45 02929-009 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 8. INL vs. Code, VDD/VSS = ±5 V Figure 11. DNL vs. Code vs. Supply Voltages Rev. C | Page 7 of 28

AD5280/AD5282 1.0 2.0 RTAA B= =2 52°0CkΩ 1.8 RAB = 20kΩ AVG +3σ 1.6 0.5 AVG LSB) 1.4 VDD/VSS= +5V/0V R ( O 1.2 INL (LSB) 0 AVG –3σ CALE ERR 01..80 VDD/VSS= ±5V RO-S 0.6 VDD/VSS= +15V/0V –0.5 E Z 0.4 –1.0 929-01002 0.20 02929-013 0 5 10 15 20 –40 –20 0 20 40 60 80 100 |VDD– VSS| (V) TEMPERATURE (°C) Figure 12. INL Over Supply Voltage Figure 15. Zero-Scale Error 2.0 1000 1.5 RTAA B= =2 52°0CkΩ RAB = 20kΩ VVLIHO =G I+C5 =V +5V AVG +3σ VIL = 0V A) 1.0 n AVG T ( N 100 B) 0.5 AVG –3σ RRE S U R-INL (L –0.50 UPPLY C |SS@VDD/VSS= +15V/0V SS 10 |SS@VDD/VSS= ±5V S –1.0 /ID D I ––21..05 02929-011 1 |DD@VDD/VSS= ±5V 02929-014 0 5 10 15 20 –40 –7 26 59 85 |VDD– VSS| (V) TEMPERATURE (°C) Figure 13. R-INL Over Supply Voltage Figure 16. Supply Current vs. Temperature 0 26.0 RAB = 20kΩ RAB = 20kΩ –0.2 25.5 –0.4 R (LSB) –0.6 VDD/VSS= +15V/0V 25.0 VDD/VSS= +15V/0V E ERRO ––01..80 VDD/VSS= ±5V (µA)GIC 24.5 L O CA –1.2 IL ULL-S –1.4 VDD/VSS= +5V/0V 24.0 VDD/VSS= ±5V F –1.6 23.5 ––12..80 02929-012 23.0 02929-015 –40 –20 0 20 40 60 80 100 –40 –7 26 59 85 TEMPERATURE (°C) TEMPERATURE (°C) Figure 14. Full-Scale Error Figure 17. VLOGIC Supply Current vs. Temperature Rev. C | Page 8 of 28

AD5280/AD5282 1000 0 RAB = 20kΩ –6 80H TA = 25°C 40H –12 20H –18 VDD/VSS= 5V/0V 10H I (µA)LOGIC 100 VLOGIC= 5V GAIN (dB) –––323046 000842HHH –42 01H –48 VDD/VSS= 5V/0V TA = 25°C 10 VLOGIC= 3V 929-01602 ––5640 VVADD =/ V5S0Sm =V ±r5mVs 02929-019 0 1 2 3 4 5 0 10k 100k 1M VIH (V) FREQUENCY (Hz) Figure 18. VLOGIC Supply Current vs. Digital Input Voltage Figure 21. Gain vs. Frequency vs. Code, RAB = 20 kΩ 700 0 TA = 25°C 80H 600 –6 C) 40H m/° 500 –12 p 20H O (p 400 –18 C 10H EMP 300 dB) –24 08H DE T 200 2500kkΩΩ AIN ( –30 04H T MO 100 200kΩ G –36 02H TA –42 01H S O 0 E –48 RH TA = 25°C ––120000 9-0170292 ––5640 VVADD =/ V5S0Sm =V ±r5ms 02929-020 0 32 64 96 128 192 224 256 0 10k 100k 1M CODE (Decimal) FREQUENCY (Hz) Figure 19. Rheostat Mode Tempco ΔRWB/ΔT vs. Code, VDD/VSS = ±5 V Figure 22. Gain vs. Frequency vs. Code, RAB = 50 kΩ 120 0 C) TA = 25°C –6 80H m/° 100 40H pp –12 O ( 80 20H C –18 P 20kΩ EM 60 50kΩ –24 10H ODE T 40 200kΩ N (dB) –30 08H M AI 04H R G –36 E 20 MET –42 02H NTIO 0 –48 01H POTE ––2400 02929-018 ––5640 TVVAAD D ==/ V25S50S°mC =V ±r5mVs 02929-021 0 32 64 96 128 192 224 256 0 10k 100k 1M CODE (Decimal) FREQUENCY (Hz) Figure 20. Potentiometer Mode Tempco ΔVWB/ΔT vs. Code, Figure 23. Gain vs. Frequency vs. Code, RAB = 200 kΩ VDD/VSS = ±5 V Rev. C | Page 9 of 28

AD5280/AD5282 0 80 R = 20kΩ CODE = 80H, VA = VDD, VB = 0V –6 310kHz –12 60 –PSRR @ VDD/VSS = ±5V –18 R = 50kΩ DC ±10% p-pAC 150kHz B) –24 B) GAIN (d ––3306 R35 =k H2z00kΩ PSRR (d 40 –42 20 +PSRR @ VDD/VSS = ±5V DC ±10% p-pAC –48 TA = 25°C ––5640 VVDAD =/ V5S0Sm =V ±r5mVs 9-0220292 0 02929-025 0 10k 100k 1M 100 1000 10k 100k 1M FREQUENCY (Hz) FREQUENCY (MHz) Figure 24. −3 dB Bandwidth Figure 27. PSRR vs. Frequency DIV) TVAD D=/ V2S5S°C = ±5V A2 1.2V 852.0µs B/ d R = 20kΩ 1 0. S ( –6dB S E N T A R = 50kΩ L F N AI G D R = 200kΩ E Z LI A N MI NO 02929-023 2.04µs 02929-026 100 1k 10k 100k FREQUENCY (Hz) Figure 25. Normalized Gain Flatness vs. Frequency Figure 28. Midscale Glitch Energy Code 0x80 to 0x7F 500 T TA = 25°C VDD/VSS = ±5V 400 +5V A) 300 1 VW m (C CODE = 55H –5V GI O L 200 I CS 100 0 CODE = 55H 02929-024 2 02929-027 10k 100k 1M 10M CH1 5.00V CH2 5.00V M100ns A CH1 0V FREQUENCY (Hz) Figure 26. VLOGIC Supply Current vs. Frequency Figure 29. Large Signal Settling Time Rev. C | Page 10 of 28

AD5280/AD5282 40 A2 1.0V 33.41µs CODES SETTO MIDSCALE 3 LOTS SAMPLE SIZE = 135 30 Hz) M Y ( NC 20 E U Q E R F 10 1.50µs 02929-028 0 02929-030 5 5 4 5 3 5 2 5 1 5 0 5 1 5 2 –0. 0.4 –0. 0.3 –0. 0.2 –0. 0.1 –0. 0.0 0.0 0. 0.1 0. – – – – – LONG TERM CHANNEL-TO-CHANNEL RAB MATCH (%) Figure 30. Digital Feedthrough vs. Time Figure 32. Channel-to-Channel Resistance Matching (AD5282) 100 VA = VB = OPEN TA = 25°C A) 10 m (X A M B_ W L | 1.0 CA RAB = 20kΩ TI E OR RAB = 50kΩ HE 0.1 T RAB = 200kΩ 0.01 02929-029 0 32 64 96 128 192 224 256 CODE (Decimal) Figure 31. IWB_MAX vs. Code Rev. C | Page 11 of 28

AD5280/AD5282 TEST CIRCUITS Figure 33 to Figure 43 define the test conditions used in the product specification table. DUT V+ = VDD A DUT B A 1LSB = V+/2N 5V V+ W VIN W B VMS 02929-031 OFFGSNEDT OBIFAFSSET OP279 VOU02929-035T Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 37. Inverting Gain NO CONNECT 5V DUT IW OP279 VOUT A W VIN W B VMS 02929-032 OFFGSNEDT OBAIFAFSSDEUTT B 02929-036 Figure 34. Resistor Position Nonlinearity Error Figure 38. Noninverting Gain (Rheostat Operation; R-INL, R-DNL) IW = VDD/RNOMINAL A DUT +15V A VW W VMS2 W VIN DUT VOUT AD8610 B OFFSET VMS1RW = [VMS1–VMS2]/IW 02929-033 GND 2.5V B –15V 02929-037 Figure 35. Wiper Resistance Figure 39. Gain vs. Frequency VA VP+S R=R V (DdDB±)1 =0 %20 LOG( ΔΔ VV MD D S) DUT RSW = 0IS.W1V VDD A W PSS (%/%) =ΔΔVVMDDS%% W V+ B ISW 0.1V B VMS 02929-034 VSSTO VDD 02929-038 Figure 36. Power Supply Sensitivity (PSS, PSSR) Figure 40. Incremental On Resistance Rev. C | Page 12 of 28

AD5280/AD5282 NC NC = NO CONNECT A1 VDD A2 VDDUDT AW ICM VIN N/C RWD1AC1 RDAWC22 VOUT VSS GND NCB VCM 02929-039 CTA = B201 LOGV S[VSOUT/VIN]B2 02929-041 Figure 41. Common-Mode Leakage Current Figure 43. Analog Crosstalk (AD5282 Only) VLOGIC ILOGIC SCL SCA DIGITAL INPUT VOLTAGE 02929-040 Figure 42. VLOGIC Current vs. Digital Input Voltage Rev. C | Page 13 of 28

AD5280/AD5282 THEORY OF OPERATION The AD5280/AD5282 are single-channel and dual-channel, The general equation determining the digitally programmed 256-position, digitally controlled variable resistors (VRs). To output resistance between W and B is program the VR settings, see the Digital Interface section. Both D parts have an internal power-on preset that places the wiper at R (D)= ×R +R (1) WB 256 AB W midscale during power-on, which simplifies the fault condition where: recovery at power-up. Operation of the power-on preset function D is the decimal equivalent of the binary code loaded in the 8- also depends on the state of the V pin. L bit RDAC register. SWA AX RAB is the nominal end-to-end resistance. SHDN R is the wiper resistance contributed by the on resistance of W RS the internal switch. Note that in the zero-scale condition, a finite wiper resistance D7 RS 0xFF of 60 Ω is present. Care should be taken to limit the current D6 D5 flow between W and B in this state to a maximum pulse current D4 RS of no more than 20 mA. Otherwise, degradation or possible D3 D2 WX destruction of the internal switch contact can occur. D1 D0 As in the mechanical potentiometer, the resistance of the RDAC RDAC between Wiper W and Terminal A also produces a digitally LAATNCDH 0x01 SWB controlled complementary resistance, RWA. When these terminals DECODER 0x00 are used, the B terminal can be opened. Setting the resistance RS BX 502929-04 vdaelcuree afosers R aWs At hstea drtast aa tl oa amdeadx iimn uthme vlaatlcuhe ionfc rreesaissetas nince v aanlude . The Figure 44. AD5280/AD5282 Equivalent RDAC Circuit general equation for this operation is RHEOSTAT OPERATION 256−D R (D)= ×R +R (2) The nominal resistance of the RDAC between Terminal A and WA 256 AB W Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final The typical distribution of the nominal resistance, R , from AB two or three digits of the part number determine the nominal channel to channel matches within ±1%. Device-to-device resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, and matching is process lot dependent, and it is possible to have a 200 kΩ = 200. The nominal resistance (R ) of the VR has AB ±30% variation. Because the resistance element is processed in 256 contact points accessed by the wiper terminal, plus the B thin film technology, the change in R with temperature is very AB terminal contact. The eight-bit data in the RDAC latch is small (30 ppm/°C). decoded to select one of the 256 possible settings. Assuming POTENTIOMETER OPERATION that a 20 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 60 Ω wiper The digital potentiometer easily generates a voltage divider at contact resistance, such a connection yields a minimum of 60 Ω wiper to B and wiper to A to be proportional to the input voltage resistance between Terminal W and Terminal B. at A to B. Unlike the polarity of V – V , which must be DD SS positive, voltage across A to B, W to A, and W to B can be at The second connection is the first tap point that corresponds to either polarity, provided that V is powered by a negative supply. 138 Ω (R = R /256 + R = 78 Ω + 60 Ω) for data 0x01. The SS WB AB W third connection is the next tap point representing 216 Ω (78 × If the effect of the wiper resistance for approximation is ignored, 2 + 60) for data 0x02, and so on. Each LSB data value increase connecting the A terminal to 5 V and the B terminal to ground moves the wiper up the resistor ladder until the last tap point is produces an output voltage at the wiper to B starting at 0 V up reached at 19,982 Ω (R – 1 LSB + R ). Figure 46 shows a to 1 LSB less than 5 V. Each LSB of voltage is equal to the AB W simplified diagram of the equivalent RDAC circuit where the voltage applied across A to B divided by the 256 positions of the last resistor string is not accessed; therefore, there is 1 LSB less potentiometer divider. Because the AD5280/AD5282 can be of the nominal resistance at full scale in addition to the wiper supplied by dual supplies, the general equation defining the resistance. output voltage at V with respect to ground for any valid W Rev. C | Page 14 of 28

AD5280/AD5282 Operation of the digital potentiometer in divider mode results input voltage applied to Terminal A and Terminal B is in a more accurate operation over temperature. Unlike rheostat D 256−D V (D)= V + V (3) mode, the output voltage is dependent mainly on the ratio of W 256 A 256 B the internal resistors R and R and not on the absolute WA WB For a more accurate calculation that includes the effect of wiper values; therefore, the temperature drift reduces to 5 ppm/°C. resistance, V can be found as W R (D) R (D) V (D)= WB V + WA V (4) W R A R B AB AB 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W A/B RS SD O1 O2 X X X D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ACK. BY ACK. BY AD5280/5282 AD5280/AD5282 AD5280/5282 STMAARSTT EBRY SLAVEFARDADMREES 1S BYTE INSTRFURCATMIOEN 2 BYTE DFARTAAM BEY T3E SMTAOSPT EBRY 02929-043 Figure 45. Writing to the RDAC Register 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 A ACK. BY NOACK. BY STMAARSTT EBRY SLAVEFARDADMREES 1S BYTE AD5280/ADD5A28T2A BYTE FROMF RPARMEVEI O2USLY SELECTEDMASTSMETAROSPT EBRY 04402929- Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode Table 6. Serial Format of Data Accepted from the I2C Bus S 0 1 0 1 1 AD1 AD R/ A A/B RS S O1 O 2 X X X A D7 D6 D D D D D D A P 0 W D 5 4 3 2 1 0 Slave Address Byte Instruction Byte Data Byte where: Abbreviation Equals S Start condition P Stop condition A Acknowledge X Don’t care AD1, AD0 Package pin programmable address bits R/W Read enable at high and write enable at low A/B RDAC subaddress select; 0 = RDAC1 and 1 = RDAC2 RS Midscale reset, active high (only affects selected channel) SD Shutdown; same as SHDN pin operation except inverse logic (only affects selected channel) O, O Output logic pin latched values; default Logic 0 2 1 D7, D6, D5, D4, D3, D2, D1, D0 Data bits Rev. C | Page 15 of 28

AD5280/AD5282 DIGITAL INTERFACE 2-WIRE SERIAL BUS The AD5280/AD5282 are controlled via an I2C-compatible serial operation does not disturb the contents of the register. When bus. The RDACs are connected to this bus as slave devices. As brought out of shutdown, the previous setting is applied to shown in Figure 45, Figure 46, and Table 6, the first byte of the the RDAC. AD5280/AD5282 is a slave address byte. It has a 7-bit slave The following two bits are O and O. They are extra program- 1 2 address and an R/W bit. mable logic outputs that can be used to drive other digital loads, The 5 MSBs are 01011, and the two bits that follow are deter- logic gates, LED drivers, analog switches, and so on. The three mined by the state of the AD0 pin and the AD1 pin of the LSBs are don’t care bits (see Figure 45). device. AD0 and AD1 allow the user to place up to four of the After acknowledging the instruction byte, the last byte in write I2C-compatible devices on one bus. The 2-wire I2C serial bus mode is the data byte. Data is transmitted over the serial bus in protocol operates as follows. sequences of nine clock pulses (eight data bits followed by an The master initiates data transfer by establishing a start condi- acknowledge bit). The transitions on the SDA line must occur tion, which happens when a high-to-low transition on the SDA during the low period of SCL and remain stable during the high line occurs while SCL is high (see Figure 45). The following period of SCL (see Figure 45). byte is the slave address byte, which consists of the 7-bit slave In read mode, the data byte follows immediately after the address followed by an R/W bit (this bit determines whether acknowledgment of the slave address byte. Data is transmitted data is read from or written to the slave device). over the serial bus in sequences of nine clock pulses (a slight The slave whose address corresponds to the transmitted address difference from write mode, where there are eight data bits responds by pulling the SDA line low during the ninth clock followed by an acknowledge bit). Similarly, the transitions on pulse (this is called the acknowledge bit). At this stage, all other the SDA line must occur during the low period of SCL and devices on the bus remain idle while the selected device waits for remain stable during the high period of SCL (see Figure 46). data to be written to or read from its serial register. If the R/W bit When all data bits have been read or written, a stop condition is is high, the master reads from the slave device. On the other established by the master. A stop condition is defined as a low- hand, if the R/W bit is low, the master writes to the slave device. to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the tenth clock A write operation contains one instruction byte more than a pulse to establish a stop condition (see Figure 45). In read read operation. Such an instruction byte in write mode follows mode, the master issues a no acknowledge for the ninth clock the slave address byte. The most significant bit (MSB) of the pulse (that is, the SDA line remains high). The master then instruction byte labeled A/B is the RDAC subaddress select. A brings the SDA line low before the 10th clock pulse, which goes low selects RDAC1 and a high selects RDAC2 for the dual high to establish a stop condition (see Figure 46). channel AD5282. Set A/B low for the AD5280. A repeated write function gives the user flexibility to update the RS, the second MSB, is the midscale reset. A logic high on this RDAC output a number of times after addressing and instructing bit moves the wiper of a selected channel to the center tap the part only once. During the write cycle, each data byte updates where RWA = RWB. This feature effectively writes over the the RDAC output. For example, after the RDAC has acknow- contents of the register and thus, when taken out of reset mode, ledged its slave address and instruction bytes, the RDAC output the RDAC remains at midscale. updates after these two bytes. If another byte is written to the SD, the third MSB, is a shutdown bit. A logic high causes the RDAC while it is still addressed to a specific slave device with the selected channel to open circuit at Terminal A while shorting same instruction, this byte updates the output of the selected slave the wiper to Terminal B. This operation yields almost 0 Ω in device. If different instructions are needed, the write mode has to rheostat mode or 0 V in potentiometer mode. This SD bit serves start with a new slave address, instruction, and data byte again. the same function as the SHDN pin except that the SHDN pin Similarly, a repeated read function of RDAC is also allowed. reacts to active low. Also, the SHDN pin affects both channels (AD5282) as opposed to the SD bit, which affects only the channel that is being written to. Note that the shutdown Rev. C | Page 16 of 28

AD5280/AD5282 READBACK RDAC VALUE The AD5280/AD5282 allow the user to read back the RDAC In addition, shutdown can be implemented with the device values in read mode. However, for the dual-channel AD5282, digital output as shown in Figure 47. In this configuration, the the channel of interest is the one that is previously selected in device is shut down during power-up, but the user is allowed to the write mode. When users need to read the RDAC values of program the device at any preset levels. When it is done, the both channels in the AD5282, they can program the first user programs O high with the valid coding and the device 1 subaddress in write mode and then change to read mode to read exits from shutdown and responds to the new setting. This self- the first channel value. After that, they can change back to write contained shutdown function allows absolute shutdown during mode with the second subaddress and read the second channel power-up, which is crucial in hazardous environments, without value in read mode again. It is not necessary for users to issue adding extra components. Also, the sleep mode programming the Frame 3 data byte in write mode for subsequent readback feature during shutdown allows the AD5280/AD5282 to have a operation. Users should refer to Figure 45 and Figure 46 for the programmable preset at any level, a solution that can be as programming format. effective as using other high cost EEPROM devices. Because of the extra power drawn on R , note that a high value should be ADDITIONAL PROGRAMMABLE LOGIC OUTPUT PD chosen for the R . PD The AD5280/AD5282 feature additional programmable logic outputs, O1 and O2, which can be used to drive a digital load, O1 analog switches, and logic gates. O1 and O2 default to Logic 0. The SHDN logic states of O and O can be programmed in Frame 2 under RPD 1 2 write mode (see Figure 45). These logic outputs have adequate cUusrerresn cta dnr iavlisnog a ccatpivaabtieli Oty 1t oan sdin Ok/2s ionu trhcer eme iwllaiayms pweirtheso ouft load. SSDCAL 02929-046 affecting the wiper settings by programming as follows: Figure 47. Shutdown by Internal Logic Output • Perform start, slave address, acknowledge, and instruction MULTIPLE DEVICES ON ONE BUS bytes with O1 and O2 specified, acknowledge, stop. Figure 48 shows four AD5282 devices on the same serial bus. • Complete the write cycle with stop, then start, slave address Each has a different slave address because the states of their Pin byte, acknowledge, instruction byte with O1 and O2 AD0 and Pin AD1 are different. This allows each RDAC within specified, acknowledge, stop. each device to be written to or read from independently. The • Not complete the write cycle by not issuing the stop, then master device output bus line drivers are open-drain pull- start, slave address byte, acknowledge, instruction byte downs in a fully I2C-compatible interface. with O1 and O2 specified, acknowledge, stop. 5V RP RP SELF-CONTAINED SHUTDOWN FUNCTION AND SDA PROGRAMMABLE PRESET MASTER SCL 5V 5V 5V Shutdown can be activated by strobing the SHDN pin or SDA SCL SDA SCL SDA SCL SDA SCL programming the SD bit in the write mode instruction byte. AD1 AD1 AD1 AD1 AAsD s5h2o8w0n/A iDn 5F2ig8u2r oe p4e4n, wSWheAn t soh luettd tohwe nA i tse arsmseinrtaeld f,l othaet and AADD05282 AADD05282 AADD05282 AADD05282 02929-047 short the W terminal to the B terminal. The AD5280/AD5282 Figure 48. Multiple AD5282 Devices on One Bus consume negligible power during shutdown mode, resuming the previous setting once the SHDN pin is released. Rev. C | Page 17 of 28

AD5280/AD5282 LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE While most old systems can be operated at one voltage, a new VDD component can be optimized at another. When two systems operate the same signal at two different voltages, proper level +5V VIN Q3 0 0 shifting is needed. For instance, a 3.3 V EEPROM can interface Q1 with a 5 V digital potentiometer. A level-shift scheme is needed Q2 to enable a bidirectional communication so that the setting of 0 VOUT the digital potentiometer can be stored to and retrieved from R2 R3 10kΩ 10kΩ the EEPROM. Figure 49 shows one of the implementations. 0 MFD1V a3n0d1 MN 2if c VanDD b fea lalns yb eNlo-wch 2an.5n Ve.l signal FETs or low threshold VSS= –5V –5V 02929-050 Figure 51. Level Shift for Bipolar Potential Operation VDD1 = 3.3V VDD2= 5V RP RP G RP RP ESD PROTECTION S D SDA1 SDA2 All digital inputs are protected with a series input resistor and M1 G parallel Zener ESD structures, as shown in Figure 52. The S D SCL1 SCL2 protection applies to digital inputs SDA, SCL, and SHDN. M2 EE3P.3RVOM AD55V282 02929-048 340Ω LOGIC Figure 49. Level Shift for Different Potential Operation LOEPVEERLA STHIOIFNT FOR NEGATIVE VOLTAGE VSS 02929-051 Figure 52. ESD Protection of Digital Pins The digital potentiometer is popular in laser diode driver TERMINAL VOLTAGE OPERATING RANGE applications and certain telecommunications equipment level- setting applications. These applications are sometimes The AD5280/AD5282 positive VDD and negative VSS power operated between ground and a negative supply voltage such supply defines the boundary conditions for proper 3-terminal that the systems can be biased at ground to avoid large bypass digital potentiometer operation. Supply signals present on capacitors that may significantly impede the ac performance. Resistor Terminal A, Resistor Terminal B, and Wiper Terminal Like most digital potentiometers, the AD5280/AD5282 can be W that exceed VDD or VSS are clamped by the internal forward- configured with a negative supply (see Figure 50). biased diodes (see Figure 53). VDD VDD A W B –5V VGSNSD VSS 02929-053 LLEEVVEELL SSHHIIFFTTEEDD SSDCAL 02929-049 Figure 53. Maximum Terminal Voltages Set by VDD and VSS Figure 50. Biased at Negative Voltage POWER-UP SEQUENCE However, the digital inputs must also be level shifted to allow Because there are ESD protection diodes that limit the voltage proper operation because the ground is referenced to the compliance at Terminal A, Terminal B, and Terminal W (see negative potential. Figure 51 shows one implementation with a Figure 53), it is important to power V /V before applying any DD SS few transistors and a few resistors. When V is below the Q3 IN voltage to the A, B, and W terminals. Otherwise, the diode is threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state, forward biased such that V /V is unintentionally powered, DD SS V approaches 0 V. When V is above 2 V, Q3 is on, Q1 is on, OUT IN which may affect the rest of the user’s circuit. The ideal power- and Q2 is turned off. In this state, V is pulled down to V . OUT SS up sequence is the following: GND, V , V , digital inputs, and DD SS Be aware that proper time shifting is also needed for successful V /V /V . The order of powering V /V /V and digital inputs A B W A B W communication with the device. is not important as long as they are powered after V /V . DD SS Rev. C | Page 18 of 28

AD5280/AD5282 LAYOUT AND POWER SUPPLY BYPASSING VDD VDD It is a good practice to design a layout with compact, minimum C3 + C1 10µF 0.1µF AD5280/ lead lengths. The leads to the input should be as direct as possible AD5282 with a minimum conductor length. Ground paths should have C4 + C2 10µF 0.1µF low resistance and low inductance. VSS VSS GND Swiimthi lqarulayl, iitty i cs aaplsaoc iato gros ofodr p orpatcitmicue mto sbtaybpialsitsy t. hSeu pppolwy elre asdusp ptoli es 02929-054 Figure 54. Power Supply Bypassing the device should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and filter low frequency ripple (see Figure 54). Notice that the digital ground should also be joined remotely to the analog ground at one point to minimize digital ground bounce. Rev. C | Page 19 of 28

AD5280/AD5282 APPLICATIONS INFORMATION BIPOLAR DC OR AC OPERATION FROM DUAL Depending on the op amp GBP, reducing the feedback resistor SUPPLIES may extend the zero’s frequency far enough to overcome the problem. A better approach is to include a compensation The AD5280/AD5282 can be operated from dual supplies capacitor C2 to cancel the effect caused by C1. Optimum enabling control of ground-referenced ac signals or bipolar compensation occurs when R1 × C1 = R2 × C2. This is not operation. The ac signal, as high as V /V , can be applied DD SS an option unless C2 is scaled as if R2 were at its maximum directly across Terminal A to Terminal B with the output taken value. Doing so may overcompensate and compromise the from Terminal W. See Figure 55 for a typical circuit connection. performance slightly when R2 is set at low values. However, it +5.0V avoids the gain peaking, ringing, or oscillation at the worst case. For critical applications, C2 should be found empirically to suit VDD SCLK SCL A1 the need. In general, C2 in the range of a few picofarads (pF) to MICROCONTROLLER no more than a few tenths of a picofarad is usually adequate for MOSI SDA W1 ±2.5V p-p ±5V p-p GND B1 the compensation. AD5282 D–80H Similarly, there are W and A terminal capacitances connected to GND A2 the output (not shown); fortunately, their effect at this node is less significant and the compensation can be avoided in most cases. W2 B2 15 V, 8-BIT I2C DAC VSS Figure 55. Bipolar Operation from Dual Supplies –5.0V 02929-055 RBIASVDD VDD GAIN CONTROL COMPENSATION U1A U2 V+ AD5280 The digital potentiometer is commonly used in gain control D1 AD8512 ADR512 V– 200kΩ U1B applications such as the noninverting gain amplifier shown in Figure 56. B AD8512 VO 200kΩ A B R2 W R1 4.C72pF 02929-057 Figure 57. 8-Bit I2C DAC 47kΩ R1 C1 25pF U1 VO AD5280/AD5282 can be configured as a high voltage DAC, as Figure 56. TypicVaIl Noninverting Gain Amplif02929-056ie r high Vas 1(D5 )V.= ThDe o[u1t.p2uVt ×is (1+ R2)] (5) O 256 R 1 Notice that the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node. It introduces a 0 for the 1/β term with 20 dB/decade (dec), whereas a typical op O amp GBP has −20 dB/dec characteristics. A large R2 and finite C1 can cause the 0 frequency to fall well below the crossover frequency. Thus the rate of closure becomes 40 dB/dec, and the system has a 0° phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input. Rev. C | Page 20 of 28

AD5280/AD5282 8-BIT BIPOLAR DAC +15V As in the previous example, in the simpler and more common case where K = 1, a single digital AD5280 potentiometer is + V1 U2 OP2177 VO used. U1 is replaced by a matched pair of resistors to apply U1 W – A2 Vi and −Vi at the ends of the digital potentiometer. The VIN B A relationship becomes VOUT R R –15V V =⎜⎛1+ R2⎟⎞⎜⎛2D2−1⎟⎞×V (7) TRIM +5VREF +15V –5VREF O ⎝ R1⎠⎝ 256 ⎠ i GND ADR425 – If R2 is large, a compensation capacitor having a few pF may be OP2177 needed to avoid any gain peaking. + A1–15V U2–AD5280 02929-058 Tuanbitlye g7a sihno, wa sg athine oref s2u, lat nodf aad gjuaisnti nogf 1D0,. wTihteh rAes2u clto nisf iag buirpeodl aars a Figure 58. 8-Bit Bipolar DAC amplifier with linearly programmable gain and a 256-step resolution. Figure 58 shows a low cost, 8-bit, bipolar DAC. It offers the same number of adjustable steps but not the precision of conventional Table 7. Result of Bipolar Gain Amplifier DACs. The linearity and temperature coefficients, especially at D R1 = ∞, R2 = 0 R1 = R2 R2 = 9R1 low value codes, are skewed by the effects of the digital potenti- 0 −1 −2 −10 ometer wiper resistance. The output of this circuit is 64 −0.5 −1 −5 ⎛2D ⎞ 128 0 0 0 V =⎜ −1⎟×V (6) O ⎝256 ⎠ REF 192 0.5 1 5 255 0.968 1.937 9.680 BIPOLAR PROGRAMMABLE GAIN AMPLIFIER VDD PROGRAMMABLE VOLTAGE SOURCE WITH + BOOSTED OUTPUT ADU52282A2 WB22 –OP2VV1+–77 VO For applications that require high current adjustments, such as a C1 R2 laser diode driver or tunable laser, a boosted voltage source can A1 B1 A2 VS8A2 be considered (see Figure 60). V1 W1 VDD –kVI R1 U1 + V+ V5VI VO AD5282 OP2177 N1 RBIAS A1– V–VS8 02929-059 U1 AB W + A1 V+ SIGNAL LCDC IL Figure 59. Bipolar Programmable Gain Amplifier – V– Fimorp laepmpleincatatitoionns sthimati lraerq tuoi rteh eb ipproelvairo guasi nci,r Fciugiut.r Te h5e9 dshigoiwtasl one AUN111 === AAFDDDV58253800011,NA, D2N8670050,2AD8541 02929-060 potentiometer, U1, sets the adjustment range. The wiper voltage Figure 60. Programmable Booster Voltage Source at W can therefore be programmed between V and –KV at a 2 i i In this circuit, the inverting input of the op amp forces the given U setting. Configuring A in noninverting mode allows 2 2 V to be equal to the wiper voltage set by the digital potenti- BIAS linear gain and attenuation. The transfer function is ometer. The load current is then delivered by the supply via the VO =⎛⎜1+ R2⎞⎟×⎛⎜ D2 ×(1+K)−K⎞⎟ (7) N-channel FET N1. The N1 power handling must be adequate V ⎝ R1⎠ ⎝256 ⎠ to dissipate (Vi – VO) × IL power. This circuit can source a i maximum of 100 mA with a 5 V supply. A1 needs to be a rail- where K is the ratio of R /R set by U. WB1 WA1 1 to-rail input type. For precision applications, a voltage reference such as ADR423, ADR292, or AD1584 can be applied at the input of the digital potentiometer. Rev. C | Page 21 of 28

AD5280/AD5282 PROGRAMMABLE CURRENT SOURCE PROGRAMMABLE BIDIRECTIONAL CURRENT +5V SOURCE R1I R2I 2 U1 150kΩ 15kΩ VIN 0TO (2.048 + VL) 3 SLEEP VOUT 6 B C1 +15V REF191 C1 10pF GND 1µF W 4 A 1R0S2Ω OPV2+177 AD5280 V++5V A+5V +15V V– A2 R502kBΩ OOPP88551100 AD5280 V+ –15V –2.048VTO VL V– UU22 VL W OPV2–177 R1 R2A RL VL Figure 61. Programm5aVble Curre1n0t0R ΩSLource IL 02929-061 –5V –15V A1 150kΩ 14.95kΩ 500kΩ |L 02929-062 Figure 62. Programmable Bidirectional Current Source A programmable current source can be implemented with the For applications that require bidirectional current control or circuit shown in Figure 61. REF191 is a unique, low supply higher voltage compliance, a Howland current pump can be a headroom and high current handling precision reference that solution (see Figure 62). If the resistors are matched, the load can deliver 20 mA at 2.048 V. The load current is simply the current is voltage across Terminal B to Terminal W of the digital potentiometer divided by R. (R2 +R2 ) S A B V ×D I = R1 ×V (9) IL = RREF×2N (8) L R2B W S In theory, R2 can be made as small as needed to achieve the The circuit is simple, but attention must be paid to two things. B current needed within the A output current driving capability. First, dual-supply op amps are ideal because the ground 2 In this circuit, the OP2177 can deliver ±5 mA in either direction, potential of REF191 can swing from −2.048 V at zero scale to V L and the voltage compliance approaches 15 V. It can be shown at full scale of the potentiometer setting. Although the circuit that the output impedance is works under single supply, the programmable resolution of the R1'×R2 (R1+R2 ) system is reduced. Z = B A (10) O R1×R2'−R1'(R2 +R2 ) For applications that demand higher current capabilities, a A B few changes to the circuit in Figure 61 produce an adjustable This output impedance can be infinite if Resistor R1' and current in the range of hundreds of milliamps. First, the voltage Resistor R2' match precisely with R1 and R2A + R2B, reference needs to be replaced with a high current, low dropout respectively. On the other hand, it can be negative if the regulator, such as the ADP3333, and the op amp needs to be resistors are not matched. As a result, C1 must be in the range swapped with a high current dual-supply model, such as the of 1 pF to 10 pF to prevent the oscillation. AD8532. Depending on the desired range of current, an appropriate value for R must be calculated. Because of the high S current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp beyond the positive rail. Rev. C | Page 22 of 28

AD5280/AD5282 PROGRAMMABLE LOW-PASS FILTER In analog-to-digital conversion applications, it is common to At resonance, setting the following balances the bridge: include an antialiasing filter to band-limit the sampling signal. R2 =2 (16) Dual-channel digital potentiometers can be used to construct R1 a second-order Sallen key low-pass filter (see Figure 63). The In practice, R2/R1 should be set slightly larger than 2 to ensure design equations are that oscillation can start. On the other hand, the alternate turn- V ω 2 O = O (11) on of Diode D1 and Diode D2 ensures that R2/R1 are smaller ω Vi S2+ OS+ω 2 than 2 momentarily and, therefore, stabilizes the oscillation. Q O Once the frequency is set, the oscillation amplitude can be 1 tuned by R2 because ω = (12) B O R1R2C1C2 2 V =I R2 +V (17) 1 1 3 O D B D Q= + (13) R1C1 R2C2 V , I , and V are interdependent variables. With proper O D D Users can first select some convenient values for the capacitors. selection of R2B, an equilibrium is reached such that VO To achieve maximally flat bandwidth where Q = 0.707, let C1 be converges. R2B can be in series with a discrete resistor to twice the size of C2 and let R1 = R2. As a result, R1 and R2 can be increase the amplitude, but the total resistance cannot be adjusted to the same settings to achieve the desirable bandwidth. too large to prevent saturation of the output. C1 FREQUENCY ADJUSTMENT CI RI C VP 2.2nF 10kΩ B A B +2.5V R1 R2 C R W VI A B A B V+ 2.2nF 10kΩA W +2.5V W W AD8601 VO V+ U1 R R V– OP1177 VO C2 C –2.5V U1 R1 = R1I = R2B =AD5282 V– D1 = D2 = 1N4148 SAADFMJigUEu SSrTEeET 6DT3ITN. OSGallen Key Low-Pass Filter 02929-063 VN –R22.B5V2R.12kAΩ D1 10kΩ PROGRAMMABLE OSCILLATOR R1 B A D2 1kΩ W In a classic Wien-bridge oscillator (Figure 64), the Wien nanetdw Ro2rk p (rRov, iRd'e, Cne, gCa')ti pvero fveieddebsa pcko.s iAtitv teh fee eredsboancakn, tw fhreilqeu Re1n c y, f , AAMDJPULSITTUMDEENT 02929-064 O Figure 64. Programmable Oscillator with Amplitude Control the overall phase shift is 0, and the positive feedback causes the circuit to oscillate. With R = R', C = C', and R2 = R2 //(R2 + A B Rdiode), the oscillation frequency is ω = 1 or f = 1 (14) O RC o 2πRC where R is equal to R such that WA 256−D R= R (15) 256 AB Rev. C | Page 23 of 28

AD5280/AD5282 RDAC CIRCUIT SIMULATION MODEL MACRO MODEL NET LIST FOR RDAC The internal parasitic capacitances and the external capacitive .PARAM D=256, RDAC=20E3 loads dominate the ac characteristics of the RDACs. Configured * as a potentiometer divider, the −3 dB bandwidth of the AD5280 .SUBCKT DPOT (A,W,B) (20 kΩ resistor) measures 310 kHz at half scale. Figure 24 * CA A 0 25E-12 provides the Bode plot characteristics of the three available RWA A W {(1-D/256)*RDAC+60} resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic CW W 0 55E-12 simulation model is shown in Figure 65. A macro model net list RWB W B {D/256*RDAC+60} for the 20 kΩ RDAC is provided. CB B 0 25E-12 RDAC * 20kΩ A B .ENDS DPOT CA CA 25pF 25pF 8C5pWF 02929-068 Figure 65. RDAC Circuit Simulation Model for RDAC = 20 kΩ Rev. C | Page 24 of 28

AD5280/AD5282 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.2A0X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 66. 14-Lead Thin Shrink Small Outline Package (TSSOP) (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SEATING 0° 0.45 PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 67. 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) Dimensions shown in millimeters Rev. C | Page 25 of 28

AD5280/AD5282 ORDERING GUIDE No. of Temperature Package Model1 Channels R (kΩ) Range Package Description Option Ordering Quantity AB AD5280BRU20 1 20 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5280BRU20-REEL7 1 20 −40°C to +85°C 14-Lead TSSOP RU-14 1,000 AD5280BRU50 1 50 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5280BRU50-REEL7 1 50 −40°C to +85°C 14-Lead TSSOP RU-14 1,000 AD5280BRU200-REEL7 1 200 −40°C to +85°C 14-Lead TSSOP RU-14 1,000 AD5280BRUZ202 1 20 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5280BRUZ20-REEL72 1 20 −40°C to +85°C 14-Lead TSSOP RU-14 1,000 AD5280BRUZ502 1 50 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5280BRUZ50-REEL72 1 50 −40°C to +85°C 14-Lead TSSOP RU-14 1,000 AD5280BRUZ2002 1 200 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5280BRUZ200-R72 1 200 −40°C to +85°C 14-Lead TSSOP RU-14 1,000 AD5282BRU20 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5282BRU20-REEL7 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 AD5282BRU50 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5282BRU50-REEL7 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 AD5282BRU200 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5282BRU200-REEL7 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 AD5282BRUZ202 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5282BRUZ20-REEL72 2 20 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 AD5282BRUZ502 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5282BRUZ50-REEL72 2 50 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 AD5282BRUZ2002 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5282BRUZ200-R72 2 200 −40°C to +85°C 16-Lead TSSOP RU-16 1,000 AD5282-EVAL 2 20 Evaluation Board 1 Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and Line 3 contains date code YYWW. 2 Z = RoHS Compliant Part. Rev. C | Page 26 of 28

AD5280/AD5282 NOTES Rev. C | Page 27 of 28

AD5280/AD5282 NOTES ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02929-0-7/09(C) Rev. C | Page 28 of 28