1024-/256-Position, 1% Resistor Tolerance Error, I2C Interface and 50-TP Memory Digital Rheostat Data Sheet AD5272/AD5274 FEATURES FUNCTIONAL BLOCK DIAGRAM Single-channel, 1024-/256-position resolution VDD 20 kΩ, 50 kΩ, 100 kΩ nominal resistance Maximum ±1% nominal resistor tolerance error POWER-ON 50-times programmable (50-TP) wiper memory RESET AD5272/AD5274 Rheostat mode temperature coefficient: 5 ppm/°C 2.7 V to 5.5 V single-supply operation ±2.5 V to ±2.75 V dual-supply operation for ac or bipolar RDAC SCL REGISTER operations I2C 10/8 A I2C-compatible interface SDA SERIAL INTERFACE W Wiper setting readback ADDR 50-TP Power on refreshed from 50-TP memory MEMORY BLOCK Thin LFCSP 10-lead, 3 mm × 3 mm × 0.8 mm package RESET Compact MSOP, 10-lead 3 mm × 4.9 mm × 1.1 mm package APPLICATIONS VSS FigurEeX 1T._ CAP GND 08076-001 Mechanical rheostat replacements Op-amp: variable gain control Instrumentation: gain, offset adjustment Programmable voltage to current conversions Programmable filters, delays, time constants Programmable power supply Sensor calibration GENERAL DESCRIPTION The AD5272/AD52741 are single-channel, 1024-/256-position The AD5272/AD5274 device wiper settings are controllable digital rheostats that combine industry leading variable resistor through the I2C-compatible digital interface. Unlimited performance with nonvolatile memory (NVM) in a compact adjustments are allowed before programming the resistance package. value into the 50-TP memory. The AD5272/AD5274 do not require any external voltage supply to facilitate fuse blow and The AD5272/AD5274 ensure less than 1% end-to-end resistor there are 50 opportunities for permanent programming. During tolerance error and offer 50-times programmable (50-TP) memory. 50-TP activation, a permanent blow fuse command freezes the The guaranteed industry leading low resistor tolerance error wiper position (analogous to placing epoxy on a mechanical feature simplifies open-loop applications as well as precision trimmer). calibration and tolerance matching applications. The AD5272/AD5274 are available in a 3 mm × 3 mm 10-lead LFCSP package and in a 10-lead MSOP package. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. 1 Protected by U.S. Patent Number 7688240. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5272/AD5274 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Shift Register ............................................................................... 18 Applications ....................................................................................... 1 Write Operation.......................................................................... 19 Functional Block Diagram .............................................................. 1 Read Operation........................................................................... 20 General Description ......................................................................... 1 RDAC Register ............................................................................ 21 Revision History ............................................................................... 2 50-TP Memory Block ................................................................ 21 Specifications ..................................................................................... 3 Write Protection ......................................................................... 21 Electrical Characteristics—AD5272 .......................................... 3 50-TP Memory Write-Acknowledge Polling .......................... 23 Electrical Characteristics—AD5274 .......................................... 5 Reset ............................................................................................. 23 Interface Timing Specifications .................................................. 7 Resistor Performance Mode ...................................................... 23 Absolute Maximum Ratings ............................................................ 9 Shutdown Mode ......................................................................... 23 Thermal Resistance ...................................................................... 9 RDAC Architecture .................................................................... 23 ESD Caution .................................................................................. 9 Programming the Variable Resistor ......................................... 23 Pin Configuration and Function Descriptions ........................... 10 EXT_CAP Capacitor .................................................................. 24 Typical Performance Characteristics ........................................... 11 Terminal Voltage Operating Range ......................................... 24 Test Circuits ..................................................................................... 17 Power-Up Sequence ................................................................... 24 Theory of Operation ...................................................................... 18 Outline Dimensions ....................................................................... 25 Serial Data Interface ................................................................... 18 Ordering Guide .......................................................................... 25 REVISION HISTORY 3/13—Rev. C to Rev. D 3/10—Rev. 0 to Rev. A Changed Resistor Noise Density, R = 20 kΩ from 50 nV/√Hz Changes to Product Title and General Description Section ....... 1 AW to 13 nV/√Hz; Table 1 ...................................................................... 4 Changes to Theory of Operation Section.................................... 15 Changed Resistor Noise Density, R = 20 kΩ from 50 nV/√Hz AW to 13 nV/√Hz; Table 4 ...................................................................... 6 10/09—Revision 0: Initial Version Updated Outline Dimensions ....................................................... 25 11/10—Rev. B to Rev. C Changes to Figure 24 ...................................................................... 14 5/10—Rev. A to Rev. B Added LFCSP Package .................................................. Throughout Changed OTP to 50-TP ................................................ Throughout Changes to Features Section and Applications Section ............... 1 Added Endnote 1 .............................................................................. 1 Changes to Table 1 ............................................................................ 3 Added Table 3 .................................................................................... 4 Changes to Table 4 ............................................................................ 5 Added Table 6 .................................................................................... 6 Changes to Table 8 and Table 9 ....................................................... 9 Added Figure 5 ................................................................................ 10 Added Exposed Pad Note to Table 10 .......................................... 10 Changes to Typical Performance Characteristics ....................... 11 Changes to Resistor Performance Mode Section ....................... 23 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 Rev. D | Page 2 of 28

Data Sheet AD5272/AD5274 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5272 V = 2.7 V to 5.5 V, V = 0 V; V = 2.5 V to 2.75 V, V = −2.5 V to −2.75 V; −40°C < T < +125°C, unless otherwise noted. DD SS DD SS A Table 1. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resolution 10 Bits Resistor Integral Nonlinearity2, 3 R-INL R = 20 kΩ, |V − V | = 3.0 V to 5.5 V −1 +1 LSB AW DD SS R = 20 kΩ, |V − V | = 2.7 V to 3.0 V −1 +1.5 LSB AW DD SS R = 50 kΩ, 100 kΩ −1 +1 LSB AW Resistor Differential Nonlinearity2 R-DNL −1 +1 LSB Nominal Resistor Tolerance R-Perf Mode4 See Table 2 and Table 3 −1 ±0.5 +1 % Normal Mode ±15 % Resistance Temperature Coefficient5, 6 Code = full scale 5 ppm/°C Wiper Resistance Code = zero scale 35 70 Ω RESISTOR TERMINALS Terminal Voltage Range5, 7 V V V SS DD Capacitance5 A f = 1 MHz, measured to GND, code = half scale 90 pF Capacitance5 W f = 1 MHz, measured to GND, code = half scale 40 pF Common-Mode Leakage Current5 V = V 50 nA A W DIGITAL INPUTS Input Logic5 High V 2.0 V INH Low V 0.8 V INL Input Current I ±1 µA IN Input Capacitance5 C 5 pF IN DIGITAL OUTPUT Output Voltage5 High V R = 2.2 kΩ to V V − 0.1 V OH PULL_UP DD DD Low V R = 2.2 kΩ to V OL PULL_UP DD V = 2.7 V to 5.5 V, V = 0 V 0.4 V DD SS V = 2.5 V to 2.75 V, V = −2.5 V to −2.75 V 0.6 V DD SS Tristate Leakage Current −1 +1 µA Output Capacitance5 5 pF POWER SUPPLIES Single-Supply Power Range V = 0 V 2.7 5.5 V SS Dual-Supply Power Range ±2.5 ±2.75 V Supply Current Positive I 1 µA DD Negative I −1 µA SS 50-TP Store Current5, 8 Positive I 4 mA DD_OTP_STORE Negative I −4 mA SS_OTP_STORE 50-TP Read Current5, 9 Positive I 500 µA DD_OTP_READ Negative I −500 µA SS_OTP_READ Power Dissipation10 V = V or V = GND 5.5 µW IH DD IL Rev. D | Page 3 of 28

AD5272/AD5274 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit Power Supply Rejection Ratio5 PSRR ΔV /ΔV = ±5 V ± 10% dB DD SS R = 20 kΩ −66 −55 AW R = 50 kΩ −75 −67 AW R = 100 kΩ −78 −70 AW DYNAMIC CHARACTERISTICS5, 11 Bandwidth −3 dB, R = 10 kΩ, Terminal W, see Figure 41 kHz AW R = 20 kΩ 300 AW R = 50 kΩ 120 AW R = 100 kΩ 60 AW Total Harmonic Distortion V = 1 V rms, f = 1 kHz, code = half scale dB A R = 20 kΩ −90 AW R = 50 kΩ −88 AW R = 100 kΩ −85 AW Resistor Noise Density Code = half scale, T = 25°C, f = 10 kHz nV/√Hz A R = 20 kΩ 13 AW R = 50 kΩ 25 AW R = 100 kΩ 32 AW 1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 24 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. 9 Different from operating current, the supply current for the fuse read lasts approximately 500 ns. 10 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 11 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. Table 2. AD5272 Resistor Performance Mode Code Range Resistor Tolerance Per Code |V − V | = 4.5 V to 5.5 V |V − V | = 2.7 V to 4.5 V DD SS DD SS R-TOLERANCE 1% R-Tolerance From 0x078 to 0x3FF From 0x0BE to 0x3FF 2% R-Tolerance From 0x037 to 0x3FF From 0x055 to 0x3FF 3% R-Tolerance From 0x028 to 0x3FF From 0x037 to 0x3FF Table 3. AD5272 50 kΩ and 100 kΩ Resistor Performance Mode Code Range Resistor Tolerance Per Code R = 50 kΩ R = 100 kΩ AW AW R-TOLERANCE 1% R-Tolerance From 0x078 to 0x3FF From 0x04B to 0x3FF 2% R-Tolerance From 0x055 to 0x3FF From 0x032 to 0x3FF 3% R-Tolerance From 0x032 to 0x3FF From 0x019 to 0x3FF Rev. D | Page 4 of 28

Data Sheet AD5272/AD5274 ELECTRICAL CHARACTERISTICS—AD5274 VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted. Table 4. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS— RHEOSTAT MODE Resolution 8 Bits Resistor Integral Nonlinearity2, 3 R-INL −1 +1 LSB Resistor Differential R-DNL −1 +1 LSB Nonlinearity2 Nominal Resistor Tolerance R-Perf Mode4 See Table 5 and Table 6 −1 ±0.5 +1 % Normal Mode ±15 % Resistance Temperature Code = full scale 5 ppm/°C Coefficient5, 6 Wiper Resistance Code = zero scale 35 70 Ω RESISTOR TERMINALS Terminal Voltage Range5, 7 V V V SS DD Capacitance5 A f = 1 MHz, measured to GND, code = half scale 90 pF Capacitance5 W f = 1 MHz, measured to GND, code = half scale 40 pF Common-Mode Leakage V = V 50 nA A W Current5 DIGITAL INPUTS Input Logic5 High V 2.0 V INH Low V 0.8 V INL Input Current I ±1 µA IN Input Capacitance5 C 5 pF IN DIGITAL OUTPUT Output Voltage5 High V R = 2.2 kΩ to V V − 0.1 V OH PULL_UP DD DD Low V R = 2.2 kΩ to V OL PULL_UP DD V = 2.7 V to 5.5 V, V = 0 V 0.4 V DD SS V = 2.5 V to 2.75 V, V = −2.5 V to −2.75 V 0.6 V DD SS Tristate Leakage Current −1 +1 µA Output Capacitance5 5 pF POWER SUPPLIES Single-Supply Power Range V = 0 V 2.7 5.5 V SS Dual-Supply Power Range ±2.5 ±2.75 V Supply Current Positive I 1 µA DD Negative I −1 µA SS OTP Store Current5, 8 Positive I 4 mA DD_OTP_STORE Negative I −4 mA SS_OTP_STORE OTP Read Current5, 9 Positive I 500 µA DD_OTP_READ Negative I −500 µA SS_OTP_READ Power Dissipation10 V = V or V = GND 5.5 µW IH DD IL Power Supply Rejection Ratio5 PSRR ΔV /ΔV = ±5 V ± 10% dB DD SS R = 20 kΩ −66 −55 AW R = 50 kΩ −75 −67 AW R = 100 kΩ −78 −70 AW Rev. D | Page 5 of 28

AD5272/AD5274 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS5, 11 Bandwidth −3 dB, R = 10 kΩ, Terminal W, see Figure 41 kHz AW R = 20 kΩ 300 AW R = 50 kΩ 120 AW R = 100 kΩ 60 AW Total Harmonic Distortion V = 1 V rms, f = 1 kHz, code = half scale dB A R = 20 kΩ −90 AW R = 50 kΩ −88 AW R = 100 kΩ −85 AW Resistor Noise Density Code = half scale, T = 25°C, f = 10 kHz nV/√Hz A R = 20 kΩ 13 AW R = 50 kΩ 25 AW R = 100 kΩ 32 AW 1 Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. 3 The maximum current in each code is defined by IAW = (VDD − 1)/RAW. 4 The terms, resistor performance mode and R-Perf mode, are used interchangeably. See the Resistor Performance Mode section. 5 Guaranteed by design and not subject to production test. 6 See Figure 24 for more details. 7 Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 8 Different from operating current, the supply current for the fuse program lasts approximately 55 ms. 9 Different from operating current, the supply current for the fuse read lasts approximately 500 ns. 10 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 11 All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V. Table 5. AD5274 Resistor Performance Mode Code Range Resistor Tolerance per Code |V − V | = 4.5 V to 5.5 V |V − V | = 2.7 V to 4.5 V DD SS DD SS R-TOLERANCE 1% R-Tolerance From 0x1E to 0xFF From 0x32 to 0xFF 2% R-Tolerance From 0x0F to 0xFF From 0x19 to 0xFF 3% R-Tolerance From 0x06 to 0xFF From 0x0E to 0xFF Table 6. AD5274 50 kΩ and 100 kΩ Resistor Performance Mode Code Range Resistor Tolerance per Code R = 50 kΩ R = 100 kΩ AW AW R-TOLERANCE 1% R-Tolerance From 0x1E to 0xFF From 0x14 to 0xFF 2% R-Tolerance From 0x14 to 0xFF From 0x0F to 0xFF 3% R-Tolerance From 0x0A to 0xFF From 0x0A to 0xFF Rev. D | Page 6 of 28

Data Sheet AD5272/AD5274 INTERFACE TIMING SPECIFICATIONS V = 2.5 V to 5.5 V; all specifications T to T , unless otherwise noted. DD MIN MAX Table 7. Limit at T , T MIN MAX Parameter Conditions1 Min Max Unit Description f 2 Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz Serial clock frequency t Standard mode 4 µs t , SCL high time 1 HIGH Fast mode 0.6 µs t , SCL high time HIGH t Standard mode 4.7 µs t , SCL low time 2 LOW Fast mode 1.3 µs t , SCL low time LOW t Standard mode 250 ns t , data setup time 3 SU;DAT Fast mode 100 ns t , data setup time SU;DAT t Standard mode 0 3.45 µs t , data hold time 4 HD;DAT Fast mode 0 0.9 µs t , data hold time HD;DAT t Standard mode 4.7 µs t , set-up time for a repeated start condition 5 SU;STA Fast mode 0.6 µs t , set-up time for a repeated start condition SU;STA t Standard mode 4 µs t , hold time (repeated) start condition 6 HD;STA Fast mode 0.6 µs t , hold time (repeated) start condition HD;STA High speed mode 160 ns t , hold time (repeated) start condition HD;STA t Standard mode 4.7 µs t , bus free time between a stop and a start condition 7 BUF Fast mode 1.3 µs t , bus free time between a stop and a start condition BUF t Standard mode 4 µs t , setup time for a stop condition 8 SU;STO Fast mode 0.6 µs t , setup time for a stop condition SU;STO t Standard mode 1000 ns t , rise time of SDA signal 9 RDA Fast mode 300 ns t , rise time of SDA signal RDA t Standard mode 300 ns t , fall time of SDA signal 10 FDA Fast mode 300 ns t , fall time of SDA signal FDA t Standard mode 1000 ns t , rise time of SCL signal 11 RCL Fast mode 300 ns t , rise time of SCL signal RCL t Standard mode 1000 ns t , rise time of SCL signal after a repeated start condition and 11A RCL1 after an acknowledge bit Fast mode 300 ns t , rise time of SCL signal after a repeated start condition and RCL1 after an acknowledge bit t Standard mode 300 ns t , fall time of SCL signal 12 FCL Fast mode 300 ns t , fall time of SCL signal FCL t13 RESET pulse time 20 ns Minimum RESET low time t 3 Fast mode 0 50 ns Pulse width of spike suppressed SP t 4, 5 500 ns Command execute time EXEC t 2 µs RDAC register write command execute time (R-Perf mode) RDAC_R-PERF t 600 ns RDAC register write command execute time (normal mode) RDAC_NORMAL t 6 µs Memory readback execute time MEMORY_READ t 350 ms Memory program time MEMORY_PROGRAM t 600 µs Reset 50-TP restore time RESET t 6 2 ms Power-on 50-TP restore time POWER-UP 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode. 4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations. 5 Refer to tMEMORY_READ and tMEMORY_PROGRAM for memory commands operations. 6 Maximum time after VDD − VSS is equal to 2.5 V. Rev. D | Page 7 of 28

AD5272/AD5274 Data Sheet Shift Register and Timing Diagrams DB9 (MSB) DB0 (LSB) 0 0 C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS DATA BITS 08076-003 Figure 2. Shift Register Content t11 t12 t6 t8 t2 SCL t6 t1 t5 t4 t3 t10 t9 SDA t7 P S S P t13 RESET 08076-002 Figure 3. 2-Wire Serial Interface Timing Diagram Rev. D | Page 8 of 28

Data Sheet AD5272/AD5274 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Table 8. rating only and functional operation of the device at these or Parameter Rating any other conditions above those indicated in the operational V to GND –0.3 V to +7.0 V DD section of this specification is not implied. Exposure to absolute V to GND +0.3 V to −7.0 V SS maximum rating conditions for extended periods may affect V to V 7 V DD SS device reliability. V , V to GND V − 0.3 V, V + 0.3 V A W SS DD Digital Input and Output Voltage to GND −0.3 V to V + 0.3 V THERMAL RESISTANCE DD EXT_CAP to V 7 V SS θ is defined by JEDEC specification JESD-51 and the value is JA I , I A W dependent on the test board and test environment. Continuous R = 20 kΩ ±3 mA Table 9. Thermal Resistance AW RAW = 50 kΩ, 100 kΩ ±2 mA Package Type θJA1 θJC Unit Pulsed1 10-Lead LFCSP 50 3 °C/W Frequency > 10 kHz ±MCC2/d3 10-Lead MSOP 135 N/A °C/W Frequency ≤ 10 kHz ±MCC2/√d3 1 JEDEC 2S2P test board, still air (0 m/s air flow). Operating Temperature Range4 −40°C to +125°C Maximum Junction Temperature 150°C (TJ Maximum) ESD CAUTION Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (TJ max − TA)/θJA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A and W terminals at a given resistance. 2 Maximum continuous current 3 Pulse duty factor. 4 Includes programming of 50-TP memory. Rev. D | Page 9 of 28

AD5272/AD5274 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 10ADDR A 2 AD5272/ 9 SCL W 3 AD5274 8 SDA VDD 1 10 ADDR VSS 4 (EXPPAODS)ED 7 RESET AD5272/ A 2 AD5274 9 SCL EXT_CAP 5 6 GND W 3 8 SDA EXT_CVASPS 45 (NToOt Pto V SIEcaWle) 76 RGENSDET 08076-004 N1 . O TOTHREE SI SE XTPIEODS ETOD PVSASD. IS LEFT FLOATING 08076-040 Figure 4. MSOP Pin Configuration Figure 5. LFCSP Pin Configuration Table 10. Pin Function Descriptions Pin No. Mnemonic Description 1 V Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. DD 2 A Terminal A of RDAC. V ≤ V ≤ V . SS A DD 3 W Wiper terminal of RDAC. V ≤ V ≤ V . SS W DD 4 V Negative Supply. Connect to 0 V for single-supply applications. Decouple this pin with 0.1 μF ceramic capacitors SS and 10 μF capacitors. 5 EXT_CAP External Capacitor. Connect a 1 μF capacitor between EXT_CAP and V . This capacitor must have a voltage SS rating of ≥7 V. 6 GND Ground Pin, Logic Ground Reference. 7 RESET Hardware Reset Pin. Refreshes the RDAC register with the contents of the 50-TP memory register. Factory default loads midscale until the first 50-TP wiper memory location is programmed. RESET is active low. Tie RESET to V if not used. DD 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input registers. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input registers. 10 ADDR Tristate Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 11). EPAD Exposed Pad Leave floating or tie to VSS. (LFCSP Only) Rev. D | Page 10 of 28

Data Sheet AD5272/AD5274 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 0.8 ++12255°C°C RAW = 20kΩ TA = 25°C 20kΩ 0.6 –40°C 0.6 5100k0ΩkΩ 0.4 0.4 B) B) S S NL (L 0.2 NL (L0.2 I I 0 0 –0.2 –0.2 –0.40 128 256 38C4ODE 5(D12ecima6l)40 768 896 1023 08076-010 –0.40 256 CODE5 (1D2ecimal) 768 1023 08076-111 Figure 6. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5272) Figure 9. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272) 0.2 0.6 RAW = 20kΩ TA = 25°C 0.1 0.4 0 0.2 –0.1 B) B) S S L (L –0.2 L (L 0 N N D D –0.3 –0.2 –0.4 –0.4 –0.5 –40°C +25°C +125°C 20kΩ 50kΩ 100kΩ –0.60 128 256 38C4ODE 5(1D2ecima6l4)0 768 896 1023 08076-011 –0.60 256 CODE5 (1D2ecimal) 768 1023 08076-120 Figure 7. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5272) Figure 10. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5272) 0.5 0.6 ++12255°C°C RAW = 20kΩ TA = 25°C 2500kkΩΩ 0.4 –40°C 100kΩ 0.4 0.3 0.2 B) B) S S NL (L 0.2 NL (L I I 0 0.1 –0.2 0 –0.10 128 256 38C4ODE 5(D1e2cima6l)40 768 896 1023 08076-014 –0.40 256 CODE5 (1D2ecimal) 768 1023 08076-121 Figure 8. R-INL in Normal Mode vs. Code vs. Temperature (AD5272) Figure 11. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5272) Rev. D | Page 11 of 28

AD5272/AD5274 Data Sheet 0.15 0.15 ++12255°C°C RAW = 20kΩ TA = 25°C 20kΩ 50kΩ 0.10 –40°C 0.10 100kΩ 0.05 0.05 B) B) 0 S S L (L 0 L (L DN DN–0.05 –0.05 –0.10 –0.10 –0.15 –0.150 128 256 38C4ODE 5(D1e2cima6l)40 768 896 1023 08076-015 –0.200 256 CODE5 (1D2ecimal) 768 1023 08076-122 Figure 12. R-DNL in Normal Mode vs. Code vs. Temperature (AD5272) Figure 15. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5272) 0.20 0.15 ++12255°C°C RAW = 20kΩ TA = 25°C 2100k0ΩkΩ –40°C 0.15 0.10 0.10 B) B) 0.05 NL (LS 0.05 NL (LS I I 0 0 –0.05 –0.05 –0.100 64 CODE 1(D28ecimal) 192 255 08076-013 –0.100 64 CODE 1(D28ecimal) 192 255 08076-123 Figure 13. R-INL in R-Perf Mode vs. Code vs. Temperature (AD5274) Figure 16. R-INL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5274) 0.06 0.15 RAW = 20kΩ +125°C TA = 25°C 0.04 +25°C –40°C 0.10 0.02 0 0.05 B) –0.02 B) S S NL (L –0.04 NL (L 0 D –0.06 D –0.05 –0.08 –0.10 –0.10 –0.12 20kΩ 100kΩ –0.140 64 CODE 1(D28ecimal) 192 255 08076-012 –0.150 64 CODE 1(D28ecimal) 192 255 08076-125 Figure 14. R-DNL in R-Perf Mode vs. Code vs. Temperature (AD5274) Figure 17. R-DNL in R-Perf Mode vs. Code vs. Nominal Resistance (AD5274) Rev. D | Page 12 of 28

Data Sheet AD5272/AD5274 0.10 0.15 ++12255°C°C RAW = 20kΩ TA = 25°C 2100k0ΩkΩ –40°C 0.08 0.10 0.06 B) B) 0.05 S S NL (L 0.04 NL (L I I 0 0.02 –0.05 0 –0.020 64 CODE 1(D28ecimal) 192 255 08076-016 –0.100 64 CODE 1(D28ecimal) 192 255 08076-126 Figure 18. R-INL in Normal Mode vs. Code vs. Temperature (AD5274) Figure 21. R-INL in Normal Mode vs. Code vs. Nominal Resistance (AD5274) 0.03 0.010 RAW = 20kΩ +125°C 100kΩ TA = 25°C +25°C 20kΩ –40°C 0.02 0.008 0.01 0.006 B) B) S S NL (L 0 NL (L 0.004 D D –0.01 0.002 –0.02 0 –0.030 64 CODE 1(D28ecimal) 192 255 08076-017 –0.0020 64 CODE 1(D28ecimal) 192 255 008076-027 Figure 19. R-DNL in Normal Mode vs. Code vs. Temperature (AD5274) Figure 22. R-DNL in Normal Mode vs. Code vs. Nominal Resistance (AD5274) 500 0.7 400 IDD = 5V 0.6 300 0.5 200 CURRENT (nA) –1100000 ISS = 3V IDD = 3V I (mA)DD000...432 –200 ISS = 5V 0.1 –300 0 –400 –50–040 –30–20–10 0 10TEM20PE3R0AT4U0RE5 (0°C)60 70 80 90 100110 08076-018 –0.10 0.5 1.0 1.5 2.0 V2L.O5GIC3 (.V0) 3.5 4.0 4.5 5.0 5.5 08076-110 Figure 20. Supply Current (IDD, ISS) vs. Temperature Figure 23. Supply Current (IDD) vs. Digital Input Voltage Rev. D | Page 13 of 28

AD5272/AD5274 Data Sheet 50 7 VDD/VSS= 5V/0V VDD/VSS=5V/0V 45 C) 20kΩ 6 20kΩ pm/° 40 5100k0ΩkΩ A) 5100k0ΩkΩ O (p 35 (mX 5 C A EMP 30 WA_M 4 E T 25 LI D A MO 20 TIC 3 OSTAT 15 HEORE 2 E 10 T H R 1 5 0 0 00 26546 CODE 15(D2182ecimal) 179628 1205253 AADD55227724 08076-019 00 26546 CODE15(21D82ecimal) 179628 1205253 AADD55227742 08076-028 Figure 24. Tempco ΔRWA/ΔT vs. Code Figure 27. Theoretical Maximum Current vs. Code 0 0 0x200 (0x80) AD5272 (AD5274) 0x200 (0x80) AD5272 (AD5274) –10 0x100 (0x40) –10 0x100 (0x40) 0x080 (0x20) 0x080 (0x20) –20 0x040 (0x10) –20 0x040 (0x10) 0x020 (0x08) B) B)–30 N (d –30 0x020 (0x08) N (d 0x010 (0x04) GAI 0x010 (0x04) GAI–40 0x008 (0x02) 0x008 (0x02) 0x004 (0x01) –40 0x004 (0x01) –50 0x002 0x002 0x001 –50 0x001 –60 –60 –70 1k 10k FREQU1E0N0kCY (Hz) 1M 10M 08076-031 1k 10k FREQU1E0N0kCY (Hz) 1M 10M 08076-041 Figure 25. 20 kΩ Gain vs. Code vs. Frequency Figure 28. 100 kΩ Gain vs. Code vs. Frequency 0 0 0x200 (0x80) AD5272 (AD5274) VDD/VSS = 5V/0V CODE = HALF SCALE –10 –10 0x100 (0x40) 50kΩ –20 100kΩ 0x080 (0x20) 20kΩ –20 –30 0x040 (0x10) dB) 0x020 (0x08) dB)–40 N (–30 R ( GAI 0x010 (0x04) PSR–50 –40 0x008 (0x02) –60 0x004 (0x01) –70 –50 0x002 0x001 –80 –60 –90 1k 10k FREQU1E0N0kCY (Hz) 1M 10M 08076-032 100 1k FREQUENCY (Hz)10k 100k 08076-024 Figure 26. 50 kΩ Gain vs. Code vs. Frequency Figure 29. PSRR vs. Frequency Rev. D | Page 14 of 28

Data Sheet AD5272/AD5274 0 0 VCDODD/VES =S H=A 5LVF/0 SVCALE 2500kkΩΩ –10 VCDODD/VES =S H=A 5LVF/0 SVCALE –20 NVIONI S= E1 VB Wrm =s 22kHz 100kΩ –20 fNINO=IS 1Ek HBzW = 22kHz –30 20kΩ B) 50kΩ N (dB)–40 + N (d–40 100kΩ + D –50 THD –60 TH–60 –70 –80 –80 –90 –100100 1k FREQUENCY (H1z0)k 100k 08076-025 –1000.001 0.01VOLTAGE (VRMS0).1 1 08076-026 Figure 30. THD + N vs. Frequency Figure 33. THD + N vs. Amplitude 0.03 0.0010 20kΩ VDD/VSS = 5V/0V 50kΩ IAW = 200µA 0.02 100kΩ CODE = HALF SCALE 0.0005 0.01 VOLTAGE (V)–0.010 VOLTAGE (V)–0.00050 –0.02 –0.0010 –0.03 –0.04–1 4 T9IME (µs) 14 19 08076-043 –0.0015–10 0 10 2T0IME (µs3)0 40 50 60 08076-046 Figure 31. Maximum Glitch Energy Figure 34. Digital Feedthrough 45 11.25 70 15.5 TA = 25°C VDD/VSS= 5V/0V 40 20kΩ 10.00 20kΩ 50kΩ 60 50kΩ 15.0 AD5272) 3350 100kΩ 78..5705 AD5274) D5272) 50 100kΩ 12.5 D5274) DES ( 25 6.25 DES ( ES (A 40 10.0 ES (A O O D D C C O O OF 20 5.00 OF F C 30 7.5 F C MBER 15 3.75 MBER BER O 20 5.0 BER O NU 10 2.50 NU UM UM N N 10 2.5 5 1.25 02.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 0 08076-021 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 0 08076-020 Figure 32. Maximum Code Loss vs. Temperature Figure 35. Maximum Code Loss vs. Power Supply Range Rev. D | Page 15 of 28

AD5272/AD5274 Data Sheet 8 0.006 VDD/VSS = 5V/0V IAW = 10µA 0.005 CODE = HALF SCALE 7 %)0.004 E ( OLTAGE (V) 6 RESISTANC00..000023 V W0.001 A R Δ 5 0 –0.001 40.07 0.09 0T.1I1ME (Secon0d.1s3) 0.15 0.17 08076-029 –0.0020 100 200 O3P0E0RA4T0IO0N A50T0 1506°C00 (Ho7u0r0s) 800 900 1000 08076-038 Figure 36. VEXT_CAP Waveform While Writing Fuse Figure 37. Long-Term Drift Accelerated Average by Burn-In Rev. D | Page 16 of 28

Data Sheet AD5272/AD5274 TEST CIRCUITS Figure 38 to Figure 42 define the test conditions used in the Specifications section. DUT DUT IW W W 1GΩ A A V VMS 08076-033 VMS 08076-036 Figure 38. Resistor Position Nonlinearity Error Figure 41. Gain vs. Frequency (Rheostat Operation; R-INL, R-DNL) RWA=VIMWS DUT ICM GND W +2.75V DUT CODE = 0x00 IW RW =RW2A A –2.75V W GND A VMS 08076-034 N+C2.75V –2.7G5VND NC = NO CONNECT 08076-037 Figure 39. Wiper Resistance Figure 42. Common Leakage Current V+ = VDD ±10% PSRR (dB) = 20 log VMS VDD VDD W IW PSS (%/%) =ΔΔVVMDDS%% V+ A VMS 08076-035 Figure 40. Power Supply Sensitivity (PSS, PSRR) Rev. D | Page 17 of 28

AD5272/AD5274 Data Sheet THEORY OF OPERATION The AD5272 and AD5274 digital rheostats are designed to The 2-wire serial bus protocol operates as follows: The master operate as true variable resistors for analog signals within the initiates a data transfer by establishing a start condition, which terminal voltage range of V < V < V . The RDAC register is when a high-to-low transition on the SDA line occurs while SS TERM DD contents determine the resistor wiper position. The RDAC SCL is high. The next byte is the address byte, which consists register acts as a scratchpad register, which allows unlimited of the 7-bit slave address and a R/W bit. The slave device cor- changes of resistance settings. The RDAC register can be responding to the transmitted address responds by pulling programmed with any position setting using the I2C interface. SDA low during the ninth clock pulse (this is termed the When a desirable wiper position is found, this value can be acknowledge bit). At this stage, all other devices on the bus stored in a 50-TP memory register. Thereafter, the wiper remain idle while the selected device waits for data to be position is always restored to that position for subsequent written to, or read from, its shift register. power-up. The storing of 50-TP data takes approximately Data is transmitted over the serial bus in sequences of nine 350 ms; during this time, the AD5272/AD5274 is locked and clock pulses (eight data bits followed by an acknowledge bit). does not acknowledge any new command thereby preventing The transitions on the SDA line must occur during the low any changes from taking place. The acknowledge bit can be period of SCL and remain stable during the high period of SCL. polled to verify that the fuse program command is complete. When all data bits have been read or written, a stop condition is The AD5272/AD5274 also feature a patented 1% end-to-end established. In write mode, the master pulls the SDA line high resistor tolerance. This simplifies precision, rheostat mode, and during the 10th clock pulse to establish a stop condition. In read open-loop applications where knowledge of absolute resistance mode, the master issues a no acknowledge for the ninth clock is critical. pulse (that is, the SDA line remains high). The master then SERIAL DATA INTERFACE brings the SDA line low before the 10th clock pulse, and then The AD5272/AD5274 have 2-wire I2C-compatible serial inter- high during the 10th clock pulse to establish a stop condition. faces. Each of these devices can be connected to an I2C bus as SHIFT REGISTER a slave device under the control of a master device; see Figure 3 For the AD5272/AD5274, the shift register is 16 bits wide, as for a timing diagram of a typical write sequence. shown in Figure 2. The 16-bit word consists of two unused bits, The AD5272/AD5274 support standard (100 kHz) and fast which should be set to zero, followed by four control bits and (400 kHz) data transfer modes. Support is not provided for 10 RDAC data bits (note that for the AD5274 only, the lower 10-bit addressing and general call addressing. two RDAC data bits are don’t care if the RDAC register is read from or written to), and data is loaded MSB first (Bit 15). The The AD5272/AD5274 each has a 7-bit slave address. The five four control bits determine the function of the software command MSBs are 01011 and the two LSBs are determined by the state (Table 12). Figure 43 shows a timing diagram of a typical of the ADDR pin. The facility to make hardwired changes to AD5272/AD5274 write sequence. ADDR allows the user to incorporate up to three of these devices on one bus as outlined in Table 11. The command bits (Cx) control the operation of the digital potentiometer and the internal 50-TP memory. The data bits (Dx) are the values that are loaded into the decoded register. Table 11. Device Address Selection ADDR A1 A0 7-Bit I2C Device Address GND 1 1 0101111 V 0 0 0101100 DD NC (No Connection)1 1 0 0101110 1 Not available in bipolar mode. VSS < 0 V. Rev. D | Page 18 of 28

Data Sheet AD5272/AD5274 WRITE OPERATION Two bytes of data are then written to the RDAC, the most significant byte followed by the least significant byte; both of It is possible to write data for the RDAC register or the control these data bytes are acknowledged by the AD5272/AD5274. A register. When writing to the AD5272/AD5274, the user must stop condition follows. The write operations for the AD5272/ begin with a start command followed by an address byte (R/W AD5274 are shown in Figure 43. = 0), after which the AD5272/AD5274 acknowledges that it is prepared to receive data by pulling SDA low. A repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in Figure 44. 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 START BY ACK. BY ACK. BY MASTER AD5272/AD5274 AD5272/AD5274 FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE MOST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY LEAST SIGNFIFRIACMAEN T3 DATA BYTEAD5272/AD5274 MASTER 08076-005 Figure 43. Write Command 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 STARTBY ACK. BY ACK. BY MASTER AD52722/AD5274 AD52722/AD5274 FRAME1 FRAME2 SERIALBUSADDRESSBYTE MOSTSIGNIFICANTDATABYTE 9 1 9 SCL(CONTINUED) SDA(CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY AD52722/AD5274 FRAME3 LEASTSIGNIFICANTDATABYTE 9 1 9 SCL(CONTINUED) SDA(CONTINUED) 0 0 C3 C2 C1 C0 D9 D8 ACK. BY AD52722/AD5274 FRAME4 MOST SIGNIFICANTDATABYTE 9 1 9 SCL(CONTINUED) SDA(CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOPBY AD52722/AD5274 MASTER LEASTSIGNFIFRIACMAENT5DATABYTE 08076-006 Figure 44. Multiple Write Rev. D | Page 19 of 28

AD5272/AD5274 Data Sheet READ OPERATION A stop condition follows. These bytes contain the read instruc- tion, which enables readback of the RDAC register, 50-TP When reading data back from the AD5272/AD5274, the user memory, or the control register. The user can then read back must first issue a readback command to the device, this begins the data beginning with a start command followed by an with a start command followed by an address byte (R/W = 0), address byte (R/W = 1), after which the device acknowledges after which the AD5272/AD5274 acknowledges that it is that it is prepared to transmit data by pulling SDA low. Two prepared to receive data by pulling SDA low. bytes of data are then read from the device, as shown in Figure 45. Two bytes of data are then written to the AD5272/AD5274, the A stop condition follows. If the master does not acknowledge most significant byte followed by the least significant byte; both the first byte, the second byte is not transmitted by the of these data bytes are acknowledged by the AD5272/AD5274. AD5272/AD5274. 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 R/W 0 0 C3 C2 C1 C0 D9 D8 START BY ACK. BY ACK. BY MASTER AD5272/AD5274 AD5272/AD5274 FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE MOST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY STOP BY AD5272/AD5274MASTER FRAME 3 LEAST SIGNIFICANT DATA BYTE 1 9 1 9 SCL SDA 0 1 0 1 1 A1 A0 R/W 0 0 X X X X D9 D8 START BY ACK. BY ACK. BY MASTER AD5272/AD5274 MASTER FRAME 1 FRAME 2 SERIAL BUS ADDRESS BYTE MOST SIGNIFICANT DATA BYTE 9 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. BYSTOP BY LEAST SIGNFIRFIACMAEN T3 DATA BYTE MASTER MASTER 08076-007 Figure 45. Read Command Rev. D | Page 20 of 28

Data Sheet AD5272/AD5274 RDAC REGISTER Prior to 50-TP activation, the AD5272/AD5274 is preset to midscale on power-up. It is possible to read back the contents The RDAC register directly controls the position of the digital of any of the 50-TP memory registers through the I2C interface rheostat wiper. For example, when the RDAC register is loaded by using Command 5 in Table 12. The lower six LSB bits, D0 to with all zeros, the wiper is connected to Terminal A of the D5 of the data byte, select which memory location is to be read variable resistor. It is possible to both write to and read from back. A binary encoded version address of the most recently the RDAC register using the I2C interface. The RDAC register programmed wiper memory location can be read back using is a standard logic register; there is no restriction on the number Command 6 in Table 12. This can be used to monitor the spare of changes allowed. memory status of the 50-TP memory block. 50-TP MEMORY BLOCK WRITE PROTECTION The AD5272/AD5274 contain an array of 50-TP programmable On power-up, serial data input register write commands for memory registers, which allow the wiper position to be pro- both the RDAC register and the 50-TP memory registers are grammed up to 50 times. Table 16 shows the memory map. disabled. The RDAC write protect bit (Bit C1) of the control Command 3 in Table 12 programs the contents of the RDAC register (see Table 14 and Table 15) is set to 0 by default. This register to memory. The first address to be programmed is disables any change of the RDAC register content regardless of Location 0x01, see Table 16, and the AD5272/AD5274 incre- the software commands, except that the RDAC register can be ments the 50-TP memory address for each subsequent program refreshed from the 50-TP memory using the software reset, until the memory is full. Programming data to 50-TP consumes Command 4, or through hardware by the RESET pin. To enable approximately 4 mA for 55 ms, and takes approximately 350 ms programming of the variable resistor wiper position (programming to complete, during which time the shift register is locked pre- the RDAC register), the write protect bit (Bit C1) of the control venting any changes from taking place. Bit C3 of the control register must first be programmed. This is accomplished by register in Table 15 can be polled to verify that the fuse program loading the serial data input register with Command 7 (see command was successful. No change in supply voltage is required Table 12). To enable programming of the 50-TP memory block, to program the 50-TP memory; however, a 1 µF capacitor on Bit C0 of the control register, which is set to 0 by default, must the EXT_CAP pin is required as shown in Figure 47. first be set to 1. Table 12. Command Operation Truth Table Command Command[DB13:DB10] Data[DB9:B0]1 Number C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 X X X X X X X X X X NOP: do nothing. 1 0 0 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D12 D02 Write contents of serial register data to RDAC. 2 0 0 1 0 X X X X X X X X X X Read contents of RDAC wiper register. 3 0 0 1 1 X X X X X X X X X X Store wiper setting: store RDAC setting to 50-TP. 4 0 1 0 0 X X X X X X X X X X Software reset: refresh RDAC with the last 50-TP memory stored value. 53 0 1 0 1 X X X X D5 D4 D3 D2 D1 D0 Read contents of 50-TP from the SDO output in the next frame. 6 0 1 1 0 X X X X X X X X X X Read address of the last 50-TP programmed memory location. 74 0 1 1 1 X X X X X X X D2 D1 D0 Write contents of the serial register data to the control register. 8 1 0 0 0 X X X X X X X X X X Read contents of the control register. 9 1 0 0 1 X X X X X X X X X D0 Software shutdown. D0 = 0; normal mode. D0 = 1; shutdown mode. 1 X = don’t care. 2 AD5274 = don’t care. 3 See Table 16 for the 50-TP memory map. 4 See Table 15 for bit details. Rev. D | Page 21 of 28

AD5272/AD5274 Data Sheet Table 13. Write and Read to RDAC and 50-TP memory DIN SDO1 Action 0x1C03 0xXXXX Enable update of wiper position and 50-TP memory contents through digital interface. 0x0500 0x1C03 Write 0x100 to the RDAC register, wiper moves to ¼ full-scale position. 0x0800 0x0500 Prepare data read from RDAC register. 0x0C00 0x100 Stores RDAC register content into 50-TP memory. 16-bit word appears out of SDO, where last 10-bits contain the contents of the RDAC Register 0x100. 0x1800 0x0C00 Prepare data read of last programmed 50-TP memory monitor location. 0x0000 0xXX19 NOP Instruction 0 sends a 16-bit word out of SDO, where the six LSBs last 6-bits contain the binary address of the last programmed 50-TP memory location, for example, 0x19 (see Table 16). 0x1419 0x0000 Prepares data read from Memory Location 0x19. 0x2000 0x0100 Prepare data read from the control register. Sends a 16-bit word out of SDO, where the last 10-bits contain the contents of Memory Location 0x19. 0x0000 0xXXXX NOP Instruction 0 sends a 16-bit word out of SDO, where the last four bits contain the contents of the control register. If Bit C3 = 1, fuse program command successful. 1 X is don’t care. Table 14. Control Register Bit Map DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 C3 C2 C1 C0 Table 15. Control Register Description Bit Name Description C0 50-TP program enable 0 = 50-TP program disabled (default) 1 = enable device for 50-TP program C1 RDAC register write protect 0 = wiper position frozen to value in 50-TP memory (default)1 1 = allow update of wiper position through a digital interface C2 Resistor performance enable 0 = RDAC resistor tolerance calibration enabled (default) 1 = RDAC resistor tolerance calibration disabled C3 50-TP memory program success bit 0 = fuse program command unsuccessful (default) 1 = fuse program command successful 1 Wiper position is frozen to the last value programmed in the 50-TP memory. Wiper freezes to midscale if 50-TP memory has not been previously programmed. Table 16. Memory Map Data Byte [DB9:DB8]1 Command Number D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Register Contents 5 X X X 0 0 0 0 0 0 0 Reserved X X X 0 0 0 0 0 0 1 1st programmed wiper location (0x01) X X X 0 0 0 0 0 1 0 2nd programmed wiper location (0x02) X X X 0 0 0 0 0 1 1 3rd programmed wiper location (0x03) X X X 0 0 0 0 1 0 0 4th programmed wiper location (0x04) … … … … … … … … … … … X X X 0 0 0 1 0 1 0 10th programmed wiper location (0xA) X X X 0 0 1 0 1 0 0 20th programmed wiper location (0x14) X X X 0 0 1 1 1 1 0 30th programmed wiper location (0x1E) X X X 0 1 0 1 0 0 0 40th programmed wiper location (0x28) X X X 0 1 1 0 0 1 0 50th programmed wiper location (0x32) 1 X is don’t care. Rev. D | Page 22 of 28

Data Sheet AD5272/AD5274 50-TP MEMORY WRITE-ACKNOWLEDGE POLLING A After each write operation to the 50-TP registers, an internal write cycle begins. The I2C interface of the device is disabled. RL To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C RL RM interface polling can be conducted by sending a start condition, followed by the slave address and the write bit. If the I2C interface 10-/8-BIT RM SW responds with an acknowledge (ACK), the write cycle is complete ADDRESS DECODER RW and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it completes. W RESET RW The AD5272/AD5274 can be reset through software by executing 08076-008 Command 4 (see Table 12) or through hardware on the low Figure 46. Simplified RDAC Circuit pulse of the RESET pin. The reset command loads the RDAC PROGRAMMING THE VARIABLE RESISTOR register with the contents of the most recently programmed 50-TP Rheostat Operation—1% Resistor Tolerance memory location. The RDAC register loads with midscale if no The nominal resistance between Terminal W and Terminal A, R , 50-TP memory location has been previously programmed. Tie WA is available in 20 kΩ, 50 kΩ, and 100 kΩ, and 1024-/256-tap points RESET to V if the RESET pin is not used. DD accessed by the wiper terminal. The 10-/8-bit data in the RDAC RESISTOR PERFORMANCE MODE latch is decoded to select one of the 1024 or 256 possible wiper This mode activates a new, patented 1% end-to-end resistor settings. The AD5272/ AD5274 contain an internal ±1% resistor tolerance that ensures a ±1% resistor tolerance on each code, tolerance calibration feature which can be disabled or enabled, that is, code = half scale and R = 10 kΩ ± 100 Ω. See Table 2, enabled by default, or by programming Bit C2 of the control WA Table 3, Table 5, and Table 6 to check which codes achieve ±1% register (see Table 15). The digitally programmed output resis- resistor tolerance. The resistor performance mode is activated by tance between the W terminal and the A terminal, RWA, is programming Bit C2 of the control register (see Table 14 and calibrated to give a maximum of ±1% absolute resistance error Table 15). over both the full supply and temperature ranges. As a result, the general equations for determining the digitally programmed SHUTDOWN MODE output resistance between the W terminal and A terminal are as The AD5272/AD5274 can be shut down by executing the software follows: shutdown command, Command 9 (see Table 12), and setting For the AD5272 the LSB to 1. This feature places the RDAC in a zero-power- D R (D)= ×R (1) consumption state where Terminal Ax is disconnected from WA 1024 WA the wiper terminal. It is possible to execute any command from For the AD5274 Table 12 while the AD5272 or AD5274 is in shutdown mode. D The part can be taken out of shutdown mode by executing R (D)= ×R (2) WA 256 WA Command 9 and setting the LSB to 0, or by issuing a software or hardware reset. where: D is the decimal equivalent of the binary code loaded in the RDAC ARCHITECTURE 10-/8-bit RDAC register. To achieve optimum performance, Analog Devices has patented the R is the end-to-end resistance. WA RDAC segmentation architecture for all the digital potentiometers. In the zero-scale condition, a finite total wiper resistance of In particular, the AD5272/AD5274 employ a three-stage 120 Ω is present. Regardless of which setting the part is oper- segmentation approach, as shown in Figure 46. The AD5272/ ating in, take care to limit the current between the A terminal AD5274 wiper switch is designed with the transmission gate to B terminal, W terminal to A terminal, and W terminal to CMOS topology. B terminal, to the maximum continuous current of ±3 mA, or the pulse current specified in Table 8. Otherwise, degradation or possible destruction of the internal switch contact can occur. Rev. D | Page 23 of 28

AD5272/AD5274 Data Sheet EXT_CAP CAPACITOR The ground pins of the AD5272/AD5274 devices are primarily used as digital ground references. To minimize the digital A 1 μF capacitor to V must be connected to the EXT_CAP pin SS ground bounce, join the AD5272/AD5274 ground terminal (see Figure 47) on power-up and throughout the operation of remotely to the common ground. The digital input control the AD5272/AD5274. signals to the AD5272/AD5274 must be referenced to the device ground pin (GND) and satisfy the logic level defined in AD5272/ AD5274 the Specifications section. An internal level shift circuit ensures that the common-mode voltage range of the three terminals 50_OTP EXT_CAP MEMORY extends from V to V , regardless of the digital input level. C1 BLOCK SS DD 1µF POWER-UP SEQUENCE VSS VSS 08076-009 BTeercmauinsea lt hAe raen adr eT edrimodinesa lt oW li m(seite tFhieg uvorelt a4g8e), ciot mis pimliapnocret aant t to Figure 47. EXT_CAP Hardware Setup power V /V first before applying any voltage to Terminal A DD SS TERMINAL VOLTAGE OPERATING RANGE and Terminal W; otherwise, the diode is forward-biased such that V /V are powered unintentionally. The ideal power-up The positive V and negative V power supplies of the DD SS DD SS sequence is V , GND, V , digital inputs, V , and V . The AD5272/AD5274 define the boundary conditions for proper SS DD A W order of powering V , V , and digital inputs is not important 2-terminal digital resistor operation. Supply signals present on A W as long as they are powered after V /V . Terminal A and Terminal W that exceed V or V are clamped DD SS DD SS by the internal forward-biased diodes (see Figure 48). As soon as V is powered, the power-on preset activates, which DD first sets the RDAC to midscale and then restores the last VDD programmed 50-TP value to the RDAC register. A W VSS 08076-109 Figure 48. Maximum Terminal Voltages Set by VDD and VSS Rev. D | Page 24 of 28

Data Sheet AD5272/AD5274 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 49. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 3.10 2.23 3.00 SQ 2.90 0.50 BSC 6 10 PIN 1 INDEX EXPOSED 1.74 AREA PAD 1.64 0.50 1.49 0.40 0.30 5 1 0.20 MIN TOP VIEW BOTTOM VIEW PIN 1 INDICATOR (R 0.15) 0.80 FOR PROPER CONNECTION OF 0.75 0.05 MAX THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEPALTAINNGE 000...322050 0.20 REF 0.08 02-05-2013-C Figure 50. 10-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3mm Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. D | Page 25 of 28

AD5272/AD5274 Data Sheet ORDERING GUIDE Model1 R (kΩ) Resolution Temperature Range Package Description Package Option Branding AW AD5272BRMZ-20 20 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DE6 AD5272BRMZ-20-RL7 20 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DE6 AD5272BRMZ-50 50 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DE7 AD5272BRMZ-50-RL7 50 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DE7 AD5272BRMZ-100 100 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DE5 AD5272BRMZ-100-RL7 100 1,024 −40°C to +125°C 10-Lead MSOP RM-10 DE5 AD5272BCPZ-20-RL7 20 1,024 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DE4 AD5272BCPZ-100-RL7 100 1,024 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DE3 AD5274BRMZ-20 20 256 −40°C to +125°C 10-Lead MSOP RM-10 DEE AD5274BRMZ-20-RL7 20 256 −40°C to +125°C 10-Lead MSOP RM-10 DEE AD5274BRMZ-100 100 256 −40°C to +125°C 10-Lead MSOP RM-10 DED AD5274BRMZ-100-RL7 100 256 −40°C to +125°C 10-Lead MSOP RM-10 DED AD5274BCPZ-20-RL7 20 256 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DE9 AD5274BCPZ-100-RL7 100 256 −40°C to +125°C 10-Lead LFCSP_WD CP-10-9 DE8 EVAL-AD5272SDZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. D | Page 26 of 28

Data Sheet AD5272/AD5274 NOTES Rev. D | Page 27 of 28

AD5272/AD5274 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2009–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08076-0-3/13(D) Rev. D | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5274BRMZ-100 AD5272BRMZ-50 AD5272BRMZ-100-RL7 AD5272BCPZ-20-RL7 EVAL-AD5272SDZ AD5274BRMZ-20-RL7 AD5272BRMZ-20 AD5274BCPZ-100-RL7 AD5272BRMZ-50-RL7 AD5274BRMZ-100-RL7 AD5272BRMZ-100 AD5272BCPZ-100-RL7 AD5274BRMZ-20 AD5274BCPZ-20-RL7