Quad, 15 V, 256-Position, Digital Potentiometer with Pin-Selectable SPI/I2C Data Sheet AD5263 FEATURES FUNCTIONAL BLOCK DIAGRAM 256-position, 4-channel A1 W1 B1 A2 W2 B2 A3 W3 B3 A4 W4 B4 End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ VDD Pin-selectable SPI®- or I2C®-compatible interface VSS Power-on preset to midscale SHDN RDAC 1 RDAC 2 RDAC 3 RDAC 4 Two package address decode pins AD0 and AD1 RES/AD1 REGISTER REGISTER REGISTER REGISTER Rheostat mode temperature coefficient 30 ppm/°C Voltage divider temperature coefficient 5 ppm/°C VL 8 AD5263 Wide operating temperature range –40°C to +125°C CLK/SCL ADDRESS SDI/SDA DECODER SERIAL INPUT 10 V to 15 V single supply; ±5 V dual supply CS/AD0 SPI/I2C REGISTER SELECT GND LOGIC AMPecPhLaInCicAaTl pIOotNenSt iometer replacement DIS NC/O2 SDO/O1 03142-001 Optical network adjustment Figure 1. Instrumentation: gain, offset adjustment Stereo channel audio level control Automotive electronics adjustment Programmable power supply Programmable filters, delays, time constants Line impedance matching Low resolution DAC/trimmer replacement Base station power amp biasing Sensor calibration GENERAL DESCRIPTION Wiper position programming presets to midscale upon power- The AD5263 is the industry’s first quad-channel, 256-position, on. Once powered, the VR wiper position is programmed by digital potentiometer1 with a selectable digital interface. This either the 3-wire SPI or 2-wire I2C-compatible interface. In the device performs the same electronic adjustment function as I2C mode, additional programmable logic outputs enable users mechanical potentiometers or variable resistors, with enhanced to drive digital loads, logic gates, and analog switches in their resolution, solid-state reliability, and superior low temperature systems. coefficient performance. The AD5263 is available in a narrow body, 24-lead TSSOP. Each channel of the AD5263 offers a completely programmable All parts are guaranteed to operate over the automotive value of resistance between the A terminal and the wiper or temperature range of –40°C to +125°C. between the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal For single- or dual-channel applications, refer to the temperature coefficient of ±30 ppm/°C and a ±1% channel-to- AD5260/AD5280 or AD5262/AD5282 data sheets. channel matching tolerance. Another key feature of this part is 1 The terms digital potentiometer, VR, and RDAC are used interchangeably. the ability to operate from +4.5 V to +15 V, or at ±5 V. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5263 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Multiple Devices on One Bus ................................................... 21 Applications ....................................................................................... 1 Level Shift for Negative Voltage Operation ................................ 21 Functional Block Diagram .............................................................. 1 ESD Protection ........................................................................... 21 General Description ......................................................................... 1 Terminal Voltage Operating Range ......................................... 21 Revision History ............................................................................... 2 Power-Up Sequence ................................................................... 21 Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions ....... 3 V Power Supply ................................................................... 22 LOGIC Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions .......... 5 Layout and Power Supply Bypassing ....................................... 22 Absolute Maximum Ratings ............................................................ 6 RDAC Circuit Simulation Model ............................................. 22 ESD Caution .................................................................................. 6 Applications Information .............................................................. 23 Pin Configuration and Pin Function Descriptions ...................... 7 Bipolar DC or AC Operation from Dual Supplies ................. 23 Typical Performance Characteristics ............................................. 8 Gain Control Compensation .................................................... 23 Test Circuits ..................................................................................... 13 Programmable Voltage Reference ............................................ 23 SPI-Compatible Digital Interface (DIS = 0) ................................ 15 8-Bit Bipolar DAC ...................................................................... 24 Serial Data-Word Format .......................................................... 15 Bipolar Programmable Gain Amplifier ................................... 24 I2C-Compatible Digital Interface (DIS = 1) ................................ 16 Programmable Voltage Source with Boosted Output ........... 24 I2C Write Mode Data-Word Format ........................................ 16 Programmable 4 to 20 mA Current Source ............................ 25 I2C Read Mode Data-Word Format ......................................... 16 Programmable Bidirectional Current Source ......................... 25 Operation ......................................................................................... 17 Programmable Low-Pass Filter ................................................ 26 Programming the Variable Resistor ......................................... 17 Programmable Oscillator .......................................................... 26 Programming the Potentiometer Divider Voltage Output Resistance Scaling ...................................................................... 27 Operation ..................................................................................... 18 Resistance Tolerance, Drift, and Temperature Coefficient Pin-Selectable Digital Interface ................................................ 18 Mismatch Considerations ......................................................... 27 SPI-Compatible 3-Wire Serial Bus (DIS = 0) ......................... 18 Outline Dimensions ....................................................................... 28 I2C-Compatible 2-Wire Serial Bus (DIS = 1) .......................... 19 Ordering Guide .......................................................................... 28 Additional Programmable Logic Output ................................ 20 Self-Contained Shutdown Function ........................................ 20 REVISION HISTORY 10/12—Rev. E to Rev. F 7/09—Rev. A to Rev. B Changes to Self-Contained Shutdown Function Section .......... 20 Change to Features Section .............................................................. 1 Added Table 8 and Table 9; Renumbered Sequentially ............. 20 Change to Power Single-Supply Range Parameter........................ 4 Changes to Programmable Voltage Source with Boosted Output Changes to Ordering Guide .......................................................... 28 Section .............................................................................................. 24 11/06—Rev. 0 to Rev. A Updated Format .................................................................. Universal 7/12—Rev. D to Rev. E Changes to Absolute Maximum Ratings ........................................ 6 Changes to SD Description ........................................................... 16 Changes to Ordering Guide .......................................................... 28 4/12—Rev. C to Rev. D 6/03—Revision 0: Initial Version Change to Rheostat Operation Section ....................................... 17 Deleted Equation 4 and Accompanying Text ............................. 18 5/11—Rev. B to Rev. C Change to Digital Inputs and Output Voltage Parameter .............. 6 Changes to Ordering Guide .......................................................... 28 Changes to I2C Disclaimer ............................................................ 28 Rev. F | Page 2 of 28

Data Sheet AD5263 ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS V = +5 V, V = –5 V, V = +5 V, V = +V , V = 0 V, –40°C < T < +125°C, unless otherwise noted. DD SS L A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Specifications apply to all VRs Resistor Differential NL2 R-DNL R , V = NC −1 ±1/4 +1 LSB WB A Resistor Nonlinearity2 R-INL R , V = NC −1 ±1/2 +1 LSB WB A Nominal Resistor Tolerance3 ∆R T = 25°C −30 +30 % AB A Resistance Mode Temperature ∆R /∆T 30 ppm/°C WB Coefficient ∆R /∆T 30 ppm/°C WA Wiper Resistance R I = 1 V/R 60 150 Ω W W AB DC CHARACTERISTICS—POTENTIOMETER Specifications apply to all VRs DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity4 DNL −1 ±1/4 +1 LSB Integral Nonlinearity4 INL −1 ±1/2 +1 LSB Voltage Divider Temperature Coefficient ∆V /∆T Code = 0x80 5 ppm/°C W Full-Scale Error V Code = 0xFF −2 −1 +0 LSB WFSE Zero-Scale Error V Code = 0x00 0 +1 +2 LSB WZSE RESISTOR TERMINALS Voltage Range5 V V V V A,B,W SS DD Capacitance6 Ax, Bx C f = 1 MHz, measured to GND, 25 pF A,B Code = 0x80 Capacitance6 Wx C f = 1 MHz, measured to GND, 55 pF W Code = 0x80 Common-Mode Leakage I V = V = V /2 1 nA CM A B DD Shutdown Current7 I 0.02 5 µA SHDN DIGITAL INPUTS Input Logic High V 2.4 V IH Input Logic Low V 0.8 V IL Input Logic High (SDA and SCL) V V = 0 V 0.7 × V V + 0.5 V IH SS L L Input Logic Low (SDA and SCL) V V = 0 V −0.5 0.3 × V V IL SS L Input Current I V = 0 V or +5 V ±1 µA IL IN Input Capacitance6 C 5 pF IL DIGITAL OUTPUTS SDA V I = 3 mA 0.4 V OL SINK V I = 6 mA 0.6 V OL SINK O1, O2 V I = 40 µA 4 V OH SOURCE O1, O2 V I = 1.6 mA 0.4 V OL SINK SDO V R = 2.2 kΩ to V V − 0.1 V OH L DD DD SDO V I = 3 mA 0.4 V OL SINK Three-State Leakage Current I V = 0 V or +5 V ±1 µA OZ IN Output Capacitance6 C 3 8 pF OZ Rev. F | Page 3 of 28

AD5263 Data Sheet Parameter Symbol Conditions Min Typ1 Max Unit POWER SUPPLIES Logic Supply8 V 2.7 5.5 V L Power Single-Supply Range V V = 0 V 4.5 16.5 V DD RANGE SS Power Dual-Supply Range V ±4.5 ±7.5 V DD/SS RANGE Logic Supply Current9 IL VL = +5 V 25 60 µA Positive Supply Current I V = +5 V or V = 0 V 1 µA DD IH IL Negative Supply Current I V = –5 V 1 µA SS SS Power Dissipation10 P V = +5 V or V = 0 V, V = 0.6 mW DISS IH IL DD +5 V, V = –5 V SS Power Supply Sensitivity PSS ∆V = +5 V ± 10% 0.002 0.01 %/% DD DYNAMIC CHARACTERISTICS6, 11 Bandwidth (3 dB) BW R = 20 kΩ/50 kΩ/200 kΩ 300/150/35 kHz AB Total Harmonic Distortion THD V = 1 V rms, V = 0 V, f = 1 kHz, 0.05 % W A B R = 20 kΩ AB V Settling Time12 t V = 10 V, V = 0 V, ±1 LSB error 2 µs W S A B band Resistor Noise Voltage e R = 10 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz N_WB WB 1 Typicals represent average readings at +25°C and V = +5 V, V = −5 V. DD SS 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I = V /R for both V = +5 V and W DD DD V = –5 V. SS 3 V = V , Wiper (V ) = no connect. AB DD W 4 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V = V and V = 0 V. DNL specification limits W A DD B of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 V is limited to V or 5.5 V, whichever is less. L DD 9 Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic. 10 P is calculated from I × V . CMOS logic level inputs result in minimum power dissipation. DISS DD DD 11 All dynamic characteristics use V = +5 V, V = −5 V, V = +5 V. DD SS L 12 Settling time depends on value of V , R, and C. DD L L Rev. F | Page 4 of 28

Data Sheet AD5263 TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS V = +5 V, V = –5 V, V = +5 V, V = +V , V = 0 V, –40°C < T < +125°C, unless otherwise noted. DD SS L A DD B A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit SPI INTERFACE TIMING CHARACTERISTICS Specifications apply to all parts2, 3 Clock Frequency f 25 MHz CLK Input Clock Pulse Width t , t Clock level high or low 20 ns CH CL Data Setup Time t 10 ns DS Data Hold Time t 10 ns DH CS Setup Time t 15 ns CSS CS High Pulse Width t 20 ns CSW CLK Fall to CS Fall Hold Time t 0 ns CSH0 CLK Fall to CS Rise Hold Time t 0 ns CSH1 CS Rise to Clock Rise Setup t 10 ns CS1 Reset Pulse Width t 5 ns RS I2C INTERFACE TIMING CHARACTERISTICS Specifications apply to all parts2, 3 SCL Clock Frequency f 400 kHz SCL t Bus Free Time Between Stop and Start t 1.3 µs BUF 1 t Hold Time (Repeated Start) t After this period, the first clock 0.6 µs HD;STA 2 pulse is generated. t Low Period of SCL Clock t 1.3 µs LOW 3 t High Period of SCL Clock t 0.6 50 µs HIGH 4 t Setup Time for Start Condition t 0.6 µs SU;STA 5 t Data Hold Time t 0.9 µs HD;DAT 6 t Data Setup Time t 100 ns SU;DAT 7 t Fall Time of Both SDA and SCL Signals t 300 ns F 8 t Rise Time of Both SDA and SCL Signals t 300 ns R 9 t Setup Time for Stop Condition t 0.6 µs SU;STO 10 1 Typicals represent average readings at +25°C and V = +5 V, V = −5 V DD SS 2 Guaranteed by design and not subject to production test. 3 See timing diagrams for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of 3 V) and timed from a voltage level R F of 1.5 V. Switching characteristics are measured using V = 5 V. L Rev. F | Page 5 of 28

AD5263 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Value may cause permanent damage to the device. This is a stress V to GND −0.3 V to +16.5 V DD rating only; functional operation of the device at these or any V to GND −7.5 V to 0 V SS other conditions above those indicated in the operational V to V +16.5 V DD SS section of this specification is not implied. Exposure to absolute V to GND −0.3 V to +6.5 V L maximum rating conditions for extended periods may affect V , V , V to GND V to V A B W SS DD device reliability. Terminal Current, Ax to Bx, Ax to Wx, Bx to Wx Pulsed1 ±20 mA ESD CAUTION Continuous ±3 mA Digital Inputs and Output Voltage to GND −0.3 V to +7 V Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (T ) 150°C JMAX Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Thermal Resistance2 θ JA TSSOP-24 143°C/W 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation: (T − T)/θ . JMAX A JA Rev. F | Page 6 of 28

Data Sheet AD5263 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS B1 1 24 B2 A1 2 23 A2 W1 3 22 W2 AD5263 B3 4 21 B4 TOP VIEW A3 5 (Not to Scale) 20 A4 W3 6 19 W4 VDD 7 18 VSS GND 8 17 NC/O2 DIS 9 16 SDO/O1 VLOGIC 10 15 SHDN CSLDKI//SSDCAL 1112 1143 RCESS/A/ADD01 03142-072 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin Name Description 1 B1 Resistor Terminal B1. 2 A1 Resistor Terminal A1 (ADDR = 00). 3 W1 Wiper Terminal W1. 4 B3 Resistor Terminal B3. 5 A3 Resistor Terminal A3. 6 W3 Wiper Terminal W3 (ADDR = 10). 7 V Positive Power Supply, specified for +5 V to +15 V operation. DD 8 GND Ground. 9 DIS Digital Interface Select (SPI/I2C Select). SPI when DIS = 0, I2C when DIS = 1 10 V 2.7 V to 5.5 V Logic Supply Voltage. The logic supply voltage should always be less than or equal to V . In addition, logic LOGIC DD levels must be limited to the logic supply voltage regardless of V . DD 11 SDI/SDA SDI = 3-Wire Serial Data Input. SDA = 2-Wire Serial Data Input/Output. 12 CLK/SCL Serial Clock Input. 13 CS/AD0 Chip Select in SPI Mode. Device Address Bit 0 in I2C Mode. 14 RES/AD1 RESET in SPI Mode. Device Address Bit 1 in I2C Mode. 15 SHDN Shutdown. Shorts wiper to Terminal B, opens Terminal A. Tie to +5 V supply if not used. Do not tie to V if V > 5 V. DD DD 16 SDO/O1 Serial Data Output in SPI Mode. Open-drain transistor requires pull-up resistor. Digital Output O1 in I2C Mode. Can be used to drive external logic. 17 NC/O2 No Connection in SPI Mode. Digital Output O2 in I2C Mode. Can be used to drive external logic. 18 V Negative Power Supply. Specified for operation from 0 V to –5 V. SS 19 W4 Wiper Terminal W4 (ADDR = 11). 20 A4 Resistor Terminal A4. 21 B4 Resistor Terminal B4. 22 W2 Wiper Terminal W2 (ADDR = 01). 23 A2 Resistor Terminal A2. 24 B2 Resistor Terminal B2. Rev. F | Page 7 of 28

AD5263 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS R = 20 kΩ, unless otherwise noted. AB 1.0 1.0 0.8 ±5V 0.8 –+4205°°CC +15/0V +85°C 0.6 0.6 +125°C B) B) S S L 0.4 L 0.4 L ( L ( N N RHEOSTAT MODE D––000...4202 RHEOSTAT MODE I ––000...4202 –0.6 –0.6 ––10..08 03142-073 ––10..08 03142-004 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 3. R-DNL vs. Code vs. Supply Voltage Figure 6. R-INL vs. Code; VDD = ±5 V 1.0 1.0 0.8 0.8 ±+51V5/0V E INL (LSB) 000...426 ±+51V5/0V MODE INL (LSB) 000...264 T MOD 0 ETER 0 TA –0.2 OM –0.2 RHEOS ––00..64 POTENTI ––00..46 ––10..080 32 64 96 128 160 192 224 25603142-002 ––10..080 32 64 96 128 160 192 224 25603142-005 CODE (Decimal) CODE (Decimal) Figure 4. R-INL vs. Code vs. Supply Voltage Figure 7. INL vs. Code vs. Supply Voltage 1.0 1.0 E DNL (LSB) 0000....4286 –+++42810552°°°5CCC°C MODE INL (LSB) 0000....4286 –+++42810552°°°5CCC°C MOD 0 TER 0 AT –0.2 ME –0.2 T O RHEOS ––00..46 POTENTI ––00..46 ––10..08 03142-003 ––10..08 03142-007 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 5. R-DNL vs. Code; V = ±5 V Figure 8. INL vs. Code vs. Supply Voltage DD Rev. F | Page 8 of 28

Data Sheet AD5263 1.0 2.0 0.8 –+4205°°CC 1.8 VDD/VSS = +4.5/0V B) +85°C S 0.6 +125°C 1.6 L NL ( 0.4 1.4 E I VDD/VSS = ±5V OD 0.2 B) 1.2 M S ER 0 E (L 1.0 T S ME –0.2 Z 0.8 O ENTI –0.4 0.6 VDD/VSS = +16.5/0V T O –0.6 0.4 P ––10..08 03142-007 0.02 03142-010 0 32 64 96 128 160 192 224 256 –40 –20 0 20 40 60 80 100 120 CODE (Decimal) TEMPERATURE (°C) Figure 9. INL vs. Code; V = ±5 V Figure 12. Zero-Scale Error vs. Temperature DD 1.0 10 VLOGIC = 5V B) 0.8 –++428055°°°CCC VVIIHL == 05VV E DNL (LS 00..46 +125°C RENT (µA) 1 D 0.2 R MO CU ISS@ VDD/VSS = ±5V R 0 Y 0.1 METE –0.2 UPPL OTENTIO ––00..46 I/I SDDSS 0.01 IDD @ VDD/VSS = +15/0V P ––10..08 03142-008 0.001 IDD@ VDD/VSS = ±5V 03142-011 0 32 64 96 128 160 192 224 256 –40 0 40 80 120 CODE (Decimal) TEMPERATURE (°C) Figure 10. DNL vs. Code; V = ±5 V Figure 13. Supply Current vs. Temperature DD 0 10 –0.5 VDD/VSS = +16.5/0V µA) 1 T ( N E B) –1.0 RR S U FSE (L –1.5 VDD/VSS = ±5V OWN C 0.1 VDD/VSS = ±5V D T U VDD/VSS = +4.5/0V SH 0.01 –2.0 VDD/VSS = +15/0V –2.5 03142-009 0.001 03142-012 –40 –20 0 20 40 60 80 100 120 –40 0 40 80 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 11. Full-Scale Error vs. Temperature Figure 14. Shutdown Current vs. Temperature Rev. F | Page 9 of 28

AD5263 Data Sheet 27 150 C) 20kΩ m/° 100 50kΩ 26 pp 200kΩ O ( 50 C P A) 25 VDD/VSS = +15/0V TEM 0 I (µLOGIC 24 VDD/VSS = ±5V TER MODE –1–0500 E M 23 NTIO –150 E 22 03142-013 POT ––225000 03142-016 –40 0 40 80 120 0 32 64 96 128 160 192 224 256 TEMPERATURE (°C) CODE (Decimal) Figure 15. ILOGIC vs. Temperature Figure 18. Potentiometer Mode Tempco ∆RWB/∆T vs. Code 85 0 0x80 80 –6 RON @ VDD/VSS = +5/0V –12 0x40 Ω) 75 0x20 CE ( 70 –18 0x10 AN B) –24 SIST 65 RON @ VDD/VSS = ±5V N (d –30 0x08 ER RE 60 GAI –36 00xx0042 P WI RON @ VDD/VSS = +15/0V –42 55 0x01 –48 4550 03142-014 ––6504 VVTAAD D ==/ V25S50S°mC =V ±r5mVs 03142-017 –5 0 5 10 15 1k 10k 100k 1M VBIAS (V) FREQUENCY (Hz) Figure 16. Wiper On-Resistance vs. Bias Voltage Figure 19. Gain vs. Frequency vs. Code; R = 20 kΩ AB 700 0 0x80 20kΩ –6 m/°C) 500 5200k0ΩkΩ –12 0x40 O (pp 300 –18 0x20 C 0x10 ODE TEMP –110000 GAIN (dB) –––323046 00xx0048 T M 0x02 STA –300 –42 0x01 O E –48 RH ––750000 03142-015 ––5640 VVTAAD D ==/ V25S50S°mC =V ±r5mVs 03142-018 0 32 64 96 128 160 192 224 256 1k 10k 100k 1M CODE (Decimal) FREQUENCY (Hz) Figure 17. Rheostat Mode Tempco ∆RWB/∆T vs. Code Figure 20. Gain vs. Freque ncy vs. Code; RAB = 50 kΩ Rev. F | Page 10 of 28

Data Sheet AD5263 0 –6 0x80 CODE = 0x80 –12 0x40 VVDBD/V/VAS=S ± =5V±5.5V 0x20 –18 0x10 –24 B) N (d–30 0x08 1 VW AI 0x04 G–36 0x02 –42 0x01 –48 ––5640 VVTAAD D ==/ V25S50S°mC =V ±r5mVs 03142-0-019 CH1 50.0mV M100ns A CH2 2.70V 03142-022 1k 10k 100k FREQUENCY (Hz) Figure 21. Gain vs. Frequency vs. Code; R = 200 kΩ Figure 24. Digital Feedthrough AB 0 R = 20kΩ T –6 300kHz VDD/VSS = 5/0V VA= 5V –12 VB= 0V –18 R = 50kΩ 150kHz B) –24 AIN (d –30 R = 23050kkHΩz 1 G –36 VW –42 –48 ––6504 VTVADA D ==/ V25S50S°mC =V ±r5mVs 03142-020 CH1 50.0mV T20.00% M2.00µs A CH2 2.00V 03142-023 1k 10k 100k 1M FREQUENCY (Hz) Figure 22. Gain vs. Frequency at –3 db Bandwidth Figure 25. Midscale Glitch; Code 0x80 to 0x7F (4.7 nF Capacitor Used from Wiper to Ground) 80 CODE = 0x80, VA = VDD, VB = 0V VVDAD/V/VBS=S ± =5 V±5.5V 60 VW –PSRR @ VDD/VSS = ±5V DC ± 10% p-p AC B) d R (– 40 1 R PS +PSRR @ VDD/VSS = ±5V DC ± 10% p-p AC CS 20 0 03142-021 2 CH1 5.00V CH2 5.00V M400ns A CH1 2.70V 03142-024 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 23. PSRR vs. Frequency Figure 26. Large Signal Settling Time; Code 0x00 to 0xFF Rev. F | Page 11 of 28

AD5263 Data Sheet 1.0 2.0 RAB = 20kΩ RAB = 20kΩ TA = 25°C 1.5 TA = 25°C 0.5 1.0 Avg – 3σ SB) AAvvgg – 3σ LSB) 0.5 AAvvgg – 3σ INL (L 0 R-INL ( 0 Avg – 3σ –0.5 –0.5 –1.0 –1.0 03142-025 ––12..50 03142-026 0 5 10 15 20 0 5 10 15 20 |VDD – VSS| (–V) |VDD – VSS| (V) Figure 27. INL vs. Supply Voltage Figure 28. R-INL vs. Supply Voltage Rev. F | Page 12 of 28

Data Sheet AD5263 TEST CIRCUITS Figure 29 to Figure 39 define the test conditions used in the Electrical Characteristics—20 KΩ, 50 KΩ, 200 KΩ Versions section and the Timing Characteristics—20 KΩ, 50 KΩ, 200 KΩ Versions. A DUT B DUT V+= VDD 5V A 1LSB = V+/2N VIN W V+ W OFFSET OP279 VOUT B VMS 03142-028 GND OBIFAFSSET 03142-032 Figure 29. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 33. Test Circuit for Inverting Gain 5V NO CONNECT ADUT IW VIN W OP279 VOUT W OFFSET B GND A DUT B VMS 03142-029 OBIFAFSSET 03142-033 Figure 30. Test Circuit for Resistor Position Nonlinearity Error Figure 34. Test Circuit for Noninverting Gain (Rheostat Operation; R-INL, R-DNL) A DUT +15V IW= VDD/RNOMINAL W VMS2 A W VW OFFSET VIN DUT AD8610 VOUT B VMS1 RW= [VMS1– VMS2]/IW 03142-030 GND 2.5V B –15V 03142-034 Figure 31. Test Circuit for Wiper Resistance Figure 35. Test Circuit for Gain vs. Frequency 0.1V VA DUT RSW= ISW V+ = VDD 10% ΔVMS W CODE = 0x00 PSRR (dB) = 20 log V+ VDD A W PSS (%/%) =ΔVMS% ΔVDD B ISW 0.1V B ΔVDD% VMS 03142-031 VSSTO VDD 03142-035 Figure 32. Test Circuit for Power Supply Sensitivity (PSS, PSRR) Figure 36. Test Circuit for Incremental On Resistance Rev. F | Page 13 of 28

AD5263 Data Sheet NC A1 VDD A2 RDAC1 RDAC2 DVVUDSDTS GNDNCAB W IVCCMM 03142-036 VIN N/CCTAW =1 20B l1og V[VSOSUT/VIN]WB22 VOUT03142-038 Figure 37. Test Circuit for Common-Mode Leakage Current Figure 39. Test Circuit for Analog Crosstalk ILOGIC VLOGIC SCL SCA 03142-037 Figure 38. Test Circuit for V Current vs. Digital Input Voltage LOGIC Rev. F | Page 14 of 28

Data Sheet AD5263 SPI-COMPATIBLE DIGITAL INTERFACE (DIS = 0) SERIAL DATA-WORD FORMAT MSB LSB Addr Data B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 29 27 20 1 SDI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 RDAC REGISTER LOAD CS 0 VOUT 10 03142-039 Figure 40. AD5263 Timing Diagram (V = 5 V, V = 0 V, V = V ) A B W OUT 1 SDI Dx Dx (DATA IN) 0 tDS tCH tCH tCS1 1 CLK 0 tCSHO tCL tCSH1 tCSS 1 CS tC-SW 0 tS VOUTVDD0 ±LSB 03142-040 Figure 41. Detailed SPI Timing Diagram (V = 5 V, V = 0 V, V = V ) A B W OUT Rev. F | Page 15 of 28

AD5263 Data Sheet I2C-COMPATIBLE DIGITAL INTERFACE (DIS = 1) The word format maps in this section use the following abbreviations. Abbreviation Description S Start condition. P Stop condition. A Acknowledge. AD1, AD0 I2C device address bits. Must match with the logic states at Pin AD1 and Pin AD0. Refer to Figure 49. A1, A0 RDAC channel select. RS Software reset wiper (A1, A0) to midscale position. SD Shutdown active high; ties wiper (A1, A0) to Terminal B, opens Terminal A, RDAC register contents are not disturbed. To exit shutdown, the command SD = 0 must be executed for each RDAC (A1, A0). O1, O2 Data to digital output pins, Pin O1 and Pin O2 in I2C mode, used to drive external logic. The logic high level is determined by V and the logic low level is GND. L W Write = 0. R Read = 1. D7, D6, D5, D4, D3, Data bits. D2, D1, D0 X Don’t care. I2C WRITE MODE DATA-WORD FORMAT S 0 1 0 1 1 AD1 AD0 W A X A1 A0 RS SD O1 O2 X A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Instruction Byte Data Byte I2C READ MODE DATA-WORD FORMAT S 0 1 0 1 1 AD1 AD0 R A D7 D8 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte t8 t9 t2 SCL t2 t3 t4 t7 t5 t10 t8 t9 SDA t1 03142-041 P S S P Figure 42. Detailed I2C Timing Diagram 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W X A1 A0 RS SD O1 O2 X D7 D6 D5 D4 D3 D2 D1 D0 ACK BY ACK BY ACK BY STMAARSTT EBRY SLAVE FARDADMREE S1S BYTE AD5263 INSTRFURCATMIOEN 1 BYTE AD5263 DFARTAAMBEY T1E AD52SM6T3AOSPT EBRY 03142-042 Figure 43. Writing to the RDAC Register 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 ACK BY NO ACK STMAARSTT EBRY SLAVE FARDADMREE S1S BYTE AD5263 RDAFCR RAEMGEI S2TER BY MASTSMETRAOSPT EBRY 03142-043 Figure 44. Reading Data from a Previously Selected RDAC Register in Write Mode Rev. F | Page 16 of 28

Data Sheet AD5263 OPERATION The AD5263 is a quad-channel, 256-position, digitally (R – 1 LSB + 2 × R ). Figure 45 shows a simplified diagram of AB W controlled, variable resistor (VR) device. the equivalent RDAC circuit, where the last resistor string is not accessed; therefore, there is 1 LSB less of the nominal resistance at To program the VR settings, refer to the SPI-Compatible Digital full scale in addition to the wiper resistance. Interface (DIS = 0) section and the I2C-Compatible Digital Interface (DIS = 1) section. The part has an internal power-on The general equation determining the digitally programmed preset that places the wiper at midscale during power-on, output resistance between the W and B terminals is simplifying the fault condition recovery at power-up. In addition, D the shutdown (SHDN) pin of AD5263 places the RDAC in an RWB(D)= 256×RAB+2×RW (1) almost zero-power consumption state where Terminal A is where: open circuited and the wiper W is connected to Terminal B, D is the decimal equivalent of the binary code loaded in the 8-bit resulting in only leakage current consumption in the VR structure. RDAC register. During shutdown, the VR latch settings are maintained or new R is the end-to-end resistance. settings can be programmed. When the part is returned from AB R is the wiper resistance contributed by the on-resistance of one shutdown, the corresponding VR setting is applied to the RDAC. W internal switch. Ax In summary, if R = 20 kΩ and the A terminal is open circuited, SD BIT AB the RDAC latch codes in Table 5 result in the corresponding output RS resistance, R . D7 WB D6 D5 RS Table 5. Codes and Corresponding R Resistances D4 WB D3 D (Dec) R (Ω) Output State D2 RS WB D1 D0 Wx 255 20,042 Full-scale (RAB − 1 LSB + 2 × RW) 128 10,120 Midscale RDAC 1 198 1 LSB + 2 × R W LATCH 0 120 Zero-scale (wiper contact resistance) AND DECODER RS Bx Note that in the zero-scale condition a finite wiper resistance of 03142-044 1b2et0w Ωee ins pWre asenndt .B C inar teh sihs osutaltde btoe taa mkeanx itmo luimmi pt uthlsee c cuurrrreenntt f olofw Figure 45. AD5263 Equivalent RDAC Circuit no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation Similar to the mechanical potentiometer, the resistance of the RDAC between the W wiper and Terminal A also produces a The nominal resistance of the RDAC between Terminal A and digitally controlled complementary resistance, R . When these Terminal B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final WA terminals are used, the B terminal can be opened. Setting the two or three digits of the part number determine the nominal resistance value for R starts at a maximum value of resistance resistance value, for example, 20 kΩ = 20; 50 kΩ = 50; WA and decreases as the data loaded in the latch increases in value. 200 kΩ = 200. The nominal resistance (R ) of the VR has AB The general equation for this operation is 256 contact points accessed by the wiper terminal, plus the B 256−D terminal contact. The 8-bit data in the RDAC latch is decoded to R (D)= ×R +2×R (2) select one of the 256 possible settings. Assuming a 20 kΩ part is WA 256 AB W used, the wiper’s first connection starts at the B terminal for data For R = 20 kΩ and the B terminal is open circuited, the RDAC 0x00. Because there is a 60 Ω wiper contact resistance, such a AB latch codes in Table 6 result in the corresponding output connection yields a minimum of 2 × 60 Ω resistance between the resistance R . WA W and B terminals. The second connection is the first tap point, Table 6. Codes and Corresponding R Resistances and corresponds to 198 Ω (R = R /256 + R = 78 Ω + 2 × WA WB AB W D (Dec) R (Ω) Output State 60 Ω) for Data 0x01. The third connection is the next tap point WA representing 276 Ω (R = 78 Ω × 2 + 2 × 60 Ω) for Data 0x02, 255 198 Full scale WB 128 10,120 Midscale and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 20,042 Ω 1 20,042 1 LSB + 2 × RW 0 20,120 Zero scale Rev. F | Page 17 of 28

AD5263 Data Sheet The typical distribution of the end-to-end resistance R from SPI-COMPATIBLE 3-WIRE SERIAL BUS (DIS = 0) AB channel to channel matches within ±1%. Device-to-device The AD5263 contains a 3-wire SPI-compatible digital interface matching is process-lot dependent, and it is possible to have (SDI, CS, and CLK). The 10-bit serial word must be loaded with ±30% variation. Because the resistance element is processed in address bits A1 and A0, followed by the data byte, MSB first. The thin film technology, the change in R with temperature has a AB format of the word is shown in the Serial Data-Word Format very low temperature coefficient of 30 ppm/°C. section and bit map. PROGRAMMING THE POTENTIOMETER DIVIDER The positive-edge sensitive CLK input requires clean transitions VOLTAGE OUTPUT OPERATION to avoid clocking incorrect data into the serial input register. The digital potentiometer easily generates a voltage divider at Standard logic families work well. If mechanical switches are wiper-to-B and wiper-to-A proportional to the input voltage from used for product evaluation, they should be debounced by a Terminal A and Terminal B. Unlike the polarity from VDD to VSS, flip-flop or other suitable means. When CS is low, the clock which must be positive, the voltage across A to B, W to A, and loads data into the serial register on each positive clock edge W to B can be at either polarity, if VSS is powered by a negative (see Figure 40). supply. Table 7. AD5263 Address Decode Table If the effect of the wiper resistance for approximation is ignored, A1 A0 Latch Loaded connecting the A terminal to 5 V and the B terminal to ground 0 0 RDAC 1 produces an output voltage from the wiper to B, starting at 0 V 0 1 RDAC 2 up to 1 LSB below 5 V. Each LSB step of voltage is equal to the 1 0 RDAC 3 voltage applied across Terminal A to Terminal B divided by the 1 1 RDAC 4 256 positions of the potentiometer divider. Because the AD5263 The data setup and data hold times in the specification table can be powered by dual supplies, the general equation defining determine the valid timing requirements. The AD5263 uses a the output voltage V with respect to ground for any valid input W 10-bit serial input data register word that is transferred to the voltages applied to Terminal A and Terminal B is internal RDAC register when the CS line returns to logic high. D 256−D Note that only the last 10 bits that are clocked into the register V (D)= V + V (3) W A B 256 256 are latched into the decoder. As CS goes high, it activates the address decoder and updates the corresponding channel Operation of the digital potentiometer in the divider mode according to Table 7. results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on During shutdown (SHDN), the serial data output (SDO) pin is the ratio of the internal resistances RWA and RWB, and not their forced to logic high in order to avoid power dissipation in the absolute values; therefore, the temperature drift reduces to external pull-up resistor. For an equivalent SDO output circuit 5 ppm/°C. schematic, see Figure 46. PIN-SELECTABLE DIGITAL INTERFACE SHDN The AD5263 provides the flexibility of a selectable interface. CS SDO When the digital interface select (DIS) pin is tied low, the SPI SDI SERIAL D Q REGISTER mode is engaged. When the DIS pin is tied high to the V supply, the I2C mode is engaged. L RCELKS CK RS 03142-045 Figure 46. Detailed SDO Output Schematic of the AD5263 During reset (RES), the wiper is set to midscale. Note that unlike SHDN, when the part is taken out of reset, the wiper remains at midscale and does not revert to its pre-reset setting. Rev. F | Page 18 of 28

Data Sheet AD5263 Daisy-Chain Operation The 2-wire I2C serial bus protocol operates as follows. The serial data output (SDO) pin contains an open-drain 1. The master initiates a data transfer by establishing a N-channel FET. This output requires a pull-up resistor in order START condition, which is when a high-to-low transition to transfer data to the SDI pin of the next package. This allows on the SDA line occurs while SCL is high (see Figure 43). for daisy-chaining several RDACs from a single processor serial The following byte is the slave address byte, which consists data line. The pull-up resistor termination voltage can be greater of the 7-bit slave address followed by an R/W bit. This R/W than the V supply voltage. It is recommended to increase the DD bit determines whether data will be read from or written to clock period when using a pull-up resistor to the SDI pin of the the slave device. following device because capacitive loading at the daisy-chain node (SDO to SDI) between devices may induce time delay to subsequent The slave whose address corresponds to the transmitted devices. Users should be aware of this potential problem to achieve address responds by pulling the SDA line low during the data transfer successfully (see Figure 47). If two AD5263s are ninth clock pulse (this is termed the acknowledge bit). At daisy-chained, a total of 20 bits of data is required. The first 10 bits, this stage, all other devices on the bus remain idle while the complying with the format shown in the Serial Data-Word Format selected device waits for data to be written to or read from section and bit map, go to U2 and the second 10 bits, with the its serial register. If the R/W bit is high, the master reads same format, go to U1. CS should be kept low until all 20 bits are from the slave device. If the R/W bit is low, the master clocked into their respective serial registers. After this, CS is pulled writes to the slave device. high to complete the operation and load the RDAC latch. Data 2. In write mode, the second byte is the instruction byte. The appears on SDO on the negative edge of the clock, thus making first bit (MSB) of the instruction byte is a don’t care. The it available to the input of the daisy-chained device on the rising following two bits, labeled A1 and A0, are the RDAC edge of the next clock. subaddress select bits. VL The fourth MSB (RS) is the midscale reset. A logic high on this bit moves the wiper of the selected channel to the center SPI ADU51263 RP ADU52263 tap where RWA = RWB. This feature effectively writes over MOSI SDI SDO 2.2kΩ SDI SDO the contents of the register, so that when taken out of reset CLK CS CSCLK CS CLK mode, the RDAC remains at midscale. The fifth MSB (SD) is the shutdown bit. A logic high causes 03142-046 the selected channel to open circuit at Terminal A while shorting the wiper to Terminal B. This operation yields Figure 47. Daisy-Chain Configuration almost 0 Ω in rheostat mode or 0 V in potentiometer I2C-COMPATIBLE 2-WIRE SERIAL BUS (DIS = 1) mode. This SD bit serves the same function as the SHDN In the I2C-compatible mode, the RDACs are connected to the pin except that the SHDN pin reacts to active low. In bus as slave devices. addition, the SHDN pin affects all channels, as opposed to the SD bit, which affects only the channel being written to. Referring to the bit maps in the I2C-Compatible Digital It is important to note that the shutdown operation does Interface (DIS = 1) section, the first byte of the AD5263 is a not disturb the contents of the register. When brought out slave address byte, consisting of a 7-bit slave address and a R/W of shutdown, the previous setting is applied to the RDAC. bit. The five MSBs are 01011 and the following two bits are The next two bits are O2 and O1. They are extra programmable determined by the state of the AD0 and AD1 pins of the device. logic outputs that can be used to drive other digital loads, AD0 and AD1 allow the user to place up to four of the I2C- logic gates, LED drivers, analog switches, etc. compatible devices on one bus. The LSB is a don’t care bit (see the bit map in the I2C Write Mode Data-Word Format section). After acknowledging the instruction byte, the last byte in write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 43). Rev. F | Page 19 of 28

AD5263 Data Sheet 3. In read mode, the data byte follows immediately after the • Do not complete the write cycle by not issuing the stop, acknowledgment of the slave address byte. Data is transmitted then start, slave address byte, acknowledge, instruction over the serial bus in sequences of nine clock pulses (a slight byte with O1 and O2 specified, acknowledge, stop. difference with the write mode, where there are eight data SELF-CONTAINED SHUTDOWN FUNCTION bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and Shutdown can be activated by strobing the SHDN pin or remain stable during the high period of SCL (see Figure 44). programming the SD bit in the write mode instruction byte. In addition, shutdown can even be implemented with the device’s Note that the channel of interest is the one that was digital output, as shown in Figure 48. In this configuration, the previously selected in write mode. In cases where users device is shut down during power-up, but users are allowed to need to read the RDAC values of both channels, they must program the device. Thus, when O1 is programmed high, the program the first channel in write mode and then change device exits from the shutdown mode and responds to the new to read mode to read the first channel value. After that, setting. This self-contained shutdown function allows absolute they must change back to write mode with the second channel shutdown during power-up, which is crucial in hazardous selected and read the second channel value in read mode environments, without adding extra components. again. It is not necessary for users to issue the Frame 3 data byte in the write mode for subsequent readback operation. O1 Refer to Figure 44 for the programming format. SHDN 4. After all data bits have been read or written, a stop condition is RPULL-DOWN AD5263 established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. Itenn wthr ictelo mcko pdue,l steh teo m esatsatberli sphu lal ss ttohpe ScDonAd iltinioen h (isgehe dFuigruinrge 4th3e) . SSDCAL 03142-047 In read mode, the master issues a no acknowledge for the Figure 48. Shutdown by Internal Logic Output ninth clock pulse (that is, the SDA line remains high). The If the shutdown function is enabled by using the SD bit, see the I2C master then brings the SDA line low before the tenth clock Write Mode Data-Word Format section. Table 8 and Table 9 pulse, which goes high to establish a stop condition (see show the sequences that can place any channel in an undesirable Figure 44). shutdown state. A repeated write function gives the user flexibility to update the Table 8. Direct Sequence RDAC output a number of times after addressing and instructing Command Sequence RDAC Shutdown the part only once. For example, after the RDAC has acknowledged Write RDAC 1, SHDN RDAC 2 RDAC1 and RDAC2 its slave address and instruction bytes in the write mode, the Write RDAC 2, SHDN RDAC 1 RDAC1 and RDAC2 RDAC output updates on each successive byte. If different Write RDAC 3, SHDN RDAC 4 RDAC3 and RDAC4 instructions are needed, the write/read mode has to start again Write RDAC 4, SHDN RDAC 3 RDAC3 and RDAC4 with a new slave address, instruction, and data byte. Similarly, a To overcome the issue, employ the following sequence, as an repeated read function of the RDAC is also allowed. example for the first case: ADDITIONAL PROGRAMMABLE LOGIC OUTPUT • Start, slave address byte, acknowledge, instruction byte The AD5263 features additional programmable logic outputs, O1 (write RDAC1), acknowledge, data byte, acknowledge, stop. and O2, which can be used to drive a digital load, analog switches, • Start, slave address byte, acknowledge, instruction byte and logic gates. O1 and O2 default to Logic 0. The voltage level can (write RDAC1), acknowledge, stop. swing from GND to V . The logic states of O1 and O2 can be L programmed in Frame 2 under write mode (see Figure 43). These • Start, slave address byte, acknowledge, instruction byte logic outputs have adequate current driving capability to (SHDN RDAC2), acknowledge, data byte, acknowledge, stop. sink/source milliamperes of load. Table 9. Indirect Sequence Command Sequence RDAC Shutdown Users can also activate O1 and O2 in three different ways without Write RDAC 1, SHDN RDAC 1, SHDN RDAC 4 RDAC1, RDAC3, affecting the wiper settings. They may do the following: and RDAC4 • Start, slave address byte, acknowledge, instruction byte Write RDAC 3, SHDN RDAC 3, SHDN RDAC 2 RDAC1, RDAC2, with O1 and O2 specified, acknowledge, Stop. and RDAC3 • Complete the write cycle with stop, then start, slave address To overcome this issue, swap the SHDN order command, for byte, acknowledge, instruction byte with O1 and O2 example, write RDAC 1, SHDN RDAC 4, and then SHDN specified, acknowledge, stop. RDAC 1. Rev. F | Page 20 of 28

Data Sheet AD5263 MULTIPLE DEVICES ON ONE BUS +5V VIN 0V R3 Figure 49 shows four AD5263 devices on the same serial bus. Each 1kΩ Q1 has a different slave address because the states of their AD0 and 2N3906 Q2 2N3906 AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device VOUT output bus line drivers are open-drain, pull-downs in a fully R1 R2 10kΩ 10kΩ I2C-compatible interface. +5V –5V –5V –50VV 03142-051 Figure 51. Level Shift for Bipolar Potential Operation RP RP ESD PROTECTION SDA All digital inputs are protected with a series input resistor and MASTER parallel Zener ESD structures shown in Figure 52 and Figure 53. SCL This protection applies to digital input pins SDI/SDA, CLK/SCL, 5V 5V 5V SDA SCL SDA SCL SDA SCL SDA SCL CS/AD0, RES/AD1, and SHDN. AD1 AD1 AD1 AD1 AADD0F5ig2u6r3e 49. MultipAAleDD 0A5D2562363 DevicAAeDsD 0o5n2 6O3ne I2C BuAAsD D05263 03142-048 34V0SΩS LOGIC 03142-052 LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION Figure 52. ESD Protection of Digital Pins The digital potentiometer is popular in laser diode driver and A,B,W cTehretasien a tpepleliccoamtiomnus naricea stoiomne etqimuiepsm openetr aletevde lb-seettwtienegn a gprpoluicnadti oannds. VSS 03142-053 some negative supply voltage so that the systems can be biased Figure 53. ESD Protection of Resistor Terminals at round to avoid large bypass capacitors that may significantly TERMINAL VOLTAGE OPERATING RANGE impede the ac performance. Like most digital potentiometers, the AD5263 can be configured with a negative supply (see Figure 50). The AD5263 positive V and negative V power supply defines DD SS the boundary conditions for proper 3-terminal digital VDD potentiometer operation. Supply signals present on the A, B, AD5263 and W terminals that exceed V or V are clamped by the DD SS VSS internal forward-biased diodes shown in Figure 54. –5V GND VDD LEVEL SHIFTED SDA LEVEL SHIFTED SCL 03142-050 A Figure 50. Biased at Negative Voltage W However, the digital inputs must also be level shifted to allow B pprootpenert ioapl.e Arast iao nre bsueclta, uFsieg tuhree g5r1o ushnodw iss roenfeer einmcpedle mto etnhtet anteigoant ive VSS 03142-054 Figure 54. Maximum Terminal Voltages Set by V and V with a couple of transistors and a few resistors. When V is DD SS IN high, Q1 is turned on and its emitter is clamped at one threshold POWER-UP SEQUENCE above ground. This threshold appears at the base of Q2, which Because the ESD protection diodes limit the voltage compliance causes Q2 to turn off. In this state, V approaches −5 V. When OUT at the A, B, and W terminals (see Figure 54), it is important to V is low, Q1 is turned off and the base of Q2 is pulled low, which IN power V and V before applying any voltage to the A, B, and in turn causes Q2 to turn on. In this state, V approaches 0 V. DD SS OUT W terminals; otherwise, the diodes are forward biased such that Beware that proper time shifting is also needed for successful V and V are powered unintentionally and may affect the rest communication with the device. DD SS of the circuit. The ideal power-up sequence is in the following order: GND, V , V , V , digital inputs, and V . The relative DD SS L A/B/W order of powering V , V, V , and digital inputs is not important as A B W long as they are powered after V and V . DD SS Rev. F | Page 21 of 28

AD5263 Data Sheet V POWER SUPPLY RDAC CIRCUIT SIMULATION MODEL LOGIC The AD5263 is capable of operating at high voltages beyond the The internal parasitic capacitances and the external capacitive loads internal logic levels, which are limited to operation at 5 V. As a dominate the ac characteristics of the RDACs. Configured as a result, V always needs to be tied to a separate 2.7 V to 5.5 V source potentiometer divider, the –3 dB bandwidth of the AD5263 (20 kΩ L to ensure proper digital signal levels. Logic levels must be limited to resistor) measures 300 kHz at half scale. Figure 22 provides the V , regardless of V . In addition, V should always be less than large signal BODE plot characteristics of the three available L DD L or equal to V . resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation DD model is shown in Figure 56. The following code provides a LAYOUT AND POWER SUPPLY BYPASSING macro model net list for the 20 kΩ RDAC. It is a good practice to employ compact, minimum-lead length RDAC layout design. The leads to the input should be as direct as possible 20kΩ A B with a minimum conductor length. Ground paths should have CA CB low resistance and low inductance. 25pF 25pF CW Similarly, it is also a good practice to bypass the power supplies wthieth d qevuiacleit syh coaupladc biteo rbsy fpoars osepdti mwiuthm 0 s.0ta1b µilFit yt.o S 0u.p1 pµlFy lceeardasm tioc W 55pF 03142-069 disc or chip capacitors. Low ESR 1 µF to 10 µF tantalum or Figure 56. RDAC Circuit Simulation Model for RDAC = 20 kΩ electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple Listing 1. Macro Model Net List for RDAC (see Figure 55). Notice the digital ground should also be joined .PARAM D=256, RDAC=20E3 remotely to the analog ground at one point to minimize the * ground bounce. .SUBCKT DPOT (A,W,B) * VDD VDD CA A 0 25E-12 RWA A W {(1-D/256)*RDAC+60} C3 + C1 10µF 0.1µF CW W 0 55E-12 AD5263 RWB W B {D/256*RDAC+60} C4 + C2 CB B 0 25E-12 10µF 0.1µF * VSS VSS GND .ENDS DPOT 03142-055 Figure 55. Power Supply Bypassing Rev. F | Page 22 of 28

Data Sheet AD5263 APPLICATIONS INFORMATION BIPOLAR DC OR AC OPERATION FROM DUAL Depending on the op amp GBP, reducing the feedback resistor SUPPLIES may extend the zero’s frequency far enough to overcome the problem. A better approach is to include a compensation capacitor The AD5263 can be operated from dual supplies, enabling C2 to cancel the effect caused by C1. Optimum compensation control of ground referenced ac signals or bipolar operation. occurs when R1 × C1 = R2 × C2. This is not an option, because The ac signal, as high as V /V , can be applied directly across DD SS of the variation of R2. As a result, one may use the relationship Terminal A to Terminal B, with the output taken from Terminal W. described and scale C2 as if R2 is at its maximum value. Doing +5.0V so may overcompensate and compromise the performance slightly when R2 is set at low values. However, it avoids the gain peaking, VDD VDD µC SCLK SCL A1 ±5V p-p ringing, or oscillation in the worst case. For critical applications, ±2.5V p-p C2 should be found empirically to suit the need. In general, C2 GND MCSI SDA W1 in the range of a few pF to no more than a few tenths of pF is B1 D = 0x90 A2 usually adequate for the compensation. GND W2 Similarly, there are W and A terminal capacitances connected to B2 AD5263 VSS the output (not shown); fortunately, their effect at this node is less _5.0V 03142-056 PsigRnOifiGcaRntA aMndM thAe BcoLmEp VenOsaLtiTonA cGanE bReE dFisEreRgaErNdeCdE in most cases. Figure 57. Bipolar Operation from Dual Supplies For voltage divider mode operation (Figure 59), it is common to GAIN CONTROL COMPENSATION buffer the output of the digital potentiometer unless the load is A digital potentiometer is commonly used in gain control such much larger than R . Not only does the buffer serve the purpose WB as the noninverting gain amplifier shown in Figure 58. of impedance conversion, but it also allows a heavier load to be driven. C2 4.7pF 5V R2 AD5263 200kΩ 1 U1 B A VIN 3 5V W VOUT R1 47kΩ AD1582 A W C1 25pF U1 VO GND B AD8601 VO VI 03142-057 A1 03142-058 Figure 58. Typical Noninverting Gain Amplifier Figure 59. Programmable Voltage Reference Notice the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node. It introduces a zero for the 1/β o term with +20 dB/dec, whereas a typical op amp GBP has −20 dB/dec characteristics. A large R2 and finite C1 can cause this zero’s frequency to fall well below the crossover frequency. Thus, the rate of closure becomes 40 dB/dec and the system has 0° phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values, because this is equivalent to a step change at the input. Rev. F | Page 23 of 28

AD5263 Data Sheet 8-BIT BIPOLAR DAC Similar to the previous example, in the simpler (and much more usual) case where K = 1, a single channel is used and U1 is Figure 60 shows a low cost, 8-bit, bipolar DAC. It offers the replaced by a matched pair of resistors to apply V and –V at same number of adjustable steps, but not the precision as compared I I the ends of the digital potentiometer. The relationship becomes to conventional DACs. The linearity and temperature coefficient, especially at low values codes, are skewed by the effects of the  R2 2×D2  V =1+ × −1×V (6) digital potentiometer wiper resistance. The output of this circuit is O  R1  256  I 2D  V = −1×V (4) If R2 is large, a compensation capacitor of a few pF may be O 256  REF needed to avoid any gain peaking. +15V Table 10 shows the result of adjusting D, with A2 configured with unity gain, gain of 2, and gain of 10. The result is a bipolar amplifier V+ with linearly programmable gain and 256-step resolution. AD5263 OP2177 VO VI W V– Table 10. Result of Bipolar Gain Amplifier A2 D R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1 1 U1 B A VIN –15V 0 –1 –2 –10 VOUT –5VREF ADR425 +5VREF +15V 64 –0.5 –1 –5 TRIM 128 0 0 0 GND 192 0.5 1 5 V+ OP2177 255 0.968 1.937 9.680 V– A1 03142-059 PBROOOGSRTEADM OMUATBPLUET V OLTAGE SOURCE WITH Figure 60. 8-Bit Bipolar DAC For applications that require high current adjustment, such as a BIPOLAR PROGRAMMABLE GAIN AMPLIFIER laser diode driver or tunable laser, a boosted voltage source can be considered. See Figure 62. For applications requiring bipolar gain, Figure 61 shows one implementation similar to the previous circuit. The digital U3 2N7002 VIN VOUT potentiometer U1 sets the adjustment range. The wiper voltage U1 at W2 can therefore be programmed between VI and –KVI at a AD5263 +V CC RBIAS given U2 setting. Configuring A2 in the noninverting mode A W U2 IL SIGNAL allows linear gain and attenuation. The transfer function is B AD8601 LD VVO =1+RR21×2D526×(1+K)−K (5) –V 03142-061 I Figure 62. Programmable Booster Voltage Source where K is the ratio of RWB1/RWA1 set by U1. In this circuit, the inverting input of the op amp forces the VOUT to be equal to the wiper voltage set by the digital potentiometer. The VDD load current is then delivered by the supply via the N-channel FET, N1. N1 power handling must be adequate to dissipate power U2 AD5263 W2 OPV2+177 VO equal to (VIN − VOUT) × IL. This circuit can source a maximum of V– 100 mA with a 5 V supply. For precision applications, a voltage A2 B2 C1 R2 reference such as ADR421 or ADR03 can be applied at the A A2 VI A1 B1 –KVI VSS terminal of the digital potentiometer. R1 W1 VDD U1 AD5263 V+ OP2177 V– A1 VSS 03142-060 Figure 61. Bipolar Programmable Gain Amplifier Rev. F | Page 24 of 28

Data Sheet AD5263 PROGRAMMABLE 4 TO 20 MA CURRENT SOURCE PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE A programmable 4–20 mA current source can be implemented with the circuit shown in Figure 63. The REF191 is a unique low For applications that require bidirectional current control or supply headroom and high current handling precision reference higher voltage compliance, a Howland current pump can be a that can deliver 20 mA at +2.048 V. The load current is simply solution (see Figure 64). If the resistors are matched, the load the voltage across Terminal B to Terminal W of the digital current is potentiometer divided by RS: (R2A+R2B) R1 I = ×V (8) I =VREF ×D (7) L R2B W L RS ×2N R1 R2 150kΩ 15kΩ +5V 2 U1 C1 VIN 0 TO (2.048V + VL) +15V 10pF 6 VOUT 3 B S4GRLNEEDFEP191 C1µ1F A+D5V5263 AW RS A+5V +15V C2 OPVV2+–177A2 R502ΩB 102Ω AD5263 10pF –15V U2 W V+ –2.048V TO VL O–P5VV8V–+510 R10L0VΩL IL 03142-062 –5VFigure 6O4–.P1 PV52rV–1o7gA7r1ammab1le5R 0B1kiΩdirectional C14uR.9r2r5eAknΩt SourR5c0Le0 ΩVL |L 03142-063 Figure 63. Programmable 4–20 mA Current Source R2B, in theory, can be made as small as needed to achieve the The circuit is simple, but beware of two things. First, dual-supply current needed within the A2 output current driving capability. op amps are ideal because the ground potential of the REF191 In this circuit, OP2177 can deliver ±5 mA in either direction, can swing from −2.048 V at zero scale to VL at full scale of the and the voltage compliance approaches +15 V. It can be shown potentiometer setting. Although the circuit works with a single that the output impedance is supply, the programmable resolution of the system is reduced. R1′×R2B(R1+R2A) Z = (9) For applications that demand higher current capabilities, a few o R1×R2′−R1′(R2A+R2B) changes to the circuit in Figure 63 produce an adjustable current in This output impedance can be infinite if resistors R1′ and R2′ the range of hundreds of mA. First, the voltage reference needs match precisely with R1 and R2A + R2B, respectively. On the to be replaced with a high current, low dropout regulator, such other hand, it can be negative if the resistors are not matched. as the ADP3333, and the op amp needs to be swapped with a As a result, C1 in the range of 1 pF to 10 pF is needed to prevent high current, dual-supply model, such as the AD5263. Depending oscillation. on the desired range of current, an appropriate value for R S must be calculated. Because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp past the positive rail. Rev. F | Page 25 of 28

AD5263 Data Sheet PROGRAMMABLE LOW-PASS FILTER At resonance, setting In analog-to-digital conversion applications, it is common to R2 =2 (15) include an antialiasing filter to band-limit the sampling signal. R1 Dual-channel digital potentiometers can be used to construct a balances the bridge. In practice, R2/R1 should be set slightly second-order Sallen-Key low-pass filter (see Figure 65). The design greater than 2 to ensure that the oscillation can start. On the equations are other hand, the alternating turn-on of the diodes D1 and D2 VO = ωO2 (10) ensures that R2/R1 is momentarily less than 2, thereby ω VI S2+ O S+ω 2 stabilizing the oscillation. O Q Once the frequency is set, the oscillation amplitude can be 1 tuned by R2B because ω = (11) O R1×R2×C1×C2 2 V =I ×R2B+V (16) O D D 1 1 3 Q = + (12) R1×C1 R2×C2 V , I , and V are interdependent variables. With proper selection O D D Users can first select some convenient values for the capacitors. of R2B, an equilibrium is reached such that VO converges. R2B To achieve maximally flat bandwidth where Q = 0.707, let C1 be can be in series with a discrete resistor to increase the amplitude, twice the size of C2, and let R1 = R2. As a result, the user can adjust but the total resistance should not be so large that it saturates R1 and R2 to the same settings to achieve the desired bandwidth. the output. C1 FREQUENCY ADJUSTMENT C R’ C +2.5V VP 2.2nF 10kΩ R1 R2 VI A WB A WB AD86V0+1 VO 2.2nF 10kΩRBA W +2.5V AW B R R V–U1 V+ U1 C2 C –2.5V OP1177 VO SAADMJUE SSTEETDTITNOG 03142-064 RD11 == RD12 ’ == 1RN24B1 4=8AD5263 –2.5VV– VN Figure 65. Sallen-Key Low-Pass Filter R2A R2B 2.1kΩ D1 PROGRAMMABLE OSCILLATOR 10kΩ R1 B A D2 In a classic Wien bridge oscillator (Figure 66), the Wien network 1kΩ W n(Reg, Rat′i,v Ce ,f eCe′d) bparcokv.i dAets t phoe srietisvoen faenetd fbraecqku,e wnchyil, ef OR, 1th aen odv Rer2a lpl rpohvaidsee AAMDJPULSITTUMDEENT 03142-065 shift is zero, and the positive feedback causes the circuit to oscillate. Figure 66. Programmable Oscillator with Amplitude Control With R = R′, C = C′, and R2 = R2A||(R2B + R ), the oscillation DIODE frequency is 1 1 ω = , or f = (13) O RC O 2πRC where R is equal to R , such that WA 256−D R= R (14) AB 256 Rev. F | Page 26 of 28

Data Sheet AD5263 RESISTANCE SCALING RESISTANCE TOLERANCE, DRIFT, AND The AD5263 offers 20 kΩ, 50 kΩ, and 200 kΩ nominal resistances. TEMPERATURE COEFFICIENT MISMATCH Users who need a lower resistance and the same number of step CONSIDERATIONS adjustments can place multiple devices in parallel. For example, In rheostat mode operation, such as the gain control circuit of Figure 67 shows a simple scheme of using two channels in parallel. Figure 70, the tolerance mismatch between the digital potent- To adjust half of the resistance linearly per step, users need to iometer and the discrete resistor can cause repeatability issues program both channels to the same settings. among various systems. Because of the inherent matching of the VDD silicon process, it is practical to apply the multichannel device in this type of application. As such, R1 should be replaced by one of the channels of the digital potentiometer. R1 should be A1 A2 programmed to a specific value while R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes W1 W2 B1 B2 the tolerance and temperature coefficient mismatch between R1 LED 03142-066 aonvder R t2im. Ien. aAdsd ait iroensu, tlht,i st haepsper onaocnhi dalesaol tpraarcakms tehtee rrse sbisetcaonmcee d lreisfst Figure 67. Reduce Resistance by Half with Linear Adjustment Characteristics sensitive to system variations. R2 Applicable only to the voltage divider mode, by connecting a B A discrete resistor in parallel as shown in Figure 68, a proportionately W lower voltage appears at Terminal A. This translates into a finer degree of precision because the step size at Terminal W is smaller. R11 C1 – The voltage can be found as AD8601 VO VW(D)= 2D56×R2+(VRDADB ||R1)×(RAB ||R1) (17) 1REPLACED WVIITHAN+OTHEUR1 CHANNEL OF RDAC03142-070 Figure 70. Linear Gain Control with Tracking Resistance Tolerance and Drift VDD Notice that the circuit in Figure 71 can also be used to track the R2 tolerance, temperature coefficient, and drift in this particular A application. However, the characteristics of the transfer function R1 W change from a linear to a pseudologarithmic gain function. R R1 << RBAB 03142-067 AW B C1 Figure 68. Decreasing Step Size by Lowering the Nominal Resistance – V+ pFiogtuenret i6o7m aentedr sF icghuarneg 6e8 s tsehposw l ianpepalrilcya. tOionn sth ien owthheicrh h tahned d, ilgoigt al VI +AD860U11 VO 03142-071 taper adjustment is usually preferred in applications such as Figure 71. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift volume control. Figure 69 shows another method of resistance scaling which produces a pseudolog taper output. In this circuit, the smaller the value of R2 with respect to R , the more the AB output approaches log type behavior. VI A VO R1 B R2 03142-068 Figure 69. Resistor Scaling with Log Adjustment Characteristics Rev. F | Page 27 of 28

AD5263 Data Sheet OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 72. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Notes R (kΩ) Temperature Package Description Package Option Ordering Quantity AB AD5263BRU20 20 −40°C to +125°C 24-Lead TSSOP RU-24 62 AD5263BRUZ20 3 20 −40°C to +125°C 24-Lead TSSOP RU-24 62 AD5263BRUZ20-REEL7 3 20 −40°C to +125°C 24-Lead TSSOP RU-24 1,000 AD5263BRU50 50 −40°C to +125°C 24-Lead TSSOP RU-24 62 AD5263BRU50-REEL7 50 −40°C to +125°C 24-Lead TSSOP RU-24 1,000 AD5263BRUZ50 3 50 −40°C to +125°C 24-Lead TSSOP RU-24 62 AD5263BRUZ50-REEL7 3 50 −40°C to +125°C 24-Lead TSSOP RU-24 1,000 AD5263BRU200 200 −40°C to +125°C 24-Lead TSSOP RU-24 62 AD5263BRUZ200 3 200 −40°C to +125°C 24-Lead TSSOP RU-24 62 AD5263BRUZ200-R7 3 200 −40°C to +125°C 24-Lead TSSOP RU-24 1,000 EVAL-AD5263EBZ 4 Evaluation Board 1 The AD5263 contains 5,184 transistors. Die size: 108 mil × 198 mil = 21,384 sq. mil. 2 Package branding: Line 1 contains the model number, Line 2 contains the end-to-end resistance, and Line 3 contains the date code YYWW. 3 Z = RoHS Compliant Part. 4 The evaluation board is shipped with the 20 kΩ R resistor option; however, the board is compatible with all available resistor value options. AB I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03142-0-10/12(F) Rev. F | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5263EBZ AD5263BRUZ200 AD5263BRU50 AD5263BRUZ50 AD5263BRUZ20 AD5263BRU20 AD5263BRUZ20-REEL7 AD5263BRUZ50-REEL7 AD5263BRUZ200-R7