Nonvolatile, I2C®-Compatible 64-Position, Digital Potentiometer Data Sheet AD5258 FEATURES FUNCTIONAL BLOCK DIAGRAMS Nonvolatile memory maintains wiper settings 64-position digital potentiometer VDD RDAC A Compact MSOP-10 (3 mm × 4.9 mm) VLOGIC EERPDRAOCM RERGDISATCER W GND I2C-compatible interface B VLOGIC pin provides increased interface flexibility SCL 6 DATA End-to-end resistance 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ SDA I2C 6 CONTROL SERIAL Resistance tolerance stored in EEPROM (0.1% accuracy) INTERFACE Power-on EEPROM refresh time <1 ms AADD01 DECCOOMDMEA LNODGIC Software write protect command ADDRESS AD5258 DECODE LOGIC Address Decode Pin AD0 and Address Decode Pin AD1 allow POWER- ON RESET 10f0o-uyer apra tcykpaigceasl dpaetra b rueste ntion at 55°C CONTROL LOGIC 05029-001 Figure 1. Block Diagram Wide operating temperature −40°C to +85°C 3 V to 5 V single supply VLOGIC VDD APPLICATIONS A EEPROM LCD panel V adjustment COM SCL RDAC LCD panel brightness and contrast control SADDA0 INTSEEIRR2CFIAALCE RELGAEINVSDETLER Mechanical potentiometer replacement in new designs AD1 SHIFTER W Programmable power supplies COMMAND DECODE LOGIC RF amplifier biasing ADDRESS DECODE LOGIC Automotive electronics adjustment CONTROL GFiabienr c toon tthreo lh aonmde o sffyssette madsj ustment GND LOGIC B 05029-002 Electronics level settings Figure 2. Block Diagram Showing Level Shifters GENERAL DESCRIPTION The AD5258 provides a compact, nonvolatile 3 mm × 4.9 mm of 0.1%. There is also a software write protection function that packaged solution for 64-position adjustment applications. These ensures data cannot be written to the EEPROM register. devices perform the same electronic adjustment function as A separate V pin delivers increased interface flexibility. For LOGIC mechanical potentiometers1 or variable resistors, but with users who need multiple parts on one bus, Address Bit AD0 and enhanced resolution and solid-state reliability. Address Bit AD1 allow up to four devices on the same bus. The wiper settings are controllable through an I2C-compatible digital interface that is also used to read back the wiper register 1 The terms digital potentiometer, VR (variable resistor), and RDAC are used interchangeably. and EEPROM content in addition, resistor tolerance is stored within EEPROM, providing an end-to-end tolerance accuracy Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5258 Data Sheet TABLE OF CONTENTS Writing ......................................................................................... 15 Features .............................................................................................. 1 Storing/Restoring ....................................................................... 15 Applications ....................................................................................... 1 Reading ........................................................................................ 15 Functional Block Diagrams ............................................................. 1 I2C Byte Formats ............................................................................. 16 General Description ......................................................................... 1 Generic Interface ........................................................................ 16 Revision History ............................................................................... 2 Write Modes ................................................................................ 16 Specifications ..................................................................................... 3 Read Modes ................................................................................. 17 Electrical Characteristics ............................................................. 3 Store/Restore Modes .................................................................. 17 Timing Characteristics ................................................................ 5 Tolerance Readback Modes ...................................................... 18 Absolute Maximum Ratings ............................................................ 6 ESD Protection of Digital Pins and Resistor Terminals ........ 19 ESD Caution .................................................................................. 6 Power-Up Sequence ................................................................... 19 Pin Configuration and Function Descriptions ............................. 7 Layout and Power Supply Bypassing ....................................... 19 Typical Performance Characteristics ............................................. 8 Multiple Devices on One Bus ................................................... 19 Test Circuits ..................................................................................... 13 Display Applications ...................................................................... 20 Theory of Operation ...................................................................... 14 Circuitry ...................................................................................... 20 Programming the Variable Resistor ......................................... 14 Outline Dimensions ....................................................................... 21 Programming the Potentiometer Divider ............................... 14 Ordering Guide .......................................................................... 21 I2C Interface ..................................................................................... 15 REVISION HISTORY 1/13—Rev. C to Rev. D 3/07—Rev. 0 to Rev. A Changes to Zero-Scale Error Parameter and Logic Supply Updated Format .................................................................. Universal Parameter, Table 1 .............................................................................. 3 Changes to Features Section ............................................................ 1 Removed Evaluation Board Section and Figure 43, Renumbered Changes to General Description Section ....................................... 1 Sequentially ...................................................................................... 19 Changes to Table 4 ............................................................................. 7 Changes to I2C Interface Section .................................................. 15 5/10—Rev. B to Rev. C Changes to Table 5 .......................................................................... 16 Changes to Storing/Restoring Section ......................................... 15 Changes to Multiple Devices on One Bus Section ..................... 19 Changes to Table 7 .......................................................................... 16 3/05—Revision 0: Initial Version Changes to Table 14 ........................................................................ 17 1/10—Rev. A to Rev. B Changes to Figure 44 ...................................................................... 20 Updated Outline Dimensions ....................................................... 21 Rev. D | Page 2 of 24

Data Sheet AD5258 SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = V = 5 V ± 10%, or 3 V ± 10%; V = V ; V = 0 V; −40°C < T < +85°C, unless otherwise noted. DD LOGIC A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity R-DNL R , V = no connect LSB WB A 1 kΩ −1.5 ±0.3 +1.5 10 kΩ/50 kΩ/100 kΩ −0.25 ±0.1 +0.25 Resistor Integral Nonlinearity R-INL R , V = no connect LSB WB A 1 kΩ −5 ±0.5 +5 10 kΩ/100 kΩ −0.5 ±0.1 +0.5 50 kΩ −0.25 ±0.1 +0.25 Nominal Resistor Tolerance T = 25°C, V = 5.5 V A DD 1 kΩ R 0.9 1.5 kΩ AB 10 kΩ/50 kΩ/100 kΩ ΔR −30 +30 % AB Resistance Temperature Coefficient (ΔR × 106)/(R × ΔT) Code = 0x00/0x20 200/15 ppm/°C AB AB Total Wiper Resistance R Code = 0x00 75 350 Ω WB DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Differential Nonlinearity DNL LSB 1 kΩ −1 ±0.3 +1 10 kΩ/50 kΩ/100 kΩ −0.25 ±0.1 +0.25 Integral Nonlinearity INL LSB 1 kΩ −1 ±0.3 +1 10 kΩ/50 kΩ/100 kΩ −0.25 ±0.1 +0.25 Full-Scale Error V Code = 0x3F LSB WFSE 1 kΩ −6 −3 0 10 kΩ −1 −0.3 0 50 kΩ/100 kΩ −1 −0.1 0 Zero-Scale Error V Code = 0x00 LSB WZSE 1 kΩ −40°C < T < 85°C 0 3 5 LSB A 85°C < T < 125°C 6 LSB A 10 kΩ −40°C < T < 85°C 0 0.3 1 LSB A 85°C < T < 125°C 1.5 LSB A 50 kΩ/100 kΩ 0 0.1 0.5 LSB Voltage Divider Temperature Coefficient (ΔV × 106)/(V × ΔT) Code = 0x00/0x20 120/15 ppm/°C W W RESISTOR TERMINALS Voltage Range V , V ,V GND V V A B W DD Capacitance A, Capacitance B C , C f = 1 MHz, measured to 45 pF A B GND, code = 0x20 Capacitance W C f = 1 MHz, measured to 60 pF W GND, code = 0x20 Common-Mode Leakage I V = V = V /2 10 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V 0.7 × V V + 0.5 V IH L L Input Logic Low V −0.5 +0.3 × V V IL L Leakage Current I µA IL SDA, AD0, AD1 V = 0 V or 5 V 0.01 ±1 IN SCL – Logic High V = 0 V −2.5 −1.4 +1 IN SCL – Logic Low V = 5 V 0.01 ±1 IN Input Capacitance C 5 pF IL Rev. D | Page 3 of 24

AD5258 Data Sheet Parameter Symbol Conditions Min Typ1 Max Unit POWER SUPPLIES Power Supply Range V 2.7 5.5 V DD Positive Supply Current I 0.5 2 µA DD Logic Supply V 2.7 5.5 V LOGIC Logic Supply Current I V = 5 V or V = 0 V LOGIC IH IL −40°C < T < 85°C 3 6 µA A 85°C < T < 125°C 9 µA A Programming Mode Current (EEPROM) I V = 5 V or V = 0 V 35 mA LOGIC(PROG) IH IL Power Dissipation P V = 5 V or V = 0 V, 20 40 µW DISS IH IL V = 5 V DD Power Supply Rejection Ratio PSRR V = +5 V ± 10%, ±0.01 ±0.06 %/% DD Code = 0x20 DYNAMIC CHARACTERISTICS Bandwidth −3 dB BW Code = 0x20 R = 1 kΩ 18000 kHz AB R = 10 kΩ 1000 kHz AB R = 50 kΩ 190 kHz AB R = 100 kΩ 100 kHz AB Total Harmonic Distortion THD R = 10 kΩ, V = 1 V rms, 0.1 % W AB A V = 0, f = 1 kHz B V Settling Time t R = 10 kΩ, V = 5 V, 500 ns W S AB AB ±1 LSB error band Resistor Noise Voltage Density e R = 5 kΩ, f = 1 kHz 9 nV/√Hz N_WB WB 1 Typical values represent average readings at 25°C and VDD = 5 V. Rev. D | Page 4 of 24

Data Sheet AD5258 TIMING CHARACTERISTICS V = V = 5 V ± 10%, or 3 V ± 10%; V = V ; V = 0 V; −40°C < T < +85°C, unless otherwise noted. DD LOGIC A DD B A Table 2. Parameter Symbol Conditions Min Typ Max Unit I2C INTERFACE TIMING CHARACTERISTICS SCL Clock Frequency f 0 400 kHz SCL t Bus-Free Time Between Stop and Start t 1.3 µs BUF 1 t Hold Time (Repeated start) t After this period, the first clock pulse is 0.6 µs HD;STA 2 generated. t Low Period of SCL Clock t 1.3 µs LOW 3 t High Period of SCL Clock t 0.6 µs HIGH 4 t Setup Time for Repeated Start Condition t 0.6 µs SU;STA 5 t Data Hold Time t 0 0.9 µs HD;DAT 6 t Data Setup Time t 100 ns SU;DAT 7 t Fall Time of Both SDA and SCL Signals t 300 ns F 8 t Rise Time of Both SDA and SCL Signals t 300 ns R 9 t Setup Time for Stop Condition t 0.6 µs SU;STO 10 EEPROM Data Storing Time t 26 ms EEMEM_STORE EEPROM Data Restoring Time at Power On1 t V rise time dependant. Measure with- 300 µs EEMEM_RESTORE1 DD out decoupling capacitors at V and GND. DD EEPROM Data Restoring Time upon Restore t V = 5 V. 300 µs EEMEM_RESTORE2 DD Command1 EEPROM Data Rewritable Time2 t 540 µs EEMEM_REWRITE FLASH/EE MEMORY RELIABILITY Endurance3 100 700 kCycles Data Retention4 100 Years 1 During power-up, the output is momentarily preset to midscale before restoring EEPROM content. 2 Delay time after power-on preset prior to writing new EEPROM data. 3 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and is measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles. 4 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature. t8 t9 t6 SCL t2 t3 t4 t5 t7 t10 t8 t9 SDA P t1 S P 05029-004 Figure 3. I2C Interface Timing Diagram Rev. D | Page 5 of 24

AD5258 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V rating only; functional operation of the device at these or any DD VA, VB, VW to GND GND − 0.3 V, VDD + 0.3 V other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute I MAX maximum rating conditions for extended periods may affect Pulsed1 ±20 mA device reliability. Continuous ±5 mA Digital Inputs and Output Voltage to GND 0 V to 7 V ESD CAUTION Operating Temperature Range −40°C to +85°C Maximum Junction Temperature (T ) 150°C JMAX Storage Temperature −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Thermal Resistance2 200°C/W θ : MSOP-10 JA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX – TA)/θJA. Rev. D | Page 6 of 24

Data Sheet AD5258 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS W 1 10 A AD0 2 AD5258 9 B AD1 3 TOP VIEW 8 VDD SSDCAL 45 (Not to Scale) 76 GVLNODGIC 05029-005 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 W W Terminal, GND ≤ V ≤ V . W DD 2 AD0 Programmable Pin 0 for Multiple Package Decoding. State is registered on power-up. 3 AD1 Programmable Pin 1 for Multiple Package Decoding. State is registered on power-up. 4 SDA Serial Data Input/Output. 5 SCL Serial Clock Input. Positive edge triggered. 6 V Logic Power Supply. LOGIC 7 GND Digital Ground. 8 V Positive Power Supply. DD 9 B B Terminal, GND ≤ V ≤ V . B DD 10 A A Terminal, GND ≤ V ≤ V . A DD Rev. D | Page 7 of 24

AD5258 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = V = 5.5 V, R = 10 kΩ, T = 25°C, unless otherwise noted. DD LOGIC AB A 0.5 0.10 0.4 0.08 B) 0.3 S0.06 LSB) 0.2 NL (L0.04 E INL ( 0.1 2.7V ODE D0.02 D M T MO 0 5.5V TER 0 A–0.1 E–0.02 RHEOST–0.2 ENTIOM–0.04 +–8450°°CC +25°C –0.3 OT–0.06 P ––00..54 05029-006 ––00..1008 05029-009 0 8 16 24 32 40 48 56 64 0 8 16 24 32 40 48 56 64 CODE (Decimal) CODE (Decimal) Figure 5. R-INL vs. Code vs. Supply Voltages Figure 8. DNL vs. Code vs. Temperature 0.25 0.10 0.20 0.08 B)0.15 LSB)0.06 DNL (LS00..0150 5.5V DE INL (00..0024 2.7V ODE 0 R MO 0 M E STAT –0.05 OMET–0.02 5.5V O–0.10 TI–0.04 E N H 2.7V E R–0.15 OT–0.06 P ––00..2250 05029-007 ––00..1008 05029-010 0 8 16 24 32 40 48 56 64 0 8 16 24 32 40 48 56 64 CODE (Decimal) CODE (Decimal) Figure 6. R-DNL vs. Code vs. Supply Voltages Figure 9. INL vs. Code vs. Supply Voltages 0.10 0.10 0.08 0.08 NL (LSB)00..0046 NL (LSB)00..0046 2.7V DE I0.02 DE D0.02 O +85ºC O M M METER –0.020 METER –0.020 O O OTENTI––00..0064 –40°C +25ºC OTENTI––00..0064 5.5V P P ––00..1008 05029-008 ––00..1008 05029-011 0 8 16 24 32 40 48 56 64 0 8 16 24 32 40 48 56 64 CODE (Decimal) CODE (Decimal) Figure 7. INL vs. Code vs. Temperature Figure 10. DNL vs. Code vs. Supply Voltages Rev. D | Page 8 of 24

Data Sheet AD5258 0.50 0.25 0.45 0.20 ZSE @ VDD = 2.7V 0.40 0.15 B) S 0.35 L0.10 L ( ZSE @ VDD = 5.5V MODE IN0.050 –40°C +85°C E (LSB)00..3205 TAT –0.05 ZS0.20 S O 0.15 E–0.10 RH +25°C 0.10 –0.15 ––00..2250 05029-012 0.050–40 –20 0 20 40 60 80 05029-015 0 8 16 24 32 40 48 56 64 CODE (Decimal) TEMPERATURE (°C) Figure 14. Zero-Scale Error vs. Temperature Figure 11. R-INL vs. Code vs. Temperature 1 0.25 0.20 0.15 B) S NL (L0.10 +25°C –40°C +85°C VDD = 5.5V ODE D0.050 (µA)D M D T I A–0.05 T S EO–0.10 H R –0.15 ––00..2250 05029-013 0.1–40 –20 0 20 40 60 80 05029-016 0 8 16 24 32 40 48 56 64 TEMPERATURE (°C) CODE (Decimal) Figure 15. Supply Current vs. Temperature Figure 12. R-DNL vs. Code vs. Temperature 0 6 –0.05 –0.10 T (µA) 5 –0.15 RREN 4 VLOGIC = 5.5V U E (LSB)––00..2205 FSE @ VDD = 5.5V UPPLY C 3 FS–0.30 C S GI 2 –0.35 O L FSE @ VDD = 2.7V , C –0.40 OGI 1 ––00..4550 05029-014 IL 0 VLOGIC = 2.7V 05029-017 –40 –20 0 20 40 60 80 –40 –20 0 20 40 60 80 TEMPERATURE (ºC) TEMPERATURE (°C) Figure 13. Full-Scale Error vs. Temperature Figure 16. Logic Supply Current vs. Temperature vs. VLOGIC Rev. D | Page 9 of 24

AD5258 Data Sheet 250 120 200 C) m/° 100k RT @ VDD = 5.5V p 150 100 O (p 1k kΩ) E TEMPC 10500 50k STANCE ( 80 D 10k SI 60 MO 0 RE 50k RT @ VDD = 5.5V AT AL T T 40 OS –50 TO 10k RT @ VDD = 5.5V RHE––1150000 8100k16 24 32 40 48 56 6405029-018 200–40 –20 0 20 1k RT 4@0 VDD = 56.50V 80 05029-021 CODE (Decimal) TEMPERATURE (°C) Figure 17. Rheostat Mode Tempco (ΔRAB ×106)/(RAB × ∆T) vs. Code Figure 20. Total Resistance vs. Temperature 120 0 C) 0x20 m/° 100 –6 pp 1k –12 0x10 PCO ( 80 –18 00xx0084 M E 0x02 E T 60 B) –24 D d 0x01 ER MO 40 50k GAIN ( ––3360 T E M 20 –42 O TI N –48 POTE –2000 10100kk8 16 24 32 40 48 56 6405029-019 ––5640 05029-022 10k 100k 1M 10M 100M CODE (Decimal) FREQUENCY (Hz) Figure 18. Potentiometer Mode Tempco (ΔVW × 106)/(VW × ΔT) vs. Code Figure 21. Gain vs. Frequency vs. Code, RAB = 1 kΩ 350 0 0x20 300 –6 0x10 –12 250 RWB @ VDD = 2.7V 0x08 –18 0 0x04 @ 0x0WB 125000 AIN (dB) ––3204 00xx0021 R G –36 100 –42 –48 500–40 –20 0 RWB @2 0VDD = 5.54V0 60 80 05029-020 ––5640 05029-023 1k 10k 100k 1M 10M TEMPERATURE (°C) FREQUENCY (Hz) Figure 19. RWB vs. Temperature Figure 22. Gain vs. Frequency vs. Code, RAB = 10 kΩ Rev. D | Page 10 of 24

Data Sheet AD5258 0 10k 0x20 –6 0x10 –12 –18 0x08 VDD = VLOGIC = 5V 1k 0x04 AIN (dB) ––3204 00xx0021 (µA)OGIC G –36 IL VDD = VLOGIC = 3V 100 –42 –48 ––5640 05029-024 10 05029-026 1k 10k 100k 1M 0 1 2 3 4 5 FREQUENCY (Hz) VIH (V) Figure 23. Gain vs. Frequency vs. Code, RAB = 50 kΩ Figure 25. Logic Supply Current vs. Input Voltage 0 80 0x20 CODE = MIDSCALE, VA = VLOGIC, VB = 0V –6 0x10 –12 PSRR @ VLOGIC = 5V DC ± 10% p-pAC 60 0x08 –18 0x04 AIN (dB) ––3204 00xx0021 SRR (dB) 40 PSRR @ VLOGIC = 3V DC ± 10% p-pAC G –36 P –42 20 –48 ––5640 05029-025 0 05029-027 1k 10k 100k 1M 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 24. Gain vs. Frequency vs. Code, RAB = 100 kΩ Figure 26. Power Supply Rejection Ratio vs. Frequency Rev. D | Page 11 of 24

AD5258 Data Sheet V DI V V/ DI 00m VW 2V/ 5 1 VW 1 V SCL V V/DI2 V/DI 5 5 SCL 05029-028 2 05029-030 400ns/DIV 200ns/DIV Figure 27. Digital Feedthrough Figure 29. Large-Signal Settling Time V DI VW mV/1 0 0 2 05029-029 1µs/DIV Figure 28. Midscale Glitch, Code 0×7F to Code 0×80 Rev. D | Page 12 of 24

Data Sheet AD5258 TEST CIRCUITS Figure 30 through Figure 35 illustrate the test circuits that define the test conditions used in the product specification tables. VA DUT V+ = VDD DUT V+ = VDD ± 10% V+ A W 1LSB = V+/2N V+ ΔVDD A W PSSR (%/%) =ΔΔVVMDDS%% B B VMS 05029-031 VMS 05029-034 Figure 30. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 33. Test Circuit for Power Supply Sensitivity (PSS, PSSR) NO CONNECT DUT +5V DUT A A W IW VIN W B AD8610 VOUT OFFSET B GND VMS 05029-032 +2.5V –5V 05029-035 Figure 31. Test Circuit for Resistor Position Nonlinearity Error Figure 34. Test Circuit for Gain vs. Frequency (Rheostat Operation; R-INL, R-DNL) DUT RSW= 0IS.1WV CODE = 0x00 DUT W A IW = VDD/RNOMINAL VMS2 W VW ISW 0.1V B B RW = [VMS1 – VMS2]/IW VMS1 05029-033 GNDTO VDD 05029-036 Figure 32. Test Circuit for Wiper Resistance Figure 35. Test Circuit for Common-Mode Leakage Current Rev. D | Page 13 of 24

AD5258 Data Sheet THEORY OF OPERATION The AD5258 is a 64-position digitally controlled variable Similar to the mechanical potentiometer, the resistance of the resistor (VR) device. The wipers default value prior to pro- RDAC between Wiper W and Terminal A produces a digitally gramming the EEPROM is midscale. controlled complementary resistance, R . The resistance value WA PROGRAMMING THE VARIABLE RESISTOR setting for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. Rheostat Operation The general equation for this operation is The nominal resistance (R ) of the RDAC between Terminal A AB 64−D and Terminal B is available in 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. R (D)= ×R +2×R (2) WA 64 AB W The nominal resistance of the VR has 64 contact points accessed by the wiper terminal. The 6-bit data in the RDAC latch is Typical device-to-device matching is process lot dependent and decoded to select one of 64 possible settings. may vary by up to ±30%. For this reason, resistance tolerance is stored in the EEPROM such that the user will know the actual A A A R within 0.1%. AB W W W PROGRAMMING THE POTENTIOMETER DIVIDER B B B 05029-037 Voltage Output Operation Figure 36. Rheostat Mode Configuration The digital potentiometer easily generates a voltage divider at Wiper W-to-Terminal B and Wiper W-to-Terminal A propor- The general equation determining the digitally programmed tional to the input voltage at Terminal A-to-Terminal B. Unlike output resistance between Wiper W and Terminal B is the polarity of V -to-GND, which must be positive, voltage DD R (D)= D ×R +2×R (1) across Terminal A-to-Terminal B, Wiper W-to-Terminal A, WB 64 AB W and Wiper W-to-Terminal B can be at either polarity. where: VI A D is the decimal equivalent of the binary code loaded in the W 6-bit RDAC register. VO RRAWB iiss tthhee wenipde-rt ore-esnisdta rnecseis ctaonnctrei.b uted by the on resistance of B 05029-039 each internal switch. Figure 38. Potentiometer Mode Configuration A If ignoring the effect of the wiper resistance for approximation, RS connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at Wiper W-to-Terminal B starting D5 RS at 0 V up to 1 LSB less than 5 V. The general equation defining D4 the output voltage at V with respect to ground for any valid D3 W D2 RS input voltage applied to Terminal A and Terminal B is D1 D0 W V (D)= D V + 64−DV (3) W 64 A 64 B A more accurate calculation, which includes the effect of wiper resistance (V ) is W RDAC RS V (D)= RWB(D)V +RWA(D)V (4) DELCAATONCDDHER B 05029-038 OperatWion of theR dAiBgital pAotentRioAmB eterB in the divider mode Figure 37. AD5258 Equivalent RDAC Circuit results in a more accurate operation over temperature. Unlike Note that in the zero-scale condition, there is a relatively the rheostat mode, the output voltage is dependent mainly on low value finite wiper resistance. Care should be taken to the ratio of internal resistors (RWA and RWB) and not the abso- limit the current flow between Wiper W and Terminal B in lute values. this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or destruction of the internal switch contact may occur. Rev. D | Page 14 of 24

Data Sheet AD5258 I2C INTERFACE Note that the wiper’s default value prior to programming the READING EEPROM is midscale. Assuming the register of interest was not just written to, it is The master initiates a data transfer by establishing a start con- necessary to write a dummy address and instruction byte. The dition when a high-to-low transition on the SDA line occurs instruction byte will vary depending on whether the data that while SCL is high (see Figure 3). The next byte is the slave is wanted is the RDAC register, EEPROM register, or tolerance address byte, which consists of the slave address (first seven bits) register (see Table 11 to Table 16). followed by an R/W bit (see Table 6). When the R/W bit is high, After the dummy address and instruction bytes are sent, a repeat the master reads from the slave device. When the R/W bit is start is necessary. After the repeat start, another address byte is low, the master writes to the slave device. needed, except this time the R/W bit is logic high. Following The slave address of the part is determined by two configurable this address byte is the readback byte containing the informa- address pins, AD0 and AD1. The state of these two pins is regis- tion requested in the instruction byte. Read bits appear on the tered upon power-up and decoded into a corresponding I2C negative edges of the clock. Don’t cares may be in either a high 7-bit address (see Table 5). The slave address corresponding to or low state. the transmitted address bits responds by pulling the SDA line The tolerance register can be read back individually (see low during the ninth clock pulse (this is termed the slave Table 15) or consecutively (see Table 16). Refer to the Read acknowledge bit). Modes section for detailed information on the interpretation At this stage, all other devices on the bus remain idle while the of the tolerance bytes. selected device waits for data to be written to or read from its After all data bits have been read or written, a stop condition is serial register. established by the master. A stop condition is defined as a low- WRITING to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock In the write mode, the last bit (R/W) of the slave address byte is pulse to establish a stop condition (see Table 8). In read mode, logic low. The second byte is the instruction byte. The first three the master issues a no acknowledge for the ninth clock pulse bits of the instruction byte are the command bits (see Table 6). (that is, the SDA line remains high). The master then brings the The user must choose whether to write to the RDAC register or SDA line low before the 10th clock pulse and raises SDA high to EEPROM register or to activate the software write protect (see establish a stop condition (see Table 11). Table 7 to Table 10). The final five bits are all zeros (see Table 13 and Table 14). The slave again responds by pulling the SDA line A repeated write function provides the user with the flexibility low during the ninth clock pulse. of updating the RDAC output multiple times after addressing and instructing the part only once. For example, after the RDAC The final byte is the data byte MSB first. Don’t cares can be has acknowledged its slave address and instruction bytes in the left either high or low. In the case of the write protect mode, write mode, the RDAC output is updated on each successive data is not stored; rather, a logic high in the LSB enables write byte until a stop condition is received. If different instructions protect. Likewise, a logic low disables write protect. The slave are needed, the write/read mode must restart with a new slave again responds by pulling the SDA line low during the ninth address, instruction, and data byte. Similarly, a repeated read clock pulse. function of the RDAC is also allowed. STORING/RESTORING In this mode, only the address and instruction bytes are nec- essary. The last bit (R/W) of the address byte is logic low. The first three bits of the instruction byte are the command bits (see Table 6). The two choices are transfer data from RDAC- to-EEPROM (store) or from EEPROM-to-RDAC (restore). The final five bits are all zeros (see Table 13 and Table 14). In addition, users should issue an NOP command immediately after restoring the EEMEM setting to RDAC, thereby mini- mizing supply current dissipation. Rev. D | Page 15 of 24

AD5258 Data Sheet I2C BYTE FORMATS The following generic, write, read, and store/restore control Table 5. Device Address Lookup registers for the AD5258 refer to the device addresses listed in AD1 Address Pin AD0 Address Pin I2 C Device Address Table 5, and following is the mode/condition reference key. 0 0 0011000 • S = Start Condition 1 0 0011010 0 1 1001100 • P = Stop Condition 1 1 1001110 • SA = Slave Acknowledge • MA = Master Acknowledge • NA = No Acknowledge • W = Write • R = Read • X = Don’t Care • AD1 and AD0 are two-state address pins. GENERIC INTERFACE Table 6. Generic Interface Format 7-Bit Device Address S (See Table 5) R/W SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P Slave Address Byte Instruction Byte Data Byte Table 7. RDAC-to-EEPROM Interface Command Descriptions C2 C1 C0 Command Description 0 0 0 Operation between I2C and RDAC 0 0 1 Operation between I2C and EEPROM 0 1 0 Operation between I 2C and Write Protection Register. See Table 10. 1 0 0 NOP 1 0 1 Restore EEPROM to RDAC1 1 1 0 Store RDAC to EEPROM 1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state. WRITE MODES Table 8. Writing to RDAC Register 7-Bit Device Address S (See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA X X D5 D4 D3 D2 D1 D0 SA P Slave Address Byte Instruction Byte Data Byte Table 9. Writing to EEPROM Register 7-Bit Device Address S (See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA X X D5 D4 D3 D2 D1 D0 SA P Slave Address Byte Instruction Byte Data Byte The wiper’s default value prior to programming the EEPROM is midscale. Table 10. Activating/Deactivating Software Write Protect 7-Bit Device Address S (See Table 5) 0 SA 0 1 0 0 0 0 0 0 SA 0 0 0 0 0 0 0 WP SA P Slave Address Byte Instruction Byte Data Byte To activate the write protection mode, the WP bit in Table 10 must be logic high. To deactivate the write protection, the command must be resent except with the WP in logic zero state. Rev. D | Page 16 of 24

Data Sheet AD5258 READ MODES Read modes are referred to as traditional because the first two interested in reading a register that was previously written to. bytes for all three cases are dummy bytes that function to place For example, if the EEPROM was just written to, the user can the pointer toward the correct register. This is the reason for the skip the two dummy bytes and proceed directly to the slave repeat start. In theory, this step can be avoided if the user is address byte followed by the EEPROM readback data. Table 11. Traditional Readback of RDAC Register Value 7-Bit Device Address 7-Bit Device Address S (See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA S (See Table 5) 1 SA X X D5 D4 D3 D2 D1 D0 NA P Slave Address Byte Instruction Byte Slave Address Byte Read-back Data ↑ Repeat Start Table 12. Traditional Readback of Stored EEPROM Value 7-Bit Device Address 7-Bit Device Address S (See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA S (See Table 5) 1 SA X X D5 D4 D3 D2 D1 D0 NA P Slave Address Byte Instruction Byte Slave Address Byte Read-back Data ↑ Repeat Start STORE/RESTORE MODES Table 13. Storing RDAC Value to EEPROM 7-Bit Device Address S (See Table 5) 0 SA 1 1 0 0 0 0 0 0 SA P Slave Address Byte Instruction Byte Table 14. Restoring EEPROM to RDAC1 7-Bit Device Address S (See Table 5) 0 SA 1 0 1 0 0 0 0 0 SA P Slave Address Byte Instruction Byte 1 User should issue an NOP command immediately after this command to conserve power. Rev. D | Page 17 of 24

AD5258 Data Sheet TOLERANCE READBACK MODES Table 15. Traditional Readback of Tolerance (Individually) 7-Bit Device Address 7-Bit Device Address S (See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte ↑ Repeat Start 7-Bit Device Address 7-Bit Device Address S (See Table 5) 0 SA 0 0 1 1 1 1 1 1 SA S (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P Slave Address Byte Instruction Byte Slave Address Byte Decimal Byte ↑ Repeat Start Table 16. Traditional Readback of Tolerance (Consecutively) 7-Bit Device Address 7-Bit Device Address S (See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S (See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte Decimal Byte ↑ Repeat Start Calculating R Tolerance Stored in Read-Only Memory AB A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SIGN 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 SIGN SEVEN BITS FORAN INTEGER NUMBER EIGHT BITS FOR A DECIMAL NUMBER 05029-040 Figure 39. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit is Percent; Only Data Bytes are Shown) The AD5258 features a patented R tolerance storage in the In the first memory location, the MSB is designated for the sign AB nonvolatile memory. Tolerance is stored in the memory during (0 = + and 1 = −) and the seven LSBs are designated for the integer factory production and can be read by users at any time. The portion of the tolerance. In the second memory location, all eight knowledge of stored tolerance allows users to accurately calcu- data bits are designated for the decimal portion of tolerance. Note late R . This feature is valuable for precision, rheostat mode, that the decimal portion has a limited accuracy of only 0.1%. For AB and open-loop applications where knowledge of absolute example, if the rated R = 10 kΩ and the data readback from AB resistance is critical. Address 11110 shows 0001 1100 and from Address 11111 shows 0000 1111, the tolerance can be calculated as The stored tolerance resides in the read-only memory and is expressed as a percentage. The tolerance is stored in two memory MSB: 0 = + location bytes in sign magnitude binary form (see Figure 39). The Next 7 MSB: 001 1100 = 28 two EEPROM address bytes are 11110 (sign + integer) and 11111 8 LSB: 0000 1111 = 15 × 2–8 = 0.06 (decimal number). The two bytes can be individually accessed Tolerance = 28.06% with two separate commands (see Table 15). Alternatively, read- Rounded Tolerance = 28.1% and therefore back of the first byte followed by the second byte can be done R = 12.810 kΩ AB_ACTUAL in one command (see Table 16). In the latter case, the memory pointer automatically increments from the first to the second EEPROM location (increments from 11110 to 11111) if read consecutively. Rev. D | Page 18 of 24

Data Sheet AD5258 ESD PROTECTION OF DIGITAL PINS AND of powering V , V , V and the digital inputs is not important A B W RESISTOR TERMINALS as long as they are powered after GND, V , and V . DD LOGIC The AD5258 V , V , and GND power supplies define the LAYOUT AND POWER SUPPLY BYPASSING DD LOGIC boundary conditions for proper 3-terminal and digital input It is good practice to employ compact, minimum lead length operation. Supply signals present on Terminal A, Terminal B, layout design. The leads to the inputs should be as direct as and Terminal W that exceed V or GND are clamped by the DD possible with minimum conductor length. Ground paths internal forward-biased ESD protection diodes (see Figure 40). should have low resistance and low inductance. Digital Input SCL and Digital Input SDA are clamped by ESD Similarly, it is also good practice to bypass the power supplies protection diodes with respect to V and GND as shown in LOGIC with quality capacitors for optimum stability. Supply leads to Figure 41. the device should be bypassed with disc or chip ceramic capaci- VDD tors of 0.01 µF to 0.1 µF. In addition, low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should be applied at the A supplies to minimize any transient disturbance and low fre- W quency ripple (see Figure 42). As well, the digital ground B should be joined remotely to the analog ground at one point GND 05029-041 to minimize the ground bounce. Figure 40. Maximum Terminal Voltages Set by VDD and GND VDD VDD + C2 C1 VLOGIC 10µF 0.1µF AD5258 SCL SDA GND GND 05029-042 Figure 42. Power Supply Bypassing 05029-043 Figure 41. Maximum Terminal Voltages Set by VLOGIC and GND MULTIPLE DEVICES ON ONE BUS POWER-UP SEQUENCE The AD5258 has two configurable address pins, AD0 and AD1. Because the ESD protection diodes limit the voltage compliance The state of these two pins is registered upon power-up and at Terminal A, Terminal B, and Terminal W (see Figure 40), it is decoded into a corresponding I2C-compatible 7-bit address (see important to power GND/VDD/VLOGIC before applying any volt- Table 5). This allows up to four devices on the bus to be written age to Terminal A, Terminal B, and Terminal W; otherwise, the to or read from independently. diode is forward-biased such that V and V are powered DD LOGIC unintentionally and may affect the user’s circuit. The ideal power-up sequence is in the following order: GND, V , DD V , digital inputs, and then V , V , V . The relative order LOGIC A B W Rev. D | Page 19 of 24

AD5258 Data Sheet DISPLAY APPLICATIONS CIRCUITRY affect that node’s bias because it is only on the order of microamps. V is tied to the microcontroller’s (MCU) 3.3 V A special feature of the AD5258 is its unique separation of LOGIC digital supply because V will draw the 35 mA that is needed the V and V supply pins. The reason for doing this is LOGIC LOGIC DD when writing to the EEPROM. It would be impractical to try to to provide greater flexibility in applications that do not always source 35 mA through the 70 kΩ resistor; therefore, V is provide the needed supply voltages. LOGIC not connected to the same node as V . DD In particular, LCD panels often require a V voltage in COM For this reason, V and V are provided as two separate the range of 3 V to 5 V. The circuit in Figure 43 is the rare LOGIC DD supply pins that can either be tied together or treated inde- exception in which a 5 V supply is available to power the pendently; V supplies the logic/EEPROM with power, and digital potentiometer. LOGIC V biases up the A, B, and W terminals for added flexibility. DD SUPPLIES POWER VCC (~3.3V) 5V 14.4V VCC (~3.3V) TO BOTH THE MCU 14.4V AND THE LOGIC SUPPLY OF THE R1 R1 DPOIGTITEANLTIOMETER 70kΩ 70kΩ 1CµF1 AD5258 1CµF1 AD5258 MCU10kRΩ6 10kRΩ5 VSVDLCODLGICA R102WkΩ –+ADU81565 3.5V < VCOM < 4.5V MCU10kRΩ6 10kRΩ5 VVSSDLCDODLAGICBA R102WkΩ –+ADU81565 3.5V < VCOM < 4.5V SDA B GND GND R3 Figure 43. VCOM AdjR2u53sktΩment Application 05029-045 Figure 44. Circuitry When a Separ2a5kteΩ Supply Is Not Available for VDD 05029-046 For a more detailed look at this application, refer to the article, More commonly, only analog 14.4 V and digital logic 3.3 V sup- “Simple V Adjustment uses any Logic-Supply Voltage” in the plies are available (see Figure 44). By placing discrete resistors COM September 30, 2004, issue of EDN magazine. above and below the digital potentiometer, V can be tapped DD off the resistor string itself. Based on the chosen resistor values, the voltage at V in this case equals 4.8 V, allowing the wiper to DD be safely operated up to 4.8 V. The current draw of V will not DD Rev. D | Page 20 of 24

Data Sheet AD5258 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 R (kΩ) Temperature Range Package Description2 Package Option Branding AB AD5258BRMZ1 1 −40°C to +85°C 10-Lead MSOP RM-10 D4K AD5258BRMZ1-R7 1 −40°C to +85°C 10-Lead MSOP RM-10 D4K AD5258BRMZ10 10 −40°C to +85°C 10-Lead MSOP RM-10 D4L AD5258BRMZ10-R7 10 −40°C to +85°C 10-Lead MSOP RM-10 D4L AD5258BRMZ50 50 −40°C to +85°C 10-Lead MSOP RM-10 D4M AD5258BRMZ50-R7 50 −40°C to +85°C 10-Lead MSOP RM-10 D4M AD5258BRMZ100 100 −40°C to +85°C 10-Lead MSOP RM-10 D4N AD5258BRMZ100-R7 100 −40°C to +85°C 10-Lead MSOP RM-10 D4N EVAL-AD5258DBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. Rev. D | Page 21 of 24

AD5258 Data Sheet NOTES Rev. D | Page 22 of 24

Data Sheet AD5258 NOTES Rev. D | Page 23 of 24

AD5258 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05029-0-1/13(D) Rev. D | Page 24 of 24

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5258DBZ AD5258BRMZ10 AD5258BRMZ50 AD5258BRMZ1 AD5258BRMZ100 AD5258BRMZ100-R7 AD5258BRMZ10-R7 AD5258BRMZ1-R7 AD5258BRMZ50-R7