Quad 64-/256-Position I2C Nonvolatile Memory Digital Potentiometers Data Sheet AD5253/AD5254 FEATURES FUNCTIONAL BLOCK DIAGRAM AD5253: quad 64-position resolution AD5254: quad 256-position resolution VDD RDAC EEMEM RDAC0 RDAC0 A0 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VSS EEMEM REGIS- W0 Nonvolatile memory1 stores wiper settings w/write protection DGND PROEWFERRE-SOHN RAB TOL TER B0 WP Power-on refreshed to EEMEM settings in 300 µs typ DATA RDAC1 EEMEM rewrite time = 540 µs typ SCL RDAC1 A1 SDA I2C REGIS- W1 Resistance tolerance stored in nonvolatile memory INTSEERRFIAALCE CONTROL TER B1 12 extra bytes in EEMEM for user-defined information AD0 COMMAND I2C-compatible serial interface AD1 DECODE LOGIC RDAC2 RDAC2 A2 Direct read/write access of RDAC2 and EEMEM registers ADDRESS REGIS- W2 DECODE LOGIC TER B2 Predefined linear increment/decrement commands CONTROL LOGIC Predefined ±6 dB step change commands RDAC3 A3 RDAC3 Synchronous or asynchronous quad-channel update REGIS- W3 Wiper setting readback AD5253/AD5254 TER B3 4Si MngHlez bsuapnpdlwy i2d.t7h V— t1o k5Ω.5 v Ve rsion 03824-0-001 Dual supply ±2.25 V to ±2.75 V Figure 1. 2 slave address-decoding bits allow operation of 4 devices The AD5253/AD5254 allow the host I2C controllers to write 100-year typical data retention, T = 55°C A any of the 64-/256-step wiper settings in the RDAC registers Operating temperature: –40°C to +105°C and store them in the EEMEM. Once the settings are stored, APPLICATIONS they are restored automatically to the RDAC registers at system Mechanical potentiometer replacement power-on; the settings can also be restored dynamically. Low resolution DAC replacement RGB LED backlight control The AD5253/AD5254 provide additional increment, White LED brightness adjustment decrement, +6 dB step change, and –6 dB step change in RF base station power amp bias control synchronous or asynchronous channel update mode. The Programmable gain and offset control increment and decrement functions allow stepwise linear Programmable attenuators adjustments, with a ± 6 dB step change equivalent to doubling Programmable voltage-to-current conversion or halving the RDAC wiper setting. These functions are useful Programmable power supply for steep-slope, nonlinear adjustments, such as white LED Programmable filters brightness and audio volume control. Sensor calibrations The AD5253/AD5254 have a patented resistance-tolerance GENERAL DESCRIPTION storing function that allows the user to access the EEMEM and The AD5253/AD5254 are quad-channel, I2C®, nonvolatile obtain the absolute end-to-end resistance values of the RDACs mem-ory, digitally controlled potentiometers with 64/256 for precision applications. positions, respectively. These devices perform the same electronic adjust-ment functions as mechanical potentiometers, The AD5253/AD5254 are available in TSSOP-20 packages in trimmers, and variable resistors. 1 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are guaranteed to operate over the –40°C to +105°C extended The parts’ versatile programmability allows multiple modes of industrial temperature range. operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes 1The terms nonvolatile memory and EEMEM are used interchangeably. 2The terms digital potentiometer and RDAC are used interchangeably. in ±6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information, such as memory data for other components, look-up table, or system identification information. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5253/AD5254 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 I2C-Compatible 2-Wire Serial Bus ........................................... 20 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 21 General Description ......................................................................... 1 Linear Increment/Decrement Commands ............................. 21 Functional Block Diagram .............................................................. 1 ±6 dB Adjustments (Doubling/Halving Wiper Setting) ....... 21 Revision History ............................................................................... 2 Digital Input/Output Configuration........................................ 22 Electrical Characteristics ................................................................. 3 Multiple Devices on One Bus ................................................... 22 1 kΩ Version .................................................................................. 3 Terminal Voltage Operation Range ......................................... 23 10 kΩ, 50 kΩ, 100 kΩ Versions .................................................. 5 Power-Up and Power-Down Sequences .................................. 23 Interface Timing Characteristics ................................................ 7 Layout and Power Supply Biasing ............................................ 23 Absolute Maximum Ratings ............................................................ 8 Digital Potentiometer Operation ............................................. 24 ESD Caution .................................................................................. 8 Programmable Rheostat Operation ......................................... 24 Pin Configuration and Function Descriptions ............................. 9 Programmable Potentiometer Operation ............................... 25 Typical Performance Characteristics ........................................... 10 Applications Information .............................................................. 26 I2C Interface ..................................................................................... 14 RGB LED Backlight Controller for LCD Panels .................... 26 I2C Interface General Description ............................................ 14 Outline Dimensions ....................................................................... 28 I2C Interface Detail Description ............................................... 15 Ordering Guide .......................................................................... 29 REVISION HISTORY 9/12—Rev. B to Rev. C 9/05—Rev. 0 to Rev. A Changed Temperature Range from –40°C to +85°C to –40°C Change to Figure 6 ......................................................................... 10 to +105°C (Throughout).................................................................. 1 Change to EEMEM Write Protection Section ............................ 18 Changed WP Leakage Current from 5 µA to 8 µA, Table 1 ........ 4 Changes to Figure 37 ...................................................................... 22 Changed WP Leakage Current from 5 µA to 8 µA, Table 2 ........ 5 Deleted Table 13 and Table 14 ...................................................... 24 Changes to Figure 11 and Figure 12 ............................................. 12 Change to Figure 43 ....................................................................... 25 Changes to Ordering Guide .......................................................... 29 Changes to Ordering Guide .......................................................... 29 10/09—Rev. A to Rev. B 5/03—Revision 0: Initial Version Change to Figure 27 ....................................................................... 15 Rev. C | Page 2 of 32

Data Sheet AD5253/AD5254 ELECTRICAL CHARACTERISTICS 1 kΩ VERSION V = +3 V ± 10% or +5 V ± 10%, V = 0 V or V /V = ±2.5 V ± 10%, V = V , V = 0 V, –40°C < T < +105°C, unless otherwise noted. DD SS DD SS A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS— RHEOSTAT MODE Resolution N AD5253 6 Bits AD5254 8 Bits Resistor Differential Nonlinearity2 R-DNL R , R = NC, V = 5.5 V, AD5253 –0.5 ±0.2 +0.5 LSB WB WA DD R , R = NC, V = 5.5 V, AD5254 –1.00 ±0.25 +1.00 LSB WB WA DD R , R = NC, V = 2.7 V, AD5253 –0.75 ±0.30 +0.75 LSB WB WA DD R , R = NC, V = 2.7 V, AD5254 –1.5 ±0.3 +1.5 LSB WB WA DD Resistor Nonlinearity2 R-INL R , R = NC, V = 5.5 V, AD5253 –0.5 ±0.2 +0.5 LSB WB WA DD R , R = NC, V = 5.5 V, AD5254 –2.0 ±0.5 +2.0 LSB WB WA DD R , R = NC, V = 2.7 V, AD5253 –1.0 +2.5 +4.0 LSB WB WA DD R , R = NC, V = 2.7 V, AD5254 –2 +9 +14 LSB WB WA DD Nominal Resistor Tolerance ΔR /R T = 25°C –30 +30 % AB AB A Resistance Temperature Coefficient (ΔR /R ) × 106/ΔT 650 ppm/°C AB AB Wiper Resistance R I = 1 V/R, V = 5 V 75 130 Ω W W DD I = 1 V/R, V = 3 V 200 300 Ω W DD Channel-Resistance Matching ΔR /ΔR 0.15 % AB1 AB2 DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Differential Nonlinearity3 DNL AD5253 –0.5 ±0.1 +0.5 LSB AD5254 –1.00 ±0.25 +1.00 LSB Integral Nonlinearity3 INL AD5253 –0.5 ±0.2 +0.5 LSB AD5254 –2.0 ±0.5 +2.0 LSB Voltage Divider Tempco (ΔV /V ) × 106/ΔT Code = half scale 25 ppm/°C W W Full-Scale Error V Code = full scale, V = 5.5 V, AD5253 –5 –3 0 LSB WFSE DD Code = full scale, V = 5.5 V, AD5254 –16 –11 0 LSB DD Code = full scale, V = 2.7 V, AD5253 –6 –4 0 LSB DD Code = full scale, V = 2.7 V, AD5254 –23 –16 0 LSB DD Zero-Scale Error V Code = zero scale, V = 5.5 V, AD5253 0 3 5 LSB WZSE DD Code = zero scale, V = 5.5 V, AD5254 0 11 16 LSB DD Code = zero scale, V = 2.7 V, AD5253 0 4 6 LSB DD Code = zero scale, V = 2.7 V, AD5254 0 15 20 LSB DD RESISTOR TERMINALS Voltage Range4 V , V , V V V V A B W SS DD Capacitance5 A, B C , C f = 1 kHz, measured to GND, 85 pF A B code = half scale Capacitance5 W C f = 1 kHz, measured to GND, 95 pF W code = half scale Common-Mode Leakage Current I V = V = V /2 0.01 1.00 µA CM A B DD Rev. C | Page 3 of 32

AD5253/AD5254 Data Sheet Parameter Symbol Conditions Min Typ1 Max Unit DIGITAL INPUTS AND OUTPUTS Input Logic High V V = 5 V, V = 0 V 2.4 V IH DD SS V /V = +2.7 V/0 V or V /V = ±2.5 V 2.1 V DD SS DD SS Input Logic Low V V = 5 V, V = 0 V 0.8 V IL DD SS V /V = +2.7 V/0 V or V /V = ±2.5 V 0.6 V DD SS DD SS Output Logic High (SDA) V R = 2.2 kΩ to V = 5 V, V = 0 V 4.9 V OH PULL-UP DD SS Output Logic Low (SDA) V R = 2.2 kΩ to V = 5 V, V = 0 V 0.4 V OL PULL-UP DD SS WP Leakage Current I WP = V 8 µA WP DD A0 Leakage Current I A0 = GND 3 µA A0 Input Leakage Current I V = 0 V or V ±1 µA I IN DD (Other than WP and A0) Input Capacitance5 C 5 pF I POWER SUPPLIES Single-Supply Power Range V V = 0 V 2.7 5.5 V DD SS Dual-Supply Power Range V /V ±2.25 ±2.75 V DD SS Positive Supply Current I V = V or V = GND 5 15 µA DD IH DD IL Negative Supply Current I V = V or V = GND, V = 2.5 V, –5 –15 µA SS IH DD IL DD V = –2.5 V SS EEMEM Data Storing Mode Current I V = V or V = GND 35 mA DD_STORE IH DD IL EEMEM Data Restoring Mode I V = V or V = GND 2.5 mA DD_RESTORE IH DD IL Current6 Power Dissipation7 P V = V = 5 V or V = GND 0.075 mW DISS IH DD IL Power Supply Sensitivity PSS ΔV = 5 V ± 10% −0.025 +0.010 +0.025 %/% DD ΔV = 3 V ± 10% –0.04 +0.02 +0.04 %/% DD DYNAMIC CHARACTERISTICS5, 8 Bandwidth –3 dB BW R = 1 kΩ 4 MHz AB Total Harmonic Distortion THD V =1 V rms, V = 0 V, f = 1 kHz 0.05 % A B V Settling Time t V = V , V = 0 V 0.2 µs W S A DD B Resistor Noise Voltage e R = 500 Ω, f = 1 kHz 3 nV/√Hz N_WB WB (thermal noise only) Digital Crosstalk C V = V , V = 0 V, measure V with –80 dB T A DD B W adjacent RDAC making full-scale change Analog Coupling C Signal input at A0 and measure the –72 dB AT output at W1, f = 1 kHz 1 Typical values represent average readings at 25°C and V = 5 V. DD 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at V = 2.7 V, DD I = V /R for both V = 3 V and V = 5 V. W DD DD DD 3 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. V = V and V = 0 V. W A DD B DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Command 0 NOP should be activated after Command 1 to minimize I current consumption. DD_RESTORE 7 P is calculated from I × V = 5 V. DISS DD DD 8 All dynamic characteristics use V = 5 V. DD Rev. C | Page 4 of 32

Data Sheet AD5253/AD5254 10 kΩ, 50 kΩ, 100 kΩ VERSIONS V = +3 V ± 10% or +5 V ± 10%, V = 0 V or V /V = ±2.5 V ± 10%, V = V , V = 0 V, –40°C < T < +105°C, unless otherwise noted. DD SS DD SS A DD B A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS— RHEOSTAT MODE Resolution N AD5253/AD5254 6/8 Bits Resistor Differential Nonlinearity2 R-DNL R , R = NC, AD5253 −0.75 ±0.10 +0.75 LSB WB WA R , R = NC, AD5254 −1.00 ±0.25 +1.00 LSB WB WA Resistor Nonlinearity2 R-INL R , R = NC, AD5253 −0.75 ±0.25 +0.75 LSB WB WA R , R = NC, AD5254 −2.5 ±1.0 +2.5 LSB WB WA Nominal Resistor Tolerance ΔR /R T = 25°C −20 +20 % AB AB A Resistance Temperature (ΔR /R ) × 106/ΔT 650 ppm/°C AB AB Coefficient Wiper Resistance R I = 1 V/R, V = 5 V 75 130 Ω W W DD I = 1 V/R, V = 3 V 200 300 Ω W DD Channel-Resistance Matching ΔR /ΔR R = 10 kΩ, 50 kΩ 0.15 % AB1 AB2 AB R = 100 kΩ 0.05 % AB DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Differential Nonlinearity3 DNL AD5253 −0.5 ±0.1 +0.5 LSB AD5254 −1.0 ±0.3 +1.0 LSB Integral Nonlinearity3 INL AD5253 −0.50 ±0.15 +0.50 LSB AD5254 −1.5 ±0.5 +1.5 LSB Voltage Divider (ΔV /V ) × 106/ΔT Code = half scale 15 ppm/°C W W Temperature Coefficient Full-Scale Error V Code = full scale, AD5253 −1.0 −0.3 0 LSB WFSE Code = full scale, AD5254 −3 −1 0 LSB Zero-Scale Error V Code = zero scale, AD5253 0 0.3 1.0 LSB WZSE Code = zero scale, AD5254 0 1.2 3.0 LSB RESISTOR TERMINALS Voltage Range4 V , V , V V V V A B W SS DD Capacitance5 A, B C , C f = 1 kHz, measured to GND, 85 pF A B code = half scale Capacitance5 W C f = 1 kHz, measured to GND, 95 pF W code = half scale Common-Mode Leakage Current I V = V = V /2 0.01 1 µA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V V = 5 V, V = 0 V 2.4 V IH DD SS V /V = +2.7 V/0 V or V /V = ±2.5 V 2.1 V DD SS DD SS Input Logic Low V V = 5 V, V = 0 V 0.8 V IL DD SS V /V = +2.7 V/0 V or V /V = ±2.5 V 0.6 V DD SS DD SS Output Logic High (SDA) V R = 2.2 kΩ to V = 5 V, V = 0 V 4.9 V OH PULL-UP DD SS Output Logic Low (SDA) V R = 2.2 kΩ to V = 5 V, V = 0 V 0.4 V OL PULL-UP DD SS WP Leakage Current I WP = V 8 µA WP DD A0 Leakage Current I A0 = GND 3 µA A0 Input Leakage Current I V = 0 V or V ±1 µA I IN DD (Other than WP and A0) Input Capacitance5 C 5 pF I Rev. C | Page 5 of 32

AD5253/AD5254 Data Sheet Parameter Symbol Conditions Min Typ1 Max Unit POWER SUPPLIES Single-Supply Power Range V V = 0 V 2.7 5.5 V DD SS Dual-Supply Power Range V /V ±2.25 ±2.75 V DD SS Positive Supply Current I V = V or V = GND 5 15 µA DD IH DD IL Negative Supply Current I V = V or V = GND, V = 2.5 V, −5 −15 µA SS IH DD IL DD V = −2.5 V SS EEMEM Data Storing Mode I V = V or V = GND, T = 0°C to 105°C 35 mA DD_STORE IH DD IL A Current EEMEM Data Restoring Mode I V = V or V = GND, T = 0°C to 105°C 2.5 mA DD_RESTORE IH DD IL A Current6 Power Dissipation7 P V = V = 5 V or V = GND 0.075 mW DISS IH DD IL Power Supply Sensitivity PSS ΔV = 5 V ± 10% −0.005 +0.002 +0.005 %/% DD ΔV = 3 V ± 10% −0.010 +0.002 +0.010 %/% DD DYNAMIC CHARACTERISTICS5, 8 –3 dB Bandwidth BW R = 10 kΩ/50 kΩ/100 kΩ 400/80/40 kHz AB Total Harmonic Distortion THD V = 1 V rms, V = 0 V, f = 1 kHz 0.05 % W A B V Settling Time t V = V , V = 0 V, 1.5/7/14 µs W S A DD B R = 10 kΩ/50 kΩ/100 kΩ AB Resistor Noise Voltage e R = 10 kΩ/50 kΩ/100 kΩ, code = 9/20/29 nV/√Hz N_WB AB midscale, f = 1 kHz (thermal noise only) Digital Crosstalk C V = V , V = 0 V, measure V with −80 dB T A DD B W adjacent RDAC making full-scale change Analog Coupling C Signal input at A0 and measure output −72 dB AT at W1, f = 1 kHz 1 Typical values represent average readings at 25°C and V = 5 V. DD 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum and minimum resistance wiper positions. R-DNL is the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5254 1 kΩ version at V = 2.7 V, DD I = V /R for both V = 3 V and V = 5 V. W DD DD DD 3 INL and DNL are measured at V with the RDAC configured as a potentiometer divider, similar to a voltage output DAC. V = V and V = 0 V. DNL specification limits W A DD B of ±1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 Command 0 NOP should be activated after Command 1 to minimize I current consumption. DD_RESTORE 7 P is calculated from I × V = 5 V. DISS DD DD 8 All dynamic characteristics use V = 5 V. DD Rev. C | Page 6 of 32

Data Sheet AD5253/AD5254 INTERFACE TIMING CHARACTERISTICS All input control voltages are specified with t = t = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching R F characteristics are measured using both V = 3 V and 5 V. DD Table 3. Parameter1 Symbol Conditions Min Typ2 Max Unit INTERFACE TIMING SCL Clock Frequency f 400 kHz SCL t Bus-Free Time Between Stop and Start t 1.3 μs BUF 1 t Hold Time (Repeated Start) t After this period, the first clock pulse is 0.6 μs HD;STA 2 generated. t Low Period of SCL Clock t 1.3 μs LOW 3 t High Period of SCL Clock t 0.6 μs HIGH 4 t Set-up Time for Start Condition t 0.6 μs SU;STA 5 t Data Hold Time t 0 0.9 μs HD;DAT 6 t Data Set-up Time t 100 ns SU;DAT 7 t Fall Time of Both SDA and SCL Signals t 300 ns F 8 t Rise Time of Both SDA and SCL Signals t 300 ns R 9 t Set-up Time for Stop Condition t 0.6 μs SU;STO 10 EEMEM Data Storing Time t 26 ms EEMEM_STORE EEMEM Data Restoring Time at Power-On3 t V rise time dependent. Measure without 300 μs EEMEM_RESTORE1 DD decoupling capacitors at V and V . DD SS EEMEM Data Restoring Time upon Restore t V = 5 V. 300 μs EEMEM_RESTORE2 DD Command or Reset Operation3 EEMEM Data Rewritable Time4 t 540 μs EEMEM_REWRITE FLASH/EE MEMORY RELIABILITY Endurance5 100 K cycles Data Retention6, 7 100 Years 1 See Figure 23 for location of measured values. 2 Typical values represent average readings at 25°C and VDD = 5 V. 3 During power-up, all outputs are preset to midscale before restoring the EEMEM contents. RDAC0 has the shortest EEMEM restore time, whereas RDAC3 has the longest. 4 Delay time after power-on or reset before new EEMEM data to be written. 5 Endurance is qualified to 100,000 cycles per JEDEC Std. 22 Method A117 and measured at –40°C, +25°C, and +105°C; typical endurance at +25°C is 700,000 cycles. 6 Retention lifetime equivalent at junction temperature TJ = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature. 7 When the part is not in operation, the SDA and SCL pins should be pulled high. When these pins are pulled low, the I2C interface at these pins conducts a current of about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V. Rev. C | Page 7 of 32

AD5253/AD5254 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted A Table 4. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V, +7 V DD rating only; functional operation of the device at these or any V to GND +0.3 V, −7 V SS other conditions above those indicated in the operational V to V 7 V DD SS section of this specification is not implied. Exposure to absolute V , V , V to GND V , V A B W SS DD maximum rating conditions for extended periods may affect Maximum Current device reliability. I , I Pulsed ±20 mA WB WA I Continuous (R ≤ 1 kΩ, A Open)1 ±5 mA WB WB I Continuous (R ≤ 1 kΩ, B Open)1 ±5 mA WA WA ESD CAUTION I Continuous ±5 mA/±500 µA/ AB (R = 1 kΩ/10 kΩ/50 kΩ/100 kΩ)1 ±100 µA/±50 µA AB Digital Inputs and Output Voltage to GND 0 V, 7 V Operating Temperature Range −40°C to +105°C Maximum Junction Temperature (T ) 150°C JMAX Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C TSSOP-20 Thermal Resistance2 θ 143°C/W JA 1 Maximum terminal current is bound by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. V = 5 V. DD 2 Package power dissipation = (T − T)/θ . JMAX A JA Rev. C | Page 8 of 32

Data Sheet AD5253/AD5254 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS W0 1 20 VDD B0 2 AD5253/ 19 W3 A0 3 AD5254 18 B3 AD0 4 TOP VIEW 17 A3 WP 5 (Not to Scale) 16 AD1 W1 6 15 DGND B1 7 14 SCL A1 8 13 W2 SVDSAS 190 1121 BA22 03824-0-002 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 W0 Wiper Terminal of RDAC0. V ≤ V ≤ V . SS W0 DD 2 B0 B Terminal of RDAC0. V ≤ V ≤ V . SS B0 DD 3 A0 A Terminal of RDAC0. V ≤ V ≤ V . SS A0 DD 4 AD0 I2C Device Address 0. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed. 5 WP Write Protect, Active Low. V ≤ V + 0.3 V. WP DD 6 W1 Wiper Terminal of RDAC1. V ≤ V ≤ V . SS W1 DD 7 B1 B Terminal of RDAC1. V ≤ V ≤ V . SS B1 DD 8 A1 A Terminal of RDAC1. V ≤ V ≤ V . SS A1 DD 9 SDA Serial Data Input/Output Pin. Shifts in one bit at a time upon positive clock edges. MSB loaded first. Open-drain MOSFET requires pull-up resistor. 10 V Negative Supply. Connect to 0 V for single supply or –2.7 V for dual supply, where V – V ≤ +5.5 V. If V is used SS DD SS SS rather than grounded in dual supply, V must be able to sink 35 mA for 26 ms when storing data to EEMEM. SS 11 A2 A Terminal of RDAC2. V ≤ V ≤ V . SS A2 DD 12 B2 B Terminal of RDAC2. V ≤ V ≤ V . SS B2 DD 13 W2 Wiper Terminal of RDAC2. V ≤ V ≤ V . SS W2 DD 14 SCL Serial Input Register Clock Pin. Shifts in one bit at a time upon positive clock edges. V ≤ (V + 0.3 V). Pull-up SCL DD resistor is recommended for SCL to ensure minimum power. 15 DGND Digital Ground. Connect to system analog ground at a single point. 16 AD1 I2C Device Address 1. AD0 and AD1 allow four AD5253/AD5254 devices to be addressed. 17 A3 A Terminal of RDAC3. V ≤ V ≤ V . SS A3 DD 18 B3 B Terminal of RDAC3. V ≤ V ≤ V . SS B3 DD 19 W3 Wiper Terminal of RDAC3. V ≤ V ≤ V . SS W3 DD 20 V Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or ±2.7 V for dual supply, where V – V ≤ +5.5 V. DD DD SS V must be able to source 35 mA for 26 ms when storing data to EEMEM. DD Rev. C | Page 9 of 32

AD5253/AD5254 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 TA=–40°C, +25°C, +85°C, +125°C 0.6 TA=–40°C, +25°C, +85°C, +125°C 0.6 0.4 0.4 SB) 0.2 B) 0.2 L S NL ( 0 L (L 0 R-I–0.2 DN–0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 03824-0-015 –1.00 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 03824-0-018 Figure 3. R-INL vs. Code Figure 6. DNL vs. Code 1.0 10 0.8 TA =–40°C, +25°C, +85°C, +125°C 8 0.6 6 IDD @ VDD= +5.5V 0.4 4 DNL (LSB) 0.02 µ (A)DD 02 IDD @ VDD= +2.7V R-–0.2 I –2 –0.4 –4 ISS @ VDD= +2.7V, VSS=–2.7V –0.6 –6 –0.8 –8 –1.00 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 03824-0-016 –10–40 –20 0 2T0EMPER40ATURE6 0(°C) 80 100 120 03824-0-019 Figure 4. R-DNL vs. Code Figure 7. Supply Current vs. Temperature 1.0 10 0.8 TA=–40°C, +25°C, +85°C, +125°C 0.6 1 VDD= 5.5V 0.4 0.2 0.1 B) A) L (LS 0 (mDD IN–0.2 I0.01 –0.4 VDD= 2.7V –0.6 0.001 –0.8 –1.00 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 03824-0-017 0.00010 1 DIG2ITAL INPU3T VOLTAG4E (V) 5 6 03824-0-020 Figure 5. INL vs. Code Figure 8. Supply Current vs. Digital Input Voltage, T = 25°C A Rev. C | Page 10 of 32

Data Sheet AD5253/AD5254 240 50 220 DATA = 0x00 C) 45 VDD= 5V 210800 VTDAD== 2 25.7CV O (ppm/° 40 TVVAAB === 0V–V4D0D°C TO +85°C 160 C 35 P M ) 140 TE 30 R (WB110200 VTDAD== 2 55.5CV R MODE 2205 80 TE 60 ME 15 100kΩ 10kΩ O 40 NTI 10 E 20 OT 5 50kΩ P 00 1 2 VBIA3S(V) 4 5 6 03824-0-021 00 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 03824-0-024 Figure 9. Wiper Resistance vs. VBIAS Figure 12. Potentiometer Mode Tempco (∆VWB/VWB)/∆T × 106 vs. Code 6 0 0xFF –6 0x80 4 0x40 –12 0x20 –18 0x10 2 R(%)WB 0 GAIN (dB) –––233460 0x08 0x04 0x02 –2 –42 0x01 0x00 –48 –4 –54 –6–40 –20 0 T2E0MPERA40TURE (60C) 80 100 120 03824-0-022 –6010 100 1k FREQ1U0kENCY (1H0z0)k 1M 10M 03824-0-025 Figure 10. Change of RWB vs. Temperature Figure 13. Gain vs. Frequency vs. Code, RAB = 1 kΩ, TA = 25°C 1000 0 0xFF O (ppm/°C) 899505000 TVVVADAB D=== =V0– V45D0VD°C TO +85°C ––11–286 000xxx842000 C E TEMP 785000 10kΩ N (dB) ––2340 00xx1008 MOD 700 100kΩ GAI –36 0x04 STAT 650 50kΩ –42 0x01 O HE 600 –48 0x00 R 550 –54 0x02 5000 32 64 9C6ODE 1(D28ecima1l6)0 192 224 256 03824-0-023 –6010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 03824-0-026 Figure 11. Rheostat Mode Tempco (∆RWB/RWB)/∆T × 106 vs. Code Figure 14. Gain vs. Frequency vs. Code, RAB = 10 kΩ, TA = 25°C Rev. C | Page 11 of 32

AD5253/AD5254 Data Sheet 0 1.2 –6 0xFF TA= 25°C 0x80 1.0 –12 0x40 –18 0x20 0.8 –24 GAIN (dB) ––3360 00xx1008 I (mA)DD 0.6 VDD= 5.5V 0x04 0.4 –42 0x02 –48 0x01 0.2 VDD= 2.7V –54 0x00 –6010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M 03824-0-027 01 10 100CLOC1Kk FREQ1U0EkNCY (1H0z0)k 1M 10M 03824-0-030 Figure 15. Gain vs. Frequency vs. Code, RAB = 50 kΩ, TA = 25°C Figure 18. Supply Current vs. Digital Input Clock Frequency 0 0x80 0xFF CLK –6 0x40 VDD = 5V –12 0x20 –18 0x10 –24 B) d 0x08 N ( –30 GAI –36 0x04 VW 0x02 –42 DIGITAL FEEDTHROUGH 0x01 MIDSCALE TRANSITION –48 7FH  80H –54 0x00 –6010 100 1kFREQU1E0NkCY (Hz1)00k 1M 10M03824-0-028 400ns/DIV 03824-0-031 Figure 16. Gain vs. Frequency vs. Code, RAB = 100 kΩ, TA = 25°C Figure 19. Clock Feedthrough and Midscale Transition Glitch 100 VDD = 5.5V 80 100k 60 VDD (NO DE- 40 10k RESTORE RDAC0 COUPLING SETTING TO 0xFF CAPS) 20 MIDSCALE ) 1k PRESET VWB0 (AB 0 RESTORE RDAC3 (S0TxOFFRED R –20 SETTING TO 0xFF IN EEMEM) 50k MIDSCALE –40 PRESET VWB3 (0xFF –60 STORED VDD = VA0 = VA3 = 3.3V IN EEMEM) –80 GND = VB0 = VB3 –1000 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 03824-0-029 03824-0-046 Figure 17. ΔRAB vs. Code, TA = 25°C Figure 20. tEEMEM_RESTORE of RDAC0 and RDAC3 Rev. C | Page 12 of 32

Data Sheet AD5253/AD5254 6 6 5 RAB= 1kΩ 5 RAB= 1kΩ A) A) m m (B_MAX 4 VTAA== 2V5B°C=OPEN (B_MAX 4 VTAA== 2V5B°C=OPEN W W L I 3 L I 3 A A C C TI TI ORE 2 RAB= 10kΩ ORE 2 RAB= 10kΩ E E H H T T 1 RAB= 50kΩ 1 RAB= 50kΩ RAB= 100kΩ RAB= 100kΩ 00 8 16 24CODE3 2(Decim4a0l) 48 56 64 03824-0-033 00 32 64 96COD1E2 (8Decim1a6l0) 192 224 256 03824-0-034 Figure 21. AD5253 I vs. Code Figure 22. AD5254 I vs. Code WB_MAX WB_MAX Rev. C | Page 13 of 32

AD5253/AD5254 Data Sheet I2C INTERFACE t8 t6 t9 t2 SCL t2 t3 t4 t7 t5 t10 t8 t9 SDA P t1 S S P 03824-0-003 Figure 23. I2C Interface Timing Diagram I2C INTERFACE GENERAL DESCRIPTION From Master to Slave From Slave to Master S = start condition P = stop condition A = acknowledge (SDA low) A = not acknowledge (SDA high) R/W = read enable at high; write enable at low SLAVE ADDRESS INSTRUCTIONS DATA S R/W A A A/A P (7-BIT) (8-BIT) (8-BIT) 0 WRITE (N BDYATTEAS T+R AACNKSNFOEWRRLEEDDGE) 03824-0-004 Figure 24. I2C—Master Writing Data to Slave SLAVE ADDRESS DATA DATA S R/W A A A P (7-BIT) (8-BIT) (8-BIT) 1 READ (N BDYATTEAS T+R AACNKSNFOEWRRLEEDDGE) 03824-0-005 Figure 25. I2C—Master Reading Data from Slave S SLAVE ADDRESS R/W A DATA A/A S SLAVE ADDRESS R/W A DATA A/A P (7-BIT) READ OR WRITE (N BYTES + REPEATED START READ (N BYTES + 03824-0-006 ACKNOWLEDGE) OR WRITE ACKNOWLEDGE) DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT Figure 26. I2C—Combined Write/Read Rev. C | Page 14 of 32

Data Sheet AD5253/AD5254 I2C INTERFACE DETAIL DESCRIPTION From Master to Slave From Slave to Master S = start condition P = stop condition A = acknowledge (SDA low) A = not acknowledge (SDA high) AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0 R/W= read enable bit at logic high; write enable bit at logic low CMD/REG = command enable bit at logic high; register access bit at logic low EE/RDAC = EEMEM register at logic high; RDAC register at logic low A4, A3, A2, A1, A0 = RDAC/EEMEM register addresses S 0 1 0 1 1 A A 0 A CMD/ 0 EE/ A A A A A A DATA A/ P D D REG RDAC 4 3 2 1 0 A 1 0 SLAVEADDRESS 0 WRITE IANNSDTRAUDCDTRIOENSSS ACK(1N OBYWTLEE +DGE) 03824-0-007 0 REG Figure 27. Single Write Mode S 0 1 0 1 1 A A 0 A CMD/ 0 EE/ A A A A A A RDAC_N A RDAC_N + 1 A/ P D D REG RDAC 4 3 2 1 0 DATA DATA A 1 0 SLAVE ADDRESS 0 WRITE IANNSDTR AUDCDTRIOENSSS ACK(NN OBWYTLEE D+GE) 03824-0-008 0 REG Figure 28. Consecutive Write Mode Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0) A4 A3 A2 A1 A0 RDAC Data Byte Description 0 0 0 0 0 RDAC0 6-/8-bit wiper setting (2 MSB of AD5253 are X) 0 0 0 0 1 RDAC1 6-/8-bit wiper setting (2 MSB of AD5253 are X) 0 0 0 1 0 RDAC2 6-/8-bit wiper setting (2 MSB of AD5253 are X) 0 0 0 1 1 RDAC3 6-/8-bit wiper setting (2 MSB of AD5253 are X) 0 0 1 0 0 Reserved : : : : : : : : : : : : 0 1 1 1 1 Reserved Rev. C | Page 15 of 32

AD5253/AD5254 Data Sheet RDAC/EEMEM Write Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers Setting the wiper position requires an RDAC write operation. (R/W = 0, CMD/REG = 0, EE/RDAC = 1) The single write operation is shown in Figure 27, and the A4 A3 A2 A1 A0 Data Byte Description consecutive write operation is shown in Figure 28. In the 0 0 0 0 0 Store RDAC0 setting to EEMEM01 consecutive write operation, if the RDAC is selected and the 0 0 0 0 1 Store RDAC1 setting to EEMEM11 address starts at 0, the first data byte goes to RDAC0, the second 0 0 0 1 0 Store RDAC2 setting to EEMEM21 data byte goes to RDAC1, the third data byte goes to RDAC2, 0 0 0 1 1 Store RDAC3 setting to EEMEM31 and the fourth data byte goes to RDAC3. This operation can be 0 0 1 0 0 Store user data to EEMEM4 continued for up to eight addresses with four unused addresses; 0 0 1 0 1 Store user data to EEMEM5 it then loops back to RDAC0. If the address starts at any of the 0 0 1 1 0 Store user data to EEMEM6 eight valid addresses, N, the data first goes to RDAC_N, 0 0 1 1 1 Store user data to EEMEM7 RDAC_N + 1, and so on; it loops back to RDAC0 after the 0 1 0 0 0 Store user data to EEMEM8 eighth address. The RDAC address is shown in Table 6. 0 1 0 0 1 Store user data to EEMEM9 While the RDAC wiper setting is controlled by a specific 0 1 0 1 0 Store user data to EEMEM10 RDAC register, each RDAC register corresponds to a specific 0 1 0 1 1 Store user data to EEMEM11 EEMEM location, which provides nonvolatile wiper storage 0 1 1 0 0 Store user data to EEMEM12 functionality. The addresses are shown in Table 7. The single 0 1 1 0 1 Store user data to EEMEM13 and consecutive write operations also apply to EEMEM write 0 1 1 1 0 Store user data to EEMEM14 operations. 0 1 1 1 1 Store user data to EEMEM15 There are 12 nonvolatile memory locations: EEMEM4 to EEMEM15. Users can store 12 bytes of information, such as Table 8. Addresses for Reading (Restoring) RDAC Settings memory data for other components, look-up tables, or system and User Data from EEMEM identification information. (R/W = 1, CMD/REG = 0, EE/RDAC = 1) A4 A3 A2 A1 A0 Data Byte Description In a write operation to the EEMEM registers, the device disables 0 0 0 0 0 Read RDAC0 setting from EEMEM0 the I2C interface during the internal write cycle. Acknowledge 0 0 0 0 1 Read RDAC1 setting from EEMEM1 polling is required to determine the completion of the write 0 0 0 1 0 Read RDAC2 setting from EEMEM2 cycle. See the EEMEM Write-Acknowledge Polling section. 0 0 0 1 1 Read RDAC3 setting from EEMEM3 RDAC/EEMEM Read 0 0 1 0 0 Read User data from EEMEM4 0 0 1 0 1 Read user data from EEMEM5 The AD5253/AD5254 provide two different RDAC or EEMEM 0 0 1 1 0 Read user data from EEMEM6 read operations. For example, Figure 29 shows the method of 0 0 1 1 1 Read user data from EEMEM7 reading the RDAC0 to RDAC3 contents without specifying the 0 1 0 0 0 Read user data from EEMEM8 address, assuming Address RDAC0 was already selected in the 0 1 0 0 1 Read user data from EEMEM9 previous operation. If an RDAC_N address other than RDAC0 0 1 0 1 0 Read user data from EEMEM10 was previously selected, readback starts with Address N, 0 1 0 1 1 Read user data from EEMEM11 followed by N + 1, and so on. 0 1 1 0 0 Read user data from EEMEM12 Figure 30 illustrates a random RDAC or EEMEM read 0 1 1 0 1 Read user data from EEMEM13 operation. This operation allows users to specify which RDAC 0 1 1 1 0 Read user data from EEMEM14 or EEMEM register is read by issuing a dummy write command 0 1 1 1 1 Read user data from EEMEM15 to change the RDAC address pointer and then proceeding with 1 Users can store any of the 64 RDAC settings for AD5253 or any of the 256 the RDAC read operation at the new address location. RDAC settings for the AD5254 directly to the EEMEM. This is not limited to current RDAC wiper setting. Rev. C | Page 16 of 32

Data Sheet AD5253/AD5254 From Master to Slave From Slave to Master S = start condition P = stop condition A = acknowledge (SDA low) A = not acknowledge (SDA high) AD1, AD0 = I2C device address bits, must match with the logic states at Pins AD1, AD0 R/W = read enable bit at logic high; write enable bit at logic low CMD/REG = command enable bit at logic high; register access bit at logic low C3, C2, C1, C0 = command bits A2, A1, A0 = RDAC/EEMEM register addresses S 0 1 0 1 1 A A 1 A RDAC_N OR EEMEM_N A RDAC_N + 1 OR EEMEM_N + 1 A P D D REGISTER DATA REGISTER DATA 1 0 SLAVE ADDRESS 1 READ (N BYTES + ACKNOWLEDGE) 03824-0-009 Figure 29. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register) S SLAVE ADDRESS 0 A INSTRUCTIONAL AND A S SLAVE ADDRESS 1 A RDAC OR A/A P ADDRESS EEMEM DATA 0 WRITE REPEATED START 1 READ (N BYTES + ACKNOWLEDGE) 03824-0-010 Figure 30. RDAC or EEMEM Random Read S 0 1 0 1 1 A A 0 A CMD/ C C C C A A A A P D D REG 3 2 1 0 2 1 0 1 0 RDAC SLAVE ADDRESS0 WRITE 1 CMD 03824-0-011 Figure 31. RDAC Quick Command Write (Dummy Write) Rev. C | Page 17 of 32

AD5253/AD5254 Data Sheet RDAC/EEMEM Quick Commands bits are designated for the decimal portion of tolerance. As shown in Table 10 and Figure 32, for example, if the rated R is The AD5253/AD5254 feature 12 quick commands that facilitate AB 10 kΩ and the data readback from Address 11000 shows 0001 easy manipulation of RDAC wiper settings and provide RDAC- 1100 and Address 11001 shows 0000 1111, then RDAC0 to-EEMEM storing and restoring functions. The command tolerance can be calculated as format is shown in Figure 31, and the command descriptions are shown in Table 9. MSB: 0 = + Next 7 MSB: 001 1100 = 28 When using a quick command, issuing a third byte is not 8 LSB: 0000 1111 = 15 × 2–8 = 0.06 needed, but is allowed. The quick commands reset and store Tolerance = 28.06% and, therefore, RDAC to EEMEM require acknowledge polling to determine R = 12.806 kΩ whether the command has finished executing. AB_ACTUAL EEMEM Write-Acknowledge Polling R Tolerance Stored in Read-Only Memory AB After each write operation to the EEMEM registers, an internal The AD5253/AD5254 feature patented R tolerances storage in AB write cycle begins. The I2C interface of the device is disabled. To the nonvolatile memory. The tolerance of each channel is stored determine if the internal write cycle is complete and the I2C in the memory during the factory production and can be read interface is enabled, interface polling can be executed. I2C by users at any time. The knowledge of the stored tolerance, interface polling can be conducted by sending a start condition which is the average of R over all codes (see Figure 16), allows AB followed by the slave address and the write bit. If the I2C users to predict R accurately. This feature is valuable for AB interface responds with an ACK, the write cycle is complete and precision, rheostat mode, and open-loop applications, in which the interface is ready to proceed with further operations. Other- knowledge of absolute resistance is critical. wise, I2C interface polling can be repeated until it succeeds. The stored tolerances reside in the read-only memory and are Command 2 and Command 7 also require acknowledge polling. expressed as percentages. Each tolerance is 16 bits long and is EEMEM Write Protection stored in two memory locations (see Table 10). The tolerance Setting the WP pin to logic low after EEMEM programming data is expressed in sign magnitude binary format stored in two bytes; an example is shown in Figure 32 . For the first byte in protects the memory and RDAC registers from future write Register N, the MSB is designated for the sign (0 = + and 1 = –) operations. In this mode, the EEMEM and RDAC read and the 7 LSB is designated for the integer portion of the operations function as normal. tolerance. For the second byte in Register N + 1, all eight data Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0) C3 C2 C1 C0 Command Description 0 0 0 0 NOP 0 0 0 1 Restore EEMEM (A1, A0) to RDAC (A1, A0)1 0 0 1 0 Store RDAC (A1, A0) to EEMEM (A1, A0) 0 0 1 1 Decrement RDAC (A1, A0) 6 dB 0 1 0 0 Decrement all RDACs 6 dB 0 1 0 1 Decrement RDAC (A1, A0) one step 0 1 1 0 Decrement all RDACs one step 0 1 1 1 Reset: restore EEMEMs to all RDACs 1 0 0 0 Increment RDACs (A1, A0) 6 dB 1 0 0 1 Increment all RDACs 6 dB 1 0 1 0 Increment RDACs (A1, A0) one step 1 0 1 1 Increment all RDACs one step 1 1 0 0 Reserved : : : : : : : : : : 1 1 1 1 Reserved 1 This command leaves the device in the EEMEM read power state, which consumes power. Issue the NOP command to return the device to its idle state. Rev. C | Page 18 of 32

Data Sheet AD5253/AD5254 Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1) A4 A3 A2 A1 A0 Data Byte Description 1 1 0 0 0 Sign and 7-bit integer values of RDAC0 tolerance (read only) 1 1 0 0 1 8-bit decimal value of RDAC0 tolerance (read only) 1 1 0 1 0 Sign and 7-bit integer values of RDAC1 tolerance (read only) 1 1 0 1 1 8-bit decimal value of RDAC1 tolerance (read only) 1 1 1 0 0 Sign and 7-bit integer values of RDAC2 tolerance (read only) 1 1 1 0 1 8-bit decimal value of RDAC2 tolerance (read only) 1 1 1 1 0 Sign and 7-bit integer values of RDAC3 tolerance (read only) 1 1 1 1 1 8-bit decimal value of RDAC3 tolerance (read only) A D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 A SIGN 26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 SIGN 7 BITS FOR INTEGER NUMBER 8 BITS FOR DECIMAL NUMBER 03824-0-012 Figure 32. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions (Unit is Percent, Only Data Bytes Are Shown) Rev. C | Page 19 of 32

AD5253/AD5254 Data Sheet I2C-COMPATIBLE 2-WIRE SERIAL BUS 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 AD1AD0 R/W X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ACK. BY ACK. BY STMAARSTT EBRY SLAVE FARDADMREE S1S BYTE AD525x INSTRFURCATMIOEN 2 BYTE AD525x DFARTAAM BEY T1E AD525xSMTAOSPT EBRY 03824-0-013 Figure 33. General I2C Write Pattern 1 9 1 9 SCL SDA 0 1 0 1 1 AD1AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY NO ACK. BY STMAARSTT BERY SLAVE FARDADMREE1SS BYTE AD525x RDAFCR RAEMGEI S2TER MASTESMRTAOSPT EBRY 03824-0-014 Figure 34. General I2C Read Pattern enables the RDAC register. The 5 LSB, A4 to A0, designates The first byte of the AD5253/AD5254 is a slave address byte the addresses of the EEMEM and RDAC registers (see (see Figure 33 and Figure 34). It has a 7-bit slave address and an Figure 27 and Figure 28). When MSB = 1 or when the R/W bit. The 5 MSB of the slave address is 01011, and the next device is in CMD mode, the four bits following the MSB 2 LSB is determined by the states of the AD1 and AD0 pins. are C3 to C1, which correspond to 12 predefined EEMEM AD1 and AD0 allow the user to place up to four controls and quick commands; there are also four factory- AD5253/AD5254 devices on one bus. reserved commands. The 3 LSB—A2, A1, and A0—are 4- AD5253/AD5254 can be controlled via an I2C-compatible serial channel RDAC addresses (see Figure 31). After bus and are connected to this bus as slave devices. The 2-wire acknowledging the instruction byte, the last byte in the I2C serial bus protocol (see Figure 33 and Figure 34) follows: write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits 1. The master initiates a data transfer by establishing a start followed by an acknowledge bit). The transitions on the condition, such that SDA goes from high to low while SCL SDA line must occur during the low period of SCL and is high (see Figure 33). The following byte is the slave remain stable during the high period of SCL (see Figure 33). address byte, which consists of the 5 MSB of a slave address defined as 01011. The next two bits are AD1 and AD0, I2C 3. In current read mode, the RDAC0 data byte immediately device address bits. Depending on the states of their AD1 follows the acknowledgment of the slave address byte. and AD0 bits, four AD5253/AD5254 devices can be After an acknowledgement, RDAC1 follows, then RDAC2, addressed on the same bus. The last LSB, the R/W bit, and so on. (There is a slight difference in write mode, determines whether data is read from or written to the where the last eight data bits representing RDAC3 data are slave device. followed by a no acknowledge bit.) Similarly, the transitions on the SDA line must occur during the low The slave whose address corresponds to the transmitted period of SCL and remain stable during the high period of address responds by pulling the SDA line low during the SCL (see Figure 34). Another reading method, random ninth clock pulse (this is called an acknowledge bit). At read method, is shown in Figure 30. this stage, all other devices on the bus remain idle while 4. When all data bits have been read or written, a stop the selected device waits for data to be written to or read condition is established by the master. A stop condition is from its serial register. defined as a low-to-high transition on the SDA line that 2. In the write mode (except when restoring EEMEM to the occurs while SCL is high. In write mode, the master pulls RDAC register), there is an instruction byte that follows the SDA line high during the 10th clock pulse to establish a the slave address byte. The MSB of the instruction byte is stop condition (see Figure 33). In read mode, the master labeled CMD/REG. MSB = 1 enables CMD, the command issues a no acknowledge for the ninth clock pulse, that is, the SDA line remains high. The master brings the SDA line instruction byte; MSB = 0 enables general register writing. low before the 10th clock pulse and then brings the SDA The third MSB in the instruction byte, labeled EE/RDAC, line high to establish a stop condition (see Figure 34). is true when MSB = 0 or when the device is in general writing mode. EE enables the EEMEM register, and REG Rev. C | Page 20 of 32

Data Sheet AD5253/AD5254 THEORY OF OPERATION Table 11. Quick Commands The AD5253/AD5254 are quad-channel digital potentiometers Command Description in 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ that allow 64/256 linear resis- 0 NOP. tance step adjustments. The AD5253/AD5254 employ double- 1 Restore EEMEM content to RDAC. User should gate CMOS EEPROM technology, which allows resistance issue NOP immediately after this command to settings and user-defined data to be stored in the EEMEM conserve power. registers. The EEMEM is nonvolatile, such that settings remain 2 Store RDAC register setting to EEMEM. when power is removed. The RDAC wiper settings are restored 3 Decrement RDAC 6 dB (shift data bits right). from the nonvolatile memory settings during device power-up 4 Decrement all RDACs 6 dB (shift all data bits right). and can also be restored at any time during operation. 5 Decrement RDAC one step. The AD5253/AD5254 resistor wiper positions are determined 6 Decrement all RDACs one step. by the RDAC register contents. The RDAC register acts like a 7 Reset EEMEM contents to all RDACs. scratch-pad register, allowing unlimited changes of resistance 8 Increment RDAC 6 dB (shift data bits left). settings. RDAC register contents can be changed using the 9 Increment all RDACs 6 dB (shift all data bits left). device’s serial I2C interface. The format of the data-words and 10 Increment RDAC one step. the commands to program the RDAC registers are discussed in 11 Increment all RDACs one step. the I2C Interface section. 12 to 15 Reserved. The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistor wiper LINEAR INCREMENT/DECREMENT COMMANDS position settings. The AD5253/AD5254 provide commands to The increment and decrement commands (10, 11, 5, and 6) are store the RDAC register contents to their respective EEMEM useful for linear step-adjustment applications. These commands memory locations. During subsequent power-on sequences, the simplify microcontroller software coding by allowing the RDAC registers are automatically loaded with the stored value. controller to send just an increment or decrement command to the AD5253/AD5254. The adjustments can be directed to a Whenever the EEMEM write operation is enabled, the device single RDAC or to all four RDACs. activates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level; this essentially erases the ±6 dB ADJUSTMENTS current content in the EEMEM register and allows subsequent (DOUBLING/HALVING WIPER SETTING) storage of the new content. Saving data to an EEMEM register The AD5253/AD5254 accommodate ±6 dB adjustments of the consumes about 35 mA of current and lasts approximately RDAC wiper positions by shifting the register contents to left/ 26 ms. Because of charge-pump operation, all RDAC channels right for increment/decrement operations, respectively. Com- may experience noise coupling during the EEMEM writing mand 3, Command 4, Command 8, and Command 9 can be operation. used to increment or decrement the wiper positions in 6 dB The EEMEM restore time in power-up or during operation is steps synchronously or asynchronously. about 300 µs. Note that the power-up EEMEM refresh time Incrementing the wiper position by +6 dB essentially doubles depends on how fast V reaches its final value. As a result, any DD the RDAC register value, whereas decrementing the wiper supply voltage decoupling capacitors limit the EEMEM restore position by –6 dB halves the register content. Internally, the time during power-up. For example, Figure 20 shows the AD5253/AD5254 use shift registers to shift the bits left and power-up profile of the V where there is no decoupling DD right to achieve a ±6 dB increment or decrement. The capacitors and the applied power is a digital signal. The device maximum number of adjustments is nine and eight steps for initially resets the RDACs to midscale before restoring the incrementing from zero scale and decrementing from full scale, EEMEM contents. The omission of the decoupling capacitors respectively. These functions are useful for various audio/video should only be considered when the fast restoring time is level adjustments, especially for white LED brightness settings absolutely needed in the application. In addition, users should in which human visual responses are more sensitive to large issue a NOP Command 0 immediately after using Command 1 adjustments than to small adjustments. to restore the EEMEM setting to RDAC, thereby minimizing supply current dissipation. Reading user data directly from EEMEM does not require a similar NOP command execution. In addition to the movement of data between RDAC and EEMEM registers, the AD5253/AD5254 provide other shortcut commands that facilitate programming, as shown in Table 11. Rev. C | Page 21 of 32

AD5253/AD5254 Data Sheet DIGITAL INPUT/OUTPUT CONFIGURATION MULTIPLE DEVICES ON ONE BUS SDA is a digital input/output with an open-drain MOSFET that The AD5253/AD5254 are equipped with two addressing pins, requires a pull-up resistor for proper communication. On the AD1 and AD0, that allow up to four AD5253/AD5254 devices other hand, SCL and WP are digital inputs for which pull-up to be operated on one I2C bus. To achieve this result, the states of resistors are recommended to minimize the MOSFET cross- AD1 and AD0 on each device must first be defined. An example conduction current when the driving signals are lower than is shown in Table 12 and Figure 37. In I2C programming, each VDD. SCL and WP have ESD protection diodes, as shown in device is issued a different slave address—01011(AD1)(AD0)— Figure 35 and Figure 36. to complete the addressing. Table 12. Multiple Devices Addressing WP can be permanently tied to V without a pull-up resistor if DD AD1 AD0 Device Addressed the write-protect feature is not used. If WP is left floating, an 0 0 U1 internal current source pulls it low to enable write protection. In 0 1 U2 applications in which the device is programmed infrequently, 1 0 U3 this allows the part to default to write-protection mode after 1 1 U4 any one-time factory programming or field calibration without using an on-board pull-down resistor. Because there are protection diodes on all inputs, the signal levels must not be 5V greater than VDD to prevent forward biasing of the diodes. RP RP VDD SDA MASTER SCL 5V 5V 5V SDA SCL SDA SCL SDA SCL SDA SCL SCL AD1 AD1 AD1 AD1 03824-0-035 AAADDD055225534/ AAADDD055225534/ AAADDD055225534/ AAADDD055225534/ 03824-0-037 Figure 37. Multiple AD5253/AD5254 Devices on a Single Bus GND Figure 35. SCL Digital Input In wireless base station smart-antenna systems that require arrays of digital potentiometers to bias the power amplifiers, VDD large numbers of AD5253/AD5254 devices can be addressed by using extra decoders, switches, and I/O buses, as shown in INPUTS Figure 38. For example, to communicate to a total of 16 devices, four decoders and 16 sets of combinational switches (four sets WP shown in Figure 38) are needed. Two I/O buses serve as the common inputs of the four 2 × 4 decoders and select four sets 03824-0-036 ocof moubtipnuattsio ant esawcihtc cho omubtpinuattsi oarne. uBneciqauues,e atsh seh foowurn s ient sF oigf ure 38, a specific device is addressed by properly programming the I2C GND with the slave address defined as 01011(AD1)(AD0). This Figure 36. Equivalent WP Digital Input operation allows one of 16 devices to be addressed, provided that the inputs of the two decoders do not change states. The inputs of the decoders are allowed to change once the operation of the specified device is completed. Rev. C | Page 22 of 32

Data Sheet AD5253/AD5254 +5V VDD  4 R1 AD1 A 2 2 4 4 N1 AD0 W DECODER B +5V R2X  4 AD1 VSS 03824-0-039 2 4 4 N2X Figure 39. Maximum Termina l Voltages Set by VDD and VSS DECODER +5 POWER-UP AND POWER-DOWN SEQUENCES P2Y AD0 Because the ESD protection diodes limit the voltage compliance at Terminal A, Terminal B, and Terminal W (Figure 39), it is P2Y important to power V /V before applying any voltage to DD SS these terminals. Otherwise, the diodes are forward biased such 4 +5V that VDD/VSS are powered unintentionally and may affect the 2DE C4ODER  4 user’s circuit. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is in the following order: GND, P3X AD1 V , V , digital inputs, and V /V /V . The order of powering DD SS A B W R3X R3Y VA, VB, VW, and the digital inputs is not important, as long as they are powered after V /V . AD0 DD SS N3Y LAYOUT AND POWER SUPPLY BIASING It is always a good practice to employ a compact, minimum +5V lead-length layout design. The leads to the input should be as 4 2 4 direct as possible, with a minimum conductor length. Ground DECODER  4 paths should have low resistance and low inductance. P4 AD1 Similarly, it is also good practice to bypass the power supplies R4 AD0 with quality capacitors. Low equivalent series resistance (ESR) 03824-0-038 1ap μpFli etod 1a0t tμhFe tsaunptpalluiems t oor m eliencitmroizlyet iacn cya tpraacnistioernst s dhiosutuldrb baen ce Figure 38. Four Devices with AD1 and AD0 of 00 and filter low frequency ripple. Figure 40 illustrates the basic supply-bypassing configuration for the AD5253/AD5254. TERMINAL VOLTAGE OPERATION RANGE AD5253/AD5254 The AD5253/AD5254 are designed with internal ESD diodes for protection; these diodes also set the boundaries for the VDDC3 C1 VDD terminal operating voltages. Positive signals present on 10F 0.1F Terminal A, Terminal B, or Terminal W that exceed V are DD C4 C2 conlneag mTaetpirvemde itbnhyaa ltn hA Ve, STfSoe arrwrmea iarnldsa-olb Bcia,l asoemrd pT deeidrom d(sieen.e aS lFi mWigiu ltarhrela y3t, 9 an)r.ee gI mnat poivrreae cstiigcnea, ls VSS 10F 0.1F VSS GND 03824-0-040 users should not operate V , V , and V to be higher than AB WA WB Figure 40. Power Supply-Bypassing Configuration the voltage across V to V , but V , V , and V have no DD SS AB WA WB polarity constraint. The ground pin of the AD5253/AD5254 is used primarily as a digital ground reference. To minimize the digital ground bounce, the AD5253/AD5254 ground terminal should be joined remotely to the common ground (see Figure 40). Rev. C | Page 23 of 32

AD5253/AD5254 Data Sheet DIGITAL POTENTIOMETER OPERATION PROGRAMMABLE RHEOSTAT OPERATION The structure of the RDAC is designed to emulate the If either the W-to-B or W-to-A terminal is used as a variable performance of a mechanical potentiometer. The RDAC resistor, the unused terminal can be opened or shorted with W; contains a string of resistor segments with an array of analog such operation is called rheostat mode (see Figure 42). The switches that act as the wiper connection to the resistor array. resistance tolerance can range ±20%. The number of points is the resolution of the device. For A A A example, the AD5253/AD5254 emulate 64/256 connection points with 64/256 equal resistance, R, allowing them to provide better than 1.5%/0.4% resolutiSon. B W B W B W 03824-0-042 Figure 41 provides an equivalent diagram of the connections Figure 42. Rheostat Mode Configuration between the three terminals that make up one channel of the RDAC. Switches SW and SW are always on, but only one of A B The nominal resistance of the AD5253/AD5254 has 64/256 switches SW(0) to SW(2N–1) can be on at a time (determined by contact points accessed by the wiper terminal, plus the B the setting decoded from the data bit). Because the switches are terminal contact. The 6-/8-bit data-word in the RDAC register nonideal, there is a 75 Ω wiper resistance, R . Wiper resistance W is decoded to select one of the 64/256 settings. The wiper’s first is a function of supply voltage and temperature: Lower supply connection starts at the B terminal for Data 0x00. This B termi- voltages and higher temperatures result in higher wiper nal connection has a wiper contact resistance, R , of 75 Ω, W resistances. Consideration of wiper resistance dynamics is regardless of the nominal resistance. The second connection important in applications in which accurate prediction of (the AD5253 10 kΩ part) is the first tap point where R = 231 Ω WB output resistance is required. (R = R /64 + R = 156 Ω + 75 Ω) for Data 0x01, and so on. WB AB W SWA Each LSB data value increase moves the wiper up the resistor AX ladder until the last tap point is reached at R = 9893 Ω. See WB Figure 41 for a simplified diagram of the equivalent RDAC circuit. SW (2N– 1) The general equation that determines the digitally programmed output resistance between W and B is RDAC WX REWGIPISETRER RS SW (2N– 2) AD5253: RWB(D) = (D/64) × RAB + 75 Ω (1) AND AD5254: RWB(D) = (D/256) × RAB + 75 Ω (2) DECODER where: D is the decimal equivalent of the data contained in the RS RDAC latch. SW(1) R is the nominal end-to-end resistance. AB RS SW(0) RS= RAB/2N DIGITAL COCILMRAICIRTUITTIETYRDY FOR SWB BX 03824-0-041 Figure 41. Equivalent RDAC Structure Rev. C | Page 24 of 32

Data Sheet AD5253/AD5254 PROGRAMMABLE POTENTIOMETER OPERATION 100 RWA RWB If all three terminals are used, the operation is called potenti- ometer mode (see Figure 44); the most common configuration 75 is the voltage divider operation. (%)B VI A RA 50 25 B W VC 03824-0-044 Figure 44. Potentiometer Mode Configuration If the wiper resistance is ignored, the transfer function is simply 00 10 D (Code i3n2 Decimal) 48 63 03824-0-043 AD5253: VW =6D4×VAB +VB (5) Figure 43. AD5253 R (D) and R (D) vs. Decimal Code WA WB D AD5254: V = ×V +V (6) Since the digital potentiometer is not ideal, a 75 Ω finite wiper W 256 AB B resistance is present that can easily be seen when the device is A more accurate calculation that includes the wiper resistance programmed at zero scale. Because of the fine geometric and effect is interconnects employed by the device, care should be taken to limit the current conduction between W and B to no more than D R +R ±5 mA continuous for a total resistance of 1 kΩ or a pulse of V (D)= 2N AB W V (7) ±20 mA to avoid degradation or possible destruction of the W R +2R A AB W device. The maximum dc current for AD5253 and AD5254 are shown in Figure 21 and Figure 22, respectively. where 2N is the number of steps. Similar to the mechanical potentiometer, the resistance of the Unlike in rheostat mode operation, where the tolerance is high, RDAC between Wiper W and Terminal A also produces a potentiometer mode operation yields an almost ratiometric digitally controlled complementary resistance, R . When these function of D/2N with a relatively small error contributed by the WA terminals are used, the B terminal can be opened. The R R terms. Therefore, the tolerance effect is almost cancelled. WA W starts at a maximum value and decreases as the data loaded into Similarly, the ratiometric adjustment also reduces the the latch increases in value (see Figure 43. The general equation temperature coefficient effect to 50 ppm/°C, except at low value for this operation is codes where R dominates. W AD5253: RWA(D) = [(64 – D)/64] × RAB + 75 Ω (3) Potentiometer mode operations include other applications such AD5254: RWA(D) = [(256 – D)/256] × RAB + 75 Ω (4) as op amp input, feedback-resistor networks, and other voltage- scaling applications. The A, W, and B terminals can, in fact, be The typical distribution of RAB from channel-to-channel input or output terminals, provided that |VA|, |VW|, and |VB| do matches is about ±0.15% within a given device. On the other not exceed V to V . DD SS hand, device-to-device matching is process-lot dependent with a ±20% tolerance. Rev. C | Page 25 of 32

AD5253/AD5254 Data Sheet APPLICATIONS INFORMATION RGB LED BACKLIGHT CONTROLLER The ADP1610 (U2 in Figure 45) is an adjustable boost regulator FOR LCD PANELS with its output adjusted by the AD5254’s RDAC3. Such an output should be set high enough for proper operation but low Because high power (>1 W) RGB LEDs offer superior color enough to conserve power. The ADP1610’s 1.2 V band gap quality compared with cold cathode florescent lamps (CCFLs) reference is buffered to provide the reference level for the as backlighting sources, it is likely that high-end LCD panels voltage dividers set by the AD5254’s RDAC0 to RDAC2 and will employ RGB LEDs as backlight in the near future. Unlike Resistor R2 to Resistor R4. For example, by adjusting the conventional LEDs, high power LEDs have a forward voltage of AD5254’s RDAC0, the desirable voltage appears across the 2 V to 4 V and consume more than 350 mA at maximum sense resistors, R . If U2’s output is set properly, op amp U3A brightness. The LED brightness is a linear function of the R and power MOSFET N1 do whatever is necessary to regulate conduction current, but not of the forward voltage. To increase the current of the loop. As a result, the current through the the brightness of a given color, multiple LEDs can be connected sense resistor and the red LEDs is in series, rather than in parallel, to achieve uniform brightness. For example, three red LEDs configured in series require an V I = RR (8) average of 6 V to 12 V headroom, but the circuit operation R R R requires current control. As a result, Figure 45 shows the implementation of one high power RGB LED controller using a R8 is needed to prevent oscillation. AD5254, a boost regulator, an op amp, and power MOSFETs. In addition to the 256 levels of adjustable current/brightness, users can also apply a PWM signal at U3’s SD pin to achieve finer brightness resolution or better power efficiency. Rev. C | Page 26 of 32

Data Sheet AD5253/AD5254 +5V C10 10F U1 R1 U2 VDD R5 IN L1 10F C1 R6 R7 A3 10k 10k ADP161S0W D1 VOUT 0.1F 22k 22k RD10AkC3 B3 FSBD C3 10F DB1 DG1 DR1 U3D SSCDLA CSDLKI RC 100k CSOSMPRTGND DB2 DG2 DR2 AD8594 VREF = 2.5V AD5254 CC CSS10F +5VC11 DB3 DG3 DR3 R4 R3 R2 390F VB 250k 250k250k A2 8 0.1F IB RDAC2 W2 U3C N3 V+ R10 10k B2 AD8594 IG V– 4.7 IRFL3103 4 VRB VG A1 U3B RB 0.1 RDAC1 W1 N2 R9 10k B1 AD8594 4.7 IRFL3103 IR VRG A0 U3A RG 0.1 VR RDAC0 W0 N1 LD11 -- SMLBFR60052250-1L0T01M1R0 10k B0 AD8594 4R.78 IRFL3103 VSSGNDAD0AD1 VRR PWM SD RR 0.1 03824-0-045 Figure 45. Digital Potentiometer-Based RGB LED Controller Rev. C | Page 27 of 32

AD5253/AD5254 Data Sheet OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 46. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. C | Page 28 of 32

Data Sheet AD5253/AD5254 ORDERING GUIDE Package Ordering Model1, 2, 3 Step R (kΩ) Temperature Range Package Description Option Quantity AB AD5253BRU1 64 1 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRU1-RL7 64 1 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRUZ1 64 1 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRUZ1-RL7 64 1 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRU10 64 10 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRU10-RL7 64 10 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRUZ10 64 10 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRUZ10-RL7 64 10 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRU50 64 50 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRU50-RL7 64 50 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRUZ50 64 50 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRUZ50-RL7 64 50 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRU100 64 100 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRU100-RL7 64 100 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5253BRUZ100 64 100 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5253BRUZ100-RL7 64 100 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRU1 256 1 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRU1-RL7 256 1 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRUZ1 256 1 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRUZ1-RL7 256 1 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRU10 256 10 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRU10-RL7 256 10 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRUZ10 256 10 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRUZ10-RL7 256 10 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRU50 256 50 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRU50-RL7 256 50 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRUZ50 256 50 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRUZ50-RL7 256 50 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRU100 256 100 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRU100-RL7 256 100 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 AD5254BRUZ100 256 100 −40°C to +105°C 20-Lead TSSOP RU-20 75 AD5254BRUZ100-RL7 256 100 −40°C to +105°C 20-Lead TSSOP RU-20 1,000 EVAL-AD5254SDZ 256 Evaluation Board 1 1 In the package marking, Line 1 shows the part number. Line 2 shows the branding information, such that B1 = 1 kΩ, B10 = 10 kΩ, and so on. There is also a “#” marking for the Pb-free part. Line 3 shows the date code in YYWW. 2 Z = RoHS Compliant Part. 3 The evaluation board is shipped with the 10 kΩ R resistor option; however, the board is compatible with all available resistor value options. AB Rev. C | Page 29 of 32

AD5253/AD5254 Data Sheet NOTES Rev. C | Page 30 of 32

Data Sheet AD5253/AD5254 NOTES Rev. C | Page 31 of 32

AD5253/AD5254 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03824-0-9/12(C) Rev. C | Page 32 of 32