I2C-Compatible, 256-Position Digital Potentiometers Data Sheet AD5241/AD5242 FEATURES FUNCTIONAL BLOCK DIAGRAM 256 positions A1 W1 B1 O1 O2 10 kΩ, 100 kΩ, 1 MΩ Low temperature coefficient: 30 ppm/°C SHDN Internal power on midscale preset Single-supply 2.7 V to 5.5 V or dual-supply ±2.7 V for ac or VDD RDAC REGISTER 2 REGISTER 1 bipolar operation VSS I2C-compatible interface with readback capability Extra programmable logic outputs ADDR DECODE AD5241 8 Self-contained shutdown feature Extended temperature range: −40°C to +105°C SDA PWR-ON SCL SERIAL INPUT REGISTER RESET APPLICATIONS Multimedia, video, and audio GND AD0 AD1 00926-001 Communications Figure 1. AD5241 Functional Block Diagram Mechanical potentiometer replacement Instrumentation: gain, offset adjustment A1 W1 B1 A2 W2 B2 O1 O2 Programmable voltage-to-current conversion Line impedance matching SHDN REGISTER VDD RDAC RDAC REGISTER 1 REGISTER 2 VSS ADDR DECODE AD5242 8 1 SSDCAL SERIAL INPUT REGISTER PRWERS-EOTN GND AD0 AD1 00926-002 Figure 2. AD5242 Functional Block Diagram GENERAL DESCRIPTION The AD5241/AD5242 provide a single-/dual-channel, 256- Wiper position programming defaults to midscale at system position, digitally controlled variable resistor (VR) device. These power on. When powered, the VR wiper position is programmed devices perform the same electronic adjustment function as a by an I2C-compatible, 2-wire serial data interface. Both parts potentiometer, trimmer, or variable resistor. Each VR offers a have two extra programmable logic outputs available that completely programmable value of resistance between the A enable users to drive digital loads, logic gates, LED drivers, and terminal and the wiper, or the B terminal and the wiper. For the analog switches in their system. AD5242, the fixed A-to-B terminal resistance of 10 kΩ, 100 kΩ, The AD5241/AD5242 are available in surface-mount, 14-lead or 1 MΩ has a 1% channel-to-channel matching tolerance. The SOIC and 16-lead SOIC packages and, for ultracompact solutions, nominal temperature coefficient of both parts is 30 ppm/°C. 14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended temperature range of −40°C to +105°C. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2001–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5241/AD5242 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Test Circuits ..................................................................................... 11 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 12 Functional Block Diagram .............................................................. 1 Programming the Variable Resistor ......................................... 12 General Description ......................................................................... 1 Programming the Potentiometer Divider ............................... 13 Revision History ............................................................................... 2 Digital Interface .......................................................................... 13 Specifications ..................................................................................... 3 Readback RDAC Value .............................................................. 14 10 kΩ, 100 kΩ, 1 MΩ Version .................................................... 3 Multiple Devices on One Bus ................................................... 14 Timing Diagrams .......................................................................... 5 Level-Shift for Bidirectional Interface ..................................... 14 Absolute Maximum Ratings ............................................................ 6 Additional Programmable Logic Output ................................ 15 ESD Caution .................................................................................. 6 Shutdown Function .................................................................... 15 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 16 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 18 REVISION HISTORY 6/15—Rev. C to Rev. D 2/02—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 18 Edits to Features................................................................................. 1 Edits to Functional Block Diagrams ............................................... 1 12/09—Rev. B to Rev. C Edits to Absolute Maximum Ratings .............................................. 4 Changes to Features Section............................................................ 1 Changes to Ordering Guide ............................................................. 4 Changes to 10 kΩ, 100 kΩ, 1 MΩ Version Section ...................... 3 Edits to Pin Function Descriptions ................................................. 5 Changes to Table 3 ............................................................................ 6 Edits to Figures 1, 2, 3 ....................................................................... 6 Deleted Digital Potentiometer Selection Guide Section ........... 14 Added Readback RDAC Value Section, Additional Changed Self-Contained Shutdown Function Section to Programmable Logic Output Section, and Figure 7; Shutdown Function Section .......................................................... 15 Renumbered Sequentially ............................................................. 11 Changes to Shutdown Function Section ..................................... 15 Changes to Digital Potentiometer Selection Guide ................... 14 Changes to Ordering Guide .......................................................... 18 8/02—Rev. A to Rev. B Additions to Features ....................................................................... 1 Changes to General Description .................................................... 1 Changes to Specifications ................................................................ 2 Changes to Absolute Maximum Ratings ....................................... 4 Additions to Ordering Guide .......................................................... 4 Changes to TPC 8 and TPC 9 ......................................................... 8 Changes to Readback RDAC Value Section ................................ 11 Changes to Additional Programmable Logic Output Section .. 11 Added Self-Contained Shutdown Section ................................... 12 Added Figure 8 ................................................................................ 12 Changes to Digital Potentiometer Selection Guide ................... 14 Rev. D | Page 2 of 18

Data Sheet AD5241/AD5242 SPECIFICATIONS 10 kΩ, 100 kΩ, 1 MΩ VERSION V = 2.7 V to 5.5 V, V = V , V = 0 V, −40°C < T < +105°C, unless otherwise noted. DD A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS, RHEOSTAT MODE (SPECIFICATIONS APPLY TO ALL VRs) Resolution N 8 Bits Resistor Differential Nonlinearity2 R-DNL R , V = no connect −1 ±0.4 +1 LSB WB A Resistor Integral Nonlinearity2 R-INL R , V = no connect −2 ±0.5 +2 LSB WB A Nominal Resistor Tolerance ΔR /R T = 25°C, R = 10 kΩ −30 +30 % AB AB A AB T = 25°C, −30 +50 % A R = 100 kΩ/1 MΩ AB Resistance Temperature Coefficient (ΔR /R )/ V = V , wiper = 30 ppm/°C AB AB AB DD ΔT × 106 no connect Wiper Resistance R I = V /R 60 120 Ω W W DD DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (SPECIFICATIONS APPLY TO ALL VRs) Resolution N 8 Bits Differential Nonlinearity3 DNL −1 ±0.4 +1 LSB Integral Nonlinearity3 INL −2 ±0.5 +2 LSB Voltage Divider Temperature Coefficient (ΔV /V )/∆T × 106 Code = 0x80 5 ppm/°C W W Full-Scale Error V Code = 0xFF −1 −0.5 0 LSB WFSE Zero-Scale Error V Code = 0x00 0 0.5 1 LSB WZSE RESISTOR TERMINALS Voltage Range4 V , V , V V V V A B W SS DD Capacitance (A, B)5 C , C f = 1 MHz, measured 45 pF A B to GND, code = 0x80 Capacitance (W)5 C f = 1 MHz, measured 60 pF W to GND, code = 0x80 Common-Mode Leakage I V = V = V 1 nA CM A B W DIGITAL INPUTS Input Logic High (SDA and SCL) V 0.7 × V V + 0.5 V V IH DD DD Input Logic Low (SDA and SCL) V −0.5 +0.3 × V V IL DD Input Logic High (AD0 and AD1) V V = 5 V 2.4 V V IH DD DD Input Logic Low (AD0 and AD1) V V = 5 V 0 0.8 V IL DD Input Logic High V V = 3 V 2.1 V V IH DD DD Input Logic Low V V = 3 V 0 0.6 V IL DD Input Current I V = 5 V or V = GND 1 µA IL IH IL Input Capacitance5 C 3 pF IL DIGITAL OUTPUT V I = 3 mA 0.4 V OL OL Output Logic Low (SDA) V I = 6 mA 0.6 V OL OL Output Logic Low (O and O) V I = 1.6 mA 0.4 V 1 2 OL SINK Output Logic High (O and O) V I = 40 µA 4 V 1 2 OH SOURCE Three-State Leakage Current (SDA) I V = 5 V or V = GND ±1 µA OZ IH IL Output Capacitance5 C 3 8 pF OZ POWER SUPPLIES Power Single-Supply Range V V = 0 V 2.7 5.5 V DD RANGE SS Power Dual-Supply Range V /V ±2.3 ±2.7 V DD SS RANGE Positive Supply Current I V = 5 V or V = GND 0.1 50 µA DD IH IL Negative Supply Current I V = −2.5 V, V = +2.5 V +0.1 −50 µA SS SS DD Power Dissipation6 P V = 5 V or V = GND, 0.5 250 DISS IH IL µW V = 5 V DD Power Supply Sensitivity PSS −0.01 +0.002 +0.01 %/% Rev. D | Page 3 of 18

AD5241/AD5242 Data Sheet Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS5, 7, 8 −3 dB Bandwidth BW_10 kΩ R = 10 kΩ, code = 0x80 650 kHz AB BW_100 kΩ R = 100 kΩ, code = 0x80 69 kHz AB BW_1 MΩ R = 1 MΩ, code = 0x80 6 kHz AB Total Harmonic Distortion THD V = 1 V rms + 2 V dc, 0.005 % W A V = 2 V dc, f = 1 kHz B V Settling Time t V = V , V = 0 V, ± 1 LSB 2 µs W S A DD B error band, R = 10 kΩ AB Resistor Noise Voltage e R = 5 kΩ, f = 1 kHz 14 nV√Hz N_WB WB INTERFACE TIMING CHARACTERISTICS (APPLIES TO ALL PARTS5, 9) SCL Clock Frequency f 0 400 kHz SCL Bus Free Time Between Stop and Start, t t 1.3 µs BUF 1 Hold Time (Repeated Start), t t After this period, the first 600 ns HD;STA 2 clock pulse is generated Low Period of SCL Clock, t t 1.3 µs LOW 3 High Period of SCL Clock, t t 0.6 50 µs HIGH 4 Setup Time for Repeated Start Condition, t t 600 ns SU; STA 5 Data Hold Time, t t 900 ns HD; DAT 6 Data Setup Time, t t 100 ns SU; DAT 7 Rise Time of Both SDA and SCL Signals, t t 300 ns R 8 Fall Time of Both SDA and SCL Signals, t t 300 ns F 9 Setup Time for Stop Condition, t t SU; STO 10 1 Typicals represent average readings at 25°C, VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Test Circuits. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 37. 4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 5 Guaranteed by design, not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use VDD = 5 V. 9 See timing diagram in Figure 3 for location of measured values. Rev. D | Page 4 of 18

Data Sheet AD5241/AD5242 TIMING DIAGRAMS t8 SDA t1 t8 t9 t2 SCL P S t2 t3 t6 t4 t7 S t5 P t10 00926-005 Figure 3. Detail Timing Diagram Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format. Table 2. S 0 1 0 1 1 AD1 AD0 R/W A A/B RS SD O1 O2 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Instruction Byte Data Byte where: S = start condition P = stop condition A = acknowledge X = don’t care AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at Pin AD1 and Pin AD0. R/W = Read enable at high and output to SDA. Write enable at low. A/B = RDAC subaddress select; 0 for RDAC1 and 1 for RDAC2. RS = Midscale reset, active high. SD = Shutdown in active high. Same as SHDN except inverse logic. O, O = Output logic pin latched values 1 2 D7, D6, D5, D4, D3, D2, D1, D0 = data bits. 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W A/B RS SD O1 O2 X X X D7 D6 D5 D4 D3 D2 D1 D0 ACK BY ACK BY ACK BY STMAARSTT EBRY SLAVE FARDADMREE S1S BYTE AD5241 INSTRFURCATMIOEN 2 BYTE AD5241 DFARTAAM BEY T3E AD524SM1TAOSPT EBRY 00926-006 Figure 4. Writing to the RDAC Serial Register 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 ACK BY NO ACK BY AD5241 MASTER STMAARSTT EBRY SLAVE FARDADMREE S1S BYTE DATAR DBAYTCE R FERGOISMFTR EPARRM EINEV I2WOURSITLEY M SOEDLEECTED SMTAOSPT EBRY 00926-007 Figure 5. Reading Data from a Previously Selected RDAC Register in Write Mode Rev. D | Page 5 of 18

AD5241/AD5242 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 3. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond V to GND 0 V to −7 V SS the maximum operating conditions for extended periods may V to V 7 V DD SS affect product reliability. V , V , V to GND V to V A B W SS DD I , I , I A B W R = 10 kΩ in TSSOP-14 5.0 mA1 ESD CAUTION AB R = 100 kΩ in TSSOP-14 1.5 mA1 AB R = 1 MΩ in TSSOP-14 0.5 mA1 AB Digital Input Voltage to GND 0 V to V + 0.3 V DD Operating Temperature Range −40°C to +105°C Thermal Resistance θ JA 14-Lead SOIC 158°C/W 16-Lead SOIC 73°C/W 14-Lead TSSOP 206°C/W 16-Lead TSSOP 180°C/W Maximum Junction Temperature (T max) 150°C J Package Power Dissipation P = (T max − T )/θ D J A JA Storage Temperature Range −65°C to +150°C Lead Temperature Vapor Phase, 60 sec 215°C Infrared, 15 sec 220°C 1 Maximum current increases at lower resistance and different packages. Rev. D | Page 6 of 18

Data Sheet AD5241/AD5242 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS A1 1 14 O1 O1 1 16 A2 W1 2 13 NC A1 2 15 W2 B1 3 12 O2 W1 3 14 B2 AD5241 VDD 4 TOP VIEW 11 VSS B1 4 AD5242 13 O2 (Not to Scale) TOP VIEW SHDN 5 10 DGND VDD 5 (Not to Scale)12 VSS SCL 6 9 AD1 SHDN 6 11 DGND SDA N7C = NO CONNEC8T AD0 00926-003 SSDCAL 78 190 AADD10 00926-004 Figure 6. AD5241 Pin Configuration Figure 7. AD5242 Pin Configuration Table 4. AD5241 Pin Function Descriptions Table 5. AD5242 Pin Function Descriptions Pin No. Mnemonic Description Pin No. Mnemonic Description 1 A Resistor Terminal A. 1 O Logic Output Terminal O. 1 1 1 1 2 W Wiper Terminal W. 2 A Resistor Terminal A. 1 1 1 1 3 B Resistor Terminal B. 3 W Wiper Terminal W. 1 1 1 1 4 V Positive Power Supply, Specified for 4 B Resistor Terminal B. DD 1 1 Operation from 2.2 V to 5.5 V. 5 V Positive Power Supply, Specified for DD 5 SHDN Active low, asynchronous connection of Operation from 2.2 V to 5.5 V. Wiper W to Terminal B, and open circuit 6 SHDN Active Low, Asynchronous Connection of Terminal A. RDAC register contents of Wiper W to Terminal B, and Open unchanged. SHDN should tie to VDD Circuit of Terminal A. RDAC register if not used. contents unchanged. SHDN should 6 SCL Serial Clock Input. tie to VDD, if not used. 7 SDA Serial Data Input/Output. 7 SCL Serial Clock Input. 8 AD0 Programmable Address Bit for Multiple 8 SDA Serial Data Input/Output. Package Decoding. Bit AD0 and Bit AD1 9 AD0 Programmable Address Bit for Multiple provide four possible addresses. Package Decoding. Bit AD0 and Bit AD1 9 AD1 Programmable Address Bit for Multiple provide four possible addresses. Package Decoding. Bit AD0 and Bit AD1 10 AD1 Programmable Address Bit for Multiple provide four possible addresses. Package Decoding. Bit AD0 and Bit AD1 10 DGND Common Ground. provide four possible addresses. 11 V Negative Power Supply, Specified for 11 DGND Common Ground. SS Operation from 0 V to −2.7 V. 12 V Negative Power Supply, Specified for SS 12 O Logic Output Terminal O. Operation from 0 V to −2.7 V. 2 2 13 NC No Connect. 13 O2 Logic Output Terminal O2. 14 O1 Logic Output Terminal O1. 14 B2 Resistor Terminal B2. 15 W Wiper Terminal W. 2 2 16 A Resistor Terminal A. 2 2 Rev. D | Page 7 of 18

AD5241/AD5242 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.50 VVVDDDDDD === ++±225...775VVV VVVDDDDDD === ±++225...775VVV ALINTEREFFDIB)SLY (T 0.5 VDD/VSS = +2.7V/0V EDOMR ET)BLS(Y ITREAN 0.25 VDD/VSS = +2.7V DEOMRIAEN 0 EMIOTINLON 0 ATTSOERHLINNO–0.5 VDD/VSS = +5.5V/0V, ±2.7V ENTOPL ARGTENI –0.25 VDD/VSS = +2.7V/0V, +5.5V/0V –1.00 32 64 9C6ODE (1D2e8cima1l)60 192 224 256 00926-008 –0.500 32 64 9C6ODE (1D2e8cima1l)60 192 224 256 00926-011 Figure 8. RDNL vs. Code Figure 11. INL vs. Code 1.0 10k VDD = +2.7V VDD = 2.7V VDD = +5.5V TA = 25°C VDD/VSS = +2.7V/0V VDD = ±2.7V 1MΩ L ARGEB)S 0.5 )kΩ(E 1k TL C NIE DOM(Y TRIAE 0 NATSSIE 100 100kΩ T N R AIL L TN A SOEON VDD/VSS = +5.5V/0V, ±2.7V INM 10kΩ H –0.5 O 10 R N –1.0 1 0 32 64 9C6ODE (1D2e8cima1l)60 192 224 256 00926-009 –40 –20 0 TEMPE2R0ATURE (4°C0) 60 80 00926-012 Figure 9. RINL vs. Code Figure 12. Nominal Resistance vs. Temperature 0.25 10k VDD = +2.7V VDD = +5.5V B) VDD = ±2.7V S ELY ( 0.13 )A 1k VDD = 5V DOMR EETMTRIAENLINO 0 VDD/VSS = +2.7V/0V, +5.5V/0V, ±2.7V (NTERRUCµ 100 VDD = 3V OTINETPO NLIANTEREF –0.13 YPLPUSI DD 10 F ID VDD = 2.5V –0.250 32 64 9C6ODE 1(D2e8cimal1)60 192 224 256 00926-010 10 1 INPUT L2OGIC VOLTA3GE (V) 4 5 00926-013 Figure 10. DNL vs. Code Figure 13. Supply Current vs. Input Logic Voltage Rev. D | Page 8 of 18

Data Sheet AD5241/AD5242 0.1 100 RAB= 10kΩ TA = 25°C VDD = 5.5V 90 80 A)µ VDD/VSS = +2.7V/0V ( TENRRUCN W 0.01 Ω)(E CANTSSI 765000 ODT ERR 40 VDD/VSS = ±2.7V/0V U E H P S IW 30 VDD/VSS = +5.5V/0V 20 0.001 10 –40 –20 0 TEMPE2R0ATURE(4°0C) 60 80 00926-014 –3 –2 –1 0COMM1ON-MO2DE (V)3 4 5 6 00926-017 Figure 14. Shutdown Current vs. Temperature Figure 17. Incremental Wiper Contact vs. VDD/VSS 70 300 VDD/VSS = 2.7V/0V A: VDD/VSS = 5.5V/0V m/°C) 60 10MΩ VERSION TA = 25°C 250 B : VCDODD/VES =S 0=x 3F.F3V/0V D CO (pp 5400 10kΩ VERSION )µA(T C : CVCODODDD/EVE S ==S 0 0=xx F2FF.F5V/0V A MP 100kΩ VERSION EN200 D: VDD/VSS = 5.5V/0V TE 30 RR CODE = 0x55 ODE 20 UCY 150 E : CVODDD/EV S=S 0 =x 535.3V/0V ER M 10 LPPU F : CVODDD/EVS =S 0=x 525.5V/0V TENTIOMET –100 IS DD10500 CEBF O –20 P –300 32 64 9C6ODE (1D2e8cima1l)60 192 224 256 00926-015 010 FREQUE1N0C0Y (kHz) 1k 00926-018 Figure 15. ΔVWB/ΔT Potentiometer Mode Temperature Coefficient Figure 18. Supply Current vs. Frequency 120 6 VDD/VSS = 2.7V/0V 0xFF 100 TA = 25°C 0 C) 100kΩ VERSION 0x80 °m/ 80 –6 p 0x40 pO (C 60 –12 0x20 PM 40 )B–18 E d 0x10 TE D 20 (N AI–24 0x08 MO 0 G–30 T 0x04 TASOE––2400 10kΩ VERSION ––4326 00xx0021 H R 10MΩ VERSION –60 –48 –800 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 00926-016 –54100 1k FREQUE10NkCY (Hz) 100k 1M 00926-019 Figure 16. ΔRWB/ΔT Rheostat Mode Temperature Coefficient Figure 19. AD5242 10 k Ω Gain vs. Frequency vs. Code Rev. D | Page 9 of 18

AD5241/AD5242 Data Sheet 6 6 0xFF 0xFF 0 0 0x80 0x80 –6 –6 0x40 0x40 –12 –12 0x20 0x20 B)–18 )B–18 dN (–24 0x10 (dN –24 0x10 AIG 0x08 AIG 0x08 –30 –30 0x04 0x04 –36 –36 0x02 0x02 –42 –42 0x01 0x01 –48 –48 –54100 1kFREQUENCY (Hz)10k 100k 00926-020 –54100 1kFREQUENCY (Hz)10k 100k 00926-021 Figure 20. AD5242 100 kΩ Gain vs. Frequency vs. Code Figure 21. AD5242 1 MΩ Gain vs. Frequency vs. Code Rev. D | Page 10 of 18

Data Sheet AD5241/AD5242 TEST CIRCUITS Figure 22 to Figure 30 define the test conditions used in the product specifications table. 5V OP279 VOUT DUT V1 +L S= BV D=D V+/2N VIN W A V+ W OFFSET GND A DUT B B VMS 00926-029 OBIFAFSSET 00926-034 Figure 22. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 27. Noninverting Gain NO CONNECT A DUT +15V A IW W W VIN DUT OP42 VOUT B OFFSET VMS 00926-030 GND 2.5V B –15V 00926-035 Figure 23. Resistor Position Nonlinearity Error Figure 28. Gain vs. Frequency (Rheostat Operation; R-INL, R-DNL) 0.1V DUT RSW = ISW CODE = 0x00 DUT W VMS2 A W VW IW = VDD/RNOMINAL B ISW 0.1V B VMS1 RW = [VMS1 – VMS2]/IW 00926-031 VSS TO VDD 00926-036 Figure 24. Wiper Resistance Figure 29. Incremental On Resistance VA NC V+ = VDD ±10% ∆VMS V+ VDD AB W VMPPSSSRSR (% (d/%B)) == 20∆∆ VVLOMDDSG%% ∆VDD 00926-032 DVVDUSDST GND NCABW ICM VCM 00926-037 Figure 25. Power Supply Sensitivity (PSS, PSRR) Figure 30. Common-Mode Leakage Current A DUT B 5V W OP279 VOUT OFFSET GND OBIFAFSSET 00926-033 Figure 26. Inverting Gain Rev. D | Page 11 of 18

AD5241/AD5242 Data Sheet THEORY OF OPERATION The AD5241/AD5242 provide a single-/dual-channel, 256- Figure 31 shows a simplified diagram of the equivalent RDAC position digitally controlled variable resistor (VR) device. The circuit where the last resistor string is not accessed; therefore, terms VR, RDAC, and programmable resistor are commonly there is 1 LSB less of the nominal resistance at full scale in used interchangeably to refer to digital potentiometer. addition to the wiper resistance. To program the VR settings, refer to the Digital Interface section. The general equation determining the digitally programmed Both parts have an internal power-on preset that places the wiper resistance between W and B is in midscale during power-on that simplifies the fault condition D recovery at power-up. In addition, the shutdown pin (SHDN) RWB(D) = × RAB + RW (1) 256 of AD5241/AD5242 places the RDAC in an almost zero power where: consumption state where Terminal A is open circuited and Wiper D is the decimal equivalent of the binary code between 0 and 255, W is connected to Terminal B, resulting in only leakage current which is loaded in the 8-bit RDAC register. being consumed in the VR structure. During shutdown, the VR R is the nominal end-to-end resistance. latch contents are maintained when the RDAC is inactive. When AB R is the wiper resistance contributed by the on resistance of the part returns from shutdown, the stored VR setting is applied W the internal switch. to the RDAC. Again, if R = 10 kΩ, Terminal A can be either open circuit or A AB tied to W. Table 6 shows the R resistance based on the code SHDN WB set in the RDAC latch. SWSHDN D7 R SW2N–1 D6 Table 6. R (D) at Selected Codes for R = 10 kΩ D5 WB AB DD43 R SW2N–2 D (DEC) RWB (Ω) Output State D2 D1 255 10021 Full-scale (RWB – 1 LSB + RW) D0 128 5060 Midscale W 1 99 1 LSB R SW1 0 60 Zero-scale (wiper contact resistance) RDAC LATCH R RAB/2N DECAONDDER R SW0 Note that in the zero-scale condition, a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow B DOIMGIITTTAELD C FIROCRU CITLRAYRITY 00926-022 between W and B in this state to a maximum current of no more than 20 mA. Otherwise, degradation or possible destruction of Figure 31. Equivalent RDAC Circuit the internal switch contact can occur. PROGRAMMING THE VARIABLE RESISTOR Similar to the mechanical potentiometer, the resistance of the Rheostat Operation RDAC between Wiper W and Terminal A also produces a The nominal resistance of the RDAC between Terminal A and digitally controlled resistance, RWA. When these terminals are Terminal B is available in 10 kΩ, 100 kΩ, and 1 MΩ. The final two used, Terminal B can be opened or tied to the wiper terminal. or three digits of the part number determine the nominal resistance The minimum RWA resistance is for Data 0xFF and increases as value, for example, 10 kΩ = 10, 100 kΩ = 100, and 1 MΩ = 1 M. the data loaded in the latch decreases in value. The general The nominal resistance (R ) of the VR has 256 contact points equation for this operation is AB accessed by the wiper terminal, plus the B terminal contact. The 256D 8-bit data in the RDAC latch is decoded to select one of the 256 RWA(D) = × RAB + RW (2) 256 possible settings. Assume a 10 kΩ part is used; the first connection For R = 10 kΩ, Terminal B can be either open circuit or tied of the wiper starts at the B terminal for Data 0x00. Because there is AB to W. Table 7 shows the R resistance based on the code set in a 60 Ω wiper contact resistance, such connection yields a minimum WA the RDAC latch. of 60 Ω resistance between Terminal W and Terminal B. The second connection is the first tap point that corresponds to 99 Ω Table 7. R (D) at Selected Codes for R = 10 kΩ WA AB (R = R /256 + R = 39 + 60) for Data 0x01. The third connection WB AB W D (DEC) R (Ω) Output State WA is the next tap point representing 138 Ω (39 × 2 + 60) for Data 0x02, 255 99 Full-scale and so on. Each LSB data value increase moves the wiper up the 128 5060 Midscale resistor ladder until the last tap point is reached at 10,021 Ω 1 10021 1 LSB [R – 1 LSB + R ]. AB W 0 10060 Zero-scale Rev. D | Page 12 of 18

Data Sheet AD5241/AD5242 The typical distribution of the nominal resistance R from DIGITAL INTERFACE AB channel to channel matches within ±1% for AD5242. Device- 2-Wire Serial Bus to-device matching is process lot dependent, and it is possible to The AD5241/AD5242 are controlled via an I2C-compatible have ±30% variation. Because the resistance element is processed in serial bus. The RDACs are connected to this bus as slave devices. thin film technology, the change in R with temperature has no AB more than a 30 ppm/°C temperature coefficient. Referring to Figure 3 and Figure 4, the first byte of AD5241/ AD5242 is a slave address byte. It has a 7-bit slave address and PROGRAMMING THE POTENTIOMETER DIVIDER an R/W bit. The five MSBs are 01011 and the following two bits Voltage Output Operation are determined by the state of the AD0 and AD1 pins of the The digital potentiometer easily generates output voltages at device. AD0 and AD1 allow users to use up to four of these wiper-to-B and wiper-to-A to be proportional to the input devices on one bus. voltage at A-to-B. Unlike the polarity of V /V , which must DD SS The 2-wire, I2C serial bus protocol operates as follows: be positive, voltage across terminal A to terminal B, terminal W 1. The master initiates a data transfer by establishing a start to terminal A, and terminal W to terminal B can be at either condition, which is when a high-to-low transition on the SDA polarity provided that V is powered by a negative supply. SS line occurs while SCL is high (see Figure 4). The following If ignoring the effect of the wiper resistance for approximation, byte is the Frame 1, slave address byte, which consists of the connecting Terminal A to 5 V and Terminal B to ground produces 7-bit slave address followed by an R/W bit (this bit determines an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less whether data is read from or written to the slave device). than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256 positions of the potentiometer The slave whose address corresponds to the transmitted divider. Because AD5241/AD5242 can be supplied by dual address responds by pulling the SDA line low during the supplies, the general equation defining the output voltage at V W ninth clock pulse (this is the acknowledge bit). At this stage, with respect to ground for any valid input voltage applied to all other devices on the bus remain idle while the selected Terminal A and Terminal B is device waits for data to be written to or read from its serial V (D)= D V +256−DV (3) register. If the R/W bit is high, the master reads from the W 256 A 256 B slave device. If the R/W bit is low, the master writes to the which can be simplified to slave device. 2. A write operation contains an extra instruction byte more D V (D)= V +V (4) than the read operation. The Frame 2 instruction byte in W 256 AB B write mode follows the slave address byte. The MSB of the where D is the decimal equivalent of the binary code between 0 instruction byte labeled A/B is the RDAC subaddress select. A to 255 that is loaded in the 8-bit RDAC register. low selects RDAC1 and a high selects RDAC2 for the dual- For a more accurate calculation, including the effects of wiper channel AD5242. Set A/B to low for the AD5241. The resistance, V can be found as second MSB, RS, is the midscale reset. A logic high of this W bit moves the wiper of a selected RDAC to the center tap R (D) R (D) V (D)= WB V + WA V (5) where R = R . The third MSB, SD, is a shutdown bit. A W R A R B WA WB AB AB logic high on SD causes the RDAC to open circuit at where R (D) and R (D) can be obtained from Equation 1 and Terminal A while shorting the wiper to Terminal B. This WB WA Equation 2. operation yields almost a 0 Ω rheostat mode or 0 V in potentiometer mode. This SD bit serves the same function Operation of the digital potentiometer in divider mode results as the SHDN pin except that the SHDN pin reacts to active in a more accurate operation over temperature. Unlike rheostat low. The following two bits are O and O. They are extra mode, the output voltage is dependent on the ratio of the internal 2 1 programmable logic outputs that users can use to drive resistors, R and R , and not the absolute values; therefore, WA WB other digital loads, logic gates, LED drivers, analog switches, the temperature drift reduces to 5 ppm/°C. and the like. The three LSBs are don’t care (see Figure 4). 3. After acknowledging the instruction byte, the last byte in write mode is the, Frame 3 data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 4). Rev. D | Page 13 of 18

AD5241/AD5242 Data Sheet 4. Unlike the write mode, the data byte follows immediately MULTIPLE DEVICES ON ONE BUS after the acknowledgment of the slave address byte in Figure 33 shows four AD5242 devices on the same serial bus. Frame 2 read mode. Data is transmitted over the serial bus Each has a different slave address because the state of their AD0 in sequences of nine clock pulses (slightly different from and AD1 pins are different. This allows each RDAC within each the write mode, there are eight data bits followed by a no device to be written to or read from independently. The master acknowledge Logic 1 bit in read mode). Similarly, the device output bus line drivers are open-drain pull-downs in a transitions on the SDA line must occur during the low fully I2C-compatible interface. Note, a device is addressed properly period of SCL and remain stable during the high period of only if the bit information of AD0 and AD1 in the slave address SCL (see Figure 5). byte matches with the logic inputs at the AD0 and AD1 pins of 5. When all data bits have been read or written, a stop condition that particular device. is established by the master. A stop condition is defined as LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during While most old systems can operate at one voltage, a new the tenth clock pulse to establish a stop condition (see component may be optimized at another. When they operate Figure 4). In read mode, the master issues a no acknowledge the same signal at two different voltages, a proper method of for the ninth clock pulse (that is, the SDA line remains high). level-shifting is needed. For instance, a 3.3 V E2PROM can be The master then brings the SDA line low before the tenth used to interface with a 5 V digital potentiometer. A level-shift clock pulse, which goes high to establish a stop condition scheme is needed to enable a bidirectional communication so that (see Figure 5). the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 32 shows one of the techniques. A repeated write function gives the user flexibility to update the M1 and M2 can be N-channel FETs (2N7002) or low threshold RDAC output a number of times after addressing and instructing FDV301N if V falls below 2.5 V. the part only once. During the write cycle, each data byte updates DD the RDAC output. For example, after the RDAC has acknowledged VDD = 3.3V VDD = 5V its slave address and instruction bytes, the RDAC output is RP RP G RP RP S D updated. If another byte is written to the RDAC while it is still SDA1 SDA2 M1 G addressed to a specific slave device with the same instruction, S D this byte updates the output of the selected slave device. If SCL1 SCL2 M2 dcoifmfeprelentte liyn snteruwc stieoqnuse anrcee nweietdhe ad ,n tehwe swlarvitee amddordees sh, ains sttoru scttairotn a, E23P.R3VOM AD55V242 00926-024 and data bytes transferred again. Similarly, a repeated read Figure 32. Level-Shift for Different Voltage Devices Operation function of the RDAC is also allowed. READBACK RDAC VALUE Specific to the AD5242 dual-channel device, the channel of interest is the one that was previously selected in the write mode. In addition, to read both RDAC values consecutively, users have to perform two write-read cycles. For example, users may first specify the RDAC1 subaddress in write mode (it is not necessary to issue the data byte and stop condition), and then change to read mode to read the RDAC1 value. To continue reading the RDAC2 value, users have to switch back to write mode, specify the subaddress, and then switch once again to read mode to read the RDAC2 value. It is not necessary to issue the write mode data byte or the first stop condition for this operation. Users should refer to Figure 4 and Figure 5 for the programming format. 5V RP RP SDA MASTER SCL SDA SCL VDD SDA SCL VDD SDA SCL VDD SDA SCL AD1 AD1 AD1 AD1 AADD05242 AADD05242 AADD05242 AADD05242 00926-023 Figure 33. Multiple AD5242 Devices on One Bus Rev. D | Page 14 of 18

Data Sheet AD5241/AD5242 ADDITIONAL PROGRAMMABLE LOGIC OUTPUT SHUTDOWN FUNCTION The AD5241/AD5242 feature additional programmable logic Shutdown can be activated by strobing the SHDN pin or outputs, O1 and O2, that can be used to drive digital load, analog programming the SD bit in the write mode instruction byte (see switches, and logic gates. They can also be used as a self-contained Table 2). If the RDAC Register 1 or RDAC Register 2 (AD5242 shutdown preset to Logic 0 that is further explained in the only) is placed in shutdown mode by the software, SD bit, the Shutdown Function section. O1 and O2 default to Logic 0 during part returns the wiper to its prior position when a new command power-up. The logic states of O1 and O2 can be programmed in is received. Frame 2 under the write mode (see Figure 4). Figure 34 shows In addition, shutdown can be implemented with the device digital the output stage of O, which employs large P-channel and N- 1 output, as shown in Figure 35. In this configuration, the device channel MOSFETs in push-pull configuration. As shown in is shutdown during power-up but users are allowed to program Figure 34, the output is equal to V or V , and these logic DD SS the device. Thus, when O is programmed high, the device exits 1 outputs have adequate current driving capability to drive shutdown mode and responds to the new setting. This self-contained milliamperes of load. shutdown function allows absolute shutdown during power-up, VDD which is crucial in hazardous environments, and it does not add MP extra components. 1 2 IN O1 O1 SHDN OO1F DWARTIAT EIN M FORDAEME 2 MN VSS 00926-025 RPD Users can also aFicgtuivrea t3e4 O. Ou atnpudt OSta ig ne othf eL ofgoilclo Owuitnpugt t, hOr1e e different SSDCAL 00926-026 1 2 Figure 35. Shutdown by Internal Logic Output, O1 ways without affecting the wiper settings: 340Ω LOGIC 1. Start, slave address byte, acknowledge, instruction byte 2. wCoitmh pOle1 taen tdh eO w2 srpiteec cifyicelde, wacitkhn sotwople, dtghee,n s tsotapr.t , slave address VSS 00926-027 byte, acknowledge, instruction byte with O and O specified, Figure 36. ESD Protection of Digital Pins 1 2 acknowledge, stop. 3. Do not complete the write cycle by not issuing the stop, A,B,W then start, slave address byte, acknowledge, instruction All dbigyittea lw initphu Ots1 aarned p Oro2t espcteecdif wieidt,h a ac ksneroiwesl eindpgeu,t srteospis. t or and VSS 00926-028 Figure 37. ESD Protection of Resistor Terminals the parallel Zener ESD structures shown in Figure 36. This applies to the digital input pins, SDA, SCL, and SHDN. Rev. D | Page 15 of 18

AD5241/AD5242 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.A20X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 39. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Rev. D | Page 16 of 18

Data Sheet AD5241/AD5242 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 0.65 0.19 SEATING 0° 0.45 BSC PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 10.00 (0.3937) 9.80 (0.3858) 16 9 4.00 (0.1575) 6.20 (0.2441) 3.80 (0.1496) 1 8 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 45° 1.75 (0.0689) 0.25 (0.0098) 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AC C(RINEOFNPEATRRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 41. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. D | Page 17 of 18

AD5241/AD5242 Data Sheet ORDERING GUIDE Model1, 2 No. of Channels End-to-End R Temperature Range Package Description Package Option AB AD5241BRZ10 1 10 kΩ –40°C to +105°C 14-Lead SOIC_N R-14 AD5241BRZ10-RL7 1 10 kΩ –40°C to +105°C 14-Lead SOIC_N R-14 AD5241BRUZ10 1 10 kΩ –40°C to +105°C 14-Lead TSSOP RU-14 AD5241BRUZ10-R7 1 10 kΩ –40°C to +105°C 14-Lead TSSOP RU-14 AD5241BRZ100 1 100 kΩ –40°C to +105°C 14-Lead SOIC_N R-14 AD5241BRUZ100 1 100 kΩ –40°C to +105°C 14-Lead TSSOP RU-14 AD5241BRUZ100-R7 1 100 kΩ –40°C to +105°C 14-Lead TSSOP RU-14 AD5241BRZ1M 1 1 MΩ –40°C to +105°C 14-Lead SOIC_N R-14 AD5241BRZ1M-REEL 1 1 MΩ –40°C to +105°C 14-Lead SOIC_N R-14 AD5241BRU1M-REEL7 1 1 MΩ –40°C to +105°C 14-Lead TSSOP RU-14 AD5242BR10-REEL7 2 10 kΩ –40°C to +105°C 16-Lead SOIC_N R-16 AD5242BRZ10 2 10 kΩ –40°C to +105°C 16-Lead SOIC_N R-16 AD5242BRZ10-REEL7 2 10 kΩ –40°C to +105°C 16-Lead SOIC_N R-16 AD5242BRUZ10 2 10 kΩ –40°C to +105°C 16-Lead TSSOP RU-16 AD5242BRUZ10-RL7 2 10 kΩ –40°C to +105°C 16-Lead TSSOP RU-16 AD5242BRZ100 2 100 kΩ –40°C to +105°C 16-Lead SOIC_N R-16 AD5242BRZ100-REEL7 2 100 kΩ –40°C to +105°C 16-Lead SOIC_N R-16 AD5242BRU100 2 100 kΩ –40°C to +105°C 16-Lead TSSOP RU-16 AD5242BRUZ100 2 100 kΩ –40°C to +105°C 16-Lead TSSOP RU-16 AD5242BRUZ100-RL7 2 100 kΩ –40°C to +105°C 16-Lead TSSOP RU-16 AD5242BRZ1M 2 1 MΩ –40°C to +105°C 16-Lead SOIC_N R-16 AD5242BRUZ1M 2 1 MΩ –40°C to +105°C 16-Lead TSSOP RU-16 AD5242BRUZ1M-REEL7 2 1 MΩ –40°C to +105°C 16-Lead TSSOP RU-16 EVAL-AD5242DBZ 2 Evaluation Board 1 The AD5241/AD5242 die size is 69 mil × 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5,495,245 applies. 2 Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2001–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00926-0-6/15(D) Rev. D | Page 18 of 18

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5242BRZ1M AD5242BRU100 AD5242BRUZ100 AD5242BRZ100 AD5242BRUZ1M AD5241BRZ100 AD5241BRUZ100 AD5242BRUZ10 AD5241BRUZ10 AD5241BRZ10 AD5242BRZ10 AD5241BRZ1M AD5241BRU1M-REEL7 AD5241BRUZ100-R7 AD5241BRUZ10-R7 AD5241BRZ10-RL7 AD5241BRZ1M-REEL AD5242BRUZ100-RL7 AD5242BRUZ10-RL7 AD5242BRUZ1M-REEL7 AD5242BRZ100-REEL7 AD5242BRZ10- REEL7 AD5242BR10-REEL7 EVAL-AD5242DBZ