Nonvolatile Memory, Dual 1024-Position Digital Potentiometer Enhanced Product AD5235-EP FEATURES FUNCTIONAL BLOCK DIAGRAM Dual-channel, 1024-position resolution AD5235-EP 25 kΩ nominal resistance ADDR VDD CS DECODE RDAC1 Low temperature coefficient: 35 ppm/°C REGISTER A1 CLK Nonvolatile memory stores wiper settings SERIAL W1 SDI Permanent memory write protection INTERFACE B1 SDO EEMEM1 RDAC1 Wiper setting readback Resistance tolerance stored in EEMEM PR POWER-ON RESET RDAC2 Predefined linear increment/decrement instructions REGISTER A2 Predefined ±6 dB/step log taper increment/decrement WP EEMEM W2 RDY CONTROL instructions B2 EEMEM2 RDAC2 SPI-compatible serial interface +2.7 V to +5 V single supply or ±2.5 V dual supply VSS 26 BYTES RTOL* 26 bytes extra nonvolatile memory for user-defined USER EEMEM GND information 1P0o0w-eyre-aorn t ryepfirceaslh deadt aw riethte EnEtMioEnM, T sAe =t t5in5g°Cs *RAB TOLERANCE 09185-001 Figure 1. Enhanced Features In scratchpad programming mode, a specific setting can be Supports defense and aerospace applications (AQEC) programmed directly to the RDAC2 register that sets the resistance Temperature range: −40°C to +125°C between Terminal W and Terminal A, and Terminal W and Controlled manufacturing baseline Terminal B. This setting can be stored into the EEMEM and 1 assembly/test site is restored automatically to the RDAC register during system 1 fabrication site power-on. Product change notification Qualification data available on request The EEMEM content can be restored dynamically or through APPLICATIONS external PR strobing, and a WP function protects EEMEM contents. DWDM laser diode driver, optical supervisory systems To simplify the programming, the independent or simultaneous Mechanical potentiometer replacement linear-step increment or decrement commands can be used to move Instrumentation: gain, offset adjustment the RDAC wiper up or down, one step at a time. For logarithmic Programmable voltage-to-current conversion ±6 dB changes in the wiper setting, the left or right bit shift Programmable filters, delays, time constants command can be used to double or halve the RDAC wiper setting. Programmable power supply The AD5235-EP patterned resistance tolerance is stored in the Low resolution DAC replacement EEMEM. Therefore, in readback mode, the host processor can Sensor calibration know the actual end-to-end resistance. The host can execute the GENERAL DESCRIPTION appropriate resistance step through a software routine that simplifies The AD5235-EP is a dual-channel, nonvolatile memory,1 open-loop applications as well as precision calibration and digitally controlled potentiometer2 with 1024-step resolution. tolerance matching applications. The device performs the same electronic adjustment function as a The AD5235-EP is available in a thin, 16-lead TSSOP package. mechanical potentiometer with enhanced resolution, solid state The part is guaranteed to operate over the extended industrial reliability, and superior low temperature coefficient performance. temperature range of −40°C to +125°C. The AD5235-EP’s versatile programming via an SPI®-compatible Full details about this enhanced product, including theory of serial interface allows 16 modes of operation and adjustment operation, register details, and applications information, are including scratchpad programming, memory storing and restoring, available in the AD5235 data sheet, which should be consulted increment/decrement, ±6 dB/step log taper adjustment, wiper setting in conjunction with this data sheet. readback, and extra EEMEM1 for user-defined information such as memory data for other components, look-up tables, or system 1 The terms nonvolatile memory and EEMEM are used interchangeably. 2 The terms digital potentiometer and RDAC are used interchangeably. identification information. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5235-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions ..............................8 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 13 Specifications ..................................................................................... 3 Outline Dimensions ....................................................................... 14 Electrical Characteristics ............................................................. 3 Ordering Guide .......................................................................... 14 Interface Timing and EEMEM Reliability Characteristics ..... 5 REVISION HISTORY 1/2018—Rev. A to Rev. B Change to Features Section ............................................................. 1 Changes to Ordering Guide .......................................................... 14 7/2012—Rev. 0 to Rev. A Change to Features Section ............................................................. 1 Changes to Electrical Characteristics Section and Table 1 ......... 3 Changes to Interface Timing and EEMEM Reliability Characteristics Section and Table 2 ............................................... 5 Changes to Typical Performance Characteristics Section ........... 9 Added Figure 14 and Figure 16, Renumbered Sequentially ..... 10 Deleted Figure 21 ............................................................................ 11 Added Figure 23 .............................................................................. 12 7/2010—Revision 0: Initial Version Rev. B | Page 2 of 14

Enhanced Product AD5235-EP SPECIFICATIONS ELECTRICAL CHARACTERISTICS V = 2.7 V to 5.5 V, V = 0 V; V = 2.5 V, V = −2.5 V, V = V , V = V , −40°C < T < +125°C, unless otherwise noted. DD SS DD SS A DD B SS A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (All RDACs) Resistor Differential Nonlinearity2 R-DNL R −1 +1 LSB WB Resistor Integral Nonlinearity2 R-INL R −2 +2 LSB WB Nominal Resistor Tolerance ∆R /R Code = full-scale −8 +8 % AB AB Resistance Temperature Coefficient (∆R /R )/∆T × 106 35 ppm/°C AB AB Wiper Resistance R I = 1 V/R , V = 5 V, code = 30 65 Ω W W WB DD half scale I = 1 V/R , V = 3 V, code = 50 Ω W WB DD half scale Nominal Resistance Match R /R Code = full-scale, T = 25°C ±0.1 % AB1 AB2 A DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (All RDACs) Resolution N 10 Bits Differential Nonlinearity3 DNL −1 +1 LSB Integral Nonlinearity3 INL −1 +1 LSB Voltage Divider Temperature Coefficient (∆V /V )/∆T × 106 Code = half scale 15 ppm/°C W W Full-Scale Error V Code = full-scale −7 0 LSB WFSE Zero-Scale Error V Code = zero scale 0 5 LSB WZSE RESISTOR TERMINALS Terminal Voltage Range4 V , V , V V V V A B W SS DD Capacitance Ax, Bx5 C , C f = 1 MHz, measured to GND, 11 pF A B code = half scale Capacitance Wx5 C f = 1 MHz, measured to GND, 80 pF W code = half scale Common-Mode Leakage Current5, 6 I V = V /2 0.01 ±1 µA CM W DD DIGITAL INPUTS AND OUTPUTS Input Logic High V With respect to GND, V = 5 V 2.4 V IH DD Input Logic Low V With respect to GND, V = 5 V 0.8 V IL DD Input Logic High V With respect to GND, V = 3 V 2.1 V IH DD Input Logic Low V With respect to GND, V = 3 V 0.6 V IL DD Input Logic High V With respect to GND, V = +2.5 V, 2.0 V IH DD V = −2.5 V SS Input Logic Low V With respect to GND, V = +2.5 V, 0.5 V IL DD V = −2.5 V SS Output Logic High (SDO, RDY) V R = 2.2 kΩ to 5 V 4.9 V OH PULL-UP Output Logic Low V I = 1.6 mA, V = 5 V 0.4 V OL OL LOGIC Input Current I V = 0 V or V ±2.25 µA IL IN DD Input Capacitance5 C 5 pF IL Rev. B | Page 3 of 14

AD5235-EP Enhanced Product Parameter Symbol Conditions Min Typ1 Max Unit POWER SUPPLIES Single-Supply Power Range V V = 0 V 2.7 5.5 V DD SS Dual-Supply Power Range V /V ±2.25 ±2.75 V DD SS Positive Supply Current I V = V or V = GND 2 7 µA DD IH DD IL Negative Supply Current I V = V or V = GND, V = +2.5 V, −6 −2 µA SS IH DD IL DD V = −2.5 V SS EEMEM Store Mode Current I (store) V = V or V = GND, V = GND, 2 mA DD IH DD IL SS I ≈ 0 SS I (store) V = +2.5 V, V = −2.5 V −2 mA SS DD SS EEMEM Restore Mode Current7 I (restore) V = V or V = GND, V = GND, 320 µA DD IH DD IL SS I ≈ 0 SS I (restore) V = +2.5 V, V = −2.5 V −320 µA SS DD SS Power Dissipation8 P V = V or V = GND 10 40 µW DISS IH DD IL Power Supply Sensitivity5 P ΔV = 5 V ± 10% 0.006 0.01 %/% SS DD DYNAMIC CHARACTERISTICS5, 9 Bandwidth BW −3 dB, V /V = ±2.5 V 125 kHz DD SS Total Harmonic Distortion THD V = 1 V rms, V = 0 V, f = 1 kHz 0.009 % W A B V Settling Time t V = V , V = 0 V, 4 µs W S A DD B V = 0.50% error band, W Code 0x000 to Code 0x200 Resistor Noise Density eN_WB TA = 25°C 20 nV/√Hz Crosstalk (CW1/CW2) CT VA = VDD, VB = 0 V, measured VW1 30 nV-s with V making full-scale change W2 Analog Crosstalk CTA VDD = VA1 = +2.5 V, −110 dB V = V = −2.5 V, measured SS B1 V with V = 5 V p-p at f = 1 kHz, W1 W2 Code 1 = 0x200, Code 2 = 0x3FF 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA for VDD = 2.7 V and IW ~ 400 µA for VDD = 5 V (see Figure 25). 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions (see Figure 26). 4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground- referenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any Terminal A, Terminal B, or Terminal W to a common-mode bias level of VDD/2. 7 EEMEM restore mode current is not continuous. Current is consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 22). To minimize power dissipation, a NOP, Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1). 8 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 9 All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V. Rev. B | Page 4 of 14

Enhanced Product AD5235-EP INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input control voltages are specified with t = t = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are R F measured using both V = 2.7 V and V = 5 V. DD DD Table 2. Parameter Symbol Conditions Min Typ1 Max Unit Clock Cycle Time (t ) t 20 ns CYC 1 CS Setup Time t 10 ns 2 CLK Shutdown Time to CS Rise t 1 t 3 CYC Input Clock Pulse Width t, t Clock level high or low 10 ns 4 5 Data Setup Time t From positive CLK transition 5 ns 6 Data Hold Time t From positive CLK transition 5 ns 7 CS to SDO-SPI Line Acquire t 40 ns 8 CS to SDO-SPI Line Release t 50 ns 9 CLK to SDO Propagation Delay2 t R = 2.2 kΩ, C < 20 pF 50 ns 10 P L CLK to SDO Data Hold Time t R = 2.2 kΩ, C < 20 pF 0 ns 11 P L CS High Pulse Width3 t 10 ns 12 CS High to CS High3 t 4 t 13 CYC RDY Rise to CS Fall t 0 ns 14 CS Rise to RDY Fall Time t 0.15 0.3 ms 15 Store EEMEM Time4, 5 t Applies to Instructions 0x2, 0x3 15 50 ms 16 Read EEMEM Time4 t Applies to Instructions 0x8, 0x9, 0x10 7 30 µs 16 CS Rise to Clock Rise/Fall Setup t 10 ns 17 Preset Pulse Width (Asynchronous)6 t 50 ns PRW Preset Response Time to Wiper Setting6 tPRESP PR pulsed low to refresh wiper positions 30 µs Power-On EEMEM Restore Time6 t 30 µs EEMEM FLASH/EE MEMORY RELIABILITY Endurance7 T = 25°C 1 MCycles A 100 kCycles Data Retention8 100 Years 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Propagation delay depends on the value of VDD, RPULL-UP, and CL. 3 Valid for commands that do not activate the RDY pin. 4 The RDY pin is low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 µs; CMD_9, CMD_10 ~ 7 µs; CMD_2, CMD_3 ~ 15 ms; PR hardware pulse ~ 30 µs. 5 Store EEMEM time depends on the temperature and EEMEM writes cycles. Higher timing is expected at a lower temperature and higher write cycles. 6 Not shown in Figure 2 and Figure 3. 7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +125°C. 8 Retention lifetime equivalent at junction temperature (TJ) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. Rev. B | Page 5 of 14

AD5235-EP Enhanced Product Timing Diagrams CPHA = 1 CS t12 t3 t13 t2 t1 CLK CPOL = 1 t5 Bt243 B0 t17 t7 t6 HIGH HIGH OR LOW OR LOW SDI B23 (MSB) B0 (LSB) t8 t10 t11 t9 SDO B24* B23 (MSB) B0 (LSB) t14 t15 t16 RDY *TTHHEE ECXPTORLA = B 1I TM TICHRAOTC ISO NNTORTO DLELFEIRN ECDO IMSM NAONRDMAALLILGYN TSH TEH LES IBN COOF MTIHNEG C DHAATRAATCOT TEHRE P PROEVSIIOTIUVSEL EYD TGREA NOSFM TIHTET ECDL.OCK. 09185-002 Figure 2. CPHA = 1 Timing Diagram CPHA = 0 CS t12 t 1 t3 t13 CLK t2 B23 t5 B0 t17 CPOL = 0 t4 t7 t6 HIGH HIGH OR LOW OR LOW SDI B23 (MSB IN) B0(LSB) t8 t10 t11 t9 SDO B23 (MSB OUT) B0(LSB) * t14 t15 t16 RDY *TTHHEE ECXPTORLA = B0I TM TICHRAOTC IOS NNTORTO DLELFEIRN ECDO MISM NAONRDMAALLILGYN ST HTEH EM SINBC OOFM TINHGE DCAHTAARTAOC TTEHRE JPUOSSTIT RIVEEC EEIDVGEED .OF THE CLOCK. 09185-003 Figure 3. CPHA = 0 Timing Diagram Rev. B | Page 6 of 14

Enhanced Product AD5235-EP ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 3. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND –0.3 V to +7 V DD section of this specification is not implied. Operation beyond V to GND +0.3 V to −7 V SS the maximum operating conditions for extended periods may V to V 7 V DD SS affect product reliability. V , V , V to GND V − 0.3 V to V + 0.3 V A B W SS DD I , I , I A B W Pulsed1 ±2.5 mA ESD CAUTION Continuous ±1.1 mA Digital Input and Output Voltage to GND −0.3 V to V + 0.3 V DD Operating Temperature Range2 −40°C to +125°C Maximum Junction Temperature (T max) 150°C J Storage Temperature Range −65°C to +150°C Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C Thermal Resistance Junction-to-Ambient, θ 150°C/W JA Junction-to-Case, θ 28°C/W JC Package Power Dissipation (T max − T )/θ J A JA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package and the maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Includes programming of nonvolatile memory. Rev. B | Page 7 of 14

AD5235-EP Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLK 1 16 RDY SDI 2 15 CS SDO 3 14 PR GND 4 AD5235-EP 13 WP TOP VIEW VSS 5 (Not to Scale) 12 VDD A1 6 11 A2 W1 7 10 W2 B1 8 9 B2 09185-004 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK Serial Input Register Clock. Shifts in one bit at a time on positive clock edges. 2 SDI Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first. 3 SDO Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. 4 GND Ground Pin, Logic Ground Reference. 5 V Negative Supply. Connect to 0 V for single-supply applications. If V is used in dual supply, it must be able to sink SS SS 35 mA for 30 ms when storing data to EEMEM. 6 A1 Terminal A of RDAC1. 7 W1 Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0. 8 B1 Terminal B of RDAC1. 9 B2 Terminal B of RDAC2. 10 W2 Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1. 11 A2 Terminal A of RDAC2. 12 V Positive Power Supply. DD 13 WP Optional Write Protect. When active low, WP prevents any changes to the present contents, except PR strobe. CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Tie WP to V , if not used. DD 14 PR Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale 512 until EEMEM is loaded with a new value by the user. PR is activated 10 at the logic high transition. Tie PR to V , if not used. DD 15 CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. 16 RDY Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and PR. Rev. B | Page 8 of 14

Enhanced Product AD5235-EP TYPICAL PERFORMANCE CHARACTERISTICS 0.25 0.20 –40 –40 +25 +25 0.20 +85 +85 +125 0.15 +125 0.15 0.10 B) 0.10 SB) S L R(L 0.05 OR ( 0.05 O R R R ER 0 L E 0 L N IN 0.05 R-D–0.05 0.10 –0.10 0.15 0.20 –0.15 0 200 4D00IGITALCO6D00E 800 1000 09185-005 0 200 40D0IGITAL CO6D00E 800 1000 09185-008 Figure 5. INL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay Figure 8. R-DNL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay 0.16 200 –40 00..1124 +++2815525 ppm/°C) 118600 O ( B) 0.10 MPC 140 R(LS 0.08 E TE 120 RO 0.06 OD 100 R M LE 0.04 ER 80 N T D 0.02 ME 60 O 0 NTI 40 E T 0.02 O 20 P 0.04 0 0 200 4D0I0GITAL CO6D0E0 800 1000 09185-006 0 256 CODE5 (1D2ecimal) 768 1023 09185-009 Figure 6. DNL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay Figure 9. (∆VW/VW)/∆T × 106 Potentiometer Mode Tempco 0.20 200 –40 +25 0.15 +85 180 +125 C) m/° 160 0.10 p B) O (p 140 RROR (LS 0.050 E TEMPC 112000 E D NL 0.05 MO 80 R-I AT 60 T 0.10 S O E 40 H 0.15 R 20 0.20 0 0 200 40D0IGITAL CO6D00E 800 1000 09185-007 0 256 CODE5 (1D2ecimal) 768 1023 09185-010 Figure 7. R-INL vs. Code, TA = −40°C, +25°C, +85°C, +125°C Overlay Figure 10. (∆RWB/RWB)/∆T × 106 Rheostat Mode Tempco Rev. B | Page 9 of 14

AD5235-EP Enhanced Product 60 2.7V 2.7V 3.0V 3.0V 3.3V 400 3.3V 50 5.0V 5.0V 5.5V 5.5V Ω) E ( C 40 300 N A T N RESIS 30 I (µA)DD 200 O R 20 E P WI 100 10 0 0 0 200 4C0O0DE (Deci6m0a0l) 800 1000 09185-011 0 1 2 VDIO (V3) 4 5 09185-014 Figure 11. Wiper On Resistance vs. Code Figure 14. IDD vs. Digital Input Voltage 3 0.12 IDD = 2.7V IDD = 3.3V 2 IIDDDD == 35..00VV 0.10 IDD = 5.5V 1 0.08 A) %) I/I (µDDSS 0 THD + N ( 0.06 –1 0.04 ISS = 2.7V –2 ISS = 3.3V 0.02 ISS = 3.0V ISS = 5.0V ISS = 5.5V –3 0 –55 –50 –40 –20 T0EMP2E5RAT4U0RE (6°C0) 85 100 110 125 09185-012 10 100 FREQUE1NkCY (Hz) 10k 100k 09185-015 Figure 12. IDD vs. Temperature Figure 15. THD + Noise vs. Frequency 50 10 FULL SCALE MIDSCALE ZERO SCALE 40 1 30 %) (µA)D D + N ( 0.1 ID 20 TH 0.01 10 01 2 3 4 FREQ5UENC6Y (MHz7) 8 9 10 09185-013 0.0001.0001 0.001 AM0.P01LITUDE (V0 r.m1s) 1 10 09185-016 Figure 13. IDD vs. Clock Frequency Figure 16. THD + Noise vs. Amplitude Rev. B | Page 10 of 14

Enhanced Product AD5235-EP 3 0 VDD –3 B) N (d VW (FULL SCALE) AI G –6 f–3dB= 125kHz –1–29 VDVDA =D = /M V1ISVDS Sr=mC±As2L.5EV 10µs/DIV VVVT1VADAB/ D =D== =I250V 5VV5°VC 09185-020 1k 10kFREQUENCY (Hz1)00k 1M 09185-017 Figure 17. −3 dB Bandwidth vs. Resistance (See Figure 31) Figure 20. Power-On Reset 0 2.5196 CODE 0x200 VDD= VSS= 5V 2.516 CODE = 0x200TO 0x1FF –10 0x100 2.512 0x080 2.508 –20 0x040 V) N (dB) –30 0x020 TUDE (22..550004 AI 0x010 LI G P2.496 –40 0x008 AM 0x004 2.492 0x002 2.488 –50 0x001 2.484 –60 2.4796 1k 10kFREQUENCY (Hz)100k 1M 09185-018 0 20 40 60TIME (µ8s0) 100 120 144 09185-021 Figure 18. Gain vs. Frequency vs. Code (See Figure 31) Figure 21. Midscale Glitch Energy 0 VDD = 5V ± 10%AC VDD = 5V –10 MVSESA=S U0VR,E VDA A=T 4VV,W VWB I=T H0V CODE = 0x200 CS (5V/DIV) TA = 25°C TA= 25°C –20 CLK (5V/DIV) –30 B) d R ( –40 R S SDI (5V/DIV) P –50 –60 ––7800 IDD (2mA/DIV) 02816-023 10 100 F1RkEQUENCY 1(H0kz) 100k 1M 09185-019 Figure 19. PSRR vs. Frequency Figure 22. IDD vs. Time When Storing Data to EEMEM Rev. B | Page 11 of 14

AD5235-EP Enhanced Product 2.60 100 VA = VB = OPEN TA = 25°C A) E (V) 2.55 – mMAX 10 R VOLTAG 2.50 CAL (IWB_ 1 RAB = 25kΩ PE CTI WI E R 2.45 EO 0.1 H T 2.400 0.5 TIM1E.0 (µs) 1.5 2.0 09185-024 0.010 128 256 38C4ODE 5(D12ecima6l)40 768 896 1023 09185-125 Figure 23. Digital Feedthrough Figure 24. IWB_MAX vs. Code Rev. B | Page 12 of 14

Enhanced Product AD5235-EP TEST CIRCUITS Figure 25 to Figure 35 define the test conditions used in the Specifications section. NC A +15V ADUTW IW OFFSETVIN DUT B W OP42 VOUT GND NC B= NO CONNECVTMS 09185-026 2.5V –15V 09185-032 Figure 25. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 31. Gain vs. Frequency ADUT V1L+S =B V =D DV+/2N DUT RSW= 0IS.1WV V+ W CODE = 0x00 W B VMS 09185-027 B ISW +–0.1V A = NC VSSTO VDD 09185-033 Figure 26. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 32. Incremental On Resistance DUT IW= VDD/RNOMINAL NC VMS2 A W VW VDD A ICM B DUT W VMS1 RW = [VMS1 – VMS2]/IW 09185-028 VSS GND B VCM NCNC = NO CONNECT 09185-034 Figure 27. Wiper Resistance Figure 33. Common-Mode Leakage Current VA V+ = VDD ±10% (∆VMS) A1 VDD A2 V+ ~ VDD A W PSRR (dB) = 20 LOG ∆VDD VIN RDAC1 RDAC2 B VMS PSS (%/%) =∆∆VVDMDS%% 09185-029 NC W1B1 VSS WB22 VOUT Figure 28. Power Supply Sensitivity (PSS, PSRR) NCCTA = = N 2O0 LCOOGN[NVEOCUTT/VIN] 09185-035 Figure 34. Analog Crosstalk A DUT B 5V 200µA IOL VIN W OFFGSNEDT OP279 VOUT TO OUTPUT OVORH (MIN) OFFSET BIAS 09185-030 PIN 50pCFL VOL (MAX) 200µA IOH 09185-036 Figure 29. Inverting Gain Figure 35. Load Circuit for Measuring VOH and VOL (The diode bridge test circuit is equivalent to the application circuit with RPULL-UP of 2.2 kΩ.) 5V VIN OP279 VOUT W OFFSET GND A DUT B OFFSET BIAS 09185-031 Figure 30. Noninverting Gain Rev. B | Page 13 of 14

AD5235-EP Enhanced Product OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SEATING 0° 0.45 PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1 R (kΩ) Temperature Range Package Description Package Option AB AD5235BRU25-EP-RL7 25 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 AD5235BRUZ25-EP-R7 25 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16 1 Z = RoHS Compliant Part. ©2010–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09185-0-1/18(B) Rev. B | Page 14 of 14

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5235BRU25-EP-RL7 AD5235BRUZ250-R7 EVAL-AD5235SDZ AD5235BRUZ250 AD5235BRUZ25 AD5235BRUZ25-RL7 AD5235BRUZ25-EP-R7