None

AD5220–SPECIFICATIONS (V = +3 V 6 10% or +5 V 6 10%, V = +V , V = 0 V, –408C < T < +858C unless ELECTRICAL CHARACTERISTICS DD A DD B A otherwise noted) Parameter Symbol Conditions Min Typ1 Max Units DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL2 R-DNL R , V = NC, R = 10 kW –1 – 0.4 +1 LSB WB A AB R , V = NC, R = 50 kW or 100 kW –0.5 – 0.1 +0.5 LSB WB A AB Resistor Nonlinearity2 R-INL R , V = NC, R = 10 kW –1 – 0.5 +1 LSB WB A AB R , V = NC, R = 50 kW or 100 kW –0.5 – 0.1 +0.5 LSB WB A AB Nominal Resistor Tolerance D R T = +25(cid:176) C –30 +30 % A Resistance Temperature Coefficient D R /D T V = V , Wiper = No Connect 800 ppm/(cid:176) C AB AB DD Wiper Resistance R I = V /R, V = +3 V or +5 V 40 100 W W W DD DD DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N 7 Bits Integral Nonlinearity3 INL R = 10 kW –1 – 0.5 +1 LSB AB R = 50 kW , 100 kW –0.5 – 0.2 +0.5 LSB AB Differential Nonlinearity Error3 DNL R = 10 kW –1 – 0.4 +1 LSB AB R = 50 kW , 100 kW –0.5 – 0.1 +0.5 LSB AB Voltage Divider Temperature Coefficient D V /D T Code = 40 20 ppm/(cid:176) C W H Full-Scale Error V Code = 7F –2 –0.5 0 LSB WFSE H Zero-Scale Error V Code = 00 0 +0.5 +1 LSB WZSE H RESISTOR TERMINALS Voltage Range4 V V V 0 V V A, B, W DD Capacitance5 A, B C C f = 1 MHz, Measured to GND, Code = 40 10 pF A, B H Capacitance5 W C f = 1 MHz, Measured to GND, Code = 40 48 pF W H Common-Mode Leakage I V = V = V 7.5 nA CM A B W DIGITAL INPUTS AND OUTPUTS Input Logic High V V = +5 V/+3 V 2.4/2.1 V IH DD Input Logic Low V V = +5 V/+3 V 0.8/0.6 V IL DD Input Current I V = 0 V or +5 V – 1 m A IL IN Input Capacitance5 C 5 pF IL POWER SUPPLIES Power Supply Range V 2.7 5.5 V DD Supply Current I V = +5 V or V = 0 V, V = +5 V 15 40 m A DD IH IL DD Power Dissipation6 P V = +5 V or V = 0 V, V = +5 V 75 200 m W DISS IH IL DD Power Supply Sensitivity PSS 0.004 0.015 %/% DYNAMIC CHARACTERISTICS5, 7, 8 Bandwidth –3 dB BW_10K R = 10 kW , Code = 40 650 kHz AB H BW_50K R = 50 kW , Code = 40 142 kHz AB H BW_100K R = 100 kW , Code = 40 69 kHz AB H Total Harmonic Distortion THD V =1 V rms + 2.5 V dc, V = 2.5 V dc, f = 1 kHz 0.002 % W A B V Settling Time t V = V , V = 0 V, 50% of Final Value, W S A DD B 10K/50K/100K 0.6/3/6 m s Resistor Noise Voltage e R = 5 kW , f = 1 kHz 14 nV/(cid:214) Hz NWB WB INTERFACE TIMING CHARACTERISTICS Applies to All Parts5, 9 Input Clock Pulsewidth t , t Clock Level High or Low 25 ns CH CL CS to CLK Setup Time t 20 ns CSS CS Rise to Clock Hold Time t 20 ns CSH U/D to Clock Fall Setup Time t 10 ns UDS NOTES 1Typicals represent average readings at +25(cid:176)C and V = +5 V. DD 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit. 3INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V and V = 0 V. W A DD B DNL specification limits of – 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit. 4Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5Guaranteed by design and not subject to production test. 6P is calculated from (I · V ). CMOS logic level inputs result in minimum power dissipation. DISS DD DD 7Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest band- width. The highest R value results in the minimum overall power consumption. 8All dynamic characteristics use V = +5 V. DD 9See timing diagrams for location of measured values. All input control voltages are specified with t = t = 1 ns (10% to 90% of V ) and timed from a voltage level R F DD of 1.6 V. Switching characteristics are measured using both V = +3 V or +5 V. DD Specifications subject to change without notice. –2– REV. A

AD5220 ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION (T = +25(cid:176) C, unless otherwise noted) A V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V, +7 V DD V , V , V to GND . . . . . . . . . . . . . . . . . . . . . . . . . .0 V, V AA–BB, AW–W , B –W . . . . . . . . . . . . . . . . . . . . . . – 20 mDAD CLK 1 8 VDD X X X X X X U/D 2 AD5220 7 CS Digital Input Voltage to GND . . . . . . . . . . . 0 V, VDD + 0.3 V TOP VIEW Operating Temperature Range . . . . . . . . . . . –40(cid:176) C to +85(cid:176) C A1 3 (Not to Scale) 6 B1 Maximum Junction Temperature (T MAX) . . . . . . . .+150(cid:176) C GND 4 5 W1 J Storage Temperature . . . . . . . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300(cid:176) C Package Power Dissipation . . . . . . . . . . . . . . (T max–T )/q J A JA Thermal Resistance q JA P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103(cid:176) C/W SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158(cid:176) C/W m SOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206(cid:176) C/W *Stresses above those listed under Absolute Maximum Ratings may cause PIN FUNCTION DESCRIPTIONS permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the Pin operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. No. Name Description 1 CLK Serial Clock Input, Negative Edge Triggered Table I. Truth Table 2 U/D UP/DOWN Direction Increment Control CS CLK U/D Operation 3 A1 Terminal A1 L t H Wiper Increment Toward Terminal A 4 GND Ground L t L Wiper Decrement Toward Terminal B 5 W1 Wiper Terminal H X X Wiper Position Fixed 6 B1 Terminal B1 7 CS Chip Select Input, Active Low 8 V Positive Power Supply 1 DD CS 0 t CSS t 1 tCL CH tCSH CLK 0 t 1 UDS U/D 0 Figure 3.Detail Timing Diagram CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5220 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE precautions are recommended to avoid performance degradation or loss of functionality. REV. A –3–

AD5220–Typical Performance Characteristics 100 6 48 SS = 300 UNITS % RAB 5 VRDADB == 55.05kVV 40 VTAD D= =+ 2+528.C7V ENT OF NOMINALD RESISTANCE – 5705 V – VWB 43 FREQUENCY 2342 PERCEND-TO-EN 25 RWB RWA 21 7FH40H20H 100H8H 04H02H01H 168 0 0 0 0 32 64 96 128 0 20 40 60 80 100 120 20 28 36 44 52 60 CODE – Decimal CONDUCTION CURRENT, IWB – mA WIPER RESISTANCE – V Figure 4.Wiper to End Terminal Figure 5.Resistance Linearity vs. Figure 6.Wiper Contact Resistance Resistance vs. Code Conduction Current 0.5 0.5 0.5 0.4 VTAD D= =+ 2+558.C5V 0.4 TVAD D= =+ 2+558.C5V 0.4 0.3 0.3 100kV VERSION 0.3 10kV VERSION 0.2 50kV VERSION 100kV VERSION 0.2 50kV VERSION 0.2 50kV VERSION RDNL – LSB–000...110 RINL – LSB–000...110 INL – LSB –000...110 TA = +258C ––00..23 ––00..23 10kV VERSION ––00..23 VVDAD = =+ 5+.55.V5V 100kV VERSION 10kV VERSION VB = 0V –0.4 –0.4 –0.4 –0.5 –0.5 –0.5 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 CODE – Decimal CODE – Decimal CODE – Decimal Figure 7.R-DNL Relative Resistance Figure 8.R-INL Resistance Non- Figure 9.Potentiometer Divider INL Step Position Nonlinearity Error vs. linearity Error vs. Supply Voltage Error vs. Code Code 00..45 TVAD D= =+ 2+558.C5V 00..650205 CROABD =E 5=0 4k0VH VE – k100 100kV VERSION 0.3 VA = +5.5V R VA = VDD NC 80 DNL – LSB –0000....1102 100kV VERSION50VkVB =V 0EVRSION NTIOMETER DIVIDENLINEARITY – LSB0000....324305570505 D-TO-END RESISTA 6400 50kV VERSION –0.2 EO N –0.3 POTN0.150 AL E 20 –0.4 10kV VERSION 0.075 MIN 10kV VERSION O N –0.5 0.000 0 0 16 32 48 64 80 96 112 128 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.506.00 –40 –15 10 35 60 85 CODE – Decimal SUPPLY VOLTAGE – V TEMPERATURE – 8C Figure 10.Potentiometer Divider Figure 11.Potentiometer Divider Figure 12.Nominal Resistance vs. DNL Error vs. Code INL Error vs. Supply Voltage Temperature –4– REV. A

AD5220 C 60 60 6 8ppm/ 53 –V5D5D8 C= <+ 5T.5AV < +858C 8m/C 53 –V5D5D8 C= <+ 5T.5AV < +858C 0 00H PCO – 4369 O – pp 4369 VRAW B= MNOEA CSOUNRNEEDCT ––162 4200HH METER MODE TEM 32112518 1500kkVV V AENRDS I1O0N0kV VERSION TAT MODE TEMPC 32112518 10kV VE5R0SkVIO NAND 100kV VERSION GAIN – dB––––12338406 1000008421HHHHH O S POTENTI––1340 RHEO––1340 –––445284 DVVVBIDAN DT == A= +V +2=A.5 54 V=V0 H100mV rms AB +–2W.5V+–OP42 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 1k 10k 100k 1M CODE – Decimal CODE – Decimal FREQUENCY – Hz Figure 13. D V /D T Potentiometer Figure 14. D R /D T Rheostat Figure 15.10 kW Gain vs. Frequency WB WB Mode Tempco (10 kW and 50 kW ) vs. Code 6 6 00H 00H 0 0 –6 40H –6 40H –12 20H –12 20H N – dB––1284 1008HH N – dB––1284 1008HH GAI––3306 0042HH GAI––3306 0042HH VWB 2D0IVmV/ –––445284 VDVVDBIAND T == A = +V 2+=A.5 54 V=V0 H100mV rmsAB +–2W.5V+–OP4201H –––445284 VDVVDBIAND T == A = +V 2+=A.5 54 V=V0 H100mV rmsAB +–2W.5V+–O0P142H VfV =DA D 1= 0 =V0 +Bk5 H=.z5 0VV 1k F1R0kEQUENCY –1 0H0zk 1M 1k F1R0kEQUENCY –1 0H0zk 1M TIME 2ms / DIV Figure 16.50 kW Gain vs. Frequency Figure 17.100 kW Gain vs. Fre- Figure 18.Digital Feedthrough vs. Code quency vs. Code 1.00 –5.8 TA = +258C VDD = +5.0V dB –5.9 10kV 0.10 ORAFBF S=E 1T0 kGVND = +2.5V SS – –6.0 50kV % NE –6.1 100kV 150mV SE – NONINVERTING FLAT –6.2 DVDADT A= +=5 4V0H VWB VfVV =DAB D 1== 0 =+00 V5+k.5H5.Vz5V D40AHT vA 3FH 150500mV0mVmVV THD + NOI0.00.0011 TEST CKT 32 TIENSVTE RCTKITN G31 NORMALIZED GAIN –––––66666.....34567 VVIBN AB == +V+–2A2.5.W 5=VV 5+–0OmPV4 2rms CLK 0V 0.0001 –6.8 10 100 1k 10k 100k 10 100 1k 10k 100k 1M TIME 500ns / DIV FREQUENCY – Hz FREQUENCY – Hz Figure 19.Midscale Transition Glitch Figure 20. Total Harmonic Distortion Figure 21.Normalized Gain Flatness Plus Noise vs. Frequency vs. Frequency REV. A –5–

AD5220 80 400 80 DATA = 3FH TA = +258C 60 m– A 335000 TVAB == +02V58C 60 SFOEER FTIEGSUTR CEI R34CUIT T VDD = +2.7V N E SRR – dB40 LY CURR 220500 VVDAD = =+ 5+.55.V5V VR – ON40 VDD = +5.5V P20 CVTADO D=D =E+ 2+=55 84VC0 DHC 61V p-p AC – SUPPDD115000 VVDAD = =+ 2+.27.V7V 20 CVAL == 41V0p, FVB = 0V I 50 0 0 0 1k 10k 100k 1M 1k 10k 100k 1M 10M 0 1 2 3 4 5 6 FREQUENCY – Hz CLOCK FREQUENCY – Hz VB – Volts Figure 22.Power Supply Rejection Figure 23.I Supply Current vs. Figure 24.Incremental Wiper DD vs. Frequency Clock Frequency Contact Resistance vs. VB 0.10 10 LOGIC = 0V OR VDD TA = +258C ALL LOGIC INPUT A PINS TIED TOGETHER RRENT – m 0.01 VD = +5.5V RENT – mA 1 VDD = +5V SUPPLY CUD0.001 VDD = +3.3V SUPPLY CUR 0.00.11 VDD = +3V D I 0.0001 0.001 –40 –15 10 35 60 85 0 1.0 2.0 3.0 4.0 5.0 TEMPERATURE – 8C DIGITAL INPUT VOLTAGE – V Figure 25.Supply Current vs. Tem- Figure 26.Supply Current vs. Input perature I Logic Voltage DD –6– REV. A

Parametric Test Circuits–AD5220 A DUT B +5V ADUT V1L+S =B V =D DV+/128 VIN ~ W V+ W OFFSET OP279 VOUT B GND VMS 2.5V DC Figure 27.Potentiometer Divider Nonlinearity Error Test Figure 31.Inverting Programmable Gain Test Circuit Circuit (INL, DNL) +5V NO CONNECT ADUT IW VIN ~ W OP279 VOUT W OFFSET B GND A DUT B VMS 2.5V Figure 28.Resistor Position Nonlinearity Error (Rheostat Figure 32.Noninverting Programmable Gain Test Circuit Operation; R-INL, R-DNL) +15V A DUT IW = VDD/RNOMINAL ~ W VMS2 A W VW OFFSET VIN DUT B OP42 VOUT B GND 2.5V VMS1 RW = [VMS1 – VMS2]/IW –15V ␣␣ Figure 29.␣Wiper Resistance Test Circuit Figure 33.Gain vs. Frequency Test Circuit VA DUT RSW = 0IS.1WV V+ ~ VDD AB W VP+S R= RV D(dDB ±) 1=0 2%D0V LMOSG% ( –DD–VV–MD–DS– ) B W ISW CODE = ØØH 0.1V VMS PSS (%/%) = –D–V–D––D–%– 0 TO VDD Figure 30. Power Supply Sensitivity Test Circuit (PSS, Figure 34.Incremental ON Resistance Test Circuit PSRR) REV. A –7–

AD5220 OPERATION Ax The AD5220 provides a 128-position digitally controlled vari- D0 RS able resistor (VR) device. Changing the VR settings is accom- D1 plished by pulsing the CLK pin while CS is active low. The D2 direction of the increment is controlled by the U/D (UP/DOWN) DD34 RS control input pin. When the wiper hits the end of the resistor D5 D6 (Terminals A or B) additional CLK pulses no longer change Wx the wiper setting. The wiper position is immediately decoded RDAC by the wiper decode logic changing the wiper resistance. Ap- UP/DOWN CNTR propriate debounce circuitry is required when push button & switches are used to control the count sequence and direction DECODE of count. The exact timing requirements are shown in Figure 3. The AD5220 powers ON in a centered wiper position exhibit- RS ing nearly equal resistances of R and R . Bx WA WB RS = RNOMINAL/128 Figure 38.AD5220 Equivalent RDAC Circuit VDD CLK CS EN DE A PROGRAMMING THE VARIABLE RESISTOR DOUPW/N 7 OC W Rheostat Operation CNTR D The nominal resistance of the RDAC between terminals A and U/D RS E B B is available with values of 10 kW , 50 kW , and 100 kW . The POR GND final three characters of the part number determine the nominal 40H AD5220 resistance value, e.g., 10 kW =10; 50 kW = 50; 100 kW = 100. The nominal resistance (R ) of the VR has 128 contact points AB Figure 35.Block Diagram accessed by the wiper terminal, plus the B terminal contact. At power ON the resistance from the wiper to either end Terminal DIGITAL INTERFACING OPERATION A or B is approximately equal. Clocking the CLK pin will in- The AD5220 contains a three-wire serial input interface. The crease the resistance from the Wiper W to Terminal B by one three inputs are clock (CLK), CS and UP/DOWN (U/D). The unit of R resistance (see Figure 38). The resistance R is S WB negative-edge sensitive CLK input requires clean transitions to determined by the number of pulses applied to the clock pin. avoid clocking multiple pulses into the internal UP/DOWN Each segment of the internal resistor string has a nominal resis- counter register, see Figure 35. Standard logic families work tance value of R = R /128, which becomes 78 W in the case of S AB well. If mechanical switches are used for product evaluation the 10 kW AD5220BN10 product. Care should be taken to limit they should be debounced by a flip-flop or other suitable the current flow between W and B in the direct contact state to means. When CS is taken active low the clock begins to incre- a maximum value of 5 mA to avoid degradation or possible de- ment or decrement the internal UP/DOWN counter dependent struction of the internal switch contact. upon the state of the U/D control pin. The UP/DOWN counter Like the mechanical potentiometer the RDAC replaces, it is value (D) starts at 40 at system power ON. Each new CLK H totally symmetrical (see Figure 38). The resistance between the pulse will increment the value of the internal counter by one Wiper W and Terminal A also produces a digitally controlled LSB until the full scale value of 3F is reached as long as the H resistance R . When these terminals are used the B–terminal U/D pin is logic high. If the U/D pin is taken to logic low the WA should be tied to the wiper. counter will count down stopping at code 00 (zero-scale). H Additional clock pulses on the CLK pin are ignored when the The typical part-to-part distribution of R is process lot depen- BA wiper is at either the 00 position or the 3F position. dent having a – 30% variation. The change in R with tempera- H H BA ture has a 800 ppm/(cid:176) C temperature coefficient. All digital inputs (CS, U/D, CLK) are protected with a series input resistor and parallel Zener ESD structure shown in The R temperature coefficient increases as the wiper is pro- BA Figure 36. grammed near the B-terminal due to the larger percentage con- tribution of the wiper contact switch resistance, which has a 0.5%/(cid:176) C temperature coefficient. Figure 14 shows the effect of 1kV LOGIC the wiper contact resistance as a function of code setting. An- other performance factor influenced by the switch contact resis- tance is the relative linearity error performance between the Figure 36.Equivalent ESD Protection Digital Pins 10 kW , and the 50 kW or 100 kW versions. The same switch contact resistance is used in all three versions. Thus the perfor- 20V mance of the 50 kW and 100 kW devices which have the least A, B, W impact on wiper switch resistance exhibits the best linearity GND error, see Figures 7 and 8. Figure 37.Equivalent ESD Protection Analog Pins –8– REV. A

AD5220 PROGRAMMING THE POTENTIOMETER DIVIDER APPLICATIONS INFORMATION Voltage Output Operation The negative-edge sensitive CLK pin does not contain any The digital potentiometer easily generates an output voltage internal debounce circuitry. This standard CMOS logic input proportional to the input voltage applied to a given terminal. responds to fast negative edges and needs to be debounced For example connecting A Terminal to +5 V and B Terminal to externally with an appropriate circuit designed for the type of ground produces an output voltage at the wiper which can be switch closure device being used. Good performance results at any value starting at zero volts up to 1 LSB less than +5 V. Each the CLK input pin when the negative logic transition has a LSB of voltage is equal to the voltage applied across terminals minimum slew rate of 1 V/m s. A wide variety of standard circuits AB divided by the 128-position resolution of the potentiometer can be used such as a one-shot multivibrator, Schmitt Triggered divider. The general equation defining the output voltage with gates, cross coupled flip-flops, or RC filters to drive the CLK respect to ground for any given input voltage applied to termi- pin with uniform negative edges. This will prevent the digital nals AB is: potentiometer from skipping output codes while counting due to V (D) = D/128 · V + V (1) switch contact bounce. W AB B D represents the current contents of the internal UP/DOWN counter. Operation of the digital potentiometer in the divider mode re- sults in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value, therefore, the drift improves to 20 ppm/(cid:176) C. REV. A –9–

AD5220 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 0.280 (7.11) 0.250 (6.35) 1 4 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRERERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 39. 8-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-8) Dimensions shown in inches and (millimeters) 5.00(0.1968) 3.20 4.80(0.1890) 3.00 2.80 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 3.20 8 5 54..1950 3.00 4.65 2.80 1 4 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° PIN1 0.25(0.0098) 1.35(0.0532) 8° IDENTIFIER 0.10(0.0040) 0° 0.65BSC COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) 00..9855 1.10MAX 15°MAX PLANE 0.17(0.0067) 0.75 0.80 COMPLIANTTOJEDECSTANDARDSMS-012-AA 0.15 0.40 6° 0.23 0.55 C(RINOEFNPFEATiRgRREuOENrNLeCLT 4EIHN0EOG. SN8DE-LLISYMe)AEaANNdRDS ESIOAtRaRNOnESUdNANaORDrdETE DSAINm-POMPaFRIlFLlO LOMPIMuIRLtELIlAiTInMTEeEER TPFSEaO;RcIRNkECUaQHgSUEeDI V[IINMSAOELDENIECNSS_TIIONGSN]NF S.OR 012407-A CO0P.0L50A.1N0ARICTOYMPLIANT0.T25OJEDECSTA0°NDARDS0M.0O9-187-AA 0.40 10-07-2009-B Narrow Body Figure 41. 8-Lead Mini Small Outline Package [MSOP] (R-8) (RM-8) Dimensions in millimeters and (inches) Dimensions shown in millimeters -10- REV. A

AD5220 ORDERING GUIDE Model1, 2, 3 R (kΩ) Temperature Range Package Description Package Option Branding AB AD5220BNZ10 10 −40°C to +85°C 8-Lead PDIP N-8 AD5220BNZ100 100 −40°C to +85°C 8-Lead PDIP N-8 AD5220BNZ50 50 −40°C to +85°C 8-Lead PDIP N-8 AD5220BR10 10 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BR10-REEL7 10 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BR100 100 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BR100-REEL 100 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BR100-REEL7 100 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRZ10 10 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRZ10-REEL 10 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRZ10-REEL7 10 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220WBRZ10-REEL7 10 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRZ100 100 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRZ100-REEL7 100 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRZ50 50 −40°C to +85°C 8-Lead SOIC_N R-8 AD5220BRM100 100 −40°C to +85°C 8-Lead MSOP RM-8 DQC AD5220BRM100-REEL7 100 −40°C to +85°C 8-Lead MSOP RM-8 DQC AD5220BRMZ10 10 −40°C to +85°C 8-Lead MSOP RM-8 D9H AD5220BRMZ10-REEL7 10 −40°C to +85°C 8-Lead MSOP RM-8 D9H AD5220BRMZ100 100 −40°C to +85°C 8-Lead MSOP RM-8 #DQC AD5220BRMZ100-R7 100 −40°C to +85°C 8-Lead MSOP RM-8 #DQC AD5220BRMZ50 50 −40°C to +85°C 8-Lead MSOP RM-8 #DQB AD5220BRMZ50-RL7 50 −40°C to +85°C 8-Lead MSOP RM-8 #DQB 1 Z = RoHS Compliant Part. 2 The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies. 3 W = Qualified for Automotive Products. AUTOMOTIVE PRODUCTS The AD5220W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. REVISION HISTORY 12/10—Rev. 0 to Rev. A Changes to Features Section ........................................................... 1 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 11 Added Automotive Products Section .......................................... 11 10/98—Revision 0: Initial Version ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03426-0-12/10(A) REV. A -11-