a 256-Position and 33-Position Digital Potentiometers AD5200/AD5201 FEATURES FUNCTIONAL BLOCK DIAGRAM AD5200—256-Position AD5201—33-Position AD5200/AD5201 10k(cid:1), 50k(cid:1) VDD VSS 3-Wire SPI-Compatible Serial Data Input A Single Supply 2.7V to 5.5V or CS W Dual Supply (cid:2)2.7V for AC or Bipolar Operations CLK RSEEGR B Internal Power-On Midscale Preset SDI Dx 8/6 RRDEAGC APPLICATIONS GND SHDN Mechanical Potentiometer Replacement PWR-ON Instrumentation: Gain, Offset Adjustment PRESET Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching GENERAL DESCRIPTION has a nominal temperature coefficient of 500ppm/°C. The VR The AD5200 and AD5201 are programmable resistor devices, has a VR latch that holds its programmed resistance value. The with 256 positions and 33 positions respectively, that can be digi- VR latch is updated from an SPI-compatible serial-to-parallel tally controlled through a 3-wire SPI serial interface. The terms shift register that is loaded from a standard 3-wire serial-input programmable resistor, variable resistor (VR), and RDAC are digital interface. Eight data bits for the AD5200 and six data commonly used interchangeably to refer to digital potentiometers. bits for the AD5201 make up the data word that is clocked into These devices perform the same electronic adjustment function the serial input register. The internal preset forces the wiper to as a potentiometer or variable resistor. Both AD5200/AD5201 the midscale position by loading 80 and 10 into AD5200 and H H contain a single variable resistor in the compact MSOP AD5201 VR latches respectively. The SHDN pin forces the package. Each device contains a fixed wiper resistance at the resistor to an end-to-end open-circuit condition on the A terminal wiper contact that taps the programmable resistance at a point and shorts the wiper to the B terminal, achieving a microwatt determined by a digital code. The code is loaded in the serial power shutdown state. When SHDN is returned to logic high, input register. The resistance between the wiper and either end the previous latch setting puts the wiper in the same resistance point of the programmable resistor varies linearly with respect to setting prior to shutdown. The digital interface is still active dur- the digital code transferred into the VR latch. Each variable ing shutdown so that code changes can be made that will produce resistor offers a completely programmable value of resistance, a new wiper position when the device is returned from shutdown. between the A terminal and the wiper, or the B terminal and the All parts are guaranteed to operate over the extended industrial wiper. The fixed A-to-B terminal resistance of 10kΩ or 50kΩ temperature range of –40°C to +85°C. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/461-3113 © Analog Devices, Inc., 2012

AD5200/AD5201–SPECIFICATIONS (V = 5V (cid:2) 10%, or 3V (cid:2) 10%, V = 0V, V = +V , V = 0V, AD5200 ELECTRICAL CHARACTERISTICS DD SS A DD B –40(cid:4)C < T < +85(cid:4)C unless otherwise noted.) A Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 R-DNL R , V = No Connect –1 ±0.25 +1 LSB WB A Resistor Integral Nonlinearity 2 R-INL R , V = No Connect –2 ±0.5 +2 LSB WB A Nominal Resistor Tolerance 3 ∆R T = 25°C –30 +30 % AB A Resistance Temperature Coefficient R /∆T V = V , Wiper = No Connect 500 ppm/°C AB AB DD Wiper Resistance R V = 5V 50 100 Ω W DD DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N 8 Bits Differential Nonlinearity 4 DNL –1 ±1/4 +1 LSB Integral Nonlinearity4 INL –2 ±1/2 +2 LSB Voltage Divider Temperature Coefficient ∆V /∆T Code = 80 5 ppm/°C W H Full-Scale Error V Code = FF –1.5 –0.5 0 LSB WFSE H Zero-Scale Error V Code = 00 0 +0.5 +1.5 LSB WZSE H RESISTOR TERMINALS Voltage Range5 V V V V A,B,W SS DD Capacitance6 A, B C f = 1 MHz, Measured to GND, Code = 80 45 pF A,B H Capacitance6 W C f = 1 MHz, Measured to GND, Code = 80 60 pF W H Shutdown Supply Current 7 I V = 5.5V 0.01 5 µA DD_SD DD Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V 2.4 V IH Input Logic Low V 0.8 V IL Input Logic High V V = 3V, V = 0V 2.1 V IH DD SS Input Logic Low V V = 3V, V = 0V 0.6 V IL DD SS Input Current I V = 0V or 5V ±1 µA IL IN Input Capacitance 6 C 5 pF IL POWER SUPPLIES Logic Supply V 2.7 5.5 V LOGIC Power Single-Supply Range V V = 0V –0.3 5.5 V DDRANGE SS Power Dual-Supply Range V ±2.3 ±2.7 V DD/SSRANGE Positive Supply Current I V = +5 V or V = 0V 15 40 µA DD IH IL Negative Supply Current I V = –5V 15 40 µA SS SS Power Dissipation8 P V = +5 V or V = 0V, V = +5V, V = 0V 0.2 mW DISS IH IL DD SS Power Supply Sensitivity PSS ∆V = +5 V ± 10%, Code = Midscale –0.01 0.001 +0.01 %/% DD DYNAMIC CHARACTERISTICS 6, 9 Bandwidth –3 dB BW_10kΩ R = 10kΩ, Code = 80 600 kHz AB H BW_50kΩ R = 50kΩ, Code = 80 100 kHz AB H Total Harmonic Distortion THD V = 1 V rms, V = 0V, f = 1 kHz, R = 10kΩ 0.003 % W A B AB V Settling Time (10 kΩ/50kΩ) t V = 5V, V = 0V, ± 1 LSB Error Band 2/9 µs W S A B Resistor Noise Voltage Density e R = 5kΩ, RS = 0 9 nV√Hz N_WB WB NOTES 1Typicals represent average readings at 25°C and V = 5V, V = 0V. DD SS 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I = V /R for both V = +2.7 V, W DD DD V = –2.7 V. SS 3V = V , Wiper (V ) = No connect. AB DD W 4INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V and V = 0V. DNL W A DD B specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. 5Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 6Guaranteed by design and not subject to production test. 7Measured at the A terminal. A terminal is open-circuited in shutdown mode. 8P is calculated from (I × V ). CMOS logic level inputs result in minimum power dissipation. DISS DD DD 9All dynamic characteristics use V = 5V, V = 0V. DD SS Specifications subject to change without notice. –2– REV. D

AD5200/AD5201 (V = 5V (cid:2) 10%, or 3V (cid:2) 10%, V = 0V, V = +V , V = 0V, AD5201 ELECTRICAL CHARACTERISTICS DD SS A DD B –40(cid:4)C < T < +85(cid:4)C unless otherwise noted.) A Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 R-DNL R , V = No Connect –0.5 ±0.05 +0.5 LSB WB A Resistor Integral Nonlinearity 2 R-INL R , V = No Connect –1 ±0.1 +1 LSB WB A Nominal Resistor Tolerance 3 ∆R T = 25°C –30 +30 % AB A Resistance Temperature Coefficient R /∆T V = V , Wiper = No Connect 500 ppm/°C AB AB DD Wiper Resistance R V = 5V 50 100 Ω W DD DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution4 N 6 Bits Differential Nonlinearity 5 DNL –0.5 ±0.01 +0.5 LSB Integral Nonlinearity5 INL –1 ±0.02 +1 LSB Voltage Divider Temperature Coefficient ∆V /∆T Code = 10 5 ppm/°C W H Full-Scale Error V Code = 20 –1/2 –1/4 0 LSB WFSE H Zero-Scale Error V Code = 00 0 +1/4 +1/2 LSB WZSE H RESISTOR TERMINALS Voltage Range6 V V V V A,B,W SS DD Capacitance7 A, B C f = 1 MHz, Measured to GND, Code = 10 45 pF A,B H Capacitance7 W C f = 1 MHz, Measured to GND, Code = 10 60 pF W H Shutdown Supply Current 8 I V = 5.5V 0.01 5 µA DD_SD DD Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V 2.4 V IH Input Logic Low V 0.8 V IL Input Logic High V V = 3V, V = 0V 2.1 V IH DD SS Input Logic Low V V = 3V, V = 0V 0.6 V IL DD SS Input Current I V = 0V or 5V ±1 µA IL IN Input Capacitance 7 C 5 pF IL POWER SUPPLIES Logic Supply V 2.7 5.5 V LOGIC Power Single-Supply Range V V = 0V –0.3 5.5 V DDRANGE SS Power Dual-Supply Range V ±2.3 ±2.7 V DD/SSRANGE Positive Supply Current I V = +5V or V = 0V 15 40 µA DD IH IL Negative Supply Current I V = –5V 15 40 µA SS SS Power Dissipation9 P V = +5V or V = 0V, V = +5V, V = –5V 0.2 mW DISS IH IL DD SS Power Supply Sensitivity PSS ∆V = +5V ± 10% –0.01 0.001 +0.01 %/% DD DYNAMIC CHARACTERISTICS 7, 10 Bandwidth –3 dB BW_10kΩ R = 10kΩ, Code = 10 600 kHz AB H BW_50kΩ R = 50kΩ, Code = 10 100 kHz AB H Total Harmonic Distortion THD V = 1 V rms, V = 0V, f = 1 kHz, R = 10kΩ 0.003 % W A B AB V Settling Time (10 kΩ/50kΩ) t V = 5V, V = 0V, ± 1 LSB Error Band 2/9 µs W S A B Resistor Noise Voltage Density e R = 5kΩ, RS = 0 9 nV√Hz N_WB WB NOTES 1Typicals represent average readings at 25°C and V = 5V, V = 0V. DD SS 2Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi- tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I = V /R for both V = +2.7 V, W DD DD V = –2.7 V. SS 3V = V , Wiper (V ) = No connect. AB DD W 4Six bits are needed for 33 positions even though it is not a 64-position device. 5INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V = V and V = 0V. DNL W A DD B specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. 6Resistor Terminals A, B, W have no limitations on polarity with respect to each other. 7Guaranteed by design and not subject to production test. 8Measured at the A terminal. A terminal is open-circuited in shutdown mode. 9P is calculated from (I × V ). CMOS logic level inputs result in minimum power dissipation. DISS DD DD 10All dynamic characteristics use V = 5V, V = 0V. DD SS Specifications subject to change without notice. REV. D –3–

AD5200/AD5201–SPECIFICATIONS (V = 5V (cid:2) 10%, or 3V (cid:2) 10%, V = 0V, V = +V , V = 0V, –40(cid:4)C < T < +85(cid:4)C ELECTRICAL CHARACTERISTICS DD SS A DD B A unless otherwise noted.) Parameter Symbol Conditions Min Typ1 Max Unit INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 2, 3]) Input Clock Pulsewidth t , t Clock Level High or Low 20 ns CH CL Data Setup Time t 5 ns DS Data Hold Time t 5 ns DH CS Setup Time t 15 ns CSS CS High Pulsewidth t 40 ns CSW CLK Fall to CS Fall Hold Time t 0 ns CSH0 CLK Fall to CS Rise Hold Time t 0 ns CSH1 CS Rise to Clock Rise Setup t 10 ns CS1 NOTES 1Typicals represent average readings at 25°C and V = 5V, V = 0V. DD SS 2Guaranteed by design and not subject to production test. 3See timing diagram for location of measured values. All input control voltages are specified with t = t = 2 ns (10% to 90% of 3V) and timed from a voltage level of R F 1.5V. Switching characteristics are measured using V = 5 V. LOGIC Specifications subject to change without notice. 1 SDI D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 CS DAC REGISTER LOAD 0 1 VOUT 0 Figure 1a. AD5200 Timing Diagram 1 SDI D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 DAC REGISTER LOAD CS 0 1 VOUT 0 Figure 1b.AD5201 Timing Diagram 1 (DATAS IND)I Dx Dx 0 t 1 tCH DS tDH tCS1 CLK 0 tCSH0 tCL CS 1 tCSS tCSH1 tCSW 0 t S VDD VOUT 0 (cid:5)1LSB Figure 1c.Detail Timing Diagram –4–

AD5200/AD5201 ABSOLUTE MAXIMUM RATINGS1 PIN FUNCTION DESCRIPTIONS (TA = 25°C, unless otherwise noted) Pin Name Description V to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V DD SS V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +7 V 1 B B Terminal. DD V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V, –7 V 2 V Negative Power Supply, specified for opera- SS SS V , V , V to GND . . . . . . . . . . . . . . . . . . . . . . . . . V , V tion from 0V to –2.7 V. A B W SS DD IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA2 3 GND Ground. Digital Inputs and Output Voltage to GND . . . . . . . 0V, 7 V 4 CS Chip Select Input, Active Low. When CS Operating Temperature Range . . . . . . . . . . . –40°C to +85°C returns high, data will be loaded into the Maximum Junction Temperature (T Max) . . . . . . . . . 150°C J DAC register. Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C 5 SDI Serial Data Input. Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C Thermal Resistance θ MSOP . . . . . . . . . . . . . 200°C/W 6 CLK Serial Clock Input, positive edge triggered. JA, Package Power Dissipation = (T Max – T )/θ 7 SHDN Active Low Input. Terminal A open circuit. J A JA Shutdown controls Variable Resistors of NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- RDAC to temporary infinite. nent damage to the device. This is a stress rating; functional operation of the device 8 V Positive Power Supply (Sum of V + V DD DD SS at these or any other conditions above those listed in the operational sections of this ≤ 5.5V). specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9 W Wiper Terminal. 2Max current is bounded by the maximum current handling of the switches, 10 A A Terminal. maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. Please refer to TPC 31 and TPC 32 for detail. PIN CONFIGURATION B 1 10 A VSS 2 AD5200/ 9 W GND 3 AD5201 8 VDD CS 4 TOP VIEW 7 SHDN (Not to Scale) SDI 5 6 CLK CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD5200/AD5201 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. D –5–

AD5200/AD5201–Typical Performance Characteristics 0.20 0.12 VDD = 2.7V, VSS = 0V 0.15 0.10 VDD = 5.5V, VSS = 0V 0.10 0.08 RDNL – LSB(cid:6)000...000055 RINL – LSB00..0046 VVDSSD == –+22..77VV (cid:6)0.10 0.02 VDD = +2.7V, VSS = –2.7V VDD = 2.7V, VSS = 0V (cid:6)0.15 0.00 VDD = 5.5V, VSS = 0V (cid:6)0.20 –0.02 0 32 64 96 128 160 192 224 256 0 4 8 12 16 20 24 28 32 CODE – Decimal CODE – Decimal TPC 1. AD5200 10 kΩ RDNL vs. Code TPC 4. AD5201 10 kΩ RINL vs. Code 0.03 0.10 VDD = 2.7V, VSS = 0V VDD = 5.5V, VSS = 0V 0.05 0.02 VDD = 2.7V, VSS = 0V 0.00 0.01 RDNL – LSB 0.00 DNL – LSB–––000...110505 –0.01 –0.20 VDD = +2.7V, VSS = –2.7V –0.02 VDD = 5.5V, VSS = 0V –0.25 VDD = +2.7V, VSS = –2.7V –0.03 –0.30 0 4 8 12 16 20 24 28 32 0 32 64 96 128 160 192 224 256 CODE – Decimal CODE – Decimal TPC 2. AD5201 10 kΩ RDNL vs. Code TPC 5. AD5200 10 kΩ DNL vs. Code 0.7 0.020 0.6 VDD = 2.7V, VSS = 0V 0.015 0.5 0.010 VDD = 5.5V, VSS = 0V 0.4 SB SB VDD = +2.7V, VSS = –2.7V L L L – 0.3 L – 0.005 N N RI VDD = 5.5V, VSS = 0V D 0.2 0.000 0.1 –0.005 0.0 –0.1 VDD = +2.7V, VSS = –2.7V –0.010 VDD = 2.7V, VSS = 0V 0 32 64 96 128 160 192 224 256 0 4 8 12 16 20 24 28 32 CODE – Decimal CODE – Decimal TPC 3. AD5200 10 kΩ RINL vs. Code TPC 6. AD5201 10 kΩ DNL vs. Code –6– REV. D

AD5200/AD5201 0.3 20 VIL = VSS 0.2 18 VIH = VDD VDD = 5.5V, VSS = 0V 16 VDD = 5.5V 0.1 (cid:7)A – 14 T 0.0 N B RE 12 INL – LS ––00..21 PPLY CUR 108 VDD = 2.7V U S 6 –0.3 DD I 4 VDD = +2.7V, VSS = –2.7V –0.4 2 VDD = 2.7V, VSS = 0V –0.5 0 0 32 64 96 128 160 192 224 256 –40 –20 0 20 40 60 80 100 CODE – Decimal TEMPERATURE – (cid:4)C TPC 7. AD5200 10 kΩ INL vs. Code TPC 10. Supply Current vs. Temperature 0.020 14 VDD = +2.7V, VSS = –2.7V VDD = 5.5V 12 0.015 A VDD = 5.5V, VSS = 0V – n 10 T 0.010 N E 8 NL – LSB0.005 WN CURR 6 I O D 4 0.000 UT H S 2 A I –0.005 0 –0.010 VDD = 2.7V, VSS = 0V –2 0 4 8 12 16 20 24 28 32 –40 –20 0 20 40 60 80 100 CODE – Decimal TEMPERATURE – (cid:4)C TPC 8. AD5201 10 kΩ INL vs. Code TPC 11. Shutdown Current vs. Temperature 10 160 SEE TEST CIRCUIT 13 IDD @ VDD/VSS = 5V/0V TA = 25(cid:4)C 140 1.0 120 IDD @ VDD/VSS = (cid:2)2.5V 100 VDD = 2.7V A m (cid:1) /I – DSS 0.1 R– ON 80 D I ISS @ VDD/VSS = (cid:2)2.5V 60 VDD = 5.5V 0.01 40 IDD @ VDD/VSS = 3V/0V 20 0.001 0 0.0 1.0 2.0 3.0 4.0 5.0 0 1 2 3 4 5 6 VIH – V VSUPPLY – V TPC 9. Supply Current vs. Logic Input Voltage TPC 12. Wiper ON Resistance vs. VSUPPLY REV. D –7–

AD5200/AD5201 500 6 CODE FFH 450 0 80H 400 –6 40H 350 –12 20H (cid:7)I/I– ADDSS 322050000 IDD @IS VSD @D/ VVSDSD / V=S (cid:2)S 2 =.5 (cid:2)V2.5V GAIN – dB –––321048 100084HHH 150 –36 100 IDD @ VDD/VSS = 5V/0V –42 0021HH 50 IDD @ VDD/VSS = 3V/0V –48 010k 100k 1M 10M –541k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 13.AD5200 10 kΩ Supply Current vs. Clock Frequency TPC 16. AD5200 10 kΩ Gain vs. Frequency vs. Code 500 6 CODE 55H 450 0 400 –6 80H 350 –12 40H (cid:7)I/I– ADDSS 322050000 IIDSSD @@ VVDDDD//VVSSSS == (cid:2)(cid:2)22..55VV GAIN – dB –––321048 210008HHH 04H 150 –36 IDD @ VDD/VSS = 5V/0V 02H 100 –42 IDD @ VDD/VSS = 3V/0V 01H 50 –48 0 –54 10k 100k 1M 10M 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 14.AD5200 10 kΩ Supply Current vs. Clock Frequency TPC 17. AD5200 50 kΩ Gain vs. Frequency vs. Code 80 6 CODE = 80H, VA = VDD, VB = 0V 0 +PSRR @ VDD = 5V DC (cid:2)10% p-p AC –6 10H 60 8H –12 dB B –18 4H PSRR– 40 +PSRR @ VDD = 3V DC (cid:2)10% p-p AC GAIN – d ––3204 21HH –36 20 –PSRR @ VDD = 3V DC (cid:2)10% p-p AC –42 –48 0 –54 100 1k 10k 100k 1M 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 15. Power Supply Rejection Ratio vs. Frequency TPC 18. AD5201 10 kΩ Gain vs. Frequency vs. Code –8–

AD5200/AD5201 6 12 SEE TEST CIRCUIT 10 0 DIV 6 CODE = 80H 10H B/ VDD = 5V –1–26 8H S – 0.1d –60 TA = 25(cid:4)C 10k(cid:1) B –18 4H NES –12 50k(cid:1) GAIN – d ––3204 21HH AIN FLAT ––2148 G D –36 E –30 Z LI –42 MA –36 R –48 NO –42 –54 –48 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 19. AD5201 50 kΩ Gain vs. Frequency vs. Code TPC 22. Normalized Gain Flatness vs. Frequency 12 12 SEE TEST CIRCUIT 10 6 DIV 6 CODE = 10H 10k(cid:1) B/ VDD = 5V 0 1d 0 TA = 25(cid:4)C 0. –6 50k(cid:1) SS – –6 10k(cid:1) N – dB ––1182 FLATNE ––1182 50k(cid:1) AI N G –24 AI –24 G D –30 E –30 VIN = 100mV rms LIZ –36 VDD = 5V MA –36 –42 RL = 1M(cid:1) NOR –42 –48 –48 1k 10k 100k 1M 10 100 1k 10k 100k 1M FREQUENCY – Hz FREQUENCY – Hz TPC 20. AD5200 –3 dB Bandwidth TPC 23. AD5201 Normalized Gain Flatness vs. Frequency 12 6 10k(cid:1) 0 –6 50k(cid:1) B –12 VW d (20mV/DIV) – N –18 AI G –24 –30 VIN = 100mV rms CS –36 VDD = 5V (5V/DIV) RL = 1M(cid:1) –42 –48 1k 10k 100k 1M FREQUENCY – Hz TPC 21. AD5201 –3 dB Bandwidth TPC 24. One Position Step Change at Half Scale –9–

AD5200/AD5201 3500 C3000 (cid:4)m/ pp2500 – O(2UVT/DPUIVT) PCO 2000 M E E T1500 D O M1000 INPUT T (5V/DIV) A T OS 500 E H R 0 (cid:6)500 0 32 64 96 128 160 192 224 256 CODE – Decimal TPC 25. Large Signal Settling Time TPC 28. AD5200 ∆R /∆T Rheostat Mode Temperature WB Coefficient 3000 C (cid:4)m/2500 p p – CO 2000 P M E V(2O0UmTV/DIV) DE T1500 O R M1000 TE E M 500 O TI N TE 0 O P –500 0 4 8 12 16 20 24 28 32 CODE – Decimal TPC 26.Digital Feedthrough vs. Time TPC 29. AD5201 Potentiometer Mode Temperature Coefficient 4000 C 50 (cid:4)m/3500 C O – pp3000 (cid:4)ppm/ 40 MPC2500 CO – 30 E TE2000 EMP MOD1500 DE T 20 R O E M OMET1000 ETER 10 NTI 500 OM 0 POTE 0 TENTI–10 O (cid:6)500 P 0 32 64 96 128 160 192 224 256 CODE – Decimal –20 0 4 8 12 16 20 24 28 32 CODE – Decimal TPC 27. AD5200 ∆V /∆T Potentiometer Mode TPC 30. AD5201 ∆V /∆T Potentiometer Mode Tempco WB WB Temperature Coefficient –10–

AD5200/AD5201 100.0 Table I. AD5200 Serial-Data Word Format B7 B6 B5 B4 B3 B2 B1 B0 A m D7 D6 D5 D4 D3 D2 D1 D0 – 10.0 X MA MSB LSB L I A C 27 20 ETI RAB = 10k(cid:1) R O 1.0 E H T Table II. AD5201 Serial-Data Word Format RAB = 50k(cid:1) B5* B4 B3 B2 B1 B0 0.1 0 32 64 96 128 160 192 224 256 D5* D4 D3 D2 D1 D0 CODE – Decimal TPC 31. AD5200 I vs. Code MSB LSB MAX 25 20 100.0 *Six data bits are needed for 33 positions. PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation A m The nominal resistance of the RDAC between Terminals A and – 10.0 X B are available with values of 10kΩ and 50kΩ. The final two A M L I digits of the part number determine the nominal resistance TICA RAB = 10k(cid:1) value, e.g., 10kΩ = 10 and 50kΩ = 50. The nominal resistance E (R ) of AD5200 has 256 contact points accessed by the wiper R AB EO 1.0 terminal. The 8-bit data word in the RDAC latch of AD5200 is H T RAB = 50k(cid:1) decoded to select one of the 256 possible settings. In both parts, the wiper’s first connection starts at the B terminal for data 00 . H This B-terminal connection has a wiper contact resistance of 0.10 4 8 12 16 20 24 28 32 r5e0siΩst aansc leo.n Fgo ars av a1l0idk VΩD pDa/Vrt,S St hise aspepcolinedd, croengnaredclteiossn ooff tAheD n5o2m00in iasl CODE – Decimal the first tap point with 89Ω [R = R /255 + R = 39Ω + 50Ω] WB AB W TPC 32. AD5201 I vs. Code MAX for data 01 . The third connection is the next tap point representing H 78 + 50 = 128Ω for data 02 . Due to its unique internal structure, H OPERATION AD5201 has 5-bit + 1 resolution, but needs a 6-bit data word to The AD5200/AD5201 provide 255 and 33 positions digitally- achieve the full 33 steps resolution. The 6-bit data word in the controlled variable resistor (VR) devices. Changing the RDAC latch is decoded to select one of the 33 possible settings. programmed VR settings is accomplished by clocking in an 8-bit Data 34 to 63 will automatically be equal to Position 33. The serial data word for AD5200, and a 6-bit serial data word for wiper 00 connection of AD5201 gives 50Ω. Similarly, for a AD5201, into the SDI (Serial Data Input) pins. Table I provides 10kΩ paHrt, the first tap point of AD5201 yields 363Ω for the serial register data word format. The AD5200/AD5201 are data 01 , 675Ω for data 02 . For both AD5200 and AD5201, preset to a midscale internally during power-on condition. In H H each LSB data value increase moves the wiper up the resistor addition, the AD5200/AD5201 contain power shutdown ladder until the last tap point is reached. Figures 2a and 2b show SHDN pins that place the RDAC in a zero power consump- the simplified diagrams of the equivalent RDAC circuits. tion state where the immediate switches next to Terminals A and B are open-circuited. Meanwhile, the wiper W is connected to B terminal, resulting in only leakage current consumption in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. When the part is returned from shutdown, the stored VR setting will be applied to the RDAC. –11–

AD5200/AD5201 A Note D in AD5200 is between 0 to 255 for 256 positions. On the other hand, D in AD5201 is between 0 to 32 so that 33 SHDN SWSHDN positions can be achieved due to the slight internal structure difference, Figure 2b. DD76 SW2N(cid:6)1 Again if R = 10kΩ and Aterminal can be opened or tied to D5 AB D4 W, the following output resistance between W to B will be set D3 R SW2N(cid:6)2 for the following RDAC latch codes: D2 D1 D0 AD5200 Wiper-to-B Resistance W R SW1 D R RDAC R SW0 R 2RNA–B1 (DEC) ((cid:1)W)B Output State LATCH & DECODER 255 10050 Full-Scale (R + R ) AB W 128 5070 Midscale B DIGITAL CIRCUITRY OMITTED FOR CLARITY 1 89 1 LSB Figure 2a.AD5200 Equivalent RDAC Circuit. 255 positions 0 50 Zero-Scale (Wiper Contact Resistance) can be achieved up to Switch SW N . 2 –1 AD5201 Wiper-to-B Resistance A SHDN SWSHDN D RWB (DEC) ((cid:1)) Output State SW2N 32 10050 Full-Scale (R + R ) AB W D5 R SW2N(cid:6)1 116 3560350 1M LidSsBcale D4 D3 0 50 Zero-Scale (Wiper Contact Resistance) DD21 R SW2N(cid:6)2 D0 Note that in the zero-scale condition a finite wiper resistance of 50Ω is present. Care should be taken to limit the current flow W R SW1 between W and B in this state to no more than ±20 mA to avoid degradation or possible destruction of the internal switch contact. LARTDCAHC & R SW0 R R2ANB Like the mechanical potentiometer the RDAC replaces, it is DECODER totally symmetrical. The resistance between the wiper W and B DIGITAL CIRCUITRY Terminal A also produces a digitally controlled resistance R . OMITTED FOR CLARITY WA When these terminals are used, the Bterminal should be tied to Figure 2b.AD5201 Equivalent RDAC Circuit. Unlike AD5200, the wiper. Setting the resistance value for R starts at a maxi- 33 positions can be achieved all the way to Switch SW N. WA 2 mum value of resistance and decreases as the data loaded in The general equation determining the digitally programmed the latch is increased in value. The general equation for this output resistance between W and B is: operation is: ( ) R WB(D)= 2D55RAB +50Ω for AD5200 (1) R WA(D)= 25255−5D RAB +50Ω for AD5200 (3) ( ) D R D = R +50Ω for AD5201 (2) WB 32 AB ( ) (32−D) where: R D = R +50Ω for AD5201 (4) WA AB 32 D is the decimal equivalent of the data contained in RDAC latch. Similarly, D in AD5200 is between 0 to 255, whereas D in AD5201 is between 0 to 32. R is the nominal end-to-end resistance. AB For R = 10kΩ and B terminal is opened or tied to the wiper R is the wiper resistance contributed by the on-resistance AB W W, the following output resistance between W and A will be set of the internal switch. for the following RDAC latch codes: –12–

AD5200/AD5201 AD5200 Wiper-to-A Resistance Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output D R WA voltage is dependent on the ratio of the internal resistors and not (DEC) ((cid:1)) Output State the absolute values; therefore, the drift reduces to 15ppm/°C. 255 50 Full-Scale (R ) W 128 5030 Midscale DIGITAL INTERFACING 1 10011 1 LSB The AD5200/AD5201 contain a standard three-wire serial input 0 10050 Zero-Scale (R + R ) control interface. The three inputs are clock (CLK), CS, and AB W serial data input (SDI). The positive-edge-sensitive CLK input requires clean transitions to avoid clocking incorrect data into AD5201 Wiper-to-A Resistance the serial input register. Standard logic families work well. If D R mechanical switches are used for product evaluation, they WA (DEC) ((cid:1)) Output State should be debounced by a flip-flop or other suitable means. Figure 3 shows more detail of the internal digital circuitry. When 32 50 Full-Scale (RW) CS is low, the clock loads data into the serial register on each 16 5050 Midscale positive clock edge (see Table III). 1 9738 1 LSB 0 10050 Zero-Scale (R + R ) AB W VDD AD5200/AD5201 VSS The tolerance of the nominal resistance can be ±30% due to A process lot dependance. If users apply the RDAC in rheostat CS W (variable resistance) mode, they should be aware of such specifi- CLK SER B cation of tolerance. The change in R with temperature has a REG 8/6 RDAC AB SDI Dx REG 500ppm/°C temperature coefficient. GND SHDN PWR-ON PRESET PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation Figure 3. Block Diagram The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input volt- Table III. Input Logic Control Truth Table age at A to B. CLK CS SHDN Register Activity Unlike the polarity of V – V , which must be positive, volt- DD SS age across A–B, W–A, and W–B can be at either polarity. L L H No SR effect. P L H Shift one bit in from the SDI pin. If ignoring the effects of the wiper resistance for an approxima- X P H Load SR data into RDAC latch. tion, connecting A terminal to 5V and B terminal to ground X H H No operation. produces an output voltage at the wiper which can be any value X H L Open circuit on A terminal and short starting at almost zero to almost full scale with the minor devia- circuit between W to B terminals. tion contributed by the wiper resistance. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the NOTE 2N-1 and 2N position resolution of the potentiometer divider for P = positive edge, X = don’t care, SR = shift register. AD5200 and AD5201 respectively. The general equation defin- All digital inputs are protected with a series input resistor and ing the output voltage with respect to ground for any valid input parallel Zener ESD structure shown in Figure 4. Applies to voltage applied to Terminals A and B is: digital input pins CS, SDI, SHDN, CLK. ( ) D V D = V + V for AD5200 (5) 340(cid:1) W 255 AB B LOGIC ( ) D V D = V + V for AD5201 (6) VSS W 32 AB B Figure 4.ESD Protection of Digital Pins where D in AD5200 is between 0 to 255 and D in AD5201 is between 0 to 32. A,B,W For more accurate calculation, including the effects of wiper resistance, V can be found as: W VSS ( ) ( ) ( ) R D R D Figure 5.ESD Protection of Resistor Terminals V D = WB V + WA V (7) W A B R R AB AB where R (D) and R (D) can be obtained from Equations WB WA 1 to 4. –13–

AD5200/AD5201 TEST CIRCUITS Figures 6 to 14 define the test conditions used in the product 5V specification table. OP279 VOUT DUT V+ = VDD VIN W 1 LSB = V+/2N A V+ W OFFSET GND A DUT B B VMS OFFSET BIAS Figure 6.Potentiometer Divider Nonlinearity Error Test Figure 11.Noninverting Gain Test Circuit Circuit (INL, DNL) NO CONNECT DUT A +15V A IW W W VIN OFFSET B OP42 VOUT B GND VMS 2.5V –15V Figure 7.Resistor Position Nonlinearity Error Figure 12.Gain vs. Frequency Test Circuit (Rheostat Operation; R-INL, R-DNL) 0.1V DUT RSW = ISW VMS2 ADUWT VW IW = VDD/RNOMINAL BW ISWCODE = OOH +0.1V – B VMS1 VSS TO VDD RW = [VMS1 – VMS2]/IW Figure 8.Wiper Resistance Test Circuit Figure 13.Incremental ON Resistance Test Circuit NC VA V+ VDD ABW VMS VPP+SS SR= R(V% D(d/D%B (cid:2))) =1=0 2%0(cid:8) LVOMGS%(cid:8)(cid:8)VVMDDS VVDSDUSDT GND ABW VICCMM (cid:8)VDD% NC NC = NO CONNECT Figure 9.Power Supply Sensitivity Test Circuit Figure 14. Common-Mode Leakage Current Test Circuit (PSS, PSRR) A DUT B 5V W OFFSETVIN OP279 VOUT GND OFFSET BIAS Figure 10.Inverting Gain Test Circuit –14–

AD5200/AD5201 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 15. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Temperature Package Full Reel Branding Model1 RES kΩ Range Package Description Option Qty. Information AD5200BRMZ10 256 10 −40°C to +85°C 10-Lead MSOP RM-10 50 DLA AD5200BRMZ10-REEL7 256 10 −40°C to +85°C 10-Lead MSOP RM-10 1,000 DLA AD5200BRMZ50 256 50 −40°C to +85°C 10-Lead MSOP RM-10 50 D8T AD5200BRMZ50-REEL7 256 50 −40°C to +85°C 10-Lead MSOP RM-10 1,000 D8T AD5201BRMZ10 33 10 −40°C to +85°C 10-Lead MSOP RM-10 50 DMA AD5201BRMZ10-REEL7 33 10 −40°C to +85°C 10-Lead MSOP RM-10 1,000 DMA AD5201BRMZ50 33 50 −40°C to +85°C 10-Lead MSOP RM-10 50 DMB AD5201BRMZ50-REEL7 33 50 −40°C to +85°C 10-Lead MSOP RM-10 1,000 DMB 1 Z = RoHS Compliant Part. REVISION HISTORY 12/12—Rev. C to Rev. D Changes to Ordering Guide ........................................................... 15 6/12—Rev. B to Rev. C Removed Digital Potentiometer Selection Guide ....................... 15 Updated Outline Dimensions ........................................................ 15 Changes to Ordering Guide ........................................................... 15 8/01—Rev. A to Rev. B Edits to ORDERING GUIDE .......................................................... 5 2/01—Rev. 0 to Rev. A Edits to ORDERING GUIDE .......................................................... 5 Edits to ABSOLUTE MAXIMUM RATINGS ............................... 5 TPCs 31 and 32 added .................................................................... 11 ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02188-0-12/12(D) REV. D –15–