64-Position OTP Digital Potentiometer AD5171 FEATURES FUNCTIONAL BLOCK DIAGRAM 64 position SCL A One-time programmable (OTP) set-and-forget resistance SDA I2C INTERFACE setting—low cost alternative over EEMEM AND CONTROL LOGIC Unlimited adjustments prior to OTP activation W 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end resistance Low temperature coefficient: 5 ppm/°C in potentiometer mode AD0 B Low temperature coefficient: 35 ppm/°C in rheostat mode Compact standard 8-lead SOT-23 package WIPER Low power: I = 10 μA maximum VDD REGISTER DD Fast settling time: tS = 5 μs typical in power-up GND FUSE IC2oCm-copmutpear tsiobfltew daigreit rael pinlatceerfsa mceic rocontroller in factory LINK AD5171 03437-001 Figure 1. programming applications Full read/write of wiper register W 1 8 A Extra I2C device address pin VDD 2 AD5171 7 B Low operating voltage: 2.7 V to 5.5 V TOP VIEW GND 3 (Not to Scale) 6 AD0 OAuTtPo vmaolitdiavtei otenm chpeecrakt fuurnec rtaionng e: −40°C to +125°C SCL 4 5 SDA03437-002 Figure 2. Pin Configuration APPLICATIONS When this permanent setting is achieved, the value does not change regardless of supply variations or environmental stresses System calibrations under normal operating conditions. To verify the success of Electronics level settings permanent programming, Analog Devices, Inc., patterned the Mechanical trimmers and potentiometer replacements OTP validation such that the fuse status can be discerned from Automotive electronics adjustments two validation bits in read mode. Gain control and offset adjustments Transducer circuit adjustments For applications that program the AD5171 in factories, Analog Programmable filters up to 1.5 MHz BW1 Devices offers device programming software that operates across Windows® 95 to XP platforms, including Windows NT. This software application effectively replaces the need for external GENERAL DESCRIPTION I2C controllers or host processors and, therefore, significantly The AD5171 is a 64-position, one-time programmable (OTP) reduces the development time of the users. digital potentiometer2 that uses fuse link technology to achieve An AD5171 evaluation kit includes the software, connector, and the memory retention of the resistance setting function. OTP is cable that can be converted for factory programming applications. a cost-effective alternative over the EEMEM approach for users who do not need to reprogram new memory settings in the The AD5171 is available in a compact 8-lead SOT-23 package. digital potentiometer. This device performs the same electronic All parts are guaranteed to operate over the automotive temper- adjustment function as most mechanical trimmers and variable ature range of −40°C to +125°C. Besides its unique OTP feature, resistors. The AD5171 is programmed using a 2-wire, I2C®- the AD5171 lends itself well to other general-purpose digital compatible digital control. It allows unlimited adjustments potentiometer applications due to its temperature performance, before permanently setting the resistance value. During the small form factor, and low cost. OTP activation, a permanent fuse blown command is sent after the final value is determined, freezing the wiper position at a given setting (analogous to placing epoxy on a mechanical trimmer). 1 Applies to 5 kΩ parts only. 2 The terms digital potentiometer and RDAC are used interchangeably. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved.

AD5171 TABLE OF CONTENTS Features .............................................................................................. 1  Power-Up/Power-Down Sequences ......................................... 15  Applications ....................................................................................... 1  Controlling the AD5171 ................................................................ 16  General Description ......................................................................... 1  Software Programming ............................................................. 16  Functional Block Diagram .............................................................. 1  Device Programming ................................................................. 16  Revision History ............................................................................... 2  I2C Controller Programming .................................................... 17  Specifications ..................................................................................... 3  I2C-Compatible 2-Wire Serial Bus ........................................... 17  Electrical Characteristics: 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ .. 3  Controlling Two Devices on One Bus ..................................... 18  Timing Characteristics: 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ ...... 5  Applications Information .............................................................. 19  Absolute Maximum Ratings ............................................................ 6  DAC .............................................................................................. 19  ESD Caution .................................................................................. 6  Gain Control Compensation .................................................... 19  Pin Configuration and Function Descriptions ............................. 7  Programmable Voltage Source with Boosted Output ........... 19  Typical Performance Characteristics ............................................. 8  Level Shifting for Different Voltage Operation ...................... 19  Theory of Operation ...................................................................... 12  Resistance Scaling ...................................................................... 19  One-Time Programming (OTP) .............................................. 12  Resolution Enhancement .......................................................... 20  Variable Resistance and Voltage for Rheostat Mode ............. 13  RDAC Circuit Simulation Model ............................................. 20  Variable Resistance and Voltage for Potentiometer Mode .... 13  Evaluation Board ............................................................................ 21  Power Supply Considerations ................................................... 14  Outline Dimensions ....................................................................... 22  ESD Protection ........................................................................... 14  Ordering Guide .......................................................................... 22  Terminal Voltage Operating Range .......................................... 15  REVISION HISTORY 7/08—Rev. C to Rev. D Changes to Power Supplies Parameter in Table 1.........................3 1/05—Rev. A to Rev. B Updated Fuse Blow Condition to 400 ms Throughout ...............5 Change to Features ............................................................................ 1 1/08—Rev. B to Rev. C Changes to Electrical Characteristics ............................................. 3 Updated Format .................................................................. Universal Change to Table 3 .............................................................................. 6 Deleted Note 1; Renumbered Sequentially ................................... 1 Changes to Power Supply Considerations Section .................... 13 Changes to Table 1 ............................................................................ 3 Changes to Level Shifting for Different Voltage Operation Changes to Table 2 ............................................................................ 5 Section .............................................................................................. 19 Changes to Table 3 ............................................................................ 6 Added Note to Ordering Guide .................................................... 22 Changes to Table 4 ............................................................................ 7 11/04—Rev. 0 to Rev. A Changes to Figure 13 to Figure 16 .................................................. 9 Changes to Specifications ................................................................. 3 Changes to Figure 17 and Figure 18 ............................................. 10 Changes to Table 3 ............................................................................. 7 Inserted Figure 24 ........................................................................... 11 Changes to One-Time Programming Section ............................ 11 Changes to One-Time Programming (OTP) Section and Power Changes to Power Supply Consideration Section ...................... 11 Supply Considerations Section ..................................................... 12 Changes to Figure 26 and Figure 27............................................. 12 Deleted Figure 25 and Figure 26 ................................................... 13 1/04—Revision 0: Initial Version Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 Rev. D | Page 2 of 24

AD5171 SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ V = 3 V to 5 V ± 10%, V = V , V = 0 V, −40°C < T < +125°C, unless otherwise noted. DD A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL R , V = no connect, −0.5 ±0.1 +0.5 LSB WB A R = 10 kΩ, 50 kΩ, and 100 kΩ AB R , V = no connect, R = 5 kΩ −1 ±0.25 +1 LSB WB A AB Resistor Integral Nonlinearity2 R-INL R , V = no connect, −1.5 ±0.35 +1.5 LSB WB A R = 10 kΩ, 50 kΩ, and 100 kΩ AB R , V = no connect, R = 5 kΩ −1.5 ±0.5 +1.5 LSB WB A AB Nominal Resistor Tolerance3 ∆R /R −30 +30 % AB AB Resistance Temperature Coefficient (∆R /R )/∆T 35 ppm/°C AB AB Wiper Resistance R V = 5 V 60 115 Ω W DD DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (SPECIFICATIONS APPLY TO ALL RDACs) Resolution N 6 Bits Differential Nonlinearity4 DNL −0.5 ±0.1 +0.5 LSB Integral Nonlinearity4 INL −1 ±0.2 +1 LSB Voltage Divider Temperature Coefficient (∆V /V )/∆T Code = 0x20 5 ppm/°C W W Full-Scale Error V Code = 0x3F, R = 10 kΩ, −1 −0.5 0 LSB WFSE AB 50 kΩ, and 100 kΩ Full-Scale Error V Code = 0x3F, R = 5 kΩ −1.5 0 LSB WFSE AB Zero-Scale Error V Code = 0x00, R =10 kΩ, 0 0.5 1 LSB WZSE AB 50 kΩ, and 100 kΩ Code = 0x00, R = 5 kΩ 0 2 LSB AB RESISTOR TERMINALS Voltage Range5 V V V With respect to GND V V A, B, W DD Capacitance A, B6 C C f = 1 MHz, measured to GND, 25 pF A, B code = 0x20 Capacitance W6 C f = 1 MHz, measured to GND, 55 pF W code = 0x20 Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS Input Logic High (SDA and SCL)7 V 0.7 V V + 0.5 V IH DD DD Input Logic Low (SDA and SCL)7 V −0.5 +0.3 V V IL DD Input Logic High (AD0) V V = 3 V 3.0 V V IH DD DD Input Logic Low (AD0) V V = 3 V 0 1.0 V IL DD Input Current I V = 0 V or 5 V ±1 μA IL IN Input Capacitance8 C 3 pF IL DIGITAL OUTPUTS Output Logic Low (SDA) V I = 6 mA 0.4 V OL OL Three-State Leakage Current (SDA) I V = 0 V or 5 V ±1 μA OZ IN Output Capacitance8 C 3 pF OZ POWER SUPPLIES Power Supply Range V 2.7 5.5 V DD OTP Power Supply7, 9 V T = 25°C 4.75 5 5.25 V DD_OTP A Supply Current I V = 5 V or V = 0 V 4 10 μA DD IH IL OTP Supply Current7, 10, 11 I V = 5 V, T = 25°C 100 mA DD_OTP DD_OTP A Power Dissipation12 PDISS V IH = 5 V or VIL = 0 V, VDD = 5 V 0.02 0.055 mW Power Supply Sensitivity PSSR −0.025 +0.001 +0.025 %/% Rev. D | Page 3 of 24

AD5171 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS8, 13, 14 –3 dB Bandwidth BW_5k R = 5 kΩ, code = 0x20 1500 kHz AB BW_10k R = 10 kΩ, code = 0x20 600 kHz AB BW_50k R = 50 kΩ, code = 0x20 110 kHz AB BW_100k R = 100 kΩ, code = 0x20 60 kHz AB Total Harmonic Distortion THD V = 1 V rms, R = 10 kΩ, 0.05 % A AB V = 0 V dc, f = 1 kHz B Adjustment Settling Time t V = 5 V ± 1 LSB error band, 5 μs S1 A V = 0 V, measured at V B W Power-Up Settling Time After Fuses Blown t V = 5 V ±1 LSB error band, 5 μs S2 A V = 0 V, measured at V B W Resistor Noise Voltage e R = 5 kΩ, f = 1 kHz, 8 nV/√Hz N_WB AB code = 0x20 R = 10 kΩ, f = 1 kHz, 12 nV/√Hz AB code = 0x20 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. 6 Guaranteed by design; not subject to production test. 7 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull- up resistors. 8 Guaranteed by design; not subject to production test. 9 Different from operating power supply; power supply for OTP is used one time only. 10 Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only. 11 See Figure 24 for the energy plot during the OTP program. 12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 14 All dynamic characteristics use VDD = 5 V. Rev. D | Page 4 of 24

AD5171 TIMING CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ V = 3 V to 5 V ± 10%, V = V , V = 0 V, −40°C < T < +125°C, unless otherwise noted. DD A DD B A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit INTERFACE TIMING CHARACTERISTICS (APPLY TO ALL PARTS2, 3) SCL Clock Frequency f 400 kHz SCL t Bus Free Time Between Start and Stop t 1.3 μs BUF 1 t Hold Time (Repeated Start) t After this period, the 0.6 μs HD;STA 2 first clock pulse is generated t Low Period of SCL Clock t 1.3 μs LOW 3 t High Period of SCL Clock t 0.6 50 μs HIGH 4 t Setup Time for Start Condition t 0.6 μs SU;STA 5 t Data Hold Time t 0.9 μs HD;DAT 6 t Data Setup Time t 0.1 μs SU;DAT 7 t Fall Time of Both SDA and SCL Signals t 0.3 μs F 8 t Rise Time of Both SDA and SCL Signals t 0.3 μs R 9 t Setup Time for Stop Condition t 0.6 μs SU;STO 10 OTP Program Time t 400 ms 11 1 Typical specifications represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design; not subject to production test. 3 All dynamic characteristics use VDD = 5 V. t8 t9 t6 SCL t2 t3 t9 t4 t5 t7 t10 t 8 SDA t1 P S P 03437-024 Figure 3. Interface Timing Diagram Rev. D | Page 5 of 24

AD5171 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress V to GND −0.3 V to +7 V rating only; functional operation of the device at these or any DD V , V , and V to GND GND to V other conditions above those indicated in the operational A B W DD Maximum Current section of this specification is not implied. Exposure to absolute I , I Pulsed ±20 mA maximum rating conditions for extended periods may affect WB WA I Continuous (R ≤ 1 kΩ, A Open)1 ±5 mA device reliability. WB WB IWA Continuous (RWA ≤ 1 kΩ, B Open)1 ±5 mA Digital Inputs and Output Voltage to GND 0 V to V DD ESD CAUTION Operating Temperature Range −40°C to +125°C Maximum Junction Temperature (T max) 150°C J Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Thermal Resistance θ 2 230°C/W JA 1 Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance; the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package power dissipation = (TJ max – TA)/θJA. Rev. D | Page 6 of 24

AD5171 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS W 1 8 A VDD 2 AD5171 7 B TOP VIEW GND 3 (Not to Scale) 6 AD0 SCL 4 5 SDA03437-003 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 W Wiper Terminal W. GND ≤ V ≤ V . W DD 2 V Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, V needs to be within DD DD the 4.75 V and 5.25 V range and capable of driving 100 mA. 3 GND Common Ground. 4 SCL Serial Clock Input. Requires a pull-up resistor. If it is driven direct from a logic controller without the pull-up resistor, ensure that the V minimum is 0.7 V × V . IH DD 5 SDA Serial Data Input/Output. Requires a pull-up resistor. If it is driven direct from a logic controller without a pull-up resistor, ensure that the V minimum is 0.7 V × V . IH DD 6 AD0 I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed. 7 B Resistor Terminal B. GND ≤ V ≤ V . B DD 8 A Resistor Terminal A. GND ≤ V ≤ V . A DD Rev. D | Page 7 of 24

AD5171 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.10 VDD = 5V VDD = 5V 0.08 0.08 B) 0.06 S 0.06 SB) –40°C L (L L 0.04 N 0.04 NL ( E D +125°C E I 0.02 OD 0.02 D M T MO 0 TER 0 TA–0.02 ME–0.02 RHEOS–0.04 +125°C ENTIO–0.04 –40°C +25°C –0.06 OT–0.06 +25°C P –0.08 –0.08 –0.10 –0.10 0 8 16 2C4ODE (D32ECIMA4L0) 48 56 64 03437-004 0 8 16 2C4ODE (D32ECIMA4L0) 48 56 64 03437-007 Figure 5. R-INL vs. Code vs. Temperature Figure 8. DNL vs. Code vs. Temperature 0.10 0 VDD = 5V 0.08 –0.1 +25°C 0.06 L (LSB) 0.04 +125°C –0.2 N MODE D 0.020 E (LSB) –0.3 VDD = 5V AT –0.02 FS –0.4 EOST–0.04 –40°C –0.5 VDD = 3V H R –0.06 –0.6 –0.08 –0.10 –0.7 0 8 16 2C4ODE (D32ECIMA4L0) 48 56 64 03437-005 –40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 03437-008 Figure 6. R-DNL vs. Code vs. Temperature Figure 9. Full-Scale Error (FSE) vs. Temperature 0.10 0.6 VDD = 5V 0.08 B) 0.5 S 0.06 L NL ( 0.04 ODE I 0.02 +25°C +125°C B) 0.4 VDD = 3V M S METER –0.020 ZSE (L 0.3 VDD = 5V NTIO–0.04 –40°C 0.2 E T O–0.06 P 0.1 –0.08 –0.10 0 0 8 16 2C4ODE (D32ECIMAL40) 48 56 64 03437-006 –40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 03437-009 Figure 7. INL vs. Code vs. Temperature Figure 10. Zero-Scale Error (ZSE) vs. Temperature Rev. D | Page 8 of 24

AD5171 10 6 0 VDD = 5V 0x20 –6 A) 0x10 NT (µ –12 0x08 E –18 RR 0x04 UPPLY CU 1 VDD = 3V GAIN (dB)––2340 00xx0021 SD –36 D 0x00 I –42 –48 0.1–40 –20 0 20TEMP4E0RATU6R0E (°C8)0 100 120 140 03437-010 –54100 1k F10RkEQUENC1Y0 0(Hkz) 1M 10M03437-013 Figure 11. IDD Supply Current vs. Temperature Figure 14. Gain vs. Frequency vs. Code, RAB = 5 kΩ 180 6 0x3F 160 0 m/°C)140 –6 0x20 pp120 –12 0x10 O ( PC100 –18 0x08 M DE TE 6800 N (dB)–24 00xx0042 AT MO 40 GAI––3306 0x01 ST 20 O –42 RHE 0 0x00 –48 –20 –54 –400 8 16 2C4ODE (D32ECIMA4L0) 48 56 64 03437-011 100 1k FREQU1E0kNCY (Hz) 100k 1M03437-014 Figure 12. Rheostat Mode Tempco (∆RAB/RAB)/∆T vs. Code Figure 15. Gain vs. Frequency vs. Code, RAB = 10 kΩ 25 6 C) 0 0x3F ppm/° 20 –6 0x20 O ( 0x10 C –12 MP 15 0x08 E –18 T ODE 10 dB)–24 0x04 METER M 5 GAIN (––3306 00xx0021 O NTI –42 E 0 T O –48 P 0x00 –50 8 16 2C4ODE (D32ECIMA4L0) 48 56 64 03437-012 –54100 1k FREQUE10NkCY (Hz) 100k 1M03437-015 Figure 13. Potentiometer Mode Tempco (∆VW /VW)/∆T vs. Code Figure 16. Gain vs. Frequency vs. Code, RAB = 50 Ω Rev. D | Page 9 of 24

AD5171 6 0 0x3F VVDAD = =5 .55.V5V DATA 0x00 → 0x3F –6 0x20 fVCBL K= =G N40D0kHz 0x10 –12 VW = 5V/DIV 0x08 –18 B) –24 0x04 d N ( 0x02 SCL = 5V/DIV AI –30 G –36 0x01 –42 ––5448 0x00 5V 5V 5µs 03437-019 100 1k FREQUE10NkCY (Hz) 100k 1M03437-016 Figure 17. Gain vs. Frequency vs. Code, RAB = 100 kΩ Figure 20. Settling Time 80 O (dB) TCVAAO D== E22 5.=5° VC0,x V2B0 = 0V VVfVCDABLD K== ==5G . 5N51.V05D0VkHz TI 60 DATA 0x20 → 0x1F A N R VDD = 5V DC ± 1.0V p-pAC VW = 50mV/DIV O TI C JE 40 VDD = 3V DC ± 0.6V p-pAC E R Y L P P U R S 20 E W SCL = 5V/DIV O P 0100 1k FREQU1E0NkCY (Hz) 100k 1M03437-017 50mV 5V 200ns 03437-020 Figure 18. Power Supply Rejection Ratio vs. Frequency Figure 21. Midscale Glitch Energy VVVDABD == =5G .5N5.V5DV fCLK = 100kHz VOVRDAATD BP= ==P5 .5R15.0OV5kVGΩRAMMED AT MS VW = 10mV/DIV VW = 1V/DIV SCL = 5V/DIV VDD = 5V/DIV 10mV 5V 500ns 03437-018 1V 5V 5µs 03437-021 Figure 19. Digital Feedthrough vs. Time Figure 22. Power-Up Settling Time After Fuses Blown Rev. D | Page 10 of 24

AD5171 10 VA = VB = OPEN TA = 25°C mA) RAB = 5kΩ (X 1 CH1 MAX MA 103mA B_ RAB = 10kΩ W L I CH1 MIN CA RAB = 50kΩ –1.98mA TI E R 0.1 O HE RAB = 100kΩ T 1 0.010 8 16 2C4ODE (D32ECIMAL40) 48 56 64 03437-0-022 CH1 20F.i0gmuAreΩ 24. OTP PrograMmT 2E 0 n0 5en8rs8g.y0 0P0lnostA foCrH S1in g l e3 2F.u4mseA 03437-023 Figure 23. Theoretical IWB_MAX vs. Code Rev. D | Page 11 of 24

AD5171 THEORY OF OPERATION A SCL DAC MUX DECODER SDA I2C INTERFACE REG. W B COMPARATOR FUSES FUSE EN REG. ONE-TIME PROGRAM/TEST CONTROL BLOCK 03437-025 Figure 25. Detailed Functional Block Diagram The AD5171 allows unlimited 6-bit adjustments, except for the Table 5. Validation Status one-time programmable, set-and-forget resistance setting. OTP E1 E0 Status technology is a proven, cost-effective alternative over EEMEM 0 0 Ready for programming. in one-time memory programming applications. The AD5171 0 1 Test fuse not blown successfully. For factory setup employs fuse link technology to achieve the memory retention checking purpose only. Users should not see these of the resistance setting function. It has six data fuses that control combinations. the address decoder for programming the RDAC, one user 1 0 Fatal error. Some fuses are not blown. Do not retry. mode test fuse for checking setup error, and one programming Discard the unit. lock fuse for disabling any further programming once the data 1 1 Successful. No further programming is possible. fuses are blown. ONE-TIME PROGRAMMING (OTP) This section discusses the fuse operation in detail. When the OTP T bit is set, the internal clock is enabled. The program then Prior to OTP activation, the AD5171 presets to midscale during attempts to blow a test fuse. The operation stops if the test fuse initial power-on. After the wiper is set at the desired position, is not properly blown. The validation bits, E1 and E0, show 01. the resistance can be permanently set by programming the T bit This status is intended for factory setup checking purposes high along with the proper coding (see Table 8 and Table 9) and only; users should not see this status. If the test fuse is properly one-time V . The fuse link technology of the AD517x DD_OTP blown, the data fuses can be programmed. The six data fuses family of digital potentiometers requires V between 4.75 V DD_OTP are programmed in six clock cycles. The output of the fuses is and 5.25 V to blow the fuses to achieve a given nonvolatile compared with the code stored in the RDAC register. If they do setting. On the other hand, V can be 2.7 V to 5.5 V during DD not match, E1 and E0 of 10 are issued as fatal errors and the operation. As a result, a system supply that is lower than 4.75 V operation stops. Users should never try blowing the fuses more requires external supply for OTP. In addition, the user is only than once because the fuse structure may have changed prohibiting allowed one attempt in blowing the fuses. If the user fails to further programming. As a result, the unit must be discarded. blow the fuses at the first attempt, the fuse structures may change This error status can also occur if the OTP supply voltage goes so that they may never be blown regardless of the energy applied above or drops below the V requirement, the OTP supply DD_OTP at subsequent events. For details, see the Power Supply current is limited, or both the voltage and current ramp times Considerations section. are slow. If the output and stored code match, the programming The device control circuit has two validation bits, E1 and E0, lock fuse is blown so that no further programming is possible. that can be read back to check the programming status (see In the meantime, E1 and E0 issue 11, indicating the lock fuse is Table 5). Users should always read back the validation bits to properly blown. All the fuse latches are enabled at power-on; ensure that the fuses are properly blown. After the fuses are therefore, from this point on, the output corresponds to the blown, all fuse latches are enabled upon subsequent power-on; stored setting. Figure 25 shows a detailed functional block therefore, the output corresponds to the stored setting. diagram. Rev. D | Page 12 of 24

AD5171 VARIABLE RESISTANCE AND VOLTAGE FOR Similar to the mechanical potentiometer, the resistance of the RHEOSTAT MODE RDAC between the wiper (Terminal W) and Terminal A also produces a complementary resistance, R . When these terminals If only the W-to-B or W-to-A terminals are used as variable WA are used, Terminal B can be opened or shorted to Terminal W. resistors, the unused terminal can be opened or shorted with Setting the resistance value for R starts at a maximum value Terminal W. This operation is called rheostat mode (see Figure 26). WA of resistance and decreases as the data loaded in the latch A A A increases in value. The general equation for this operation is W W W 63−D R (D)= ×R +R (2) B B B 03437-050 Table 7W.A R vs. C6o3des: RAB = 1W0 kΩ; Terminal B Open Figure 26. Rheostat Mode Configuration WA AB D (Dec) R (Ω) Output State WA The nominal resistance (R ) of the RDAC has 64 contact points AB 63 60 Full-scale accessed by the wiper terminal, plus Terminal B contact if R is WB 32 4980 Midscale considered. The 6-bit data in the RDAC latch is decoded to 1 9901 1 LSB select one of the 64 settings. Assuming that a 10 kΩ part is used, 0 10060 Zero-scale the first connection of the wiper starts at Terminal B for Data 0x00. Such a connection yields a minimum of 60 Ω resistance between The typical distribution of the resistance tolerance from device Terminal W and Terminal B due to the 60 Ω wiper contact to device is process-lot dependent; it is possible to have ±30% resistance. The second connection is the first tap point, which tolerance. corresponds to 219 Ω (R = 1 × R /63 + R ) for Data 0x01, WB AB W and so on. Each LSB data value increase moves the wiper up A the resistor ladder until the last tap point is reached at 10,060 Ω (63 × R /63 + R ). Figure 27 shows a simplified diagram of the AB W D5 equivalent RDAC circuit. The general equation determining RWB is D4 RS D3 D D2 RWB(D)=63×RAB+RW (1) DD10 RS W where: D is the decimal equivalent of the 6-bit binary code. R is the end-to-end resistance. AB R is the wiper resistance contributed by the on-resistance of W RDAC the internal switch. LATCH RS AND DECODER Table 6. R vs. Codes: R = 10 kΩ; Terminal A Open B WB AB D63 ( Dec) R10W0B 6(Ω0 ) FOuullt-pscuatl eS t(aRtAeB + RW) 03437-026 Figure 27. AD5171 Equivalent RDAC Circuit 32 5139 Midscale 1 219 1 LSB VARIABLE RESISTANCE AND VOLTAGE FOR 0 60 Zero-scale (wiper contact resistance) POTENTIOMETER MODE If all three terminals are used, the operation is called the Because a finite wiper resistance of 60 Ω is present in the zero- potentiometer mode. The most common configuration is the scale condition, care should be taken to limit the current flow voltage divider operation (see Figure 28). between Terminal W and Terminal B in this state to a maximum pulse current 20 mA. Otherwise, degradation or possible VI A destruction of the internal switch contact can occur. W VO B 03437-051 Figure 28. Potentiometer Mode Configuration Rev. D | Page 13 of 24

AD5171 Ignoring the effect of the wiper resistance, the transfer function When operating at 2.7 V, use of the bidirectional low threshold is simply P-Ch MOSFETs is recommended for the isolation of the supply. As shown in Figure 29, this assumes that the 2.7 V system D V (D)= V (3) voltage is applied first, and the P1 and P2 gates are pulled to W 63 A ground, thus turning on P1 and, subsequently, P2. As a result, A more accurate calculation, which includes the wiper V of the AD5171 approaches 2.7 V. When the AD5171 setting DD resistance effect, yields is found, the factory tester applies the V to both the V DD_OTP DD D and the MOSFETs gates, thus turning off P1 and P2. The OTP R +R V (D)= 63 AB WV (4) command should be executed at this time to program the W R +2R A AD5171 while the 2.7 V source is protected. Once the fuse AB W programming is complete, the tester withdraws the V and Unlike in rheostat mode where the absolute tolerance is high, DD_OTP the setting of the AD5171 is permanently fixed. potentiometer mode yields an almost ratiometric function of D/63 with a relatively small error contributed by the R terms; The AD5171 achieves the OTP function through blowing W thus, the tolerance effect is almost cancelled. Although the thin internal fuses. Users should always apply the 4.75 V to film step resistor (R) and CMOS switches resistance (R ) have 5.25 V one-time program voltage requirement at the first S W very different temperature coefficients, the ratiometric adjustment fuse programming attempt. Failure to comply with this also reduces the overall temperature coefficient effect to 5 ppm/°C, requirement may lead to a change in the fuse structures, except at low value codes where R dominates. rendering programming inoperable. W Potentiometer mode includes other operations such as op amp Care should be taken when SCL and SDA are driven from a low input, feedback resistor networks, and voltage scaling applications. voltage logic controller. Users must ensure that the logic high Terminal A, Terminal W, and Terminal B can, in fact, be input level is between 0.7 V × VDD and VDD. Refer to the Level Shifting or output terminals provided that |V |, |V |, and |V | do not for Different Voltage Operation section. AB WA WB exceed V to GND. DD Poor PCB layout introduces parasitics that may affect the fuse POWER SUPPLY CONSIDERATIONS programming. Therefore, it is recommended that a 10 μF tantalum capacitor be added in parallel with a 1 nF ceramic To minimize the package pin count, both the OTP and normal capacitor as close as possible to the V pin. The type and value operating voltage supplies share the same V terminal of the DD DD chosen for both capacitors are important. This combination of AD5171. The AD5171 employs fuse link technology that requires capacitor values provides both a fast response and larger supply 4.75 V to 5.25 V for blowing the internal fuses to achieve a current handling with minimum supply droop during transients. given setting, but normal V can be anywhere between 2.7 V DD As a result, these capacitors increase the OTP programming and 5.5 V after the fuse programming process. As a result, dual success by not inhibiting the proper energy needed to blow the voltage supplies and isolation are needed if system V is lower DD internal fuses. Additionally, C1 minimizes transient disturbance than the required V . The fuse programming supply (either DD_OTP and low frequency ripple, while C2 reduces high frequency an on-board regulator or rack-mount power supply) must be noise during normal operation. rated at 4.75 V to 5.25 V and able to provide a 100 mA current for 400 ms for successful one-time programming. Once fuse ESD PROTECTION programming is complete, the V supply must be removed DD_OTP Digital inputs SDA and SCL are protected with a series input to allow normal operation at 2.7 V to 5.5 V; the device then resistor and parallel Zener ESD structures (see Figure 30). consumes current in the μA range. 340Ω APPLY FOR OTP ONLY LOGIC 5V 10Rk1Ω GND 03437-027 Figure 30. ESD Protection of Digital Pins 2.7V VDD C1 C2 P1 P2 10µF 0.1µF AD5171 P1 = P2 = FDV302P, NDS0610 03437-052 Figure 29. 5 V OTP Supply Isolated from the 2.7 V Normal Operating Supply; the VDD_OTP supply must be removed once OTP is complete. Rev. D | Page 14 of 24

AD5171 TERMINAL VOLTAGE OPERATING RANGE POWER-UP/POWER-DOWN SEQUENCES There are also ESD protection diodes between V and the Similarly, because of the ESD protection diodes, it is important DD RDAC terminals; therefore, the V of the AD5171 defines their to power V first before applying any voltages to Terminal A, DD DD voltage boundary conditions (see Figure 31). Supply signals Terminal B, and Terminal W. Otherwise, the diode is forward- present on Terminal A, Terminal B, and Terminal W that biased such that V is powered unintentionally and can affect DD exceed V are clamped by the internal forward-biased diodes the remainder of the users’ circuits. The ideal power-up sequence is DD and should be avoided. the following order: GND, V , digital inputs, and V /V /V . DD A B W VDD The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after V . Similarly, V DD DD A should be powered down last. W B GND03437-029 Figure 31. Maximum Terminal Voltages Set by VDD Rev. D | Page 15 of 24

AD5171 CONTROLLING THE AD5171 There are two ways of controlling the AD5171. Users can either Read program the devices with computer software or employ external To read the validation bits and data from the device, click Read. I2C controllers. The user may also set the bit pattern in the upper screen and SOFTWARE PROGRAMMING click Run. The format of reading data out from the device is shown in Table 9. Due to the advantage of the one-time programmable feature, users may consider programming the device in the factory DEVICE PROGRAMMING before shipping it to the end users. Analog Devices offers device To apply the device programming software in the factory, users programming software that can be implemented in the factory need to modify a parallel port cable and configure Pin 2, Pin 3, on PCs running Windows 95 to Windows XP platforms. As a Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND, result, external controllers are not required, which significantly respectively, for the control signals (see Figure 33). In addition, reduces development time. lay out the PCB of the AD5171 with SCL and SDA pads, as The program is an executable file that does not require the user shown in Figure 34, such that pogo pins can be inserted for the to know any programming languages or programming skills. It factory programming. is easy to set up and use. Figure 32 shows the software interface. 13 The software can be downloaded from the AD5171 product page. 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 R3 SCL 4 100Ω 03437-032 131265 10RR021ΩWRREIATDE SDA Figure 32. Software Interface 14 100Ω Write 1 03437-033 The AD5171 starts at midscale after power-up prior to the OTP Figure 33. Parallel Port Connection: Pin 2 = SDA_write, Pin 3 = SCL, programming. To increment or decrement the resistance, move Pin 15 = SDA_read, and Pin 25 = DGND the scrollbar on the left. To write any specific values, use the bit W A pattern control in the upper screen and click Run. The format VDD B GND AD0 odfe swirreitdi nsge tdtiantga itso f tohuen dde, vcilcicek i sP srhoogwranm in P Tearbmlea n8.e Ontn tcoe bthloew the SCL SDA 04104-034 internal fuse links for permanent setting. The user can also set Figure 34. Recommended AD5171 PCB Layout the programming bit pattern in the upper screen and click Run to achieve the same result. Table 8. SDA Write Mode Bit Format S 0 1 0 1 1 0 AD0 0 A T X X X X X X X A X X D5 D4 D3 D2 D1 D0 A P Slave Address Byte Instruction Byte Data Byte Table 9. SDA Read Mode Bit Format S 0 1 0 1 1 0 AD0 1 A E1 E0 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte Rev. D | Page 16 of 24

AD5171 Table 10. SDA Bits Definitions and Descriptions Bit Description S Start Condition. P Stop Condition. A Acknowledge. AD0 I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed. X Don’t Care. T OTP Programming Bit. Logic 1 programs the wiper position permanently. D5, D4, D3, D2, D1, D0 Data Bits. E1, E0 OTP Validation Bits: 0, 0 = Ready to Program. 0, 1 = Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these combinations. 1, 0 = Fatal Error. Do not retry. Discard the unit. 1, 1 = Programmed Successfully. No further adjustments are possible. I2C CONTROLLER PROGRAMMING Write Bit Patterns 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 0 AD0 R/W 0 X X X X X X X X X D5 D4 D3 D2 D1 D0 ACK. BY ACK. BY ACK. BY AD5171 AD5171 AD5171 STMAARSTT EBRY SLAVEFARDADMREES 1S BYTE INSTRFURCATMIOEN 2 BYTE DFARTAA MBEY T1E SMTAOSPT EBRY 03437-035 Figure 35. Writing to the RDAC Register 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 0 AD0 R/W 1 X X X X X X X X X D5 D4 D3 D2 D1 D0 ACK. BY ACK. BY ACK. BY AD5171 AD5171 AD5171 STMAARSTT EBRY SLAVEFARDADMREES 1S BYTE INSTRFURCATMIOEN 2 BYTE DFARTAA MBEY T1E SMTAOSPT EBRY 03437-036 Figure 36. Activating One-Time Programming Read Bit Pattern 1 9 1 9 SCL SDA 0 1 0 1 1 0 AD0 R/W E1 E0 D5 D4 D3 D2 D1 D0 ACK. BY NOACK. BY AD5171 MASTER STMAARSTT EBRY SLAVEFARDADMREES 1S BYTE RDAFCR RAEMGEI S2TER SMTAOSPT EBRY03437-037 Figure 37. Reading Data from RDAC Register AD5171s can be addressed on the same bus (see Figure 38). The I2C-COMPATIBLE 2-WIRE SERIAL BUS last LSB is the R/W bit, which determines whether data is read For users who prefer to use external controllers, the AD5171 from, or written to, the slave device. can be controlled via an I2C-compatible serial bus; the part is The slave address corresponding to the transmitted address bit connected to this bus as a slave device. The following section responds by pulling the SDA line low during the 9th clock pulse describes how the 2-wire I2C serial bus protocol operates (see (this is termed the acknowledge bit). At this stage, all other Figure 35, Figure 36, and Figure 37). devices on the bus remain idle while the selected device waits The master initiates data transfer by establishing a start condition, for data to be written to, or read from, its serial register. which is when SDA goes from high to low while SCL is high The write operation contains one instruction byte more than (see Figure 35 and Figure 36). The following byte is the slave the read operation. The instruction byte in the write mode address byte, which consists of the 6 MSBs as a slave address follows the slave address byte. The MSB of the instruction byte defined as 010110. The next bit is AD0, which is an I2C device labeled T is the one-time programming bit. After acknowledging address bit. Depending on the states of their AD0 bits, two Rev. D | Page 17 of 24

AD5171 the instruction byte, the last byte in the write mode is the data A repeated write function gives the user flexibility to update the byte. Data is transmitted over the serial bus in sequences of nine RDAC output a number of times, except after permanent clock pulses (eight data bits followed by an acknowledge bit). programming, addressing, and instructing the part only once. The transitions on the SDA line must occur during the low During the write cycle, each data byte updates the RDAC output. period of SCL and remain stable during the high period of SCL For example, after the RDAC has acknowledged its slave address (see Figure 35). and instruction bytes, the RDAC output updates after these two bytes. If another byte is written to the RDAC while it is still In read mode, the data byte follows immediately after the addressed to a specific slave device with the same instruction, acknowledgment of the slave address byte. Data is transmitted over this byte updates the output of the selected slave device. If the serial bus in sequences of nine clock pulses (note the slight different instructions are needed, the write mode has to be difference from the write mode; there are eight data bits followed started with a new slave address, instruction, and data bytes. by a no acknowledge bit). Similarly, the transitions on the SDA Similarly, a repeated read function of the RDAC is also allowed. line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 37). CONTROLLING TWO DEVICES ON ONE BUS When all data bits are read or written, a stop condition is Figure 38 shows two AD5171 devices on the same serial bus. established by the master. A stop condition is defined as a low- Each has a different slave address because the state of each AD0 to-high transition on the SDA line while SCL is high. In the pin is different, which allows each device to be independently write mode, the master pulls the SDA line high during the 10th operated. The master device output bus line drivers are open- clock pulse to establish a stop condition (see Figure 35 and drain pull-downs in a fully I2C-compatible interface. Figure 36). In the read mode, the master issues a no acknowledge 5V for the 9th clock pulse, that is, the SDA line remains high. The Rp Rp master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (see Figure 37). SDA MASTER SCL SDA SCL 5V SDA SCL AADD05171 AADD05171 03437-038 Figure 38. Two AD5171 Devices on One Bus Rev. D | Page 18 of 24

AD5171 APPLICATIONS INFORMATION DAC In this circuit, the inverting input of the op amp forces the V OUT to be equal to the wiper voltage set by the digital potentiometer. It is common to buffer the output of the digital potentiometer as The load current is then delivered by the supply via the N‒Ch a DAC unless the load is much larger than R . The buffer can WB FET N. N power handling must be adequate to dissipate impede conversion and deliver higher current, if needed. 1 1 (V − V ) × I power. This circuit can source a maximum of I O L 5V AD5171 100 mA with a 5 V supply. For precision applications, a voltage 1 VOUT VIN3 A W 5VU2 raepfpelrieendc aet, Tsuecrhm ains atlh Ae AofD tRh4e 2d1i,g AitaDl Rp0o3te, notri oAmDeRte3r7. 0, can be U1 AD1582 AD8601 VO LEVEL SHIFTING FOR DIFFERENT VOLTAGE G2ND B A1 03437-039 OIf PthEe RSACLT IaOndN S DA signals come from a low voltage logic Figure 39. Programmable Voltage Reference (DAC) controller and are below the minimum V level (0.7 V × V ), IH DD GAIN CONTROL COMPENSATION level shift the signals for read/write communications between The digital potentiometers are commonly used in gain the AD5171 and the controller. Figure 42 shows one of the controls or sensor transimpedance amplifier signal conditioning implementations. For example, when SDA1 is at 2.5 V, M1 turns applications (see Figure 40). To avoid gain peaking, or in worst- off, and SDA2 becomes 5 V. When SDA1 is at 0 V, M1 turns on, case oscillation due to step response, a compensation capacitor and SDA2 approaches 0 V. As a result, proper level shifting is is needed. In general, C2 in the range of a few picofarads to a established. M1 and M2 should be low threshold N-Ch power few tenths of a picofarad is adequate for the compensation. MOSFETs, such as FDV301N. C2 VDD1= 2.5V VDD2= 5V Rp Rp Rp Rp 4.7pF R2 100kΩ B A G W S D G R1 SDA1 SDA2 47kΩ U1 VO M1 S D VI 03437-040 SCL1 M2 SCL2 Figure 40. Typical Noninverting Gain Amplifier PROGRAMMABLE VOLTAGE SOURCE WITH CONT2R.5OVLLER A2.7DV5–51.75V1 03437-042 BOOSTED OUTPUT Figure 42. Level Shifting for Different Voltage Operation For applications that require high current adjustment, such as a RESISTANCE SCALING laser diode driver or tunable laser, a boosted voltage source can The AD5171 offers 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ nominal be considered (see Figure 41). resistances. For users who need to optimize the resolution with U3 2N7002 an arbitrary full range resistance, the following techniques can VIN VOUT be used. By paralleling a discrete resistor, a proportionately lower U1 A +V CC RBIAS voltage appears at Terminal A to Terminal B, which is applicable AD5171 W only to the voltage divider mode (see Figure 43). U2 AD8601 IL This translates into a finer degree of precision because the step B size at Terminal W is smaller. The voltage can be found as –V LD SIGNAL 03437-041 V (D)= (RAB||R2) × D ×V (5) Figure 41. Programmable Booster Voltage Source W R3+R ||R2 64 DD AB VDD R3 A W R2 R1 B 03437-043 Figure 43. Lowering the Nominal Resistance Rev. D | Page 19 of 24

AD5171 For log taper adjustment, such as volume control, Figure 44 RDAC CIRCUIT SIMULATION MODEL shows another way of resistance scaling. In this circuit, the The internal parasitic capacitances and the external capacitive smaller the R2 with respect to R , the more it behaves like the AB loads dominate the ac characteristics of the digital potentiometers. pseudo log taper characteristic. The wiper voltage is simply Configured as a potentiometer divider, the –3 dB bandwidth of (R ||R2) the AD5171 (5 kΩ resistor) measures 1.5 MHz at half scale. V (D)= WB ×V (6) W R +R ||R2 I Figure 14 to Figure 17 provide the large signal BODE plot WA WB characteristics of the four available resistor versions: 5 kΩ, VI 10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simulation model is A VO shown in Figure 46. Listing 1 provides a macro model net list R1 W for the 10 kΩ device. B R2 RDAC 03437-044 A CA 10kΩ CW CBB Figure 44. Resistor Scaling with Log Adjustment Characteristics 25pF 25pF RESOLUTION ENHANCEMENT W 55pF 03437-046 The resolution can be doubled in the potentiometer mode of Figure 46. Circuit Simulation Model for RDAC = 10 kΩ operation by using three digital potentiometers. Borrowed from Listing 1. Macro Model Net List for RDAC the Analog Devices patented RDAC segmentation technique, users can configure three AD5171s to double the resolution (see .PARAM D=64, RDAC=10E3 Figure 45). First, U3 must be parallel with a discrete resistor, R , P * which is chosen to be equal to a step resistance (R = R /64). P AB Adjusting U1 and U2 together forms the coarse 6-bit adjustment, .SUBCKT DPOT (A,W,B) * and adjusting U3 alone forms the finer 6-bit adjustment. As a CA A 0 25E-12 result, the effective resolution becomes 12-bit. RWA A W {(1-D/64)*RDAC+60} A1 CW W 0 55E-12 RWB W B {D/64*RDAC+60} U1 W1 CB B 0 25E-12 A3 * B1 RP U3 W3 .ENDS DPOT A2 B3 W2 U2 ADCJUOSBAT2RMSEENT ADJUFSINTEMENT 03437-045 Figure 45. Doubling the Resolution Rev. D | Page 20 of 24

AD5171 EVALUATION BOARD JP5 VCC JP3 VDD V+ 1 U4 5 C6 C7 TEMP TRIM 0.1µF 10µF 2 VDD C4 3 GVINND VOUT 4 C5 VREF CP3 –IN1 –IN1 CP4 0.1µF ADR03 0.1µF CP2 JP1 JP8 CP1 8 2 A 1 OUT1 JP7 W 3 VIN U3A CP6 VDD B 4 V– CP7 OUT1 VDD JP2 +IN1 CP5 10µCF1 R2 1 U1 8 1 U2 8 J8761 SCL10kRΩ1 100.k1ΩµCF2 234WVGSADCNDLDD51SA7DD0ABA0765 0.1Cµ3F A234DWVGS5DCN1DLD71/ASADDDABA50276573 AGND JP04.1µCF8 C9 5 10µF 4 SDA 3 JP6 VEE 2 6 1 –IN2 7 OUT2 +IN2 5 U3B 03437-047 Figure 47. Evaluation Board Schematic The AD5171 evaluation board comes with a dual op amp AD822 and a 2.5 V reference ADR03. Users can configure many building block circuits with minimal components needed. Figure 48 shows one of the examples. There is space available on the board where users can build additional circuits for further evaluations as shown in Figure 49. CP2 VREF VDD JP3 VREF JP1 U3A A A 2 4V+ W VO U2 JP7 1 OUT1 W 3 V– B JP2B JP411 AD822 03437-048 Figure 49. Evaluation Board 03437-049 Figure 48. Programmable Voltage Reference Rev. D | Page 21 of 24

AD5171 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1.60 BSC 2.80 BSC 1 2 3 4 PIN1 INDICATOR 0.65 BSC 1.95 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.60 0.15 MAX 00..3282 SEATING 84°° 00..4350 PLANE 0° COMPLIANTTO JEDEC STANDARDS MO-178-BA Figure 50. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model1 R (kΩ) Temperature Range Package Description Package Option Ordering Quantity Branding AB AD5171BRJ5-R2 5 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D12 AD5171BRJ5-RL7 5 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D12 AD5171BRJZ5-R22 5 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D12# AD5171BRJZ5-R72 5 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D12# AD5171BRJ10-R2 10 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D13 AD5171BRJ10-RL7 10 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D13 AD5171BRJZ10-R22 10 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D13# AD5171BRJZ10-R72 10 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D13# AD5171BRJ50-R2 50 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D14 AD5171BRJ50-RL7 50 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D14 AD5171BRJZ50-R22 50 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D14# AD5171BRJZ50-R72 50 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D14# AD5171BRJ100-R2 100 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D15 AD5171BRJ100-RL7 100 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D15 AD5171BRJZ100-R22 100 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D15# AD5171BRJZ100-R72 100 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D15# AD5171EVAL3 10 Evaluation Board 1 1 Parts have a YWW or #YWW marking on the bottom of the package. Y shows the year that the part was made, for example, Y = 5 for 2005. WW shows the work week that the part was made. 2 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. 3 The evaluation board is shipped with three pieces of 10 kΩ parts. Users should order extra samples or different resistance options if needed. Rev. D | Page 22 of 24

AD5171 NOTES Rev. D | Page 23 of 24

AD5171 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03437-0-7/08(D) Rev. D | Page 24 of 24