256-Position, Ultralow Power 1.8 V Logic-Level Digital Potentiometer AD5165 FEATURES FUNCTIONAL BLOCK DIAGRAM Ultralow standby power I = 50 nA typical DD VDD 256-position End-to-end resistance 100 kΩ A Logic high voltage 1.8 V CS 3-WIRE INTERFACE Power supply 2.7 V to 5.5 V SDI Low temperature coefficient 35 ppm/°C CLK W Compact thin 8-lead TSOT-8 (2.9 mm × 2.8 mm) package WIPER Simple 3-wire digital interface B REGISTER Wide operating temperature −40°C to +125°C Pin-to-pin compatible to AD5160 with CS inverted GND 04749-0-001 APPLICATIONS Figure 1. Battery-operated electronics adjustment Remote utilities meter adjustment Mechanical potentiometer replacement PIN CONFIGURATION Transducer circuit adjustment Automotive electronics adjustment W 1 8 A Gain control and offset adjustment VDD 2 AD5165 7 B SVyCsXtOem a dcjaulisbtmraetinotn GCNLKD 34 (NToOt Pto V SIEcaWle) 56 CSDSI 04749-0-002 GENERAL OVERVIEW Figure 2. The AD5165 provides a compact 2.9 mm × 2.8 mm packaged solution for 256-position adjustment applications. These devices TYPICAL APPLICATION perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, 5V solid-state reliability, and superior low temperature coefficient VOH= 1.8V MIN performance. The AD5165’s supply voltage requirement is 2.7 V VDD to 5.5 V, but its logic voltage requirement is 1.8 V to VDD. The 3.3V AD5165 VA AD5165 consumes very low quiescent power during standby WIDE TERMINAL mode and is ideal for battery-operated applications. DIGITAL VW VOLTAGE RANGE: CS CONTROL CLK VB 0V < VA,VB,VW< 5V Wiper settings are controlled through a simple 3-wire interface. LOGIC OR The interface is similar to the SPI® digital interface except for the MICRO SDI GND isnuvmerptteidon c hinip t-hsee liedclti nfugn sctatitoen. T thhea tr mesiisntiamncizee bs elotwgiece npo twhee rw ciopner- 04749-0-003 and either endpoint of the fixed resistor varies linearly with Figure 3. respect to the digital code transferred into the wiper register. Operating from a 2.7 V to 5.5 V power supply and consuming Note: The terms digital potentiometer, RDAC, and VR are used interchangeably. less than 50 nA typical standby power allows use in battery- operated portable or remote utility device applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

AD5165 TABLE OF CONTENTS Electrical Characteristics—100 kΩ Version..................................3 3-Wire Serial Bus Digital Interface..........................................14 Absolute Maximum Ratings............................................................5 ESD Protection...........................................................................14 Pin Configuration and Functional Descriptions..........................6 Terminal Voltage Operating Range..........................................14 Typical Performance Characteristics.............................................7 Power-Up Sequence...................................................................14 Test Circuits.....................................................................................11 Layout and Power Supply Bypassing.......................................15 3-Wire Digital Interface.................................................................12 Evaluation Board........................................................................15 Theory of Operation......................................................................13 Outline Dimensions.......................................................................16 Programming the Variable Resistor.........................................13 Ordering Guide..........................................................................16 Programming the Potentiometer Divider...............................14 REVISION HISTORY 4/04—Revision 0: Initial Version Rev. 0 | Page 2 of 16

AD5165 ELECTRICAL CHARACTERISTICS—100 kΩ VERSION V = 5 V ± 10%, or 3 V ± 10%; V = V ; V = 0 V; –40°C < T < +125°C; unless otherwise noted. DD A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2 ±0.25 +2 LSB Nominal Resistor Tolerance3 ∆R /R T = 25°C −20 +20 % AB AB A Resistance Temperature Coefficient (∆RAB/RAB)/∆Tx106 VAB = VDD, wiper = no connect 35 ppm/°C Wiper Resistance R V = 2.7 V/5.5 V 85/50 150/120 Ω W DD DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity4 DNL −1 ±0.1 +1 LSB Integral Nonlinearity4 INL −1 ±0.3 +1 LSB Voltage Divider Temperature (∆V /V )/∆Tx106 Code = 0x80 15 ppm/°C W W Coefficient Full-Scale Error V Code = 0xFF −0.5 −0.3 0 LSB WFSE Zero-Scale Error V Code = 0x00 0 0.1 0.5 LSB WZSE RESISTOR TERMINALS Voltage Range5 V GND V V A,B,W DD Capacitance6 A, B C f = 1 MHz, measured to GND, 90 pF A,B Code = 0x80 Capacitance6 W C f = 1 MHz, measured to GND, 95 pF W Code = 0x80 Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V V = 2.7 V to 5.5 V 1.8 V IH DD Input Logic Low V V = 2.7 V to 5.5 V 0.6 V IL DD Input Capacitance6 C 5 pF IL POWER SUPPLIES Power Supply Range V 2.7 5.5 V DD RANGE Supply Current I Digital inputs = 0 V or V 0.05 1 µA DD DD V = 2.7 V, digital inputs = 1.8 V 10 µA DD V = 5 V, digital inputs = 1.8 V 500 µA DD Power Dissipation7 P Digital inputs = 0 V or V 5.5 µW DISS DD Power Supply Sensitivity PSS V = +5 V ± 10%, ±0.001 ±0.005 %/% DD Code = Midscale DYNAMIC CHARACTERISTICS6, 8 Bandwidth −3 dB BW Code = 0x80 55 kHz Total Harmonic Distortion THD V =1 V rms, V = 0 V, f = 1 kHz, 0.05 % W A B V Settling Time t V = 5 V, V = 0 V, 2 µs W S A B ±1 LSB error band Resistor Noise Voltage Density e R = 50 kΩ 28 nV/√Hz N_WB WB 1 Typical specifications represent average readings at +25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. 5 Resistor terminals A, B, and W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 8 All dynamic characteristics use VDD = 5 V. Rev. 0 | Page 3 of 16

AD5165 TIMING CHARACTERISTICS—100 kΩ VERSION V = +5 V ± 10%, or +3 V ± 10%; V = V ; V = 0 V; −40°C < T < +125°C; unless otherwise noted. DD A DD B A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit 3-WIRE INTERFACE TIMING CHARACTERISTICS2, 3, 4 (specifications apply to all parts) Clock Frequency f = 1/( t + t ) 25 MHz CLK CH CL Input Clock Pulse Width t , t Clock level high or low 20 ns CH CL Data Setup Time t 5 ns DS Data Hold Time t 5 ns DH CS Setup Time t 15 ns CSS CS Low Pulse Width t 40 ns CSW CLK Fall to CS Rise Hold Time t 0 ns CSH0 CLK Fall to CS Fall Hold Time t 0 ns CSH1 CS Fall to Clock Rise Setup t 10 ns CS1 1 Typical specifications represent average readings at +25°C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. 3 All dynamic characteristics use VDD = 5 V. 4 See Figure 34 and Figure 35 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Rev. 0 | Page 4 of 16

AD5165 ABSOLUTE MAXIMUM RATINGS T = +25°C, unless otherwise noted.1, 2 Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 3. rating only; functional operation of the device at these or any Parameter Value other conditions above those indicated in the operational V to GND –0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute V , V, V to GND V A B W DD maximum rating conditions for extended periods may affect Maximum Current device reliability. I , I Pulsed ±20 mA WB WA I Continuous (R ≤ 1kΩ, A open)2 ±5 mA WB WB I Continuous (R ≤ 1 kΩ, B open)2 ±5 mA WA WA Digital Inputs and Output Voltage to GND 0 V to +7 V Operating Temperature Range –40°C to +125°C Maximum Junction Temperature (T ) 150°C JMAX Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 – 30 sec) 245°C Thermal Resistance2 θ : TSOT-8 200°C/W JA 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX − TA)/θJA. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16

AD5165 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS W 1 8 A VDD 2 AD5165 7 B GCNLKD 34 (NToOt Pto V SIEcaWle) 56 CSDSI 04749-0-002 Figure 4. Table 4. Pin Name Description 1 W Wiper terminal. GND ≤ V ≤ V A DD. 2 V Positive Power Supply. DD 3 GND Digital Ground. 4 CLK Serial Clock Input. Positive-edge triggered. 5 SDI Serial Data Input (data loads MSB first). 6 CS Chip Select Input, active high. When CS returns low, data is loaded into the wiper register. 7 B B terminal. GND ≤ V ≤ V . A DD 8 A A terminal. GND ≤ V ≤ V . A DD Rev. 0 | Page 6 of 16

AD5165 TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.5 0.4 5.5V 0.4 –40°C 2.7V +25°C 0.3 SB) 0.3 +85°C LSB) 0.2 NL (L 0.2 +125°C E INL ( 0.1 ODE D 0.1 D M T MO 0 TER 0 A –0.1 E –0.1 T M RHEOS ––00..32 OTENTIO ––00..32 P –0.4 –0.4 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-011 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-008 Figure 5. R-INL vs. Code vs. Supply Voltages Figure 8. DNL vs. Code vs. Temperature, VDD = 5 V 0.5 0.5 5.5V 0.4 2.7V 0.4 B) 0.3 LSB) 0.3 52..57VV NL (LS 0.2 E INL ( 0.2 D 0.1 D 0.1 DE MO O 0 R 0 M E STAT –0.1 OMET –0.1 O –0.2 TI –0.2 H N E E R –0.3 OT –0.3 P –0.4 –0.4 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-013 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-007 Figure 6. R-DNL vs. Code vs. Supply Voltages Figure 9. INL vs. Code vs. Supply Voltages 0.5 0.5 –40°C 5.5V 0.4 +25°C 0.4 2.7V DE INL (LSB) 000...123 ++18255°C°C DE DNL (LSB) 000...123 O O M M R 0 R 0 METE –0.1 METE –0.1 O O NTI –0.2 NTI –0.2 OTE –0.3 OTE –0.3 P P –0.4 –0.4 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-006 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-009 Figure 7. INL vs. Code vs. Temperature , VDD = 5 V Figure 10. DNL vs. Code vs. Supply Voltages Rev. 0 | Page 7 of 16

AD5165 0.5 0.5 0.4 –40°C 0.4 +25°C 0.3 +85°C 0.3 B) +125°C L (LS 0.2 0.2 ZSE @ VDD = 5.5V E IN 0.1 B) 0.1 D S MO 0 E (L 0 T S TA –0.1 Z –0.1 ZSE @ VDD = 2.7V S EO –0.2 –0.2 H R –0.3 –0.3 –0.4 –0.4 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-010 –0.5–40 –20 0 2T0EMPER40ATURE6 0(°C) 80 100 120 04749-0-022 Figure 11. R-INL vs. Code vs. Temperature, VDD = 5 V Figure 14. Zero-Scale Error vs. Temperature 0.5 0.5 –40°C 0.4 +25°C 0.4 +85°C B) 0.3 +125°C 0.3 DNL (LS 00..12 NT (A)µ 00..12 IDD@ VDD = 5.5V HEOSTAT MODE ––00..021 SUPPLY CURRE ––00..021 IDD@ VDD = 2.7V R –0.3 –0.3 –0.4 –0.4 –0.50 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-012 –0.5–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 04749-0-020 Figure 12. R-DNL vs. Code vs. Temperature, VDD = 5 V Figure 15. Supply Current vs. Temperature 0.5 10000 0.4 1000 0.3 0.2 FSE @ VDD = 5.5V 100 B) 0.1 VDD = VA = 5V S A) FSE (L –0.01 I (µDD 10 VDD = VA = 2.7V FSE @ VDD = 2.7V –0.2 1 –0.3 0.1 –0.4 –0.5–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 04749-0-023 0.010 1 2VIH (0) (V)3 4 5 04749-0-025 Figure 13. Full-Scale Error vs. Temperature Figure 16. Supply Current vs. Digital Input Voltage Rev. 0 | Page 8 of 16

AD5165 1000 REF LEVEL /DIV MARKER 54 089.173Hz 0.000dB 6.000dB MAG (A/R) –9.052dB 0 100 VDD = VA = 5V –6 0x80 –12 0x40 VDD = VA = 2.7V 10 –18 0x20 A) (µD –24 0x10 D I –30 0x08 1 –36 0x04 –42 0x02 0.1 0x01 –48 0.010 1 2VIH (1MHz) (V3) 4 5 04749-0-026 ––56S40TA1kRT 1 000.000Hz 1 0 k 1 0S0TkOP 1 000 000.000H1zM 04749-0-048 Figure 17. Supply Current vs. Digital Input Voltage Figure 20. Gain vs. Frequency vs. Code, RAB = 100 kΩ 20 REF LEVEL /DIV –5.000dB 0.500dB 15 –5.5 m/°C) 10 –6.0 100kΩ– 54kHz pp –6.5 O ( 5 C –7.0 M E E T 0 –7.5 D MO –5 –8.0 T TA –8.5 S –10 O E –9.0 H R –15 R = 100kΩ –9.5 –200 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-015 ––1100S..05T1A0kRT 1 000.000Hz STOP 1 000 000.0001H0zM 04749-0-047 Figure 18. Rheostat Mode Tempco ∆RWB/∆T vs. Code Figure 21. –3 dB Bandwidth @ Code = 0x80 80 8 CODE = 80H, VA = VDD, VB = 0V C) 6 m/° p 60 O (p 4 PSRR @ VDD = 5V DC± 10% p-p AC C E TEMP 2 R (–dB) 40 PSRR @ VDD = 3V DC± 10% p-p AC D 0 R O S M P R –2 E T ME 20 O –4 TI N TE –6 O P –80 32 64 9C6ODE 1(D28ecima1l)60 192 224 256 04749-0-014 0100 1k FREQU1E0NkCY (Hz) 100k 1M 04749-0-019 Figure 19. Potentiometer Mode Tempco ∆VWB/∆T vs. Code Figure 22. PSRR vs. Frequency Rev. 0 | Page 9 of 16

AD5165 800 VDD = 5V VA = 5V 700 VB = 0V 600 500 1 VW A) µ (D 400 D I 2 300 CS 120000 CODE FFCHODE 55H Ch 1 100mV BWCh 2 5.00 V BWM 200ns A CH1 152mV 04749-0-028 Figure 26. Midscale Glitch, Code 0x80–0x7F 010k 100kFREQUENCY (Hz)1M 10M 04749-0-018 Figure 23. IDD vs. Frequency 1 VW 2 CS Ch 1 200mV BWCh 2 5.00 V BWM 100ns A CH2 3.00 V 04749-0-030 Figure 24. Large Signal Settling Time, Code 0xFF–0x00 1 VW CLK 2 Ch 1 200mV BWCh 2 5.00 V BWM 100ns A CH2 3.00 V 04749-0-030 Figure 25. Digital Feedthrough Rev. 0 | Page 10 of 16

AD5165 TEST CIRCUITS Figure 27 to Figure 33 illustrate the test circuits that define the test conditions used in the product specification tables. DUT V+ = VDD DUT +15V 1LSB = V+/2N A A W V+ W VIN B AD8610 VOUT B VMS 04749-0-031 OFFGSNEDT 2.5V –15V 04749-0-035 Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error Figure 31. Test Circuit for Gain vs. Frequency (INL, DNL) NO CONNECT DUT RSW= 0IS.1WV DUT A W IW W CODE = 0x00 B B ISW 0.1V VMS 04749-0-032 GND TO VDD 04749-0-036 Figure 28. Test Circuit for Resistor Position Nonlinearity Error Figure 32. Test Circuit for Incremental ON Resistance (Rheostat Operation; R-INL, R-DNL) DUT NC VMS2 A W VW IW = VDD/RNOMINAL VDD DUT A W ICM B VMS1 RW = [VMS1– VMS2]/IW 04749-0-033 GND NCB NC = NO CONNECT VCM 04749-0-037 Figure 29. Test Circuit for Wiper Resistance Figure 33. Test Circuit for Common-Mode Leakage Current VA V+ = VDD 10% ( ∆ V M S ) PSRR (dB) = 20 LOG V+ VDD A W PSS (%/%) =∆VMS% ∆VDD ∆VDD% B VMS 04749-0-034 Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Rev. 0 | Page 11 of 16

AD5165 3-WIRE DIGITAL INTERFACE Note that in the AD5165 data is loaded MSB first. Table 5. AD5165 Serial Data-Word Format B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 27 20 1 SDI D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK 0 1 CS RDAC REGISTER LOAD VOUT010 04749-0-004 Figure 34. 3-Wire Digital Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) Dx Dx 0 1 tCH tDS tDH tCS1 CLK 0 tCSHO tCL tCSH1 t CSS 1 CS t CSW 0 t S VOUT VDD0 ±1LSB 04749-0-005 Figure 35. 3-Wire Digital Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) Rev. 0 | Page 12 of 16

AD5165 THEORY OF OPERATION The AD5165 is a 256-position digitally controlled variable where: resistor (VR) device. D is the decimal equivalent of the binary code loaded in the PROGRAMMING THE VARIABLE RESISTOR 8-bit RDAC register. Rheostat Operation RAB is the end-to-end resistance. R is the wiper resistance contributed by the on resistance of W The nominal resistance of the RDAC between terminals A and the internal switch. B is available in 100 kΩ. The nominal resistance (R ) of the VR AB has 256 contact points accessed by the wiper terminal, plus the In summary, if RAB = 100 kΩ and the A terminal is open B terminal contact. The 8-bit data in the RDAC latch is decoded circuited, the following output resistance RWB is set for the to select one of the 256 possible settings. indicated RDAC latch codes. Table 6. Codes and Corresponding R Resistance WB A A A D (Dec.) R (Ω) Output State WB W W W 255 99,710 Full scale (R – 1 LSB + R ) AB W B B B 04749-0-038 112 8 5409,01 00 M1 LidSsBc ale 0 100 Zero scale (wiper contact resistance) Figure 36. Rheostat Mode Configuration Assuming that a 100 kΩ part is used, the wiper’s first connec- Note that, in the zero-scale condition, a finite wiper resistance tion starts at the B terminal for data 0x00. Because there is a of 100 Ω is present. Care should be taken to limit the current 50 Ω wiper contact resistance, such a connection yields a mini- flow between W and B in this state to a maximum pulse current mum of 100 Ω (2 × 50 Ω) resistance between terminals W and of no more than 20 mA. Otherwise, degradation or possible B. The second connection is the first tap point, which corres- destruction of the internal switch contact can occur. ponds to 490 Ω (R = R /256 + 2 × R = 390 Ω + 2 × 50 Ω) WB AB W Similar to the mechanical potentiometer, the resistance of the for data 0x01. The third connection is the next tap point, RDAC between the wiper W and terminal A also produces a representing 880 Ω (2 × 390 Ω + 2 × 50 Ω) for data 0x02, and digitally controlled complementary resistance, R . When these so on. Each LSB data value increase moves the wiper up the WA terminals are used, the B terminal can be opened. Setting the resistor ladder until the last tap point is reached at 100,100 Ω resistance value for R starts at a maximum value of resistance (R + 2 × R ). WA AB W and decreases as the data loaded in the latch increases in value. A The general equation for this operation is RS 256−D R (D)= ×R +2×R (2) WA 256 AB W D7 RS D6 D5 For R = 100 kΩ with the B terminal open circuited, the D4 AB DD32 RS following output resistance RWA is set for the indicated RDAC D1 latch codes. D0 W Table 7. Codes and Corresponding R Resistance WA D (Dec.) R (Ω) Output State WA 255 490 Full scale 128 50,100 Midscale RDAC RS 1 99, 710 1 LSB LATCH AND B 0 100,100 Zero scale DECODER 04749-0-039 Typical device-to-device matching is process-lot dependent and may vary by up to ±20%. Because the resistance element Figure 37. AD5165 Equivalent RDAC Circuit is processed in thin film technology, the change in RAB with temperature has a very low 35 ppm/°C temperature coefficient. The general equation determining the digitally programmed output resistance between W and B is D R (D)= ×R +2×R (1) WB 256 AB W Rev. 0 | Page 13 of 16

AD5165 PROGRAMMING THE POTENTIOMETER DIVIDER The data setup and data hold times in the specifications table Voltage Output Operation determine the valid timing requirements. The AD5165 uses an The digital potentiometer easily generates a voltage divider at 8-bit serial input data register word that is transferred to the wiper-to-B and wiper-to-A proportional to the input voltage at internal RDAC register when the CS line returns to logic low. A to B. Unlike the polarity of V to GND, which must be Extra MSB bits are ignored. DD positive, voltage across A to B, W to A, and W to B can be at ESD PROTECTION either polarity. All digital inputs are protected with a series of input resistors VI and parallel Zener ESD structures, shown in Figure 39 and A Figure 40. This applies to the digital input pins SDI, CLK, W VO and CS. Figure 38. PotentioBmeter Mode Conf04749-0-040ig uration GN34D0Ω LOGIC 04749-0-041 If ignoring the effect of the wiper resistance for approximation, Figure 39. ESD Protection of Digital Pins connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the A, B, W voltage applied across terminals A and B divided by the 256 pdeofsiintiionngs t ohfe tohuet ppuott evnotlitoamgee atetr V dWiv widitehr. rTehspe egcetn teor galr oeuqunadt ifoonr any GND 04749-0-042 valid input voltage applied to terminals A and B is Figure 40. ESD Protection of Resistor Terminals D 256−D V (D)= V + V (3) W 256 A 256 B TERMINAL VOLTAGE OPERATING RANGE A more accurate calculation, which includes the effect of wiper The AD5165 V and GND power supply defines the boundary DD resistance, VW, is conditions for proper 3-terminal digital potentiometer oper- ation. Supply signals present on terminals A, B, and W that R (D) R (D) VW(D)= WRB VA+ WRA VB (4) exceed VDD or GND are clamped by the internal forward-biased AB AB diodes, as shown in Figure 41. Operation of the digital potentiometer in the divider mode VDD results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on A the ratio of the internal resistors RWA and RWB and not the W absolute values. Therefore, the temperature drift reduces to B 135- W ppIRmE/° SCE. RIAL BUS DIGITAL INTERFACE GND 04749-0-043 The AD5165 contains a 3-wire digital interface (SDI, CS, and Figure 41. Maximum Terminal Voltages Set by VDD and GND CLK). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table 5. POWER-UP SEQUENCE The positive-edge sensitive CLK input requires clean transitions Because the ESD protection diodes limit the voltage compliance to avoid clocking incorrect data into the serial input register. at terminals A, B, and W (see Figure 41), it is important to Standard logic families work well. If mechanical switches are power VDD/GND before applying any voltage to terminals A, B, used for product evaluation, they should be debounced by a and W; otherwise, the diode is forward biased such that VDD is flip-flop or other suitable means. When CS is high, the clock powered unintentionally and may affect the rest of the user’s loads data into the serial register on each positive clock edge, circuit. The ideal power-up sequence is in the following order: as shown in Figure 34. GND, VDD, digital inputs, and then VA, VB, and VW. The relative order of powering V , V , V , and the digital inputs is not A B W important as long as they are powered after V /GND. DD Rev. 0 | Page 14 of 16

AD5165 LAYOUT AND POWER SUPPLY BYPASSING EVALUATION BOARD It is good practice to employ compact, minimum lead length An evaluation board, along with all necessary software, is layout design. The leads to the inputs should be as direct as available to program the AD5165 from any PC running possible with a minimum conductor length. Ground paths Windows® 98/2000/XP. The graphical user interface, as shown should have low resistance and low inductance. in Figure 43, is straightforward and easy to use. More detailed information is available in the user manual, which comes with Similarly, it is also good practice to bypass the power supplies the board. with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disk or chip ceramic capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 42). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce. VDD + VDD 04749-0-046 C3 C1 10µF 0.1µF AD5165 Figure 43. AD5165 Evaluation Board Software The AD5165 starts at midscale upon power-up. To increment or decrement the resistance, the user may move the scroll bars GND on the left. To write any specific value, the user should use the 04749-0-044 bfoitr mpaattt eorfn w inri ttihneg udpaptae rt os ctrheee nd eavnicde c ilsi cskh othwen R iunn F biguuttroen 3. 2T. he Figure 42. Power Supply Bypassing Rev. 0 | Page 15 of 16

AD5165 OUTLINE DIMENSIONS 2.90BSC 8 7 6 5 1.60BSC 2.80BSC 1 2 3 4 PIN 1 INDICATOR 0.65BSC 1.95 0.90 BSC 0.87 0.84 1.00MAX 0.20 0.08 0.60 0.10MAX 00..3282 SEATING 84°° 00..4350 PLANE 0° COMPLIANT TO JEDEC STANDARDS MO-193BA Figure 44. 8-Lead Thin Small Outline Transistor Package [Thin SOT-23] (UJ-8) Dimensions shown in millimeters ORDERING GUIDE Model R (Ω) Temperature Package Description Package Option Quantity on Reel Branding AB AD5165BUJZ100-R21 100 k –40°C to +125°C Thin SOT-23 UJ-8 250 D3N AD5165BUJZ100-R71 100 k –40°C to +125°C Thin SOT-23 UJ-8 3,000 D3N AD5165EVAL Evaluation Board 1 Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04749–0–4/04(0) Rev. 0 | Page 16 of 16

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5165BUJZ100-R2 AD5165BUJZ100-R7 EVAL-AD5165DBZ