256-Position SPI/I2C Selectable Digital Potentiometer Data Sheet AD5161 FEATURES FUNCTIONAL BLOCK DIAGRAM 256-position VDD SDO/NC End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ SDI/SDA Compact MSOP-10 (3 mm × 4.9 mm) package A CLK/SCL SPI OR I2C Pin selectable SPI/I2C compatible interface INTERFACE DIS Extra package address decode pin AD0 CS/AD0 W Full read/write of wiper register Power-on preset to midscale WIPER B Single supply 2.7 V to 5.5 V REGISTER Low temperature coefficient 45 ppm/°C Low power, I = 8 μA DD GND Wide operating temperature −40°C to +125°C SDO output allows multiple device daisy-chaining Figure 1. Evaluation board available APPLICATIONS PIN CONFIGURATION Mechanical potentiometer replacement in new designs A 1 10 W Transducer adjustment of pressure, temperature, position, B 2 AD5161 9 VDD chemical, and optical sensors CS/ADO 3 TOP VIEW 8 DIS RF amplifier biasing SDO/NC 4 (Not to Scale) 7 GND Gain control and offset adjustment SDI/SDA 5 6 CLK/SCL Figure 2. GENERAL DESCRIPTION The AD5161 provides a compact 3 mm × 4.9 mm packaged solution for 256-position adjustment applications. These devices perform the same electronic adjustment function as mechanical potentiometers or variable resistors, with enhanced resolution, solid-state reliability, and superior low temperature coefficient performance. The wiper settings are controllable through a pin selectable SPI or I2C compatible digital interface, which can also be used to read back the wiper register content. When the SPI mode is used, the device can be daisy-chained (SDO to SDI), allowing several parts to share the same control lines. In the I2C mode, address pin AD0 can be used to place up to two devices on the same bus. In this same mode, command bits are available to reset the wiper position to midscale or to shut down the device into a state of zero power consumption. Operating from a 2.7 V to 5.5 V power supply and consuming less than 5 μA allows for usage in portable battery-operated applications. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5161 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SPI Interface .................................................................................... 13 Applications ....................................................................................... 1 I2C Interface .................................................................................... 14 General Description ......................................................................... 1 Theory of Operation ...................................................................... 15 Functional Block Diagram .............................................................. 1 Programming the Variable Resistor ......................................... 15 Pin Configuration ............................................................................. 1 Programming the Potentiometer Divider ............................... 16 Revision History ............................................................................... 2 Pin Selectable Digital Interface ................................................. 16 Electrical Characteristics—5 kΩ Version ........................................ 3 Level Shifting for Bidirectional Interface ................................ 18 Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ......... 4 ESD Protection ........................................................................... 18 Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions .. 5 Terminal Voltage Operating Range ......................................... 18 Absolute Maximum Ratings ............................................................ 6 Power-Up Sequence ................................................................... 18 ESD Caution .................................................................................. 6 Layout and Power Supply Bypassing ....................................... 18 Pin Configuration and Function Descriptions ............................. 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 19 Test Circuits ..................................................................................... 12 REVISION HISTORY 6/15—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 19 8/12—Rev. A to Rev. B Changes to Applications Section .................................................... 1 Updated Outline Dimensions ....................................................... 19 4/09—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 19 5/03—Revision 0: Initial Version Rev. C | Page 2 of 20

Data Sheet AD5161 ELECTRICAL CHARACTERISTICS—5 kΩ VERSION V = 5 V ± 10%, or 3 V ± 10%; V = +V ; V = 0 V; −40°C < T < +125°C; unless otherwise noted. DD A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1.5 ±0.1 +1.5 LSB Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −4 ±0.75 +4 LSB Nominal Resistor Tolerance3 ∆R T = 25°C −30 +30 % AB A Resistance Temperature Coefficient ∆R /∆T V = V , Wiper = no connect 45 ppm/°C AB AB DD Wiper Resistance R 50 120 Ω W DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N 8 Bits Differential Nonlinearity4 DNL −1.5 ±0.1 +1.5 LSB Integral Nonlinearity4 INL −1.5 ±0.6 +1.5 LSB Voltage Divider Temperature Coefficient ∆V /∆T Code = 0x80 15 ppm/°C W Full-Scale Error V Code = 0xFF −6 −2.5 0 LSB WFSE Zero-Scale Error V Code = 0x00 0 +2 +6 LSB WZSE RESISTOR TERMINALS Voltage Range5 V GND V V A,B,W DD Capacitance6 A, B C f = 1 MHz, measured to GND, 45 pF A,B Code = 0x80 Capacitance6 W C f = 1 MHz, measured to GND, 60 pF W Code = 0x80 Shutdown Supply Current7 I V = 5.5 V 0.01 1 µA DD_SD DD Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V 2.4 V IH Input Logic Low V 0.8 V IL Input Logic High V V = 3 V 2.1 V IH DD Input Logic Low V V = 3 V 0.6 V IL DD Input Current I V = 0 V or 5 V ±1 µA IL IN Input Capacitance6 C 5 pF IL POWER SUPPLIES Power Supply Range V 2.7 5.5 V DD RANGE Supply Current I V = 5 V or V = 0 V 3 8 µA DD IH IL Power Dissipation8 P V = 5 V or V = 0 V, V = 5 V 0.2 mW DISS IH IL DD Power Supply Sensitivity PSS ∆V = +5 V ± 10%, ±0.02 ±0.05 %/% DD Code = Midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth −3dB BW_5K R = 5 kΩ, Code = 0x80 1.2 MHz AB Total Harmonic Distortion THD V = 1 V rms, V = 0 V, f = 1 kHz 0.05 % W A B V Settling Time t V = 5 V, V = 0 V, ±1 LSB error band 1 µs W S A B Resistor Noise Voltage Density e R = 2.5 kΩ, RS = 0 6 nV/√Hz N_WB WB Rev. C | Page 3 of 20

AD5161 Data Sheet ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS V = 5 V ± 10%, or 3 V ± 10%; V = V ; V = 0 V; −40°C < T < +125°C; unless otherwise noted. DD A DD B A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±0.1 +1 LSB Resistor Integral Nonlinearity2 R-INL RWB, VA = no connect −2 ±0.25 +2 LSB Nominal Resistor Tolerance3 ∆R T = 25°C −30 +30 % AB A Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD, 45 ppm/°C Wiper = no connect Wiper Resistance R V = 5 V 50 120 Ω W DD DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs) Resolution N 8 Bits Differential Nonlinearity4 DNL −1 ±0.1 +1 LSB Integral Nonlinearity4 INL −1 ±0.3 +1 LSB Voltage Divider Temperature Coefficient ∆V /∆T Code = 0x80 15 ppm/°C W Full-Scale Error V Code = 0xFF −3 −1 0 LSB WFSE Zero-Scale Error V Code = 0x00 0 1 3 LSB WZSE RESISTOR TERMINALS Voltage Range5 V GND V V A,B,W DD Capacitance6 A, B C f = 1 MHz, measured to 45 pF A,B GND, Code = 0x80 Capacitance6 W C f = 1 MHz, measured to 60 pF W GND, Code = 0x80 Shutdown Supply Current7 I V = 5.5 V 0.01 1 µA DD_SD DD Common-Mode Leakage I V = V = V /2 1 nA CM A B DD DIGITAL INPUTS AND OUTPUTS Input Logic High V 2.4 V IH Input Logic Low V 0.8 V IL Input Logic High V V = 3 V 2.1 V IH DD Input Logic Low V V = 3 V 0.6 V IL DD Input Current I V = 0 V or 5 V ±1 µA IL IN Input Capacitance6 C 5 pF IL POWER SUPPLIES Power Supply Range V 2.7 5.5 V DD RANGE Supply Current I V = 5 V or V = 0 V 3 8 µA DD IH IL Power Dissipation8 P V = 5 V or V = 0 V, 0.2 mW DISS IH IL V = 5 V DD Power Supply Sensitivity PSS ∆V = +5 V ± 10%, ±0.02 ±0.05 %/% DD Code = Midscale DYNAMIC CHARACTERISTICS6, 9 Bandwidth −3dB BW R = 10 kΩ/50 kΩ/100 kΩ, 600/100/40 kHz AB Code = 0x80 Total Harmonic Distortion THD V =1 V rms, V = 0 V, 0.05 % W A B f = 1 kHz, R = 10 kΩ AB V Settling Time (10 kΩ/50 kΩ/100 kΩ) t V = 5 V, V = 0 V, 2 µs W S A B ±1 LSB error band Resistor Noise Voltage Density e R = 5 kΩ, RS = 0 9 nV/√Hz N_WB WB Rev. C | Page 4 of 20

Data Sheet AD5161 TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS V = +5V ± 10%, or +3V ± 10%; V = V ; V = 0 V; −40°C < T < +125°C; unless otherwise noted. DD A DD B A Table 3. Parameter Symbol Conditions Min Typ1 Max Unit SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts) Clock Frequency f 25 MHz CLK Input Clock Pulsewidth t , t Clock level high or low 20 ns CH CL Data Setup Time t 5 ns DS Data Hold Time t 5 ns DH CS Setup Time tCSS 15 ns CS High Pulsewidth tCSW 40 ns CLK Fall to CS Fall Hold Time tCSH0 0 ns CLK Fall to CS Rise Hold Time tCSH1 0 ns CS Rise to Clock Rise Setup tCS1 10 ns I2C INTERFACE TIMING CHARACTERISTICS6, 11 (Specifications Apply to All Parts) SCL Clock Frequency f 400 kHz SCL t Bus Free Time between STOP and START t 1.3 µs BUF 1 t Hold Time (Repeated START) t After this period, the first clock pulse is 0.6 µs HD;STA 2 generated. t Low Period of SCL Clock t 1.3 µs LOW 3 t High Period of SCL Clock t 0.6 50 µs HIGH 4 t Setup Time for Repeated START Condition t 0.6 µs SU;STA 5 t Data Hold Time t 0.9 µs HD;DAT 6 t Data Setup Time t 100 ns SU;DAT 7 t Fall Time of Both SDA and SCL Signals t 300 ns F 8 t Rise Time of Both SDA and SCL Signals t 300 ns R 9 t Setup Time for STOP Condition t 0.6 µs SU;STO 10 NOTES 1 Typical specifications represent average readings at +25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 Measured at the A terminal. The A terminal is open circuited in shutdown mode. 8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use VDD = 5 V. 10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. 11 See timing diagrams for locations of measured values. Rev. C | Page 5 of 20

AD5161 Data Sheet ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Table 4. Ratings may cause permanent damage to the product. This is a Parameter Value stress rating only; functional operation of the product at these V to GND −0.3 V to +7 V DD or any other conditions above those indicated in the operational V , V , V to GND V A B W DD section of this specification is not implied. Operation beyond I 1 ±20 mA MAX the maximum operating conditions for extended periods may Digital Inputs and Output Voltage to GND 0 V to +7 V affect product reliability. Operating Temperature Range −40°C to +125°C Maximum Junction Temperature (T ) 150°C JMAX Storage Temperature Range −65°C to +150°C ESD CAUTION Lead Temperature (Soldering, 10 sec) 300°C Thermal Resistance2 θ (10-Lead MSOP) 200°C/W JA NOTES 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Package power dissipation = (TJMAX − TA)/θJA. Rev. C | Page 6 of 20

Data Sheet AD5161 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A 1 10 W B 2 AD5161 9 VDD CS/ADO 3 TOP VIEW 8 DIS SDO/NC 4 (Not to Scale) 7 GND SDI/SDA 5 6 CLK/SCL Figure 3. Pin Configuration Table 5. Pin Function Description Pin No. Mnemonic Description 1 A A Terminal. 2 B B Terminal. 3 CS/AD0 Chip Select (CS) Input, Active Low. When CS returns high, data will be loaded into the DAC register. Programmable address bit 0 (AD0) for multiple package decoding. 4 SDO/NC Serial Data Output (SDO). Open-drain transistor requires pull-up resistor. No Connect (NC). 5 SDI/SDA Serial Data Input (SDI). Serial Data Input/Output (SDA). 6 CLK/SCL Serial Clock Input. Positive edge triggered. 7 GND Digital Ground. 8 DIS Digital Interface Select (SPI/I2C Select). SPI when DIS = 0, I2C when DIS = 1. 9 V Positive Power Supply. DD 10 W W Terminal. Rev. C | Page 7 of 20

AD5161 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 5V 0.8 –40°C 3V +25°C DE INL (LSB) 000...246 DE DNL (LSB) 000...246 ++18255°°CC MO 0 MO 0 OSTAT –0.2 METER –0.2 RHE–0.4 TIO–0.4 –0.6 EN–0.6 T O –0.8 P–0.8 –1.0 –1.0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 4. R-INL vs. Code vs. Supply Voltages Figure 7. DNL vs. Code, VDD = 5 V 1.0 1.0 DNL (LSB) 000...468 35VV E INL (LSB) 000...468 53VV DE 0.2 OD 0.2 O M T M 0 ER 0 A T ST–0.2 ME–0.2 O O RHE–0.4 ENTI–0.4 T –0.6 PO–0.6 –0.8 –0.8 –1.0 –1.0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 5. R-DNL vs. Code vs. Supply Voltages Figure 8. INL vs. Code vs. Supply Voltages 1.0 1.0 0.8 _40°C 0.8 5V +25°C B) 3V SB) 0.6 ++18255°°CC L(LS 0.6 E INL (L 00..24 ODE DN 00..24 D M MO 0 ER 0 TER –0.2 MET–0.2 E O OM–0.4 NTI–0.4 TENTI–0.6 POTE–0.6 O P –0.8 –0.8 –1.0 –1.0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 CODE (Decimal) CODE (Decimal) Figure 6. INL vs. Code, VDD = 5 V Figure 9. DNL vs. Code vs. Supply Voltages Rev. C | Page 8 of 20

Data Sheet AD5161 1.0 2.5 –40°C 0.8 +25°C NL (LSB) 00..46 ++18255°°CC OR (A)2.0 DE I 0.2 ERR1.5 VDD = 5.5V RHEOSTAT MO––00..042 E, ZERO-SCALE 1.0 VDD = 2.7V S –0.6 Z0.5 –0.8 –1.0 0 0 32 64 96 128 160 192 224 256 ––4400 00 4400 8800 112200 CODE (Decimal) TEMPERATURE (°C) Figure 10. R-INL vs. Code, VDD = 5 V Figure 13. Zero-Scale Error vs. Temperature 1.0 10 _40°C 0.8 +25°C B) +85°C S 0.6 +125°C DE DNL (L 00..24 RENT (A) VDD = 5.5V O R M U AT 0 Y C 1 T L S–0.2 P O P E U RH–0.4 SD D –0.6 I VDD = 2.7V –0.8 –1.0 0.1 0 32 64 96 128 160 192 224 256 –40 0 40 80 120 CODE (Decimal) TEMPERATURE (°C) Figure 11. R-DNL vs. Code, VDD = 5 V Figure 14. Supply Current vs. Temperature 2.5 70 60 SB)2.0 A) E ERROR (L1.5 VDD = 2.7V CURRENT (n 4500 AL N L-SC1.0 DOW 30 FUL VDD = 5.5V HUT 20 VDD = 5V FSE, 0.5 ISA 10 0 0 ––4400 00 4400 8800 112200 –40 0 40 80 120 TEMPERATURE (°C) TEMPERATURE (°C) Figure 12. Full-Scale Error vs. Temperature Figure 15. Shutdown Current vs. Temperature Rev. C | Page 9 of 20

AD5161 Data Sheet 200 REF LEVEL /DIV MARKER 510 634.725Hz 0.000dB 6.000dB MAG (A/R) –9.049dB 0 C) m/° 150 –6 0x80 p O (p –12 0x40 C MP 100 –18 0x20 E T 0x10 E –24 D O 0x08 M 50 –30 T 0x04 A ST –36 0x02 O E 0 –42 0x01 H R –48 –50 –54 0 32 64 96 128 160 192 224 256 CODE (Decimal) –60 1k 10k 100k 1M START 1 000.000Hz STOP 1 000 000.000Hz Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ 160 REF LEVEL /DIV MARKER 100 885.289Hz 0.000dB 6.000dB MAG (A/R) –9.014dB m/°C)140 0 (pp120 –6 0x80 CO –12 0x40 P100 EM –18 0x20 ODE T 80 –24 0x10 M 60 R –30 0x08 E MET 40 –36 0x04 O NTI 20 –42 0x02 OTE 0 –48 0x01 P –20 –54 0 32 64 96 128 160 192 224 256 CODE (Decimal) –60 1k 10k 100k 1M START 1 000.000Hz STOP 1 000 000.000Hz Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ REF LEVEL /DIV MARKER 1 000 000.000Hz REF LEVEL /DIV MARKER 54 089.173Hz 0.000dB 6.000dB MAG (A/R) –8.918dB 0.000dB 6.000dB MAG (A/R) –9.052dB 0 0 –6 0x80 –6 0x80 –12 0x40 –12 0x40 –18 0x20 –18 0x20 –24 0x10 –24 0x10 0x08 –30 0x04 –30 0x08 –36 00xx0021 –36 0x04 –42 –42 0x02 –48 –48 0x01 –54 –54 –60 –60 1k 10k 100k 1M 1k 10k 100k 1M START 1 000.000Hz STOP 1 000 000.000Hz START 1 000.000Hz STOP 1 000 000.000Hz Figure 18. Gain vs. Frequency vs. Code, RAB = 5 kΩ Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ Rev. C | Page 10 of 20

Data Sheet AD5161 REF LEVEL /DIV –5.000dB 0.500dB –5.5 –6.0 5k– 1.026 MHz 10k– 511 MHz –6.5 50k– 101 MHz 100k– 54 MHz –7.0 1 VW –7.5 –8.0 CLK –8.5 R = 50k R = 5k 2 –9.0 –9.5 R = 100k R = 10k Ch 1 200mV BWCh 2 5.00 V BWM 100ns A CH2 3.00 V –10.0 –10.5 10k 100k 1M 10M START 1 000.000Hz STOP 1 000 000.000Hz Figure 22. −3 dB Bandwidth @ Code = 0x80 Figure 25. Digital Feedthrough 60 CODE = 0x80, VA= VDD, VB = 0V VA = 5V VB = 0V 40 B) d 1 VW RR ( PSRR @ VDD = 3V DC± 10% p-p AC S P CS 20 2 PSRR @ VDD = 5V DC± 10% p-p AC Ch 1 100mV BWCh 2 5.00 V BWM 200ns A CH1 152mV 0 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 23. PSRR vs. Frequency Figure 26. Midscale Glitch, Code 0x80−0x7F 900 VDD= 5V 800 VA = 5V VB = 0V 700 600 500 1 VW A) (D 400 CODE = 0x55 D I 300 CS CODE = 0xFF 2 200 100 Ch 1 5.00V BWCh 2 5.00 V BWM 200ns A CH1 3.00 V 0 10k 100k 1M 10M FREQUENCY (Hz) Figure 24. IDD vs. Frequency Figure 27. Large Signal Settling Time, Code 0xFF−0x00 Rev. C | Page 11 of 20

AD5161 Data Sheet TEST CIRCUITS Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables. 5V OP279 VOUT DUT V+= VDD VIN 1LSB = V+/2N W A V+ W OFFSET GND A DUT B B VMS OFFSET BIAS Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 33. Test Circuit for Noninverting Gain NO CONNECT DUT A IW +15V A W W VIN DUT B OFFSET AD8610 VOUT VMS GND B 2.5V –15V Figure 29. Test Circuit for Resistor Position Nonlinearity Error Figure 34. Test Circuit for Gain vs. Frequency (Rheostat Operation; R-INL, R-DNL) 0.1V DUT RSW= ISW CODE = 0x00 DUT W VMS2 A W VW IW= VDD/RNOMINAL B ISW 0.1V B VMS1 RW= [VMS1– VMS2]/IW VSS TO VDD Figure 30. Test Circuit for Wiper Resistance Figure 35. Test Circuit for Incremental ON Resistance VA NC V+ VDD A W PPV+SS SR= RV(% D(dD/%B))1 ==0 %20V LMOS%G(  VV MD DS ) VDD DUT AW ICM B VDD% VSS GND B VCM VMS NC NC = NO CONNECT Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Figure 36. Test Circuit for Common-Mode Leakage Current A DUT B 5V VIN W OFFSET OP279 VOUT GND OFFSET BIAS Figure 32. Test Circuit for Inverting Gain Rev. C | Page 12 of 20

Data Sheet AD5161 SPI INTERFACE 1 SDI D7 D6 D5 D4 D3 D2 D1 D0 Table 6. AD5161 Serial Data-Word Format 0 1 B7 B6 B5 B4 B3 B2 B1 B0 CLK 0 D7 D6 D5 D4 D3 D2 D1 D0 1 RDAC REGISTER LOAD CS MSB LSB 0 1 27 20 VOUT 0 Figure 37. SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) 1 SDI (DATA IN) Dx Dx 0 1 tCH tDS tCH tCS1 CLK 0 tCSHO tCL tCSH1 tCSS 1 CS tCSW 0 tS VDD VOUT ±1LSB 0 Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT) Rev. C | Page 13 of 20

AD5161 Data Sheet I2C INTERFACE Table 7. Write Mode S 0 1 0 1 1 0 AD0 W A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Instruction Byte Data Byte Table 8. Read Mode S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte S = Start Condition R = Read P = Stop Condition RS = Reset wiper to Midscale 80 H A = Acknowledge SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register. X = Don’t Care D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits. W = Write t8 t9 t2 SCL t6 t2 t3 t4 t7 t5 t10 t9 t8 SDA t1 P S S P Figure 39. I2C Interface Detailed Timing Diagram 1 9 1 9 1 9 SCL SDA 0 1 0 1 1 0 AD0 R/W X RS SD X X X X X D7 D6 D5 D4 D3 D2 D1 D0 ACK BY ACK BY ACK BY AD5161 AD5161 AD5161 START BY FRAME 1 FRAME 2 FRAME 3 STOP BY MASTER SLAVE ADDRESS BYTE INSTRUCTION BYTE DATA BYTE MASTER Figure 40. Writing to the RDAC Register 1 9 1 9 SCL SDA 0 1 0 1 1 0 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 ACK BY NO ACK AD5161 BY MASTER START BY FRAME 1 FRAME 2 STOP BY MASTER SLAVE ADDRESS BYTE RDAC REGISTER MASTER Figure 41. Reading Data from a Previously Selected RDAC Register in Write Mode Rev. C | Page 14 of 20

Data Sheet AD5161 THEORY OF OPERATION The AD5161 is a 256-position digitally controlled variable The general equation determining the digitally programmed resistor (VR)1 device. output resistance between W and B is An internal power-on preset places the wiper at midscale during D R (D) R R (1) power-on, which simplifies the fault condition recovery at power-up. WB 256 AB W PROGRAMMING THE VARIABLE RESISTOR where D is the decimal equivalent of the binary code loaded in Rheostat Operation the 8-bit RDAC register, RAB is the end-to-end resistance, and R is the wiper resistance contributed by the on resistance of The nominal resistance of the RDAC between terminals A and W the internal switch. B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two or three digits of the part number determine the nominal resistance In summary, if RAB = 10 kΩ and the A terminal is open circuited, value, e.g., 10 kΩ = 10; 50 kΩ = 50. The nominal resistance (RAB) of the following output resistance RWB will be set for the indicated the VR has 256 contact points accessed by the wiper terminal, RDAC latch codes. plus the B terminal contact. The 8-bit data in the RDAC latch is Table 9. Codes and Corresponding R Resistance WB decoded to select one of the 256 possible settings. Assume a 10 kΩ D (Dec.) R (Ω) Output State part is used, the wiper’s first connection starts at the B terminal WB 255 9,961 Full Scale (R − 1 LSB + R ) for data 0x00. Since there is a 60 Ω wiper contact resistance, such AB W 128 5,060 Midscale connection yields a minimum of 60 Ω resistance between 1 99 1 LSB Terminals W and B. The second connection is the first tap point, 0 60 Zero Scale (Wiper Contact Resistance) which corresponds to 99 Ω (R = R /256 + R = 39 Ω + 60 Ω) WB AB W for data 0x01. The third connection is the next tap point, Note that in the zero-scale condition a finite wiper resistance of representing 177 Ω (2 × 39 Ω + 60 Ω) for data 0x02 and so on. Each 60 Ω is present. Care should be taken to limit the current flow LSB data value increase moves the wiper up the resistor ladder between W and B in this state to a maximum pulse current of until the last tap point is reached at 9961 Ω (R − 1 LSB + R ). no more than 20 mA. Otherwise, degradation or possible AB W Figure 42 shows a simplified diagram of the equivalent RDAC destruction of the internal switch contact can occur. circuit where the last resistor string will not be accessed; Similar to the mechanical potentiometer, the resistance of the therefore, there is 1 LSB less of the nominal resistance at full RDAC between the wiper W and terminal A also produces a scale in addition to the wiper resistance. digitally controlled complementary resistance R . When these WA A terminals are used, the B terminal can be opened. Setting the SD BIT resistance value for RWA starts at a maximum value of resistance RS and decreases as the data loaded in the latch increases in value. D7 The general equation for this operation is DD65 RS 256D D4 R (D) R R (2) DD23 RS WA 256 AB W D1 D0 W For R = 10 kΩ and the B terminal open circuited, the AB following output resistance R will be set for the indicated WA RDAC RDAC latch codes. LATCH AND RS B Table 10. Codes and Corresponding RWA Resistance DECODER D (Dec.) R (Ω) Output State WA 255 99 Full Scale Figure 42. AD5161 Equivalent RDAC Circuit 128 5,060 Midscale 1 9,961 1 LSB 1 The terms digital potentiometer, VR, and RDAC are used interchangeably. 0 10,060 Zero Scale Typical device to device matching is process lot dependent and may vary by up to ±30%. Since the resistance element is processed in thin film technology, the change in R with temperature has AB a very low 45 ppm/°C temperature coefficient. Rev. C | Page 15 of 20

AD5161 Data Sheet PROGRAMMING THE POTENTIOMETER DIVIDER Daisy-Chain Operation Voltage Output Operation The serial data output (SDO) pin contains an open-drain The digital potentiometer easily generates a voltage divider at N-channel FET. This output requires a pull-up resistor in order wiper-to-B and wiper-to-A proportional to the input voltage at to transfer data to the next package’s SDI pin. This allows for A-to-B. Unlike the polarity of V to GND, which must be daisy-chaining several RDACs from a single processor serial DD positive, voltage across A-B, W-A, and W-B can be at either data line. The pull-up resistor termination voltage can be larger polarity. than the VDD supply voltage. It is recommended to increase the clock period when using a pull-up resistor to the SDI pin of the If ignoring the effect of the wiper resistance for approximation, following device because capacitive loading at the daisy-chain connecting the A terminal to 5 V and the B terminal to ground node SDO-SDI between devices may induce time delay to produces an output voltage at the wiper-to-B starting at 0 V up subsequent devices. Users should be aware of this potential to 1 LSB less than 5 V. Each LSB of voltage is equal to the problem to achieve data transfer successfully (see Figure 43). If voltage applied across terminal AB divided by the 256 positions two AD5161s are daisy-chained, a total of at least 16 bits of data of the potentiometer divider. The general equation defining the is required. The first eight bits, complying with the format output voltage at V with respect to ground for any valid input W shown in Table 6, go to U2 and the second eight bits with the voltage applied to terminals A and B is same format go to U1. CS should be kept low until all 16 bits are V (D) D V 256DV (3) clocked into their respective serial registers. After this, CS is W 256 A 256 B pulled high to complete the operation and load the RDAC latch. For a more accurate calculation, which includes the effect of If the data word during the CS low period is greater than 16 wiper resistance, VW, can be found as bits, any additional MSBs will be discarded. V (D) RWB(D)V RWA(D)V (4) VDD W A B 256 256 Operation of the digital potentiometer in the divider mode AD5161 AD5161 results in a more accurate operation over temperature. Unlike C U1 R2.P2k U2 MOSI SDI SDO SDI SDO the rheostat mode, the output voltage is dependent mainly on CLK SC CS CLK CS CLK the ratio of the internal resistors R and R and not the WA WB absolute values. Therefore, the temperature drift reduces to 15 ppm/°C. Figure 43. Daisy-Chain Configuration PIN SELECTABLE DIGITAL INTERFACE I2C Compatible 2-Wire Serial Bus (DIS = 1) The AD5161 provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI The AD5161 can also be controlled via an I2C compatible serial mode is engaged. When the DIS pin is tied high, the I2C mode bus with DIS tied high. The RDACs are connected to this bus as is engaged. slave devices. SPI Compatible 3-Wire Serial Bus (DIS = 0) The first byte of the AD5161 is a slave address byte (see Table 7 and Table 8). It has a 7-bit slave address and a R/W bit. The six The AD5161 contains a 3-wire SPI compatible digital interface MSBs of the slave address are 010110, and the following bit is (SDI, CS, and CLK). The 8-bit serial word must be loaded MSB determined by the state of the AD0 pin of the device. AD0 first. The format of the word is shown in Table 6. allows the user to place up to two of the I2C compatible devices The positive-edge sensitive CLK input requires clean transitions on one bus. to avoid clocking incorrect data into the serial input register. The 2-wire I2C serial bus protocol operates as follows: Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a 1. The master initiates data transfer by establishing a START flip-flop or other suitable means. When CS is low, the clock condition, which is when a high-to-low transition on the loads data into the serial register on each positive clock edge SDA line occurs while SCL is high (see Figure 40). The (see Figure 37). following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit The data setup and data hold times in the specification table determines whether data will be read from or written to determine the valid timing requirements. The AD5161 uses an the slave device). 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. Rev. C | Page 16 of 20

Data Sheet AD5161 The slave whose address corresponds to the transmitted 5. When all data bits have been read or written, a STOP address responds by pulling the SDA line low during the condition is established by the master. A STOP condition is ninth clock pulse (this is termed the acknowledge bit). At defined as a low-to-high transition on the SDA line while this stage, all other devices on the bus remain idle while the SCL is high. In write mode, the master will pull the SDA selected device waits for data to be written to or read from line high during the tenth clock pulse to establish a STOP its serial register. If the R/W bit is high, the master will read condition (see Figure 40). In read mode, the master will from the slave device. On the other hand, if the R/W bit is issue a No Acknowledge for the ninth clock pulse (i.e., the low, the master will write to the slave device. SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high 2. A write operation contains an extra instruction byte that a to establish a STOP condition (see Figure 41). read operation does not contain. Such an instruction byte A repeated write function gives the user flexibility to update the in write mode follows the slave address byte. The first bit RDAC output a number of times after addressing and instructing (MSB) of the instruction byte is a don’t care. the part only once. During the write cycle, each data byte will update the RDAC output. For example, after the RDAC has The second MSB, RS, is the midscale reset. A logic high on acknowledged its slave address and instruction bytes, the RDAC this bit moves the wiper to the center tap where R = R . WA WB output will update after these two bytes. If another byte is written to This feature effectively writes over the contents of the the RDAC while it is still addressed to a specific slave device register, and thus, when taken out of reset mode, the with the same instruction, this byte will update the output of RDAC will remain at midscale. the selected slave device. If different instructions are needed, the write mode has to start again with a new slave address, instruction, The third MSB, SD, is a shutdown bit. A logic high causes and data byte. Similarly, a repeated read function of the RDAC an open circuit at terminal A while shorting the wiper to is also allowed. terminal B. This operation yields almost 0 Ω in rheostat Readback RDAC Value mode or 0 V in potentiometer mode. It is important to note that the shutdown operation does not disturb the The AD5161 allows the user to read back the RDAC values in the contents of the register. When brought out of shutdown, read mode. Refer to Table 7 and Table 8 for the programming format. the previous setting will be applied to the RDAC. Also, Multiple Devices on One Bus during shutdown, new settings can be programmed. When the part is returned from shutdown, the corresponding VR Figure 44 shows two AD5161 devices on the same serial bus. setting will be applied to the RDAC. Each has a different slave address since the states of their AD0 pins are different. This allows each RDAC within each device to The remainder of the bits in the instruction byte are don’t be written to or read from independently. The master device cares (see Table 7). output bus line drivers are open-drain pull-downs in a fully I2C compatible interface. 3. After acknowledging the instruction byte, the last byte in +5V write mode is the data byte. Data is transmitted over the RP RP serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA SDA line must occur during the low period of SCL and MASTER remain stable during the high period of SCL (see Table 7). SCL +5V SDA SCL SDA SCL 4. In the read mode, the data byte follows immediately after AD0 AD0 the acknowledgment of the slave address byte. Data is AD5161 AD5161 transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode, where there Figure 44. Multiple AD5161 Devices on One I2C Bus are eight data bits followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 41). Rev. C | Page 17 of 20

AD5161 Data Sheet LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE TERMINAL VOLTAGE OPERATING RANGE While most legacy systems may be operated at one voltage, a The AD5161 V and GND power supply defines the boundary DD new component may be optimized at another. When two systems conditions for proper 3-terminal digital potentiometer operate the same signal at two different voltages, proper level operation. Supply signals present on terminals A, B, and W that shifting is needed. For instance, one can use a 3.3 V E2PROM to exceed V or GND will be clamped by the internal forward DD interface with a 5 V digital potentiometer. A level shifting scheme is biased diodes (see Figure 48). needed to enable a bidirectional communication so that the setting VDD of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 45 shows one of the implementations. M1 and M2 can be any N-channel signal FETs, or if V falls below A DD 2.5 V, low threshold FETs such as the FDV301N. W VDD1= 3.3V VDD2=5V B RP RP RP RP G VSS SDA1 S D SDA2 Figure 48. Maximum Terminal Voltages Set by VDD and VSS G M1 SCL1 S D SCL2 M2 POWER-UP SEQUENCE 3.3V 5V Since the ESD protection diodes limit the voltage compliance at E2PROM AD5161 terminals A, B, and W (see Figure 48), it is important to power V /GND before applying any voltage to terminals A, B, and W; Figure 45. Level Shifting for Operation at Different Potentials DD otherwise, the diode will be forward biased such that V will DD be powered unintentionally and may affect the rest of the user’s ESD PROTECTION circuit. The ideal power-up sequence is in the following order: GND, V , digital inputs, and then V . The relative order of DD A/B/W All digital inputs are protected with a series input resistor and powering V , V , V , and the digital inputs is not important as A B W parallel Zener ESD structures shown in Figure 46 and Figure 47. long as they are powered after V /GND. DD This applies to the digital input pins SDI/SDA, CLK/SCL, and LAYOUT AND POWER SUPPLY BYPASSING CS/AD0. It is a good practice to employ compact, minimum lead length layout design. The leads to the inputs should be as direct as 340 LOGIC possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Vss Similarly, it is also a good practice to bypass the power supplies Figure 46. ESD Protection of Digital Pins with quality capacitors for optimum stability. Supply leads to the device should be bypassed with disc or chip ceramic A,B,W capacitors of 0.01 μF to 0.1 μF. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies VSS to minimize any transient disturbance and low frequency ripple (see Figure 49). Note that the digital ground should also be Figure 47. ESD Protection of Resistor Terminals joined remotely to the analog ground at one point to minimize the ground bounce. VDD VDD C3 + C1 10F 0.1F AD5161 GND Figure 49. Power Supply Bypassing Rev. C | Page 18 of 20

Data Sheet AD5161 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 6 5.15 3.10 4.90 3.00 4.65 2.90 1 5 PIN1 IDENTIFIER 0.50BSC 0.95 15°MAX 0.85 1.10MAX 0.75 0.70 0.15 0.30 6° 0.23 0.55 CO0P.0L5ANARITY 0.15 0° 0.13 0.40 0.10 COMPLIANTTOJEDECSTANDARDSMO-187-BA 091709-A Figure 50. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 R (Ω) Temperature Package Description Package Option Branding AB AD5161BRMZ5 5k −40°C to +125°C 10-Lead MSOP RM-10 D0C# AD5161BRMZ5-RL7 5k −40°C to +125°C 10-Lead MSOP RM-10 D0C# AD5161BRM10 10k −40°C to +125°C 10-Lead MSOP RM-10 D0D AD5161BRM10-RL7 10k −40°C to +125°C 10-Lead MSOP RM-10 D0D AD5161BRMZ10 10k −40°C to +125°C 10-Lead MSOP RM-10 D0D# AD5161BRMZ10-RL7 10k −40°C to +125°C 10-Lead MSOP RM-10 D0D# AD5161BRM50 50k −40°C to +125°C 10-Lead MSOP RM-10 D0E AD5161BRM50-RL7 50k −40°C to +125°C 10-Lead MSOP RM-10 D0E AD5161BRMZ50 50k −40°C to +125°C 10-Lead MSOP RM-10 D0E# AD5161BRMZ50-RL7 50k −40°C to +125°C 10-Lead MSOP RM-10 D0E# AD5161BRMZ100 100k −40°C to +125°C 10-Lead MSOP RM-10 D0F# AD5161BRMZ100-RL7 100k −40°C to +125°C 10-Lead MSOP RM-10 D0F# EVAL-AD5161DBZ See Note 2 Evaluation Board 1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. 2 The EVAL-AD5161DBZ evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options. The AD5161 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil. Rev. C | Page 19 of 20

AD5161 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2003−2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03435-0-6/15(C) Rev. C | Page 20 of 20

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5161BRM50 AD5161BRMZ10 AD5161BRMZ5 AD5161BRM10 AD5161BRMZ50 AD5161BRMZ100 AD5161BRM10-RL7 AD5161BRM50-RL7 AD5161BRMZ100-RL7 AD5161BRMZ10-RL7 AD5161BRMZ50-RL7 AD5161BRMZ5-RL7 EVAL-AD5161DBZ