Quad Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer Data Sheet AD5124/AD5144/AD5144A FEATURES FUNCTIONAL BLOCK DIAGRAM 10 kΩ and 100 kΩ resistance options VLOGIC VDD LRDAC Resistor tolerance: 8% maximum AD5124/AD5144 Wiper current: ±6 mA POWER-ON RDAC1 Low temperature coefficient: 35 ppm/°C RESET A1 INPUT W1 Wide bandwidth: 3 MHz REGISTER 1 B1 Fast start-up time < 75 µs RESET RDAC2 A2 Linear gain setting mode DIS INPUT W2 Single- and dual-supply operation REGISTER 2 SCLK/SCL B2 Independent logic supply: 1.8 V to 5.5 V SERIAL RDAC3 SDI/SDA INTERFACE 7/8 A3 Wide operating temperature: −40°C to +125°C INPUT REGISTER 3 W3 4 mm × 4 mm package option SYNC/ADDR0 B3 RDAC4 APPLICATIONS SDO/ADDR1 A4 INPUT REGISTER 4 W4 Portable electronics level adjustment B4 LCD panel brightness and contrast controls EEPROM MEMORY Programmable filters, delays, and time constants Programmable power supplies GND VSS WP 10877-001 Figure 1. AD5124/AD5144 24-Lead LFCSP GENERAL DESCRIPTION The AD5124/AD5144/AD5144A potentiometers provide a The AD5124/AD5144/AD5144A are available in a compact, nonvolatile solution for 128-/256-position adjustment applications, 24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts offering guaranteed low resistor tolerance errors of ±8% and up to are guaranteed to operate over the extended industrial temperature ±6 mA current density in the Ax, Bx, and Wx pins. range of −40°C to +125°C. The low resistor tolerance and low nominal temperature coefficient Table 1. Family Models simplify open-loop applications as well as applications requiring Model Channel Position Interface Package tolerance matching. AD51231 Quad 128 I2C LFCSP The linear gain setting mode allows independent programming AD5124 Quad 128 SPI/I2C LFCSP of the resistance between the digital potentiometer terminals, AD5124 Quad 128 SPI TSSOP through the RAW and RWB string resistors, allowing very accurate AD51431 Quad 256 I2C LFCSP resistor matching. AD5144 Quad 256 SPI/I2C LFCSP AD5144 Quad 256 SPI TSSOP The high bandwidth and low total harmonic distortion (THD) AD5144A Quad 256 I2C TSSOP ensure optimal performance for ac signals, making these devices AD5122 Dual 128 SPI LFCSP/TSSOP suitable for filter design. AD5122A Dual 128 I2C LFCSP/TSSOP The low wiper resistance of only 40 Ω at the ends of the resistor AD5142 Dual 256 SPI LFCSP/TSSOP array allow for pin-to-pin connection. AD5142A Dual 256 I2C LFCSP/TSSOP The wiper values can be set through an SPI-/I2C-compatible digital AD5121 Single 128 SPI/I2C LFCSP interface that is also used to read back the wiper register and AD5141 Single 256 SPI/I2C LFCSP EEPROM contents. 1 Two potentiometers and two rheostats. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5124/AD5144/AD5144A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RDAC Register and EEPROM .................................................. 23 Applications ....................................................................................... 1 Input Shift Register .................................................................... 23 Functional Block Diagram .............................................................. 1 Serial Data Digital Interface Selection, DIS ............................ 23 General Description ......................................................................... 1 SPI Serial Data Interface ............................................................ 23 Revision History ............................................................................... 2 I2C Serial Data Interface ............................................................ 25 Functional Block Diagrams—TSSOP ............................................ 3 I2C Address .................................................................................. 25 Specifications ..................................................................................... 4 Advanced Control Modes ......................................................... 27 Electrical Characteristics—AD5124 .......................................... 4 EEPROM or RDAC Register Protection ................................. 28 Electrical Characteristics—AD5144 and AD5144A ................ 7 Load RDAC Input Register (LRDAC) ..................................... 28 Interface Timing Specifications ................................................ 10 RDAC Architecture .................................................................... 31 Shift Register and Timing Diagrams ....................................... 11 Programming the Variable Resistor ......................................... 31 Absolute Maximum Ratings .......................................................... 13 Programming the Potentiometer Divider ............................... 32 Thermal Resistance .................................................................... 13 Terminal Voltage Operating Range ......................................... 32 ESD Caution ................................................................................ 13 Power-Up Sequence ................................................................... 32 Pin Configurations and Function Descriptions ......................... 14 Layout and Power Supply Biasing ............................................ 32 Typical Performance Characteristics ........................................... 17 Outline Dimensions ....................................................................... 33 Test Circuits ..................................................................................... 22 Ordering Guide .......................................................................... 34 Theory of Operation ...................................................................... 23 REVISION HISTORY 7/2019—Rev. B to Rev. C Changes to Table 7 .......................................................................... 13 Added Endnote 2, Table 14 ........................................................... 26 Changes to Figure 11 and Table 11 .............................................. 16 Added Endnote 2, Table 20 ........................................................... 29 Changes to Figure 20 ...................................................................... 18 Updated Outline Dimensions ....................................................... 33 Added Figure 21; Renumbered Sequentially .............................. 18 Changes to Figure 24 ...................................................................... 19 7/2017—Rev. A to Rev. B Change to Linear Gain Setting Mode Section ............................ 27 Changed LFCSP_WQ to LFCSP .................................. Throughout Change to RDAC Architecture Section ....................................... 31 Changes to Features Section............................................................ 1 Updated Outline Dimensions ....................................................... 33 Changes to Logic Supply Current Parameter, Table 2 ................. 5 Added Note 12 to Data Retention Parameter, Table 2; 12/2012—Rev. 0 to Rev. A Renumbered Sequentially ................................................................ 6 Changes to Table 12 and Table 13 ................................................ 25 Changes to Logic Supply Current Parameter, Table 3 ................. 8 Added Note 12 to Data Retention Parameter, Table 3; 10/2012—Revision 0: Initial Version Renumbered Sequentially ................................................................ 9 Rev. C | Page 2 of 36

Data Sheet AD5124/AD5144/AD5144A FUNCTIONAL BLOCK DIAGRAMS—TSSOP VLOGIC VDD VLOGIC VDD AD5124/AD5144 AD5144A POWER-ON RDAC 1 POWER-ON RDAC 1 RESET A1 RESET A1 INPUT W1 INPUT W1 REGISTER 1 REGISTER 1 B1 B1 SYNC RDAC 2 A2 RESET RDAC 2 A2 INPUT W2 INPUT W2 SCLK REGISTER 2 SCL REGISTER 2 SPI B2 I2C B2 SERIAL RDAC 3 SERIAL RDAC 3 SDI INTERFACE 7/8 A3 SDA INTERFACE 8 A3 INPUT INPUT REGISTER 3 W3 REGISTER 3 W3 SDO ADDR B3 B3 RDAC 4 RDAC 4 A4 A4 INPUT INPUT REGISTER 4 W4 REGISTER 4 W4 B4 B4 EEPROM EEPROM MEMORY MEMORY GND VSS 10877-002 GND VSS 10877-003 Figure 2. AD5124/AD5144 20-Lead TSSOP Figure 3. AD5144A 20-Lead TSSOP Rev. C | Page 3 of 36

AD5124/AD5144/AD5144A Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5124 V = 2.3 V to 5.5 V, V = 0 V; V = 2.25 V to 2.75 V, V = −2.25 V to −2.75 V; V = 1.8 V to 5.5 V, −40°C < T < +125°C, unless DD SS DD SS LOGIC A otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 7 Bits Resistor Integral Nonlinearity2 R-INL R = 10 kΩ AB V ≥ 2.7 V −1 ±0.1 +1 LSB DD V < 2.7 V −2.5 ±1 +2.5 LSB DD R = 100 kΩ AB V ≥ 2.7 V −0.5 ±0.1 +0.5 LSB DD V < 2.7 V −1 ±0.25 +1 LSB DD Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.1 +0.5 LSB Nominal Resistor Tolerance ΔR /R −8 ±1 +8 % AB AB Resistance Temperature Coefficient3 (ΔR /R )/ΔT × 106 Code = full scale 35 ppm/°C AB AB Wiper Resistance3 R Code = zero scale W R = 10 kΩ 55 125 Ω AB R = 100 kΩ 130 400 Ω AB Bottom Scale or Top Scale R or R BS TS R = 10 kΩ 40 80 Ω AB R = 100 kΩ 60 230 Ω AB Nominal Resistance Match R /R Code = 0xFF −1 ±0.2 +1 % AB1 AB2 DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL R = 10 kΩ −0.5 ±0.1 +0.5 LSB AB R = 100 kΩ −0.25 ±0.1 +0.25 LSB AB Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB Full-Scale Error V WFSE R = 10 kΩ −1.5 −0.1 LSB AB R = 100 kΩ −0.5 ±0.1 +0.5 LSB AB Zero-Scale Error V WZSE R = 10 kΩ 1 1.5 LSB AB R = 100 kΩ 0.25 0.5 LSB AB Voltage Divider Temperature (ΔV /V )/ΔT × 106 Code = half scale ±5 ppm/°C W W Coefficient3 Rev. C | Page 4 of 36

Data Sheet AD5124/AD5144/AD5144A Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit RESISTOR TERMINALS Maximum Continuous Current I , I , and I A B W R = 10 kΩ −6 +6 mA AB R = 100 kΩ −1.5 +1.5 mA AB Terminal Voltage Range5 V V V SS DD Capacitance A, Capacitance B3 C , C f = 1 MHz, measured to GND, A B code = half scale R = 10 kΩ 25 pF AB R = 100 kΩ 12 pF AB Capacitance W3 C f = 1 MHz, measured to GND, W code = half scale R = 10 kΩ 12 pF AB R = 100 kΩ 5 pF AB Common-Mode Leakage Current3 V = V = V −500 ±15 +500 nA A W B DIGITAL INPUTS Input Logic3 High V V = 1.8 V to 2.3 V 0.8 × V V INH LOGIC LOGIC V = 2.3 V to 5.5 V 0.7 × V V LOGIC LOGIC Low V 0.2 × V V INL LOGIC Input Hysteresis3 V 0.1 × V V HYST LOGIC Input Current3 I ±1 µA IN Input Capacitance3 C 5 pF IN DIGITAL OUTPUTS Output High Voltage3 V R = 2.2 kΩ to V V V OH PULL-UP LOGIC LOGIC Output Low Voltage3 V I = 3 mA 0.4 V OL SINK I = 6 mA, V > 2.3 V 0.6 V SINK LOGIC Three-State Leakage Current −1 +1 µA Three-State Output Capacitance 2 pF POWER SUPPLIES Single-Supply Power Range V = GND 2.3 5.5 V SS Dual-Supply Power Range ±2.25 ±2.75 V Logic Supply Range Single supply, V = GND 1.8 V V SS DD Dual supply, V < GND 2.25 V V SS DD Positive Supply Current I V = V or V = GND DD IH LOGIC IL V = 5.5 V 0.7 5.5 µA DD V = 2.3 V 400 nA DD Negative Supply Current I V = V or V = GND −5.5 −0.7 µA SS IH LOGIC IL EEPROM Store Current3, 6 I V = V or V = GND 2 mA DD_EEPROM_STORE IH LOGIC IL EEPROM Read Current3, 7 I V = V or V = GND 320 µA DD_EEPROM_READ IH LOGIC IL Logic Supply Current I V = V or V = GND 0.05 1.4 µA LOGIC IH LOGIC IL Power Dissipation8 P V = V or V = GND 3.5 µW DISS IH LOGIC IL Power Supply Rejection Ratio PSRR ∆V /∆V = V ± 10%, −66 −60 dB DD SS DD code = full scale Rev. C | Page 5 of 36

AD5124/AD5144/AD5144A Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB R = 10 kΩ 3 MHz AB R = 100 kΩ 0.43 MHz AB Total Harmonic Distortion THD V /V = ±2.5 V, V = 1 V rms, DD SS A V = 0 V, f = 1 kHz B R = 10 kΩ −80 dB AB R = 100 kΩ −90 dB AB Resistor Noise Density e Code = half scale, T = 25°C, N_WB A f = 10 kHz R = 10 kΩ 7 nV/√Hz AB R = 100 kΩ 20 nV/√Hz AB V Settling Time t V = 5 V, V = 0 V, from W S A B zero scale to full scale, ±0.5 LSB error band R = 10 kΩ 2 µs AB R = 100 kΩ 12 µs AB Crosstalk (C /C ) C R = 10 kΩ 10 nV-sec W1 W2 T AB R = 100 kΩ 25 nV-sec AB Analog Crosstalk C −90 dB TA Endurance10 T = 25°C 1 Mcycles A 100 kcycles Data Retention11, 12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. Rev. C | Page 6 of 36

Data Sheet AD5124/AD5144/AD5144A ELECTRICAL CHARACTERISTICS—AD5144 AND AD5144A V = 2.3 V to 5.5 V, V = 0 V; V = 2.25 V to 2.75 V, V = −2.25 V to −2.75 V; V = 1.8 V to 5.5 V, −40°C < T < +125°C, unless DD SS DD SS LOGIC A otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 8 Bits Resistor Integral Nonlinearity2 R-INL R = 10 kΩ AB V ≥ 2.7 V −2 ±0.2 +2 LSB DD V < 2.7 V −5 ±1.5 +5 LSB DD R = 100 kΩ AB V ≥ 2.7 V −1 ±0.1 +1 LSB DD V < 2.7 V −2 ±0.5 +2 LSB DD Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.2 +0.5 LSB Nominal Resistor Tolerance ΔR /R −8 ±1 +8 % AB AB Resistance Temperature Coefficient3 (ΔR /R )/ΔT × 106 Code = full scale 35 ppm/°C AB AB Wiper Resistance3 R Code = zero scale W R = 10 kΩ 55 125 Ω AB R = 100 kΩ 130 400 Ω AB Bottom Scale or Top Scale R or R BS TS R = 10 kΩ 40 80 Ω AB R = 100 kΩ 60 230 Ω AB Nominal Resistance Match R /R Code = 0xFF −1 ±0.2 +1 % AB1 AB2 DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL R = 10 kΩ −1 ±0.2 +1 LSB AB R = 100 kΩ −0.5 ±0.1 +0.5 LSB AB Differential Nonlinearity4 DNL −0.5 ±0.2 +0.5 LSB Full-Scale Error V WFSE R = 10 kΩ −2.5 −0.1 LSB AB R = 100 kΩ −1 ±0.2 +1 LSB AB Zero-Scale Error V WZSE R = 10 kΩ 1.2 3 LSB AB R = 100 kΩ 0.5 1 LSB AB Voltage Divider Temperature (ΔV /V )/ΔT × 106 Code = half scale ±5 ppm/°C W W Coefficient3 Rev. C | Page 7 of 36

AD5124/AD5144/AD5144A Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit RESISTOR TERMINALS Maximum Continuous Current I , I , and I A B W R = 10 kΩ −6 +6 mA AB R = 100 kΩ −1.5 +1.5 mA AB Terminal Voltage Range5 V V V SS DD Capacitance A, Capacitance B3 C , C f = 1 MHz, measured to GND, A B code = half scale R = 10 kΩ 25 pF AB R = 100 kΩ 12 pF AB Capacitance W3 C f = 1 MHz, measured to GND, W code = half scale R = 10 kΩ 12 pF AB R = 100 kΩ 5 pF AB Common-Mode Leakage Current3 V = V = V −500 ±15 +500 nA A W B DIGITAL INPUTS Input Logic3 High V V = 1.8 V to 2.3 V 0.8 × V V INH LOGIC LOGIC V = 2.3 V to 5.5 V 0.7 × V V LOGIC LOGIC Low V 0.2 × V V INL LOGIC Input Hysteresis3 V 0.1 × V V HYST LOGIC Input Current3 I ±1 µA IN Input Capacitance3 C 5 pF IN DIGITAL OUTPUTS Output High Voltage3 V R = 2.2 kΩ to V V V OH PULL-UP LOGIC LOGIC Output Low Voltage3 V I = 3 mA 0.4 V OL SINK I = 6 mA, V > 2.3 V 0.6 V SINK LOGIC Three-State Leakage Current −1 +1 µA Three-State Output Capacitance 2 pF POWER SUPPLIES Single-Supply Power Range V = GND 2.3 5.5 V SS Dual-Supply Power Range ±2.25 ±2.75 V Logic Supply Range Single supply, V = GND 1.8 V V SS DD Dual supply, V < GND 2.25 V V SS DD Positive Supply Current I V = V or V = GND DD IH LOGIC IL V = 5.5 V 0.7 5.5 µA DD V = 2.3 V 400 nA DD Negative Supply Current I V = V or V = GND −5.5 −0.7 µA SS IH LOGIC IL EEPROM Store Current3, 6 I V = V or V = GND 2 mA DD_EEPROM_STORE IH LOGIC IL EEPROM Read Current3, 7 I V = V or V = GND 320 µA DD_EEPROM_READ IH LOGIC IL Logic Supply Current I V = V or V = GND 0.05 1.4 µA LOGIC IH LOGIC IL Power Dissipation8 P V = V or V = GND 3.5 µW DISS IH LOGIC IL Power Supply Rejection Ratio PSRR ∆V /∆V = V ± 10%, −66 −60 dB DD SS DD code = full scale Rev. C | Page 8 of 36

Data Sheet AD5124/AD5144/AD5144A Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB R = 10 kΩ 3 MHz AB R = 100 kΩ 0.43 MHz AB Total Harmonic Distortion THD V /V = ±2.5 V, V = 1 V rms, DD SS A V = 0 V, f = 1 kHz B R = 10 kΩ −80 dB AB R = 100 kΩ −90 dB AB Resistor Noise Density e Code = half scale, T = 25°C, N_WB A f = 10 kHz R = 10 kΩ 7 nV/√Hz AB R = 100 kΩ 20 nV/√Hz AB V Settling Time t V = 5 V, V = 0 V, from W S A B zero scale to full scale, ±0.5 LSB error band R = 10 kΩ 2 µs AB R = 100 kΩ 12 µs AB Crosstalk (C /C ) C R = 10 kΩ 10 nV-sec W1 W2 T AB R = 100 kΩ 25 nV-sec AB Analog Crosstalk C −90 dB TA Endurance10 T = 25°C 1 Mcycles A 100 kcycles Data Retention11, 12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. Rev. C | Page 9 of 36

AD5124/AD5144/AD5144A Data Sheet INTERFACE TIMING SPECIFICATIONS V = 1.8 V to 5.5 V; all specifications T to T , unless otherwise noted. LOGIC MIN MAX Table 4. SPI Interface Parameter1 Test Conditions/Comments Min Typ Max Unit Description t V > 1.8 V 20 ns SCLK cycle time 1 LOGIC V = 1.8 V 30 ns LOGIC t V > 1.8 V 10 ns SCLK high time 2 LOGIC V = 1.8 V 15 ns LOGIC t V > 1.8 V 10 ns SCLK low time 3 LOGIC V = 1.8 V 15 ns LOGIC t4 10 ns SYNC-to-SCLK falling edge setup time t 5 ns Data setup time 5 t 5 ns Data hold time 6 t7 10 ns SYNC rising edge to next SCLK fall ignored t82 20 ns Minimum SYNC high time t 3 50 ns SCLK rising edge to SDO valid 9 t10 500 ns SYNC rising edge to SDO pin disable 1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 6). 3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. Table 5. I2C Interface Parameter1 Test Conditions/Comments Min Typ Max Unit Description f 2 Standard mode 100 kHz Serial clock frequency SCL Fast mode 400 kHz t Standard mode 4.0 µs SCL high time, t 1 HIGH Fast mode 0.6 µs t Standard mode 4.7 µs SCL low time, t 2 LOW Fast mode 1.3 µs t Standard mode 250 ns Data setup time, t 3 SU; DAT Fast mode 100 ns t Standard mode 0 3.45 µs Data hold time, t 4 HD; DAT Fast mode 0 0.9 µs t Standard mode 4.7 µs Setup time for a repeated start condition, t 5 SU; STA Fast mode 0.6 µs t Standard mode 4 µs Hold time (repeated) for a start condition, t 6 HD; STA Fast mode 0.6 µs t Standard mode 4.7 µs Bus free time between a stop and a start condition, t 7 BUF Fast mode 1.3 µs t Standard mode 4 µs Setup time for a stop condition, t 8 SU; STO Fast mode 0.6 µs t Standard mode 1000 ns Rise time of SDA signal, t 9 RDA Fast mode 20 + 0.1 C 300 ns L t Standard mode 300 ns Fall time of SDA signal, t 10 FDA Fast mode 20 + 0.1 C 300 ns L t Standard mode 1000 ns Rise time of SCL signal, t 11 RCL Fast mode 20 + 0.1 C 300 ns L t Standard mode 1000 ns Rise time of SCL signal after a repeated start condition 11A and after an acknowledge bit, t (not shown in Figure 5) RCL1 Fast mode 20 + 0.1 C 300 ns L Rev. C | Page 10 of 36

Data Sheet AD5124/AD5144/AD5144A Parameter1 Test Conditions/Comments Min Typ Max Unit Description t Standard mode 300 ns Fall time of SCL signal, t 12 FCL Fast mode 20 + 0.1 C 300 ns L t 3 Fast mode 0 50 ns Pulse width of suppressed spike SP 1 Maximum bus capacitance is limited to 400 pF. 2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. Table 6. Control Pins Parameter Min Typ Max Unit Description t1 1 µs End command to LRDAC falling edge t2 50 ns Minimum LRDAC low time t3 0.1 10 µs RESET low time t 1 15 50 ms Memory program time (not shown in Figure 8) EEPROM_PROGRAM t 7 30 µs Memory readback time (not shown in Figure 8) EEPROM_READBACK t 2 75 µs Start-up time (not shown in Figure 8) POWER_UP t 30 µs Reset EEPROM restore time (not shown in Figure 8) RESET 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 2 Maximum time after VDD − VSS is equal to 2.3 V. SHIFT REGISTER AND TIMING DIAGRAMS DB15 (MSB) DB8 DB7 DB0 (LSB) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS ADDRESS BITS DATA BITS 10877-004 Figure 4. Input Shift Register Contents t11 t12 t6 t8 t2 SCL t6 t1 t5 t4 t3 t10 t9 SDA P t7 S S P 10877-005 Figure 5. I2C Serial Interface Timing Diagram (Typical Write Sequence) Rev. C | Page 11 of 36

AD5124/AD5144/AD5144A Data Sheet t4 t2 t1 t7 SCLK t8 t3 SYNC t5 t6 SDI C3 C2 C1 C0 D7 D6 D5 D2 D1 D0 t9 t10 *PSRDEOVIOUS COMMANDC 3R*ECEIVECD2.* C1* C0* D7* D6* D5* D2* D1* D0* 10877-006 Figure 6. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1 t4 t2 t1 t7 SCLK t8 t3 SYNC t5 t6 SDI C3 C2 C1 C0 D7 D6 D5 D2 D1 D0 t9 t10 *PSRDEOVIOUS COMMANDC 3R*ECEIVECD2.* C1* C0* D7* D6* D5* D2* D1* D0* 10877-007 Figure 7. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0 SCLK SPI INTERFACE SYNC SCL I2C INTERFACE SDA P t1 t2 LRDAC RESET t3 10877-008 Figure 8. Control Pins Timing Diagram Rev. C | Page 12 of 36

Data Sheet AD5124/AD5144/AD5144A ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum A Ratings may cause permanent damage to the product. This is a Table 7. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7.0 V DD section of this specification is not implied. Operation beyond V to GND +0.3 V to −7.0 V SS the maximum operating conditions for extended periods may V to V 7 V DD SS affect product reliability. V to GND −0.3 V to V + 0.3 V or LOGIC DD THERMAL RESISTANCE +7.0 V (whichever is less) VA, VW, VB to GND VSS − 0.3 V, VDD + 0.3 V θJA is defined by the JEDEC JESD51 standard, and the value is IA, IW, IB dependent on the test board and test environment. Pulsed1 Frequency > 10 kHz Table 8. Thermal Resistance RAW = 10 kΩ ±6 mA/d2 Package Type θJA θJC Unit R = 100 kΩ ±1.5 mA/d2 24-Lead LFCSP 351 3 °C/W AW Frequency ≤ 10 kHz 20-Lead TSSOP 1431 45 °C/W RAW = 10 kΩ ±6 mA/√d2 1 JEDEC 2S2P test board, still air (0 m/sec airflow). R = 100 kΩ ±1.5 mA/√d2 AW Digital Inputs −0.3 V to V + 0.3 V or LOGIC +7 V (whichever is less) ESD CAUTION Operating Temperature Range, T 3 −40°C to +125°C A Maximum Junction Temperature, 150°C T Maximum J Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (T max − T )/θ J A JA FICDM 1.5 kV 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. Rev. C | Page 13 of 36

AD5124/AD5144/AD5144A Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SYNC 1 20 SDO GND 2 19 SDI A1 3 18 SCLK W1 4 AD5124/ 17 VLOGIC B1 5 AD5144 16 VDD TOP VIEW A3 6 (Not to Scale) 15 B4 W3 7 14 W4 B3 8 13 A4 VAS2S 190 1112 WB22 10877-010 Figure 9. 20-Lead TSSOP, SPI Interface Pin Configuration (AD5124/AD5144) Table 9. 20-Lead TSSOP, SPI Interface Pin Function Descriptions (AD5124/AD5144) Pin No. Mnemonic Description 1 SYNC Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the input shift register. 2 GND Ground Pin, Logic Ground Reference. 3 A1 Terminal A of RDAC1. V ≤ V ≤ V . SS A DD 4 W1 Wiper Terminal of RDAC1. V ≤ V ≤ V . SS W DD 5 B1 Terminal B of RDAC1. V ≤ V ≤ V . SS B DD 6 A3 Terminal A of RDAC3. V ≤ V ≤ V . SS A DD 7 W3 Wiper Terminal of RDAC3. V ≤ V ≤ V . SS W DD 8 B3 Terminal B of RDAC3. V ≤ V ≤ V . SS B DD 9 V Negative Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. SS 10 A2 Terminal A of RDAC2. V ≤ V ≤ V . SS A DD 11 W2 Wiper Terminal of RDAC2. V ≤ V ≤ V . SS W DD 12 B2 Terminal B of RDAC2. V ≤ V ≤ V . SS B DD 13 A4 Terminal A of RDAC4. V ≤ V ≤ V . SS A DD 14 W4 Wiper Terminal of RDAC4. V ≤ V ≤ V . SS W DD 15 B4 Terminal B of RDAC4. V ≤ V ≤ V . SS B DD 16 V Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. DD 17 V Logic Power Supply; 1.8 V to V . Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. LOGIC DD 18 SCLK Serial Clock Line. Data is clocked in at the logic low transition. 19 SDI Serial Data Input. 20 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. Rev. C | Page 14 of 36

Data Sheet AD5124/AD5144/AD5144A RESET 1 20 ADDR GND 2 19 SDA A1 3 18 SCL W1 4 AD5144A 17 VLOGIC B1 5 TOP VIEW 16 VDD (Not to Scale) A3 6 15 B4 W3 7 14 W4 B3 8 13 A4 VAS2S 190 1112 WB22 10877-011 Figure 10. 20-Lead TSSOP, I2C Interface Pin Configuration (AD5144A) Table 10. 20-Lead TSSOP, I2C Interface Pin Function Descriptions (AD5144A) Pin No. Mnemonic Description 1 RESET Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to V . LOGIC 2 GND Ground Pin, Logic Ground Reference. 3 A1 Terminal A of RDAC1. V ≤ V ≤ V . SS A DD 4 W1 Wiper Terminal of RDAC1. V ≤ V ≤ V . SS W DD 5 B1 Terminal B of RDAC1. V ≤ V ≤ V . SS B DD 6 A3 Terminal A of RDAC3. V ≤ V ≤ V . SS A DD 7 W3 Wiper Terminal of RDAC3. V ≤ V ≤ V . SS W DD 8 B3 Terminal B of RDAC3. V ≤ V ≤ V . SS B DD 9 V Negative Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. SS 10 A2 Terminal A of RDAC2. V ≤ V ≤ V . SS A DD 11 W2 Wiper Terminal of RDAC2. V ≤ V ≤ V . SS W DD 12 B2 Terminal B of RDAC2. V ≤ V ≤ V . SS B DD 13 A4 Terminal A of RDAC4. V ≤ V ≤ V . SS A DD 14 W4 Wiper Terminal of RDAC4. V ≤ V ≤ V . SS W DD 15 B4 Terminal B of RDAC4. V ≤ V ≤ V . SS B DD 16 V Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. DD 17 V Logic Power Supply; 1.8 V to V . Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. LOGIC DD 18 SCL Serial Clock Line. Data is clocked in at the logic low transition. 19 SDA Serial Data Input/Output. 20 ADDR Programmable Address for Multiple Package Decoding. Rev. C | Page 15 of 36

AD5124/AD5144/AD5144A Data Sheet C N O Y D TESER CADRL S0/RDDA S1/RDDA PW IDS/ADS 42 32 22 12 02 91 GND1 18DIS A12 17SCL/SCLK AD5124/ W13 AD5144 16VLOGIC B14 TOP VIEW 15VDD (Not to Scale) A35 14B4 W36 13W4 7 8 9 0 1 2 1 1 1 3 S2 2 2 4 B SA W B A V NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE POTENTIAL OF THE VSS PIN, OR, ALTERNATIVELY, LEAVE ITPTHL EAALNTE ETC HFTEOR RIPC AEADNL HLBYAE N UTCNHECEDOR TMNHNAEELRCLMYTE ACDLO. PNITEN RIESFC ORTREECMDO ATMNOCM AEE .CNODEPDPER 10877-009 Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144) Table 11. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144) Pin No. Mnemonic Description 1 GND Ground Pin, Logic Ground Reference. 2 A1 Terminal A of RDAC1. V ≤ V ≤ V . SS A DD 3 W1 Wiper Terminal of RDAC1. V ≤ V ≤ V . SS W DD 4 B1 Terminal B of RDAC1. V ≤ V ≤ V . SS B DD 5 A3 Terminal A of RDAC3. V ≤ V ≤ V . SS A DD 6 W3 Wiper Terminal of RDAC3. V ≤ V ≤ V . SS W DD 7 B3 Terminal B of RDAC3. V ≤ V ≤ V . SS B DD 8 V Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. SS 9 A2 Terminal A of RDAC2. V ≤ V ≤ V . SS A DD 10 W2 Wiper Terminal of RDAC2. V ≤ V ≤ V . SS W DD 11 B2 Terminal B of RDAC2. V ≤ V ≤ V . SS B DD 12 A4 Terminal A of RDAC4. V ≤ V ≤ V . SS A DD 13 W4 Wiper Terminal of RDAC4. V ≤ V ≤ V . SS W DD 14 B4 Terminal B of RDAC4. V ≤ V ≤ V . SS B DD 15 V Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. DD 16 V Logic Power Supply; 1.8 V to V . Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. LOGIC DD 17 SCL/SCLK I2C Serial Clock Line (SCL). Data is clocked in at the logic low transition. SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition. 18 DIS Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), and I2C when DIS = 1 (VLOGIC). This pin cannot be left floating. 19 SDA/SDI Serial Data Input/Output (SDA), When DIS = 1. Serial Data Input (SDI), When DIS = 0. 20 WP Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used, tie WP to V . LOGIC 21 ADDR1/SDO Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1. Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0. 22 ADDR0/SYNC Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1. Synchronization Data Input, When DIS = 0. This pin is active low. When SYNC returns high, data is loaded into the input shift register. 23 LRDAC Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their associated input registers were previously loaded using Command 2 (see Table 20). This allows simultaneous update of all RDAC registers. LRDAC is activated at the high-to-low transition. If not used, tie LRDAC to V . LOGIC 24 RESET Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If not used, tie RESET to V . LOGIC EPAD Exposed Pad. Connect the exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Rev. C | Page 16 of 36

Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.2 10kΩ,+125°C 0.4 10kΩ, +25°C 10kΩ,–40°C 0.1 100kΩ, +125°C 0.3 100kΩ, +25°C 100kΩ, –40°C 0 0.2 B) 0.1 B) –0.1 S S NL (L 0 NL (L –0.2 R-I –0.1 R-D –0.3 –0.2 –0.4 –0.3 –0.5 –0.4 10kΩ,+125°C 100kΩ,+125°C –0.50 1C0O0DE (Decimal) 200 10877-012 –0.60 1100kkΩΩ,,+–4205°°CC 110000kkΩΩ1,,C–+042O005D°°CCE (Decimal) 200 10877-015 Figure 12. R-INL vs. Code (AD5144/AD5144A) Figure 15. R-DNL vs. Code (AD5144/AD5144A) 0.20 0.10 0.15 0.05 0.10 0 0.05 B) B) –0.05 S 0 S NL (L –0.05 NL (L –0.10 R-I R-D –0.15 –0.10 –0.15 1100kkΩΩ,,++12255°C°C –0.20 10kΩ,–40°C –0.20 100kΩ,+125°C –0.25 100kΩ,+25°C 10kΩ,+125°C 100kΩ,+125°C 100kΩ,–40°C 10kΩ,+25°C 100kΩ,+25°C –0.25 0 C5O0DE (Decimal) 100 10877-013 –0.300 10kΩ,–40°C 100kΩ,C5–04O0D°CE (Decimal) 100 10877-016 Figure 13. R-INL vs. Code (AD5124) Figure 16. R-DNL vs. Code (AD5124) 0.3 10kΩ,–40°C 0.10 10kΩ, +25°C 10kΩ, +125°C 0.2 100kΩ,–40°C 0.05 100kΩ, +25°C 100kΩ, +125°C 0 0.1 –0.05 B) B) S S NL (L 0 NL (L–0.10 I D –0.15 –0.1 –0.20 –0.2 –0.25 10kΩ, –40°C 100kΩ, –40°C 10kΩ, +25°C 100kΩ, +25°C 10kΩ, +125°C 100kΩ, +125°C –0.30 C10O0DE (Decimal) 200 10877-014 –0.300 C10O0DE (Decimal) 200 10877-017 Figure 14. INL vs. Code (AD5144/AD5144A) Figure 17. DNL vs. Code (AD5144/AD5144A) Rev. C | Page 17 of 36

AD5124/AD5144/AD5144A Data Sheet 0.15 1000 111000kkkΩΩΩ,,, –++421025°5°CC°C 900 VVDSSD == GVLNODGIC VVLLOOGGIICC == 23..33VV 0.10 100kΩ,–40°C VLOGIC = 5.5V 100kΩ, +25°C 800 100kΩ, +125°C 700 0.05 L (LSB) 0 (nA)GIC 560000 N O I IL 400 –0.05 300 200 –0.10 100 –0.150 C50ODE (Decimal) 100 10877-018 0–40 –20 0 T2E0MPERA40TURE (6°0C) 80 100 120 10877-160 Figure 18. INL vs. Code (AD5124) Figure 21. ILOGIC vs. Temperature 450 0.06 100kΩ 10kΩ, –40°C 100kΩ, –40°C 10kΩ 10kΩ, +25°C 100kΩ, +25°C E 400 0.04 10kΩ, +125°C 100kΩ, +125°C R U AT 350 0.02 R EMPEm/°C) 300 0 MODE TENT (pp 220500 L (LSB)––00..0042 OMETER COEFFICI 110500 DN––00..0068 TI EN 50 –0.10 T O P 0 –0.12 –50 00 5205 C15O000DE (Decim175a50l) 210000 215257 AAADDD555111244444/A 10877-019 –0.140 C50ODE (Decimal) 100 10877-021 Figure 19. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) Figure 22. DNL vs. Code (AD5124) vs. Code 800 450 VVDSSD == GVLNODGIC 400 1100k0ΩkΩ 700 E R 350 U 600 T I (nA)DD 450000 MODETEMPERAFICIENT(ppm/°C)122350500000 300 TF AE STCO100 200 O E H 50 100 VDD = 2.3V R VDD = 3.3V 0 VDD = 5.5V 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10877-020 –5000 2550 C15O000DE (Decim175a50l) 120000 122575 AAADDD555111244444/A 10877-122 Figure 20. Supply Current vs. Temperature Figure 23. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs. Code Rev. C | Page 18 of 36

Data Sheet AD5124/AD5144/AD5144A 1.2 20 1.0 IIIII22222CCCCC,,,,, VVVVVLLLLLOOOOOGGGGGIIIIICCCCC ===== 12355...V.8335VVVV 0 VRDADB/ V= S1S0 k=Ω ±2.5V SPI, VLOGIC = 1.8V CURRENT (µA) 00..68 SSSSPPPPIIII,,,, VVVVLLLLOOOOGGGGIIIICCCC ==== 2355..V.335VVV SE (Degrees) ––4200 C A OGI 0.4 PH –60 L I 0.2 –80 QUARTER SCALE MIDSCALE FULL-SCALE 00 1 DIGIT2AL INPUT V3OLATGE(V4) 5 10877-023 –10010 100 1kFREQU1E0NkCY(Hz)100k 1M 10M 10877-026 Figure 24. ILOGIC Current vs. Digital Input Voltage Figure 27. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ 0 0 0x80 (0x40) 0x80 (0x40) –10 0x40 (0x20) –10 0x40 (0x20) 0x20 (0x10) –20 0x10 (0x08) 0x20 (0x10) 0x8 (0x04) –20 –30 0x10 (0x08) 0x4 (0x02) N (dB) –30 0x8 (0x04) N (dB) –40 00xx21 ((00xx0010)) AI 0x4 (0x02) AI –50 G 0x2 (0x01) G 0x00 –40 0x1 (0x00) –60 0x00 –70 –50 –80 AD5144/AD5144A (AD5124) AD5144/AD5144A (AD5124) –6010 100 1k FREQ1U0EkNCY(H1z0)0k 1M 10M 10877-022 –9010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 10877-123 Figure 25. 10 kΩ Gain vs. Frequency vs. Code Figure 28. 100 kΩ Gain vs. Frequency vs. Code –40 0 VVDAD =/ V1SVS r=m ±s2.5V 1100k0kΩΩ –10 1100k0kΩΩ –50 VB = GND CODE = HALF SCALE NOISE FILTER = 22kHz –20 –60 –30 B) B) + N (d –70 + N (d –40 D D –50 H H T T –80 –60 –70 –90 VDD/VSS= ±2.5V –80 fIN = 1kHz CODE = HALF SCALE NOISE FILTER = 22kHz –10020 200 FREQUE2NkCY (Hz) 20k 200k 10877-025 –900.001 0.01VOLTAGE (V rm0s.)1 1 10877-028 Figure 26. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency Figure 29. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude Rev. C | Page 19 of 36

AD5124/AD5144/AD5144A Data Sheet 10 0.8 0 0.7 00xx8800 TTOO 00xx77FF,, 11000kkΩΩ VVDAD =/ VVSDSD = ±2.5V VB = VSS –10 0.6 –20 V) ees) –30 GE ( 0.5 Degr –40 OLTA 0.4 SE ( E V 0.3 A –50 V H TI P A –60 EL 0.2 R –70 0.1 QUARTER SCALE –80 MIDSCALE VDD/VSS = ±2.5V 0 FULL-SCALE RAB = 100kΩ –9010 100 FR1kEQUENCY 1(H0kz) 100k 1M 10877-029 –0.10 5 TIME (µs) 10 15 10877-032 Figure 30. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ Figure 33. Maximum Transition Glitch 600 0.0025 1.2 100kΩ, VDD = 2.3V 100kΩ, VDD = 2.7V 100kΩ, VDD = 3V 500 100kΩ, VDD = 3.6V 1.0 WIPER ON RESISTANCE (Ω) 234000000 111111110000000000kkkkkkkkΩΩΩΩΩΩΩΩ,,,,,, ,,VVVVVV VVDDDDDDDDDDDDDDDD ====== == 223355 ..V.V.553765V.VVVV5V PROBABILITYDENSITY 000...000000112050 000...468 CUMULATIVEPROBABILITY 0.0005 100 0.2 00 1 2 VOLTAGE3 (V) 4 5 10877-030 0–600 –500 –400 –300 –R2E00SIS–1T0O0RD0RIF1T00(pp2m00) 300 400 500 6000 10877-033 Figure 31. Incremental Wiper On Resistance vs. Positive Power Supply (VDD) Figure 34. Resistor Lifetime Drift 10 0 9 111000kkkΩΩΩ +++ 071p55p0FpFF –10 1100k0ΩkΩ VVDSSD == G5VN D±1, 0V%A =A C4V, VB = GND 10kΩ + 250pF CODE = MIDSCALE 8 100kΩ + 0pF 100kΩ + 75pF –20 7 100kΩ + 150pF Hz) 100kΩ + 250pF –30 M6 NDWIDTH (45 PSRR (dB) ––5400 A B3 –60 2 –70 1 –80 0 00 2100 4200 CODE6300 (Decima84l)00 15000 16200 AAADDD555111442444/A 10877-031 –9010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 10877-034 Figure 32. Maximum Bandwidth vs. Code vs. Net Capacitance Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. C | Page 20 of 36

Data Sheet AD5124/AD5144/AD5144A 0.020 7 0.015 6 ATIVE VOLTAGE (V)–000...0000015500 ORETICAL I (mA)MAX345 REL–0.010 THE 2 10kΩ –0.015 VVDAD =/ VVSDSD = ±2.5V 1 VB = VSS 100kΩ CODE = HALF SCALE –0.020 0 0 500 TIM10E0 (0ns) 1500 2000 10877-035 00 5205 15C00O0DE (Deci1m755a0l) 210000 215205 AAADDD555111244444/A 10877-037 Figure 36. Digital Feedthrough Figure 38. Theoretical Maximum Current vs. Code 0 10kΩ SHUTDOWN MODE ENABLED 100kΩ –20 –40 B) d N ( –60 AI G –80 –100 –120 10 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 10877-036 Figure 37. Shutdown Isolation vs. Frequency Rev. C | Page 21 of 36

AD5124/AD5144/AD5144A Data Sheet TEST CIRCUITS Figure 39 to Figure 43 define the test conditions used in the Specifications section. NC DUT A IW VA W V+ = VDD ±10% (ΔVMS) B V+ ~ VDD A W PSRR (dB) = 20 LOG ΔVDD NC = NO CONNECVTMS 10877-038 B VMS PSS (%/%) =ΔΔVVDMDS%% 10877-041 Figure 39. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 42. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS and PSRR) 0.1V DUT RSW= ISW CODE = 0x00 W + DUT A V1L+S =B V =D DV+/2N B ISW –0.1V W V+ B VMS 10877-039 A = NC VSSTO VDD 10877-045 Figure 40. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 43. Incremental On Resistance NC DUT IW= VDD/RNOMINAL A W VW B VMS1 RW = VMS1/IW NC = NO CONNECT 10877-040 Figure 41. Wiper Resistance Rev. C | Page 22 of 36

Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION The AD5124/AD5144/AD5144A digital programmable SERIAL DATA DIGITAL INTERFACE SELECTION, DIS potentiometers are designed to operate as true variable resistors The AD5124/AD5144 LFSCP provides the flexibility of a selectable for analog signals within the terminal voltage range of V < V < SS TERM interface. When the digital interface select (DIS) pin is tied low, V . The resistor wiper position is determined by the RDAC DD the SPI mode is engaged. When the DIS pin is tied high, the I2C register contents. The RDAC register acts as a scratchpad register mode is engaged. that allows unlimited changes of resistance settings. A secondary SPI SERIAL DATA INTERFACE register (the input register) can be used to preload the RDAC register data. The AD5124/AD5144 contain a 4-wire, SPI-compatible digital The RDAC register can be programmed with any position setting interface (SDI, SYNC, SDO, and SCLK). The write sequence using the I2C or SPI interface (depending on the model). When begins by bringing the SYNC line low. The SYNC pin must be a desirable wiper position is found, this value can be stored in held low until the complete data-word is loaded from the SDI the EEPROM memory. Thereafter, the wiper position is always pin. Data is loaded in at the SCLK falling edge transition, as restored to that position for subsequent power-ups. The storing shown in Figure 6. When SYNC returns high, the serial data- of the EEPROM data takes approximately 15 ms; during this word is decoded according to the instructions in Table 20. time, the device is locked and does not acknowledge any new To minimize power consumption in the digital input buffers command, preventing any changes from taking place. when the part is enabled, operate all serial interface pins close RDAC REGISTER AND EEPROM to the V supply rails. LOGIC The RDAC register directly controls the position of the digital SYNC Interruption potentiometer wiper. For example, when the RDAC register is In a standalone write sequence for the AD5124/AD5144, the loaded with 0x80 (AD5144/AD5144A, 256 taps), the wiper is SYNC line is kept low for 16 falling edges of SCLK, and the connected to half scale of the variable resistor. The RDAC register instruction is decoded when SYNC is pulled high. However, if is a standard logic register; there is no restriction on the number the SYNC line is kept low for less than 16 falling edges of SCLK, of changes allowed. the input shift register content is ignored, and the write sequence is It is possible to both write to and read from the RDAC register considered invalid. using the digital interface (see Table 14). SDO Pin The contents of the RDAC register can be stored to the EEPROM The serial data output pin (SDO) serves two purposes: to read back using Command 9 (see Table 14). Thereafter, the RDAC register the contents of the control, EEPROM, RDAC, and input registers always sets at that position for any future on-off-on power using Command 3 (see Table 14 and Table 20), and to connect the supply sequence. It is possible to read back data saved into the AD5124/AD5144 in daisy-chain mode. EEPROM with Command 3 (see Table 14). The SDO pin contains an internal open-drain output that needs an Alternatively, the EEPROM can be written to independently external pull-up resistor. The SDO pin is enabled when SYNC is using Command 11 (see Table 20). pulled low, and the data is clocked out of SDO on the rising INPUT SHIFT REGISTER edge of SCLK, as shown in Figure 6 and Figure 7. For the AD5124/AD5144/AD5144A, the input shift register is 16 bits wide, as shown in Figure 4. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. If the AD5124 RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command, as listed in Table 14 and Table 20. Rev. C | Page 23 of 36

AD5124/AD5144/AD5144A Data Sheet Daisy-Chain Connection To prevent data from mislocking (for example, due to noise) the part includes an internal counter, if the SCLK falling edges count is Daisy chaining minimizes the number of port pins required from not a multiple of 8, the part ignores the command. A valid clock the controlling IC. As shown in Figure 44, the SDO pin of one package must be tied to the SDI pin of the next package. The clock count is 16, 24, 32, 40, and so on. The counter resets when SYNC period may need to be increased because of the propagation returns high. delay of the line between subsequent devices. When two AD5124/ AD5144 devices are daisy chained, 32 bits of data are required. The first 16 bits are assigned to U2, and the second 16 bits are assigned to U1, as shown in Figure 45. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. VLOGIC VLOGIC AD5124/ RP AD5124/ RP AD5144 2.2kΩ AD5144 2.2kΩ MOSI SDI U1 SDO SDI U2 SDO MICROCONTROLLER MISO SCLK SS SYNC SCLK SYNC SCLK N AI H C Y- DAIS 10877-046 Figure 44. Daisy-Chain Configuration SCLK 1 2 16 17 18 32 SYNC MOSI DB15 DB0 DB15 DB0 INPUT WORD FOR U2 INPUT WORD FOR U1 SDO_U1 DB15 DB0 DB15 DB0 UNDEFINED INPUT WORD FOR U2 10877-047 Figure 45. Daisy-Chain Diagram Rev. C | Page 24 of 36

Data Sheet AD5124/AD5144/AD5144A I2C SERIAL DATA INTERFACE I2C ADDRESS The AD5144/AD5144A have 2-wire, I2C-compatible serial The AD5144/AD5144A each have two different device address interfaces. These devices can be connected to an I2C bus as a options available (see Table 12 and Table 13). slave device, under the control of a master device. See Figure 5 Table 12. 20-Lead TSSOP Device Address Selection for a timing diagram of a typical write sequence. ADDR 7-Bit I2C Device Address The AD5144/AD5144A support standard (100 kHz) and fast V 0101000 LOGIC (400 kHz) data transfer modes. Support is not provided for No connect1 0101010 10-bit addressing and general call addressing. GND 0101011 The 2-wire serial bus protocol operates as follows: 1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). 1. The master initiates a data transfer by establishing a start Table 13. 24-Lead LFCSP Device Address Selection condition, which is when a high-to-low transition on the ADDR0 Pin ADDR1 Pin 7-Bit I2C Device Address SDA line occurs while SCL is high. The following byte is V V 0100000 the address byte, which consists of the 7-bit slave address LOGIC LOGIC No connect1 V 0100010 and an R/W bit. The slave device corresponding to the LOGIC GND V 0100011 transmitted address responds by pulling SDA low during LOGIC V No connect1 0101000 the ninth clock pulse (this is called the acknowledge bit). LOGIC No connect1 No connect1 0101010 At this stage, all other devices on the bus remain idle while GND No connect1 0101011 the selected device waits for data to be written to, or read V GND 0101100 from, its shift register. LOGIC No connect1 GND 0101110 If the R/W bit is set high, the master reads from the slave GND GND 0101111 device. However, if the R/W bit is set low, the master writes to the slave device. 1 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read from or written to, a stop condition is established. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then high again during the tenth clock pulse to establish a stop condition. Rev. C | Page 25 of 36

AD5124/AD5144/AD5144A Data Sheet Table 14. Reduced Commands Operation Truth Table Control Address Command Bits[DB15:DB12] Bits[DB11:DB8]1 Data Bits[DB7:DB0]1 Number C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing. 1 0 0 0 1 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 Write contents of serial register data to RDAC 2 0 0 1 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 Write contents of serial register data to input register 3 0 0 1 1 X 0 A1 A0 X X X X X X D1 D0 Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC 9 0 1 1 1 0 0 A1 A0 X X X X X X X 1 Copy RDAC register to EEPROM 10 0 1 1 1 0 0 A1 A0 X X X X X X X 0 Copy EEPROM into RDAC 14 1 0 1 1 X X X X X X X X X X X X Software reset 15 1 1 0 0 A3 0 A1 A0 X X X X X X X D0 Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode 1 X = don’t care. 2 D0 = don’t care for AD5124. Table 15. Reduced Address Bits Table A3 A2 A1 A0 Channel Stored Channel Memory 1 0 X1 X1 All channels Not applicable 0 0 0 0 RDAC1 RDAC1 0 0 0 1 RDAC2 RDAC2 0 0 1 0 RDAC3 RDAC3 0 0 1 1 RDAC4 RDAC4 1 X = don’t care. Rev. C | Page 26 of 36

Data Sheet AD5124/AD5144/AD5144A ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5124/AD5144/AD5144A digital potentiometers include The AD5124/AD5144/AD5144A include two commands to a set of user programming features to address the wide number of reduce the wiper resistance between the terminals when the applications for these universal adjustment devices (see Table 20 devices achieve full scale or zero scale. These extra positions are and Table 22). called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as R . Key programming features include the following: TS Similarly, the bottom scale resistance between Terminal B and • Input register Terminal W is specified as R . BS • Linear gain setting mode The contents of the RDAC registers are unchanged by entering • Low wiper resistance feature into these positions. There are three ways to exit from top scale • Linear increment and decrement instructions and bottom scale: by using Command 12 or Command 13 • ±6 dB increment and decrement instructions (see Table 20); by loading new data in an RDAC register, which • Burst mode (I2C only) includes increment/decrement operations; or by entering • Reset shutdown mode, Command 15 (see Table 20). • Shutdown mode Table 16 and Table 17 show the truth tables for the top scale Input Register position and the bottom scale position, respectively, when the potentiometer or linear gain setting mode is enabled. The AD5124/AD5144/AD5144A include one input register per RDAC register. These registers allow preloading of the value for Table 16. Top Scale Truth Table the associated RDAC register. These registers can be written to Linear Gain Setting Mode Potentiometer Mode using Command 2 and read back from using Command 3 (see R R R R AW WB AW WB Table 20). R R R R AB AB TS AB This feature allows a synchronous and asynchronous update of one or all of the RDAC registers at the same time. Table 17. Bottom Scale Truth Table Linear Gain Setting Mode Potentiometer Mode The transfer from the input register to the RDAC register is R R R R done asynchronously by the LRDAC pin or synchronously by AW WB AW WB R R R R TS BS AB BS Command 8 (see Table 20). Linear Increment and Decrement Instructions If new data is loaded into an RDAC register, this RDAC register automatically overwrites the associated input register. The increment and decrement commands (Command 4 and Command 5 in Table 20) are useful for linear step adjustment Linear Gain Setting Mode applications. These commands simplify microcontroller software The proprietary architecture of the AD5124/AD5144/AD5144A coding by allowing the controller to send an increment or allows the independent control of each string resistor, R , and AW decrement command to the device. The adjustment can be R . To enable this feature, use Command 16 (see Table 20) to set WB individual or in a ganged potentiometer arrangement, where Bit D2 of the control register (see Table 22). all wiper positions are changed at the same time. This mode of operation can control the potentiometer as two For an increment command, executing Command 4 automatically independent rheostats connected at a single point, the W terminal. moves the wiper to the next RDAC position. This command This feature enables a second input and an RDAC register per can be executed in a single channel or multiple channels. channel, as shown in Table 21, but the actual RDAC contents remain unchanged. The same operations are valid for potentiometer and linear gain setting modes. The EEPROM commands affect the RWB resistance only. The parts restores in potentiometer mode after a reset or power-up. Rev. C | Page 27 of 36

AD5124/AD5144/AD5144A Data Sheet ±6 dB Increment and Decrement Instructions Shutdown Mode Two programming instructions produce logarithmic taper The AD5124/AD5144/AD5144A can be placed in shutdown mode increment or decrement of the wiper position control by by executing the software shutdown command, Command 15 an individual potentiometer or by a ganged potentiometer (see Table 20), and setting the LSB (D0) to 1. This feature places arrangement where all RDAC register positions are changed the RDAC in a zero power consumption state where the device simultaneously. The +6 dB increment is activated by Command 6, operates in potentiometer mode, Terminal A is open circuited, and the −6 dB decrement is activated by Command 7 (see Table 20). and the wiper, Terminal W, is connected to Terminal B; however, a For example, starting with the zero-scale position and executing finite wiper resistance of 40 Ω is present. When the device is Command 6 ten times moves the wiper in 6 dB steps to the full- configured in linear gain setting mode, the resistor addressed, scale position. When the wiper position is near the maximum R or R , is internally place at high impedance. Table 19 shows a AW WB setting, the last 6 dB increment instruction causes the wiper to go truth table depending on the device operating mode. The contents to the full-scale position (see Table 18). of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 20 are supported while Incrementing the wiper position by +6 dB essentially doubles the in shutdown mode. Execute Command 15 (see Table 20) and set RDAC register value, whereas decrementing the wiper position the LSB (D0) to 0 to exit shutdown mode. by −6 dB halves the register value. Internally, the AD5124/ AD5144/AD5144A use shift registers to shift the bits left and Table 19. Shutdown Mode Truth Table right to achieve a ±6 dB increment or decrement. These functions Linear Gain Setting Mode Potentiometer Mode are useful for various audio/video level adjustments, especially R R R R AW WB AW WB for white LED brightness settings in which human visual responses High impedance High impedance High impedance R BS are more sensitive to large adjustments than to small adjustments. EEPROM OR RDAC REGISTER PROTECTION Table 18. Detailed Left Shift and Right Shift Functions for The EEPROM and RDAC registers can be protected by disabling the ±6 dB Step Increment and Decrement any update to these registers. This can be done by using software or Left Shift (+6 dB/Step) Right Shift (−6 dB/Step) by using hardware. If these registers are protected by software, 0000 0000 1111 1111 set Bit D0 and/or Bit D1 (see Table 22), which protects the RDAC 0000 0001 0111 1111 and EEPROM registers independently. 0000 0010 0011 1111 0000 0100 0001 1111 If the registers are protected by hardware, pull the WP pin low 0000 1000 0000 1111 (only available in the LFCSP package). If the WP pin is pulled 0001 0000 0000 0111 low when the part is executing a command, the protection is not 0010 0000 0000 0011 enabled until the command is completed (only available in the 0100 0000 0000 0001 LFCSP package). 1000 0000 0000 0000 When RDAC is protected, the only operation allowed is to copy 1111 1111 0000 0000 the EEPROM into the RDAC register. Burst Mode (I2C Only) LOAD RDAC INPUT REGISTER (LRDAC) By enabling the burst mode, multiple data bytes can be sent to LRDAC software or hardware transfers data from the input the part consecutively. After the command byte, the part interprets register to the RDAC register (and therefore updates the wiper the following consecutive bytes as data bytes for the command. position). By default, the input register has the same value as the A new command can be sent by generating a repeat start or by a RDAC register; therefore, only the input register that has been stop and start condition. updated using Command 2 is updated. The burst mode is activated by setting Bit D3 of the control Software LRDAC, Command 8, allows updating of a single RDAC register (see Table 22). register or all of the channels at once (see Table 20). This is a Reset synchronous update. The AD5124/AD5144/AD5144A can be reset through software The hardware LRDAC is completely asynchronous and copies by executing Command 14 (see Table 20) or through hardware the content of all the input registers into the associated RDAC on the low pulse of the RESET pin. The reset command loads the registers. If a command is being executed, any transition in the RDAC register with the contents of the EEPROM and takes LRDAC pin is ignored by the part to avoid data corruption. approximately 30 µs. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to V if the RESET pin is not used. DD Rev. C | Page 28 of 36

Data Sheet AD5124/AD5144/AD5144A Table 20. Advance Commands Operation Truth Table Control Address Command Bits[DB15:DB12] Bits[DB11:DB8]1 Data Bits[DB7:DB0]1 Number C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing 1 0 0 0 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 Write contents of serial register data to RDAC 2 0 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 Write contents of serial register data to input register 3 0 0 1 1 X A2 A1 A0 X X X X X X D1 D0 Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC 4 0 1 0 0 A3 A2 A1 A0 X X X X X X X 1 Linear RDAC increment 5 0 1 0 0 A3 A2 A1 A0 X X X X X X X 0 Linear RDAC decrement 6 0 1 0 1 A3 A2 A1 A0 X X X X X X X 1 +6 dB RDAC increment 7 0 1 0 1 A3 A2 A1 A0 X X X X X X X 0 −6 dB RDAC decrement 8 0 1 1 0 A3 A2 A1 A0 X X X X X X X X Copy input register to RDAC (software LRDAC) 9 0 1 1 1 0 0 A1 A0 X X X X X X X 1 Copy RDAC register to EEPROM 10 0 1 1 1 0 0 A1 A0 X X X X X X X 0 Copy EEPROM into RDAC 11 1 0 0 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 Write contents of serial register data to EEPROM 12 1 0 0 1 A3 A2 A1 A0 1 X X X X X X D0 Top scale D0 = 1; enter D0 = 0; exit 13 1 0 0 1 A3 A2 A1 A0 0 X X X X X X D0 Bottom scale D0 = 1; enter D0 = 0; exit 14 1 0 1 1 X X X X X X X X X X X X Software reset 15 1 1 0 0 A3 A2 A1 A0 X X X X X X X D0 Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode 16 1 1 0 1 X X X X X X X X D3 D2 D1 D0 Copy serial register data to control register 1 X = don’t care. 2 D0 = don’t care for AD5124. Rev. C | Page 29 of 36

AD5124/AD5144/AD5144A Data Sheet Table 21. Address Bits Potentiometer Mode Linear Gain Setting Mode Stored RDAC A3 A2 A1 A0 Input Register RDAC Register Input Register RDAC Register Memory 1 X1 X1 X1 All channels All channels All channels All channels Not applicable 0 0 0 0 RDAC1 RDAC1 R R RDAC1 WB1 WB1 0 1 0 0 Not applicable Not applicable R R Not applicable AW1 AW1 0 0 0 1 RDAC2 RDAC2 R R RDAC2 WB2 WB2 0 1 0 1 Not applicable Not applicable R R Not applicable AW2 AW2 0 0 1 0 RDAC3 RDAC3 R R RDAC3 WB3 WB3 0 1 1 0 Not applicable Not applicable R R Not applicable AW3 AW3 0 0 1 1 RDAC4 RDAC4 R R RDAC4 WB4 WB4 0 1 1 1 Not applicable Not applicable R R Not applicable AW4 AW4 1 X = don’t care. Table 22. Control Register Bit Descriptions Bit Name Description D0 RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) D1 EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) D2 Linear setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode D3 Burst mode (I2C only) 0 = disabled (default) 1 = enabled (no disable after stop or repeat start condition) Rev. C | Page 30 of 36

Data Sheet AD5124/AD5144/AD5144A RDAC ARCHITECTURE PROGRAMMING THE VARIABLE RESISTOR To achieve optimum performance, Analog Devices, Inc., has Rheostat Operation—±8% Resistor Tolerance proprietary RDAC segmentation architecture for all the digital The AD5124/AD5144/AD5144A operate in rheostat mode when potentiometers. In particular, the AD5124/AD5144 employ a only two terminals are used as a variable resistor. The unused three-stage segmentation approach, as shown in Figure 46. The terminal can be floating, or it can be tied to Terminal W, as shown AD5124/AD5144/AD5144A wiper switch is designed with the in Figure 47. transmission gate CMOS topology and with the gate voltage derived from VDD and VSS. A A A A STS W W W RH B B B 10877-049 Figure 47. Rheostat Mode Configuration RH RM The nominal resistance between Terminal A and Terminal B, R , is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by AB the wiper terminal. The 7-bit/8-bit data in the RDAC latch is RM decoded to select one of the 128/256 possible wiper settings. The RL general equations for determining the digitally programmed W output resistance between Terminal W and Terminal B are 7-BIT/8-BIT RL AD5124: DAEDCDORDESESR RM D RH RWB(D)128RAB RW From 0x00 to 0x7F (1) RM AD5144/AD5144A: RH SBS D R (D) R R From 0x00 to 0xFF (2) WB 256 AB W B where: 10877-048 DRD isA tChe r edgeicsitmera. l equivalent of the binary code in the 7-bit/8-bit Figure 46. AD5124/AD5144/AD5144A Simplified RDAC Circuit R is the end-to-end resistance. AB Top Scale/Bottom Scale Architecture RW is the wiper resistance. In addition, the AD5124/AD5144/AD5144A include new In potentiometer mode, similar to the mechanical potentiometer, positions to reduce the resistance between terminals. These the resistance between Terminal W and Terminal A also produces positions are called bottom scale and top scale. At bottom scale, a digitally controlled complementary resistance, RWA. RWA also the typical wiper resistance decreases from 130 Ω to 60 Ω (RAB = gives a maximum of 8% absolute resistance error. RWA starts at the 100 kΩ). At top scale, the resistance between Terminal A and maximum resistance value and decreases as the data loaded into Terminal W is decreased by 1 LSB, and the total resistance is the latch increases. The general equations for this operation are reduced to 60 Ω (RAB = 100 kΩ). AD5124: 128D R (D) R R From 0x00 to 0x7F (3) AW 128 AB W AD5144/AD5144A: R (D)256DR R From 0x00 to 0xFF (4) AW 256 AB W where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. R is the end-to-end resistance. AB R is the wiper resistance. W Rev. C | Page 31 of 36

AD5124/AD5144/AD5144A Data Sheet If the part is configured in linear gain setting mode, the resistance TERMINAL VOLTAGE OPERATING RANGE between Terminal W and Terminal A is directly proportional The AD5124/AD5144/AD5144A are designed with internal ESD to the code loaded in the associate RDAC register. The general diodes for protection. These diodes also set the voltage boundary equations for this operation are of the terminal operating voltages. Positive signals present on AD5124: Terminal A, Terminal B, or Terminal W that exceed V are DD clamped by the forward-biased diode. There is no polarity D RWB(D)128RAB RW From 0x00 to 0x7F (5) constraint between VA, VW, and VB, but they cannot be higher than V or lower than V . DD SS AD5144/AD5144A: VDD D R (D) R R From 0x00 to 0xFF (6) WB 256 AB W A where: D is the decimal equivalent of the binary code in the 7-bit/8-bit W RDAC register. B R is the end-to-end resistance. AB RW is the wiper resistance. VSS 10877-051 In the bottom scale condition or top scale condition, a finite Figure 49. Maximum Terminal Voltages Set by VDD and VSS total wiper resistance of 40 Ω is present. Regardless of which POWER-UP SEQUENCE setting the part is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Because there are diodes to limit the voltage compliance at Terminal W to Terminal B to the maximum continuous Terminal A, Terminal B, and Terminal W (see Figure 49), it is current of ±6 mA or to the pulse current specified in Table 7. important to power up V first before applying any voltage to DD Otherwise, degradation or possible destruction of the internal Terminal A, Terminal B, and Terminal W. Otherwise, the diode switch contact can occur. is forward-biased such that V is powered unintentionally. The DD ideal power-up sequence is V , V , V , digital inputs, and PROGRAMMING THE POTENTIOMETER DIVIDER SS DD LOGIC V , V , and V . The order of powering V , V , V , and digital A B W A B W Voltage Output Operation inputs is not important as long as they are powered after V , SS The digital potentiometer easily generates a voltage divider at V , and V . Regardless of the power-up sequence and the DD LOGIC wiper-to-B and wiper-to-A that is proportional to the input voltage ramp rates of the power supplies, once V is powered, the DD at A to B, as shown in Figure 48. power-on preset activates, which restores EEPROM values to the RDAC registers. VA A LAYOUT AND POWER SUPPLY BIASING W VOUT VB B 10877-050 Ilet nisg tahlw laayyos uat gdoeosdig pnr. aEcntiscuer teo t huaset tah ceo lmeapdasc tto, mthien iinmpuumt a lreea das Figure 48. Potentiometer Mode Configuration direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also Connecting Terminal A to 5 V and Terminal B to ground good practice to bypass the power supplies with quality capacitors. produces an output voltage at the Wiper W to Terminal B Apply low equivalent series resistance (ESR) 1 μF to 10 μF ranging from 0 V to 5 V. The general equation defining the tantalum or electrolytic capacitors at the supplies to minimize output voltage at V with respect to ground for any valid W any transient disturbance and to filter low frequency ripple. input voltage applied to Terminal A and Terminal B is Figure 50 illustrates the basic supply bypassing configuration R (D) R (D) V (D) WB V  AW V (7) for the AD5124/AD5144/AD5144A. W R A R B AB AB where: VDD + C3 C1 VDD VLOGIC + C5 C6 VLOGIC 10µF 0.1µF 0.1µF 10µF R (D) can be obtained from Equation 1 and Equation 2. AD5124/ WB AD5144/ RAW(D) can be obtained from Equation 3 and Equation 4. + C104µF C0.21µF AD5144A Operation of the digital potentiometer in the divider mode results VSS VSS GND in a more accurate operation over temperature. Unlike the rrhateioos otaf tt hmeo idnete, rthnea lo ruetspisutto rvso, lRtaAgWe aisn dd eRpWeBn,d aenndt nmoati nthlye oabns tohlue te 10877-052 values. Therefore, the temperature drift reduces to 5 ppm/°C. Figure 50. Power Supply Bypassing Rev. C | Page 32 of 36

Data Sheet AD5124/AD5144/AD5144A OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 0.30 4.00 SQ 0.25 PIN 1 INDICATOR 3.90 0.20 AREA 19 24 PININD I1CATORAREAOPTIONS 18 1 (SEEDETAILA) 0.50 BSC 2.20 EXPPAODSED 2.10 SQ 2.00 13 6 0.50 12 7 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 SIDE VIEW THE PIN CONFIGURATION AND 0.70 0.05 MAX FUNCTION DESCRIPTIONS 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE 0.203 REF PKG-004714 COMPLIANTTOJEDEC STANDARDS MO-220-WGGD-8 09-07-2018-B Figure 51. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 0.15 1.20 MAX 0.20 0.05 0.09 0.75 0.30 8° 0.60 COPLANARITY 0.19 SEATING 0° 0.45 0.10 PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 52. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. C | Page 33 of 36

AD5124/AD5144/AD5144A Data Sheet ORDERING GUIDE Model1, 2 R (kΩ) Resolution Interface Temperature Range Package Description Package Option AB AD5124BCPZ10-RL7 10 128 SPI/I2C −40°C to +125°C 24-Lead LFCSP CP-24-10 AD5124BCPZ100-RL7 100 128 SPI/I2C −40°C to +125°C 24-Lead LFCSP CP-24-10 AD5124BRUZ10 10 128 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5124BRUZ100 100 128 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5124BRUZ10-RL7 10 128 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5124BRUZ100-RL7 100 128 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5144BCPZ10-RL7 10 256 SPI/I2C −40°C to +125°C 24-Lead LFCSP CP-24-10 AD5144BCPZ100-RL7 100 256 SPI/I2C −40°C to +125°C 24-Lead LFCSP CP-24-10 AD5144BRUZ10 10 256 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5144BRUZ100 100 256 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5144BRUZ10-RL7 10 256 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5144BRUZ100-RL7 100 256 SPI −40°C to +125°C 20-Lead TSSOP RU-20 AD5144ABRUZ10 10 256 I2C −40°C to +125°C 20-Lead TSSOP RU-20 AD5144ABRUZ100 100 256 I2C −40°C to +125°C 20-Lead TSSOP RU-20 AD5144ABRUZ10-RL7 10 256 I2C −40°C to +125°C 20-Lead TSSOP RU-20 AD5144ABRUZ100-RL7 100 256 I2C −40°C to +125°C 20-Lead TSSOP RU-20 EVAL-AD5144DBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options. Rev. C | Page 34 of 36

Data Sheet AD5124/AD5144/AD5144A NOTES Rev. C | Page 35 of 36

AD5124/AD5144/AD5144A Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10877-0-7/19(C) Rev. C | Page 36 of 36