Dual Channel, 128-/256-Position, SPI, Nonvolatile Digital Potentiometer Data Sheet AD5122/AD5142 FEATURES FUNCTIONAL BLOCK DIAGRAM 10 kΩ and 100 kΩ resistance options VLOGIC VDD INDEP Resistor tolerance: ±8% maximum POWER-ON Wiper current: ±6 mA RESET AD5122/ AD5142 Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz RDAC1 A1 Fast start-up time <75 µs RESET INPUT W1 Linear gain setting mode REGISTER 1 SCLK B1 Single- and dual-supply operation SERIAL RDAC2 Independent logic supply: 1.8 V to 5.5 V SDI INTERFACE 7/8 INPUT A2 REGISTER 2 W2 Wide operating temperature: −40°C to +125°C SYNC B2 3 mm × 3 mm package option SDO EEPROM Qualified for automotive applications MEMORY APPLICATIONS GND VSS 10880-001 Portable electronics level adjustment LCD panel brightness and contrast controls Figure 1. Programmable filters, delays, and time constants Programmable power supplies GENERAL DESCRIPTION The AD5122/AD5142 are available in a compact, 16-lead, 3 mm × 3 mm LFCSP and a 16-lead TSSOP. The devices are guaranteed The AD5122/AD5142 potentiometers provide a nonvolatile to operate over the extended industrial temperature range of solution for 128-/256-position adjustment applications, offering −40°C to +125°C. guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. Table 1. Family Models The low resistor tolerance and low nominal temperature coefficient Model Channel Position Interface Package simplify open-loop applications as well as applications requiring AD51231 Quad 128 I2C LFCSP tolerance matching. AD5124 Quad 128 SPI/I2C LFCSP AD5124 Quad 128 SPI TSSOP The linear gain setting mode allows independent programming AD51431 Quad 256 I2C LFCSP of the resistance between the digital potentiometer terminals AD5144 Quad 256 SPI/I2C LFCSP through the R and R string resistors, allowing accurate AW WB AD5144 Quad 256 SPI TSSOP resistor matching. AD5144A Quad 256 I2C TSSOP The high bandwidth and low total harmonic distortion (THD) AD5122 Dual 128 SPI LFCSP/TSSOP ensure optimal performance for ac signals, making these devices AD5122A Dual 128 I2C LFCSP/TSSOP suitable for filter design. AD5142 Dual 256 SPI LFCSP/TSSOP The low wiper resistance of only 40 Ω at the ends of the resistor AD5142A Dual 256 I2C LFCSP/TSSOP array allows pin to pin connection. AD5121 Single 128 SPI/I2C LFCSP AD5141 Single 256 SPI/I2C LFCSP The wiper values can be set through an SPI-compatible digital interface that also reads back the wiper register and EEPROM 1 Two potentiometers and two rheostats. contents. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5122/AD5142 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RDAC Register and EEPROM .................................................. 20 Applications ....................................................................................... 1 Input Shift Register .................................................................... 20 Functional Block Diagram .............................................................. 1 SPI Serial Data Interface ............................................................ 20 General Description ......................................................................... 1 Advanced Control Modes ......................................................... 23 Revision History ............................................................................... 2 EEPROM or RDAC Register Protection ................................. 24 Specifications ..................................................................................... 3 INDEP Pin ................................................................................... 24 Electrical Characteristics—AD5122 .......................................... 3 RDAC Architecture .................................................................... 27 Electrical Characteristics—AD5142 .......................................... 6 Programming the Variable Resistor ......................................... 27 Interface Timing Specifications .................................................. 9 Programming the Potentiometer Divider ............................... 28 Shift Register and Timing Diagrams ....................................... 10 Terminal Voltage Operating Range ......................................... 28 Absolute Maximum Ratings .......................................................... 11 Power-Up Sequence ................................................................... 28 Thermal Resistance .................................................................... 11 Layout and Power Supply Biasing ............................................ 28 ESD Caution ................................................................................ 11 Outline Dimensions ....................................................................... 29 Pin Configurations and Function Descriptions ......................... 12 Ordering Guide .......................................................................... 30 Typical Performance Characteristics ........................................... 14 Automotive Products ................................................................. 30 Test Circuits ..................................................................................... 19 Theory of Operation ...................................................................... 20 REVISION HISTORY 5/2017—Rev. B to Rev. C Changes to RDAC Architecture Section ..................................... 27 Changes to Figure 6 and Table 8 ................................................... 12 Changes to Ordering Guide .......................................................... 30 Changes to Figure 16 and Figure 17 ............................................. 15 Added Automotive Products Section .......................................... 30 Changes to EEPROM or RDAC Register Protection Section ........ 24 Updated Outline Dimensions ....................................................... 29 2/2016—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 30 Changes to Features Section ............................................................ 1 Added Endnote, Table 2 ................................................................... 5 6/2016—Rev. A to Rev. B Added Endnote, Table 3 ................................................................... 8 Changes to Features Section............................................................ 1 Added Endnote, Table 4 ................................................................... 9 Changes to Logic Supply Current Parameter, Table 2 ................. 4 Changes to Figure 3 Caption and Figure 4 Caption .................. 10 Changes to Logic Supply Current Parameter, Table 3 ................. 7 Changes to Table 6 .......................................................................... 11 Changes to Figure 16 ...................................................................... 15 Changes to Figure 6 ........................................................................ 12 Added Figure 17; Renumbered Sequentially .............................. 15 Changes to Figure 18 ...................................................................... 16 10/2012—Revision 0: Initial Version Change to Linear Gain Setting Mode Section ............................ 23 Rev. C | Page 2 of 32

Data Sheet AD5122/AD5142 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5122 V = 2.3 V to 5.5 V, V = 0 V; V = 2.25 V to 2.75 V, V = −2.25 V to −2.75 V; V = 1.8 V to 5.5 V, −40°C < T < +125°C, unless DD SS DD SS LOGIC A otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 7 Bits Resistor Integral Nonlinearity2 R-INL R = 10 kΩ AB V ≥ 2.7 V −1 ±0.1 +1 LSB DD V < 2.7 V −2.5 ±1 +2.5 LSB DD R = 100 kΩ AB V ≥ 2.7 V −0.5 ±0.1 +0.5 LSB DD V < 2.7 V −1 ±0.25 +1 LSB DD Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.1 +0.5 LSB Nominal Resistor Tolerance ΔR /R −8 ±1 +8 % AB AB Resistance Temperature Coefficient3 (ΔR /R )/ΔT × 106 Code = full scale 35 ppm/°C AB AB Wiper Resistance3 R Code = zero scale W R = 10 kΩ 55 125 Ω AB R = 100 kΩ 130 400 Ω AB Bottom Scale or Top Scale R or R BS TS R = 10 kΩ 40 80 Ω AB R = 100 kΩ 60 230 Ω AB Nominal Resistance Match R /R Code = 0xFF −1 ±0.2 +1 % AB1 AB2 DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL R = 10 kΩ −0.5 ±0.1 +0.5 LSB AB R = 100 kΩ −0.25 ±0.1 +0.25 LSB AB Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB Full-Scale Error V WFSE R = 10 kΩ −1.5 −0.1 LSB AB R = 100 kΩ −0.5 ±0.1 +0.5 LSB AB Zero-Scale Error V WZSE R = 10 kΩ 1 1.5 LSB AB R = 100 kΩ 0.25 0.5 LSB AB Voltage Divider Temperature (ΔV /V )/ΔT × 106 Code = half scale ±5 ppm/°C W W Coefficient3 Rev. C | Page 3 of 32

AD5122/AD5142 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit RESISTOR TERMINALS Maximum Continuous Current I , I , and I A B W R = 10 kΩ −6 +6 mA AB R = 100 kΩ −1.5 +1.5 mA AB Terminal Voltage Range5 V V V SS DD Capacitance A, Capacitance B3 C , C f = 1 MHz, measured to GND, A B code = half scale R = 10 kΩ 25 pF AB R = 100 kΩ 12 pF AB Capacitance W3 C f = 1 MHz, measured to GND, W code = half scale R = 10 kΩ 12 pF AB R = 100 kΩ 5 pF AB Common-Mode Leakage Current3 V = V = V −500 ±15 +500 nA A W B DIGITAL INPUTS Input Logic3 High V V = 1.8 V to 2.3 V 0.8 × V V INH LOGIC LOGIC V = 2.3 V to 5.5 V 0.7 × V V LOGIC LOGIC Low V 0.2 × V V INL LOGIC Input Hysteresis3 V 0.1 × V V HYST LOGIC Input Current3 I ±1 µA IN Input Capacitance3 C 5 pF IN DIGITAL OUTPUTS Output High Voltage3 V R = 2.2 kΩ to V V V OH PULL-UP LOGIC LOGIC Output Low Voltage3 V I = 3 mA 0.4 V OL SINK I = 6 mA, V > 2.3 V 0.6 V SINK LOGIC Three-State Leakage Current −1 +1 µA Three-State Output Capacitance 2 pF POWER SUPPLIES Single-Supply Power Range V = GND 2.3 5.5 V SS Dual-Supply Power Range ±2.25 ±2.75 V Logic Supply Range Single supply, V = GND 1.8 V V SS DD Dual supply, V < GND 2.25 V V SS DD Positive Supply Current I V = V or V = GND DD IH LOGIC IL V = 5.5 V 0.7 5.5 µA DD V = 2.3 V 400 nA DD Negative Supply Current I V = V or V = GND −5.5 −0.7 µA SS IH LOGIC IL EEPROM Store Current3, 6 I V = V or V = GND 2 mA DD_EEPROM_STORE IH LOGIC IL EEPROM Read Current3, 7 I V = V or V = GND 320 µA DD_EEPROM_READ IH LOGIC IL Logic Supply Current I V = V or V = GND 0.05 1.4 µA LOGIC IH LOGIC IL Power Dissipation8 P V = V or V = GND 3.5 µW DISS IH LOGIC IL Power Supply Rejection Ratio PSRR ∆V /∆V = V ± 10%, −66 −60 dB DD SS DD code = full scale Rev. C | Page 4 of 32

Data Sheet AD5122/AD5142 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB R = 10 kΩ 3 MHz AB R = 100 kΩ 0.43 MHz AB Total Harmonic Distortion THD V /V = ±2.5 V, V = 1 V rms, DD SS A V = 0 V, f = 1 kHz B R = 10 kΩ −80 dB AB R = 100 kΩ −90 dB AB Resistor Noise Density e Code = half scale, T = 25°C, N_WB A f = 10 kHz R = 10 kΩ 7 nV/√Hz AB R = 100 kΩ 20 nV/√Hz AB V Settling Time t V = 5 V, V = 0 V, from W S A B zero scale to full scale, ±0.5 LSB error band R = 10 kΩ 2 µs AB R = 100 kΩ 12 µs AB Crosstalk (C /C ) C R = 10 kΩ 10 nV-sec W1 W2 T AB R = 100 kΩ 25 nV-sec AB Analog Crosstalk C −90 dB TA Endurance10 T = 25°C 1 Mcycles A 100 kcycles Data Retention11, 12 50 Years 1 Typical values represent average readings at 25°C, V = 5 V, V = 0 V, and V = 5 V. DD SS LOGIC 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × V )/R . DD AB 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V = V and V = 0 V. DNL specification limits WB A DD B of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 P is calculated from (I × V ) + (I × V ). DISS DD DD LOGIC LOGIC 9 All dynamic characteristics use V /V = ±2.5 V, and V = 2.5 V. DD SS LOGIC 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years applies to an endurance of 1k cycles. An endurance of 100k cycles has an equivalent retention lifetime of 5 years. Rev. C | Page 5 of 32

AD5122/AD5142 Data Sheet ELECTRICAL CHARACTERISTICS—AD5142 V = 2.3 V to 5.5 V, V = 0 V; V = 2.25 V to 2.75 V, V = −2.25 V to −2.75 V; V = 1.8 V to 5.5 V, −40°C < T < +125°C, unless DD SS DD SS LOGIC A otherwise noted. Table 3. Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution N 8 Bits Resistor Integral Nonlinearity2 R-INL R = 10 kΩ AB V ≥ 2.7 V −2 ±0.2 +2 LSB DD V < 2.7 V −5 ±1.5 +5 LSB DD R = 100 kΩ AB V ≥ 2.7 V −1 ±0.1 +1 LSB DD V < 2.7 V −2 ±0.5 +2 LSB DD Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.2 +0.5 LSB Nominal Resistor Tolerance ΔR /R −8 ±1 +8 % AB AB Resistance Temperature Coefficient3 (ΔR /R )/ΔT × 106 Code = full scale 35 ppm/°C AB AB Wiper Resistance3 R Code = zero scale W R = 10 kΩ 55 125 Ω AB R = 100 kΩ 130 400 Ω AB Bottom Scale or Top Scale R or R BS TS R = 10 kΩ 40 80 Ω AB R = 100 kΩ 60 230 Ω AB Nominal Resistance Match R /R Code = 0xFF −1 ±0.2 +1 % AB1 AB2 DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity4 INL R = 10 kΩ −1 ±0.2 +1 LSB AB R = 100 kΩ −0.5 ±0.1 +0.5 LSB AB Differential Nonlinearity4 DNL −0.5 ±0.2 +0.5 LSB Full-Scale Error V WFSE R = 10 kΩ −2.5 −0.1 LSB AB R = 100 kΩ −1 ±0.2 +1 LSB AB Zero-Scale Error V WZSE R = 10 kΩ 1.2 3 LSB AB R = 100 kΩ 0.5 1 LSB AB Voltage Divider Temperature (ΔV /V )/ΔT × 106 Code = half scale ±5 ppm/°C W W Coefficient3 Rev. C | Page 6 of 32

Data Sheet AD5122/AD5142 Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit RESISTOR TERMINALS Maximum Continuous Current I , I , and I A B W R = 10 kΩ −6 +6 mA AB R = 100 kΩ −1.5 +1.5 mA AB Terminal Voltage Range5 V V V SS DD Capacitance A, Capacitance B3 C , C f = 1 MHz, measured to GND, A B code = half scale R = 10 kΩ 25 pF AB R = 100 kΩ 12 pF AB Capacitance W3 C f = 1 MHz, measured to GND, W code = half scale R = 10 kΩ 12 pF AB R = 100 kΩ 5 pF AB Common-Mode Leakage Current3 V = V = V −500 ±15 +500 nA A W B DIGITAL INPUTS Input Logic3 High V V = 1.8 V to 2.3 V 0.8 × V V INH LOGIC LOGIC V = 2.3 V to 5.5 V 0.7 × V V LOGIC LOGIC Low V 0.2 × V V INL LOGIC Input Hysteresis3 V 0.1 × V V HYST LOGIC Input Current3 I ±1 µA IN Input Capacitance3 C 5 pF IN DIGITAL OUTPUTS Output High Voltage3 V R = 2.2 kΩ to V V V OH PULL-UP LOGIC LOGIC Output Low Voltage3 V I = 3 mA 0.4 V OL SINK I = 6 mA, V > 2.3 V 0.6 V SINK LOGIC Three-State Leakage Current −1 +1 µA Three-State Output Capacitance 2 pF POWER SUPPLIES Single-Supply Power Range V = GND 2.3 5.5 V SS Dual-Supply Power Range ±2.25 ±2.75 V Logic Supply Range Single supply, V = GND 1.8 V V SS DD Dual supply, V < GND 2.25 V V SS DD Positive Supply Current I V = V or V = GND DD IH LOGIC IL V = 5.5 V 0.7 5.5 µA DD V = 2.3 V 400 nA DD Negative Supply Current I V = V or V = GND −5.5 −0.7 µA SS IH LOGIC IL EEPROM Store Current3, 6 I V = V or V = GND 2 mA DD_EEPROM_STORE IH LOGIC IL EEPROM Read Current3, 7 I V = V or V = GND 320 µA DD_EEPROM_READ IH LOGIC IL Logic Supply Current I V = V or V = GND 0.05 1.4 µA LOGIC IH LOGIC IL Power Dissipation8 P V = V or V = GND 3.5 µW DISS IH LOGIC IL Power Supply Rejection Ratio PSRR ∆V /∆V = V ± 10%, −66 −60 dB DD SS DD code = full scale Rev. C | Page 7 of 32

AD5122/AD5142 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit DYNAMIC CHARACTERISTICS9 Bandwidth BW −3 dB R = 10 kΩ 3 MHz AB R = 100 kΩ 0.43 MHz AB Total Harmonic Distortion THD V /V = ±2.5 V, V = 1 V rms, DD SS A V = 0 V, f = 1 kHz B R = 10 kΩ −80 dB AB R = 100 kΩ −90 dB AB Resistor Noise Density e Code = half scale, T = 25°C, N_WB A f = 10 kHz R = 10 kΩ 7 nV/√Hz AB R = 100 kΩ 20 nV/√Hz AB V Settling Time t V = 5 V, V = 0 V, from W S A B zero scale to full scale, ±0.5 LSB error band R = 10 kΩ 2 µs AB R = 100 kΩ 12 µs AB Crosstalk (C /C ) C R = 10 kΩ 10 nV-sec W1 W2 T AB R = 100 kΩ 25 nV-sec AB Analog Crosstalk C −90 dB TA Endurance10 T = 25°C 1 Mcycles A 100 kcycles Data Retention11, 12 50 Years 1 Typical values represent average readings at 25°C, V = 5 V, V = 0 V, and V = 5 V. DD SS LOGIC 2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × V )/R . DD AB 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at V with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V = V and V = 0 V. DNL specification limits WB A DD B of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 P is calculated from (I × V ) + (I × V ). DISS DD DD LOGIC LOGIC 9 All dynamic characteristics use V /V = ±2.5 V, and V = 2.5 V. DD SS LOGIC 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years applies to an endurance of 1k cycles. An endurance of 100k cycles has an equivalent retention lifetime of 5 years. Rev. C | Page 8 of 32

Data Sheet AD5122/AD5142 INTERFACE TIMING SPECIFICATIONS V = 1.8 V to 5.5 V; all specifications T to T , unless otherwise noted. LOGIC MIN MAX Table 4. SPI Interface1 Parameter2 Test Conditions/Comments Min Typ Max Unit Description t V > 1.8 V 20 ns SCLK cycle time 1 LOGIC V = 1.8 V 30 ns LOGIC t V > 1.8 V 10 ns SCLK high time 2 LOGIC V = 1.8 V 15 ns LOGIC t V > 1.8 V 10 ns SCLK low time 3 LOGIC V = 1.8 V 15 ns LOGIC t 10 ns SYNC to SCLK falling edge setup time 4 t 5 ns Data setup time 5 t 5 ns Data hold time 6 t 10 ns SYNC rising edge to next SCLK fall ignored 7 t3 20 ns Minimum SYNC high time 8 t4 50 ns SCLK rising edge to SDO valid 9 t 500 ns SYNC rising edge to SDO pin disable 10 1 Refer to the AN-1248 for additional information about the serial peripheral interface. 2 All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. r f DD IL IH 3 Refer to t and t for memory commands operations (see Table 5). EEPROM_PROGRAM EEPROM_READBACK 4 R = 2.2 kΩ to V with a capacitance load of 168 pF. PULL_UP DD Table 5. Control Pins Parameter Min Typ Max Unit Description t 0.1 10 µs RESET low time 1 t 1 15 50 ms Memory program time (not shown in Figure 5) EEPROM_PROGRAM t 7 30 µs Memory readback time (not shown in Figure 5) EEPROM_READBACK t 2 75 µs Start-up time (not shown in Figure 5) POWER_UP t 30 µs Reset EEPROM restore time (not shown in Figure 5) RESET 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. 2 Maximum time after V − V is equal to 2.3 V. DD SS Rev. C | Page 9 of 32

AD5122/AD5142 Data Sheet SHIFT REGISTER AND TIMING DIAGRAMS DB15 (MSB) DB8 DB7 DB0 (LSB) C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CONTROL BITS ADDRESS BITS DATA BITS 10880-002 Figure 2. Input Shift Register Contents t4 t2 t1 t7 SCLK t8 t3 SYNC t5 t6 SDI C3 C2 C1 C0 D7 D6 D5 D2 D1 D0 t9 t10 *PSRDEOVIOUS COMMANDC 3R*ECEIVECD2.* C1* C0* D7* D6* D5* D2* D1* D0* 10880-003 Figure 3. SPI Serial Interface Timing Diagram, Clock Polarity (CPOL) = 0, Clock Phase (CPHA) = 1 t4 t2 t1 t7 SCLK t8 t3 SYNC t5 t6 SDI C3 C2 C1 C0 D7 D6 D5 D2 D1 D0 t9 t10 *PSRDEOVIOUS COMMANDC 3R*ECEIVECD2.* C1* C0* D7* D6* D5* D2* D1* D0* 10880-004 Figure 4. SPI Serial Interface Timing Diagram, Clock Polarity (CPOL) = 1, Clock Phase (CPHA) = 0 SCLK SYNC RESET t1 10880-005 Figure 5. Control Pins Timing Diagram Rev. C | Page 10 of 32

Data Sheet AD5122/AD5142 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 6. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7.0 V DD section of this specification is not implied. Operation beyond V to GND +0.3 V to −7.0 V SS the maximum operating conditions for extended periods may V to V 7 V DD SS affect product reliability. V to GND −0.3 V to V + 0.3 V or LOGIC DD +7.0 V (whichever is less) THERMAL RESISTANCE V , V , V to GND V − 0.3 V, V + 0.3 V or A W B SS DD θ is defined by the JEDEC JESD51 standard, and the value is +7.0 V (whichever is less) JA dependent on the test board and test environment. I , I , I A W B Pulsed1 Table 7. Thermal Resistance Frequency > 10 kHz Package Type θ θ Unit JA JC R = 10 kΩ ±6 mA/d2 AW 16-Lead LFCSP 89.51 3 °C/W RAW = 100 kΩ ±1.5 mA/d2 16-Lead TSSOP 150.41 27.6 °C/W Frequency ≤ 10 kHz R = 10 kΩ ±6 mA/√d2 1 JEDEC 2S2P test board, still air (0 m/sec airflow). AW R = 100 kΩ ±1.5 mA/√d2 AW ESD CAUTION Digital Inputs −0.3 V to V + 0.3 V or LOGIC +7 V (whichever is less) Operating Temperature Range, T 3 −40°C to +125°C A Maximum Junction Temperature, 150°C T Maximum J Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (T max − T )/θ J A JA FICDM 1.5 kV 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. Rev. C | Page 11 of 32

AD5122/AD5142 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 TESER INDEP CNYS SDO INDICATOR 61 51 41 31 GND1 12 SDI AD5122/ A12 AD5142 11 SCLK W13 TOP VIEW 10 VLOGIC B14 (Not to Scale) 9 VDD 5 6 7 8 S 2 2 2 S A W B V NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE POTENTIAL OF THE VSS PIN, OR, ALTERNATIVELY, LEAVE ITPTHL EAALNTE ETC HFTEOR RIPC AEADNL HLBAYE N UTCNHECEDOR TMNHNAEELRCLMYTE ACDLO. PNITEN RIESFC ORTREECMDO ATMNOCM AEE .CNODEPDPER 10880-006 Figure 6. 16-Lead LFCSP Pin Configuration Table 8. 16-Lead LFCSP Pin Function Descriptions Pin No. Mnemonic Description 1 GND Ground Pin, Logic Ground Reference. 2 A1 Terminal A of RDAC1. V ≤ V ≤ V . SS A DD 3 W1 Wiper Terminal of RDAC1. V ≤ V ≤ V . SS W DD 4 B1 Terminal B of RDAC1. V ≤ V ≤ V . SS B DD 5 V Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. SS 6 A2 Terminal A of RDAC2. V ≤ V ≤ V . SS A DD 7 W2 Wiper Terminal of RDAC2. V ≤ V ≤ V . SS W DD 8 B2 Terminal B of RDAC2. V ≤ V ≤ V . SS B DD 9 V Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. DD 10 V Logic Power Supply; 1.8 V to V . Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. LOGIC DD 11 SCLK Serial Clock Line. Data is clocked in at the logic low transition. 12 SDI Serial Data Input. 13 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. 14 SYNC Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register. 15 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated memory location. If INDEP is enabled, it cannot be disabled by software. 16 RESET Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to V . LOGIC EPAD Exposed Pad. Connect this exposed pad to the potential of the V pin, or, alternatively, leave it electrically SS unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Rev. C | Page 12 of 32

Data Sheet AD5122/AD5142 INDEP 1 16 SYNC RESET 2 15 SDO GND 3 14 SDI AD5122/ A1 4 AD5142 13 SCLK W1 5 TOP VIEW 12 VLOGIC (Not to Scale) B1 6 11 VDD VSS 7 10 B2 A2 8 9 W2 10880-007 Figure 7. 16-Lead TSSOP, SPI Interface Pin Configuration Table 9. 16-Lead TSSOP, SPI Interface Pin Function Descriptions Pin No. Mnemonic Description 1 INDEP Linear Gain Setting Mode at Power-Up. Each string resistor is loaded independently from the associated memory location. If INDEP is enabled, it cannot be disabled by software. 2 RESET Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to V . LOGIC 3 GND Ground Pin, Logic Ground Reference. 4 A1 Terminal A of RDAC1. V ≤ V ≤ V . SS A DD 5 W1 Wiper Terminal of RDAC1. V ≤ V ≤ V . SS W DD 6 B1 Terminal B of RDAC1. V ≤ V ≤ V . SS B DD 7 V Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. SS 8 A2 Terminal A of RDAC2. V ≤ V ≤ V . SS A DD 9 W2 Wiper Terminal of RDAC2. V ≤ V ≤ V . SS W DD 10 B2 Terminal B of RDAC2. V ≤ V ≤ V . SS B DD 11 V Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. DD 12 V Logic Power Supply; 1.8 V to V . Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. LOGIC DD 13 SCLK Serial Clock Line. Data is clocked in at the logic low transition. 14 SDI Serial Data Input. 15 SDO Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. 16 SYNC Synchronization Input, Active Low. When SYNC returns high, data is loaded into the input shift register. Rev. C | Page 13 of 32

AD5122/AD5142 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.2 10kΩ,+125°C 0.4 10kΩ, +25°C 10kΩ,–40°C 0.1 100kΩ, +125°C 0.3 100kΩ, +25°C 100kΩ, –40°C 0 0.2 B) 0.1 B)–0.1 NL (LS 0 NL (LS–0.2 R-I–0.1 R-D–0.3 –0.2 –0.4 –0.3 –0.5 –0.4 10kΩ,+125°C 100kΩ,+125°C 10kΩ,+25°C 100kΩ,+25°C 10kΩ,–40°C 100kΩ,–40°C –0.50 C10O0DE (Decimal) 200 10880-008 –0.60 1C0O0DE (Decimal) 200 10880-011 Figure 8. R-INL vs. Code (AD5142) Figure 11. R-DNL vs. Code (AD5142) 0.20 0.10 0.15 0.05 0.10 0 0.05 R-INL (LSB) –0.050 R-DNL (LSB) –––000...110505 –0.10 10kΩ,+125°C –0.20 –0.15 10kΩ,+25°C 10kΩ,–40°C –0.20 110000kkΩΩ,,++12255°C°C –0.25 1100kkΩΩ,,++12255°C°C 110000kkΩΩ,,++12255°C°C 100kΩ,–40°C 10kΩ,–40°C 100kΩ,–40°C –0.25 0 C5O0DE (Decimal) 100 10880-009 –0.300 C50ODE (Decimal) 100 10880-012 Figure 9. R-INL vs. Code (AD5122) Figure 12. R-DNL vs. Code (AD5122) 0.3 0.10 10kΩ,–40°C 10kΩ, +25°C 10kΩ, +125°C 0.05 0.2 100kΩ,–40°C 100kΩ, +25°C 100kΩ, +125°C 0 0.1 –0.05 INL (LSB) 0 DNL (LSB)–0.10 –0.15 –0.1 –0.20 –0.2 –0.25 10kΩ, –40°C 100kΩ, –40°C 10kΩ, +25°C 100kΩ, +25°C 10kΩ, +125°C 100kΩ, +125°C –0.30 C10O0DE (Decimal) 200 10880-010 –0.300 C10O0DE (Decimal) 200 10880-013 Figure 10. INL vs. Code (AD5142) Figure 13. DNL vs. Code (AD5142) Rev. C | Page 14 of 32

Data Sheet AD5122/AD5142 0.15 1000 10kΩ,–40°C VDD = VLOGIC VLOGIC = 2.3V 1100kkΩΩ,, ++21255°C°C 900 VSS = GND VLOGIC = 3.3V 0.10 100kΩ,–40°C VLOGIC = 5.5V 100kΩ, +25°C 800 100kΩ, +125°C 700 0.05 NL (LSB) 0 (nA)OGIC 560000 I IL 400 –0.05 300 200 –0.10 100 –0.150 C50ODE (Decimal) 100 10880-014 0–40 –20 0 T2E0MPERA40TURE (6°0C) 80 100 120 10880-160 Figure 14. INL vs. Code (AD5122) Figure 17. I vs. Temperature LOGIC 450 0.06 100kΩ 10kΩ, –40°C 100kΩ, –40°C 10kΩ 10kΩ, +25°C 100kΩ, +25°C RE 400 0.04 10kΩ, +125°C 100kΩ, +125°C U AT 350 0.02 R EMPEm/°C) 300 0 TIOMETER MODE TCOEFFICIENT (pp 112205050000 DNL (LSB)––––0000....00008642 TEN 50 –0.10 O P 0 –0.12 –50 00 2550 C15O000DE (Decim175a50l) 120000 122575 AADD55112422 10880-015 –0.140 C50ODE (Decimal) 100 10880-017 Figure 15. Potentiometer Mode Temperature Coefficient ((ΔV /V )/ΔT × 106) Figure 18. DNL vs. Code (AD5122) W W vs. Code 800 VDD = VLOGIC 450 1100k0ΩkΩ VSS = GND 400 700 E UR 350 (nA)DD 456000000 ODETEMPERATm/°C)CIENT(pp223050000 I MFI150 300 TF AE STCO100 200 EO H 50 100 VDD = 2.3V R VDD = 3.3V 0 VDD = 5.5V 0–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 10880-120 –5000 2550 C15O000DE (Decim175a50l) 120000 122575 AADD55112422 10880-018 Figure 16. IDD vs. Temperature Figure 19. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs. Code Rev. C | Page 15 of 32

AD5122/AD5142 Data Sheet 1.2 20 VLOGIC =1.8V VDD/VSS = ±2.5V VVLLOOGGIICC ==23..33VV RAB = 10kΩ 1.0 VLOGIC =5V 0 VLOGIC =5.5V A) CURRENT(µ 00..68 SE (Degrees) ––4200 C A OGI 0.4 PH –60 L I 0.2 –80 QUARTER SCALE MIDSCALE FULL-SCALE 00 1 I2NPUTVOLT3AGE(V) 4 5 10880-019 –10010 100 1kFREQU1E0NkCY(Hz)100k 1M 10M 10880-022 Figure 20. I Current vs. Digital Input Voltage Figure 23. Normalized Phase Flatness vs. Frequency, R = 10 kΩ LOGIC AB 0 10 0x80 (0x40) 0 0x80 (0x40) –10 0x40 (0x20) –10 0x40 (0x20) 0x20 (0x10) 0x20 (0x10) –20 0x10 (0x08) –20 0x10 (0x08) 0x8 (0x04) dB) 0x8 (0x04) dB) –30 0x4 (0x02) N ( –30 N ( –40 0x2 (0x01) AI 0x4 (0x02) AI 0x1 (0x00) G G 0x2 (0x01) –50 0x00 –40 0x1 (0x00) –60 0x00 –70 –50 –80 AD5142 (AD5122) AD5142 (AD5122) –6010 100 1k FREQ1U0EkNCY(H1z0)0k 1M 10M 10880-020 –9010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 10880-023 Figure 21. 10 kΩ Gain vs. Frequency vs. Code Figure 24. 100 kΩ Gain vs. Frequency vs. Code –40 0 VVDAD =/ V1SVS r=m ±s2.5V 1100k0kΩΩ –10 1100k0kΩΩ –50 VB = GND CODE = HALF SCALE NOISE FILTER = 22kHz –20 –60 –30 B) B) HD + N (d –70 HD + N (d ––5400 T T –80 –60 –70 –90 VDD/VSS= ±2.5V –80 fIN = 1kHz CODE = HALF SCALE NOISE FILTER = 22kHz –10020 200 FREQUE2NkCY (Hz) 20k 200k 10880-021 –900.001 0.01VOLTAGE (V rm0s.)1 1 10880-024 Figure 22. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency Figure 25. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude Rev. C | Page 16 of 32

Data Sheet AD5122/AD5142 10 0.8 0x80 TO 0x7F 100kΩ 0x80 TO 0x7F 10kΩ 0 0.7 –10 0.6 SE (Degrees) –––432000 VE VOLTAGE (V) 000...345 HA –50 ATI P L 0.2 –60 RE 0.1 –70 –80 QMUIDASRCTAELRE SCALE VDD/VSS = ±2.5V 0 FULL-SCALE RAB = 100kΩ –9010 100 FR1kEQUENCY 1(H0kz) 100k 1M 10880-025 –0.10 5 TIME (µs) 10 15 10880-028 Figure 26. Normalized Phase Flatness vs. Frequency, R = 100 kΩ Figure 29. Maximum Transition Glitch AB 600 0.0025 1.2 100kΩ, VDD = 2.3V 100kΩ, VDD = 2.7V PER ON RESISTANCE (Ω) 234500000000 111111111100000000000000kkkkkkkkkkΩΩΩΩΩΩΩΩΩΩ,,,,,, ,,,,VVVVVV VVVVDDDDDDDDDDDDDDDDDDDD ====== ==== 223355 ..V.V.33553765V.V.VVVV65VV PROBABILITYDENSITY 000...000000112050 0001....4680 UMULATIVEPROBABILITY WI 0.0005 C 0.2 100 00 1 2 VOLTAGE3 (V) 4 5 10880-026 0–600 –500 –400 –300 –R2E00SIS–1T0O0RD0RIF1T00(pp2m00) 300 400 500 6000 10880-029 Figure 27. Incremental Wiper On Resistance vs. Positive Power Supply (V ) Figure 30. Resistor Lifetime Drift DD 10 0 10kΩ + 0pF 10kΩ, RDAC1 VDD=5V±10%AC 9 1100kkΩΩ ++ 7155p0pFF –10 100kΩ, RDAC1 VCSOSD=E G=NMDI,DVSACA=L4EV,VB= GND 10kΩ + 250pF 8 100kΩ + 0pF –20 100kΩ + 75pF Hz)7 110000kkΩΩ ++ 125500ppFF –30 WIDTH (M56 SRR(dB) ––5400 ND4 P BA –60 3 –70 2 –80 1 000 2100 4200 CODE6300 (Decima84l)00 15000 16200 AADD55114222 10880-027 –9010 100 1kFREQU1E0NkCY(Hz)100k 1M 10M 10880-030 Figure 28. Maximum Bandwidth vs. Code vs. Net Capacitance Figure 31. Power Supply Rejection Ratio (PSRR) vs. Frequency Rev. C | Page 17 of 32

AD5122/AD5142 Data Sheet 0.020 7 10kΩ 100kΩ 0.015 6 ATIVE VOLTAGE (V)–000...0000015500 ORETICAL I (mA)MAX345 REL–0.010 THE2 –0.015 1 –0.0200 500 TIM10E0 (0ns) 1500 2000 10880-031 000 5205 15C00O0DE (Deci1m755a0l) 210000 215205 AADD55112422 10880-033 Figure 32. Digital Feedthrough Figure 34. Theoretical Maximum Current vs. Code 0 10kΩ SHUTDOWN MODE ENABLED 100kΩ –20 –40 B) d N ( –60 AI G –80 –100 –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 10880-032 Figure 33. Shutdown Isolation vs. Frequency Rev. C | Page 18 of 32

Data Sheet AD5122/AD5142 TEST CIRCUITS Figure 35 to Figure 39 define the test conditions used in the Specifications section. NC DUT A IW VA W V+ = VDD ±10% (∆VMS) B V+ ~ VDD A W PSRR (dB) = 20 LOG ∆VDD NC = NO CONNECVTMS 10880-034 B VMS PSS (%/%) =∆∆VVDMDS%% 10880-037 Figure 35. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 38. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS, PSRR) 0.1V DUT RSW= ISW CODE = 0x00 W + DUT A V1L+S =B V =D DV+/2N B ISW –0.1V W V+ B VMS 10880-035 A = NC VSSTO VDD 10880-038 Figure 36. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 39. Incremental On Resistance NC DUT IW= VDD/RNOMINAL A W VW B VMS1 RW = VMS1/IW NC = NO CONNECT 10880-036 Figure 37. Wiper Resistance Rev. C | Page 19 of 32

AD5122/AD5142 Data Sheet THEORY OF OPERATION The AD5122/AD5142 digital programmable potentiometers are SPI SERIAL DATA INTERFACE designed to operate as true variable resistors for analog signals The AD5122/AD5142 contain a 4-wire, SPI-compatible digital within the terminal voltage range of V < V < V . The resistor SS TERM DD interface (SDI, SYNC, SDO, and SCLK). The write sequence wiper position is determined by the RDAC register contents. The begins by bringing the SYNC line low. The SYNC pin must be RDAC register acts as a scratchpad register that allows unlimited held low until the complete data-word is loaded from the SDI changes of resistance settings. A secondary register (the input pin. Data is loaded in at the SCLK falling edge transition, as register) can preload the RDAC register data. shown in Figure 3 and Figure 4. When SYNC returns high, the The RDAC register can be programmed with any position setting serial data-word is decoded according to the instructions in using the SPI interface (depending on the model). When a Table 16. desirable wiper position is found, this value can be stored in the To minimize power consumption in the digital input buffers EEPROM memory. Thereafter, the wiper position is always when the device is enabled, operate all serial interface pins close restored to that position for subsequent power-ups. The storing to the V supply rails. of EEPROM data takes approximately 15 ms; during this time, LOGIC the device is locked and does not acknowledge any new command, SYNC Interruption preventing any changes from taking place. In a standalone write sequence for the AD5122/AD5142, RDAC REGISTER AND EEPROM the SYNC line is kept low for 16 falling edges of SCLK, and the instruction is decoded when SYNC is pulled high. However, if The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is the SYNC line is kept low for less than 16 falling edges of SCLK, loaded with 0x80 (AD5142, 256 taps), the wiper is connected to the input shift register content is ignored, and the write sequence is half scale of the variable resistor. The RDAC register is a standard considered invalid. logic register; there is no restriction on the number of changes SDO Pin allowed. The serial data output pin (SDO) serves two purposes: to read It is possible to both write to and read from the RDAC register back the contents of the control, EEPROM, RDAC, and input using the digital interface (see Table 10). registers using Command 3 (see Table 10 and Table 16), and to The contents of the RDAC register can be stored to the EEPROM connect the AD5122/AD5142 to daisy-chain mode. using Command 9 (see Table 16). Thereafter, the RDAC register The SDO pin contains an internal open-drain output that needs an always sets at that position for any future on-off-on power external pull-up resistor. The SDO pin is enabled when SYNC is supply sequence. It is possible to read back data saved into the pulled low, and the data is clocked out of SDO on the rising EEPROM with Command 3 (see Table 10). edge of SCLK, as shown in Figure 3 and Figure 4. Alternatively, the EEPROM can be written to independently using Command 11 (see Table 16). INPUT SHIFT REGISTER For the AD5122/AD5142, the input shift register is 16 bits wide, as shown in Figure 2. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. If the AD5122 RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command as listed in Table 10 and Table 16. Rev. C | Page 20 of 32

Data Sheet AD5122/AD5142 Daisy-Chain Connection To prevent data from mislocking (for example, due to noise) the device includes an internal counter, if the clock falling edges Daisy chaining minimizes the number of port pins required from count is not a multiple of 8, the device ignores the command. A the controlling IC. As shown in Figure 40, the SDO pin of one valid clock count is 16, 24, or 32. The counter resets package must be tied to the SDI pin of the next package. The clock period can be increased because of the propagation delay of the when SYNC returns high. line between subsequent devices. When two AD5122/AD5142 devices are daisy chained, 32 bits of data are required. The first 16 bits assigned to U2, and the second 16 bits assigned to U1, as shown in Figure 41. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. A typical connection is shown in Figure 40. VLOGIC VLOGIC AD5122/ RP AD5122/ RP AD5142 2.2kΩ AD5142 2.2kΩ MOSI SDI U1 SDO SDI U2 SDO MICROCONTROLLER MISO SCLK SS SYNC SCLK SYNC SCLK N AI H C DAISY- 10880-039 Figure 40. Daisy-Chain Configuration SCLK 1 2 16 17 18 32 SYNC MOSI DB15 DB0 DB15 DB0 INPUT WORD FOR U2 INPUT WORD FOR U1 SDO_U1 DB15 DB0 DB15 DB0 UNDEFINED INPUT WORD FOR U2 10880-040 Figure 41. Daisy-Chain Diagram Rev. C | Page 21 of 32

AD5122/AD5142 Data Sheet Table 10. Reduced Commands Operation Truth Table Control Address Command Bits[DB15:DB12] Bits[DB11:DB8]1 Data Bits[DB7:DB0]1 Number C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing. 1 0 0 0 1 0 0 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data to RDAC 2 0 0 1 0 0 0 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data to input register 3 0 0 1 1 X 0 A1 A0 X X X X X X D1 D0 Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC 9 0 1 1 1 0 0 0 A0 X X X X X X X 1 Copy RDAC register to EEPROM 10 0 1 1 1 0 0 0 A0 X X X X X X X 0 Copy EEPROM into RDAC 14 1 0 1 1 X X X X X X X X X X X X Software reset 15 1 1 0 0 A3 0 0 A0 X X X X X X X D0 Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode 1X means don’t care. Table 11. Reduced Address Bits Table A3 A2 A1 A0 Channel Stored Channel Memory 1 X1 X1 X1 All channels Not applicable 0 0 0 0 RDAC1 RDAC1 0 0 0 1 RDAC2 Not applicable 0 0 1 0 Not applicable RDAC2 1X means don’t care. Rev. C | Page 22 of 32

Data Sheet AD5122/AD5142 ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5122/AD5142 digital potentiometers include a set of user The AD5122/AD5142 include two commands to reduce the wiper programming features to address the wide number of applications resistance between the terminals when the devices achieve full scale for these universal adjustment devices (see Table 16 and Table 18). or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W Key programming features include the following: at top scale is specified as R . Similarly, the bottom scale resistance TS • Input register between Terminal B and Terminal W is specified as R . BS • Linear gain setting mode The contents of the RDAC registers are unchanged by entering • Low wiper resistance feature in these positions. There are three ways to exit from top scale • Lineal increment and decrement instructions and bottom scale: by using Command 12 or Command 13 (see • ±6 dB increment and decrement instructions Table 16); by loading new data in an RDAC register, which • Reset includes increment/decrement operations; or by entering • Shutdown mode shutdown mode, Command 15 (see Table 16). Input Register Table 12 and Table 13 show the truth tables for the top scale position and the bottom scale position, respectively, when the The AD5122/AD5142 include one input register per RDAC potentiometer or linear gain setting mode is enabled. register. These registers allow preloading of the value for the associated RDAC register. These registers can be written to using Table 12. Top Scale Truth Table Command 2 and read back from using Command 3 (see Table 16). Linear Gain Setting Mode Potentiometer Mode This feature allows a synchronous update of one or all the R R R R AW WB AW WB RDAC registers at the same time. R R R R AB AB TS AB The transfer from the input register to the RDAC register is done synchronously by Command 8 (see Table 16). Table 13. Bottom Scale Truth Table If new data is loaded into an RDAC register, this RDAC register Linear Gain Setting Mode Potentiometer Mode automatically overwrites the associated input register. R R R R AW WB AW WB Linear Gain Setting Mode RTS RBS RAB RBS The proprietary architecture of the AD5122/AD5142 allows the Linear Increment and Decrement Instructions independent control of each string resistor, R and R . To AW WB The increment and decrement commands (Command 4 and enable this feature, use Command 16 (see Table 16) to set Bit D2 Command 5 in Table 16) are useful for linear step adjustment of the control register (see Table 18). applications. These commands simplify microcontroller software This mode of operation can control the potentiometer as two coding by allowing the controller to send an increment or independent rheostats connected at a single point, W terminal, decrement command to the device. The adjustment can be as opposed to potentiometer mode where each resistor is individual or in a ganged potentiometer arrangement, where complementary, R = R − R . AW AB WB all wiper positions are changed at the same time. This feature enables a second input and an RDAC register per For an increment command, executing Command 4 automatically channel, as shown in Table 17; however, the actual RDAC contents moves the wiper to the next RDAC position. This command remain unchanged. The same operations are valid for can be executed in a single channel or multiple channels. potentiometer mode and linear gain setting mode. If the INDEP pin is pulled high, the device powers up in linear gain setting mode and loads the values stored in the associated memory locations for each channel (see Table 17). The INDEP pin and D2 bit are connected internally to a logic or gate, if any or both are 1, the devices cannot operate in potentiometer mode. Rev. C | Page 23 of 32

AD5122/AD5142 Data Sheet ±6 dB Increment and Decrement Instructions Shutdown Mode Two programming instructions produce logarithmic taper The AD5122/AD5142 can be placed in shutdown mode by increment or decrement of the wiper position control by executing the software shutdown command, Command 15 (see an individual potentiometer or by a ganged potentiometer Table 16); and by setting the LSB (D0) to 1. This feature places arrangement where all RDAC register positions are changed the RDAC in a special state. The contents of the RDAC register are simultaneously. The +6 dB increment is activated by Command 6, unchanged by entering shutdown mode. However, all commands and the −6 dB decrement is activated by Command 7 (see Table 16). listed in Table 16 are supported while in shutdown mode. Execute For example, starting with the zero-scale position and executing Command 15 (see Table 16) and set the LSB (D0) to 0 to exit Command 6 ten times moves the wiper in 6 dB steps to the full- shutdown mode. scale position. When the wiper position is near the maximum setting, Table 15. Truth Table for Shutdown Mode the last 6 dB increment instruction causes the wiper to go to the Linear Gain Setting Mode Potentiometer Mode full-scale position (see Table 14). A2 AW WB AW WB Incrementing the wiper position by +6 dB essentially doubles the 0 N/A1 Open Open R RDAC register value, whereas decrementing the wiper position by BS 1 Open N/A1 N/A1 N/A1 −6 dB halves the register value. Internally, the AD5122/AD5142 use shift registers to shift the bits left and right to achieve a ±6 dB 1 N/A means not applicable. increment or decrement. These functions are useful for various EEPROM OR RDAC REGISTER PROTECTION audio/video level adjustments, especially for white LED brightness The EEPROM and RDAC registers can be protected by disabling settings in which human visual responses are more sensitive to any update to these registers. This can be done by using software. If large adjustments than to small adjustments. these registers are protected by software, set Bit D0 and/or Bit D1 Table 14. Detailed Left Shift and Right Shift Functions for (see Table 18), which protects the EEPROM and RDAC registers the ±6 dB Step Increment and Decrement independently. Left Shift (+6 dB/Step) Right Shift (−6 dB/Step) When RDAC is protected, the only operation allowed is to copy 0000 0000 1111 1111 the EEPROM into the RDAC register. 0000 0001 0111 1111 INDEP PIN 0000 0010 0011 1111 0000 0100 0001 1111 If the INDEP pin is pulled high at power-up, the device operates 0000 1000 0000 1111 in linear gain setting mode, loading each string resistor, RAWx and 0001 0000 0000 0111 RWBx, with the value stored into the EEPROM (see Table 17). If 0010 0000 0000 0011 the pin is pulled low, the device powers up in potentiometer mode. 0100 0000 0000 0001 The INDEP pin and the D2 bit are connected internally to a logic 1000 0000 0000 0000 OR gate, if any or both are 1, the device cannot operate in 1111 1111 0000 0000 potentiometer mode (see Table 18). Reset The AD5122/AD5142 can be reset through software by executing Command 14 (see Table 16) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC registers with the contents of the EEPROM and takes approximately 30 µs. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to V if LOGIC the RESET pin is not used. Rev. C | Page 24 of 32

Data Sheet AD5122/AD5142 Table 16. Advance Command Operation Truth Table Control Address Command Bits[DB15:DB12] Bits[DB11:DB8]1 Data Bits[DB7:DB0]1 Number C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation 0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing 1 0 0 0 1 0 A2 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data to RDAC 2 0 0 1 0 0 A2 0 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data to input register 3 0 0 1 1 0 A2 A1 A0 X X X X X X D1 D0 Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC 4 0 1 0 0 A3 A2 0 A0 X X X X X X X 1 Linear RDAC increment 5 0 1 0 0 A3 A2 0 A0 X X X X X X X 0 Linear RDAC decrement 6 0 1 0 1 A3 A2 0 A0 X X X X X X X 1 +6 dB RDAC increment 7 0 1 0 1 A3 A2 0 A0 X X X X X X X 0 −6 dB RDAC decrement 8 0 1 1 0 A3 A2 0 A0 X X X X X X X X Copy input register to RDAC (software LRDAC) 9 0 1 1 1 0 A2 0 A0 X X X X X X X 1 Copy RDAC register to EEPROM 10 0 1 1 1 0 A2 0 A0 X X X X X X X 0 Copy EEPROM into RDAC 11 1 0 0 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register data to EEPROM 12 1 0 0 1 A3 A2 0 A0 1 0 0 0 0 0 0 D0 Top scale D0 = 0; normal mode D0 = 1; shutdown mode 13 1 0 0 1 A3 A2 0 A0 0 0 0 0 0 0 0 D0 Bottom scale D0 = 1; enter D0 = 0; exit 14 1 0 1 1 X X X X X X X X X X X X Software reset 15 1 1 0 0 A3 A2 0 A0 0 0 0 0 0 0 0 D0 Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode 16 1 1 0 1 X X X X X X X X X D2 D1 D0 Copy serial register data to control register 1 X means don’t care. Rev. C | Page 25 of 32

AD5122/AD5142 Data Sheet Table 17. Address Bits Potentiometer Mode Linear Gain Setting Mode Stored Channel A3 A2 A1 A0 Input Register RDAC Register Input Register RDAC Register Memory 1 X1 X1 X1 All channels All channels All channels All channels Not applicable 0 0 0 0 RDAC1 RDAC1 R R RDAC1/R WB1 WB1 WB1 0 1 0 0 Not applicable Not applicable R R Not applicable AW1 AW1 0 0 0 1 RDAC2 RDAC2 R R R WB2 WB2 AW1 0 1 0 1 Not applicable Not applicable R R Not applicable AW2 AW2 0 0 1 0 Not applicable Not applicable Not applicable Not applicable RDAC2/R WB2 0 0 1 1 Not applicable Not applicable Not applicable Not applicable R AW2 1 X means don’t care. Table 18. Control Register Bit Descriptions Bit Name Description D0 RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) D1 EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) D2 Lineal setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode Rev. C | Page 26 of 32

Data Sheet AD5122/AD5142 RDAC ARCHITECTURE The nominal resistance between Terminal A and Terminal B, R , AB is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the To achieve optimum performance, Analog Devices, Inc., uses a wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded proprietary RDAC segmentation architecture for all the digital to select one of the 128/256 possible wiper settings. The general potentiometers. In particular, the AD5122/AD5142 employ a equations for determining the digitally programmed output three stage segmentation approach, as shown in Figure 42. The resistance between Terminal W and Terminal B are AD5122/AD5142 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from AD5122: V and V . DD SS D R (D) R R From 0x00 to 0x7F (1) A WB 128 AB W STS AD5142: RH D R (D) R R From 0x00 to 0xFF (2) WB 256 AB W RH RM where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RM RDAC register. RL RAB is the end-to-end resistance. R is the wiper resistance. W W RL In potentiometer mode, similar to the mechanical potentiometer, 7-BIT/8-BIT the resistance between Terminal W and Terminal A also produces DAEDCDORDESESR RM a digitally controlled complementary resistance, R . R also WA WA RH gives a maximum of 8% absolute resistance error. R starts at the WA RM maximum resistance value and decreases as the data loaded into RH SBS the latch increases. The general equations for this operation are AD5122: B 128D R (D) R R From 0x00 to 0x7F (3) 10880-041 AD514A2W: 128 AB W Figure 42. AD5122/AD5142 Simplified RDAC Circuit 256D Top Scale/Bottom Scale Architecture R (D) R R From 0x00 to 0xFF (4) AW AB W 256 In addition, the AD5122/AD5142 include new positions to where: reduce the resistance between terminals. These positions are D is the decimal equivalent of the binary code in the 7-bit/8-bit called bottom scale and top scale. At bottom scale, the typical RDAC register. wiper resistance decreases from 130 Ω to 60 Ω (R = 100 kΩ). AB R is the end-to-end resistance. At top scale, the resistance between Terminal A and Terminal W is AB R is the wiper resistance. decreased by 1 LSB, and the total resistance is reduced to 60 Ω W (R = 100 kΩ). If the device is configured in linear gain setting mode, the AB resistance between Terminal W and Terminal A is directly PROGRAMMING THE VARIABLE RESISTOR proportional to the code loaded in the associate RDAC register. Rheostat Operation—±8% Resistor Tolerance The general equations for this operation are The AD5122/AD5142 operate in rheostat mode when only two AD5122: terminals are used as a variable resistor. The unused terminal can D be floating, or it can be tied to Terminal W, as shown in Figure 43. R (D) R R From 0x00 to 0x7F (5) AW 128 AB W A A A AD5142: W W W D R (D) R R From 0x00 to 0xFF (6) B B B 10880-042 where: AW 256 AB W Figure 43. Rheostat Mode Configuration D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. R is the wiper resistance. W Rev. C | Page 27 of 32

AD5122/AD5142 Data Sheet In the bottom scale condition or top scale condition, a finite VDD total wiper resistance of 40 Ω is present. Regardless of which setting the device is operating in, limit the current between A Terminal A to Terminal B, Terminal W to Terminal A, and W Terminal W to Terminal B, to the maximum continuous current of ±6 mA or to the pulse current specified in Table 6. Otherwise, B degradation or possible destruction of the internal switch contact can occur. VSS 10880-044 PROGRAMMING THE POTENTIOMETER DIVIDER Figure 45. Maximum Terminal Voltages Set by VDD and VSS Voltage Output Operation POWER-UP SEQUENCE The digital potentiometer easily generates a voltage divider at Because there are diodes to limit the voltage compliance at wiper to B and wiper to A that is proportional to the input voltage Terminal A, Terminal B, and Terminal W (see Figure 45), it is at A to B, as shown in Figure 44. important to power up V first before applying any voltage to DD VA Terminal A, Terminal B, and Terminal W. Otherwise, the diode A is forward-biased such that V is powered unintentionally. The W DD VOUT ideal power-up sequence is V , V , V , digital inputs, and VB B 10880-043 VA, VB, and VW. The order of SpSowDeDringL OVGAIC, VB, VW, and digital inputs is not important as long as they are powered after V , Figure 44. Potentiometer Mode Configuration SS V , and V . Regardless of the power-up sequence and the DD LOGIC Connecting Terminal A to 5 V and Terminal B to ground ramp rates of the power supplies, once V is powered, the LOGIC produces an output voltage at the Wiper W to Terminal B power-on preset activates, which restores EEPROM values to ranging from 0 V to 5 V. The general equation defining the the RDAC registers. output voltage at V with respect to ground for any valid W LAYOUT AND POWER SUPPLY BIASING input voltage applied to Terminal A and Terminal B is It is always a good practice to use a compact, minimum lead R (D) R (D) VW(D) WRB VA ARW VB (7) length layout design. Ensure that the leads to the input are as AB AB direct as possible with a minimum conductor length. Ground where: paths must have low resistance and low inductance. It is also R (D) can be obtained from Equation 1 and Equation 2. good practice to bypass the power supplies with quality capacitors. WB R (D) can be obtained from Equation 3 and Equation 4. Apply low equivalent series resistance (ESR) 1 μF to 10 μF AW tantalum or electrolytic capacitors at the supplies to minimize Operation of the digital potentiometer in the divider mode any transient disturbance and to filter low frequency ripple. results in a more accurate operation over temperature. Unlike Figure 46 illustrates the basic supply bypassing configuration the rheostat mode, the output voltage is dependent mainly on for the AD5122/AD5142. the ratio of the internal resistors, R and R , and not the AW WB absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. VDD + C3 C1 VDD VLOGIC C5 C6 + VLOGIC 10µF 0.1µF 0.1µF 10µF AD5122/ TERMINAL VOLTAGE OPERATING RANGE AD5142 + C4 C2 10µF 0.1µF The AD5122/AD5142 are designed with internal ESD diodes VSS VSS for protection. These diodes also set the voltage boundary of the GND terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are 10880-045 clamped by the forward-biased diode. There is no polarity Figure 46. Power Supply Bypassing constraint between V , V , and V , but they cannot be higher A W B than V or lower than V . DD SS Rev. C | Page 28 of 32

Data Sheet AD5122/AD5142 OUTLINE DIMENSIONS DETAIL A 3.10 0.30 (JEDEC 95) 3.00 SQ 0.23 PIN 1 2.90 0.18 INDICATOR 0.50 13 16 PI(NSIENDE I 1DCAETTAOILR A A)REA OPTIONS BSC 12 1 1.75 EXPPAODSED 1.60 SQ 1.45 9 4 0.50 8 5 0.20 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 0.80 FOR PROPER CONNECTION OF 0.75 TOP VIEW THE EXPOSED PAD, REFER TO 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.20 REF PKG-005138 COMPLIANTTOJEDEC STANDARDS MO-220-WEED-6. 02-23-2017-E Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. C | Page 29 of 32

AD5122/AD5142 Data Sheet ORDERING GUIDE Package Model1, 2,3 R (kΩ) Resolution Interface Temperature Range Package Description Option Branding AB AD5122BCPZ10-RL7 10 128 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH8 AD5122BCPZ100-RL7 100 128 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH9 AD5122WBCPZ10-RL7 10 128 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DMY AD5122BRUZ10 10 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122BRUZ100 100 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122BRUZ10-RL7 10 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122WBRUZ10-RL7 10 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5122BRUZ100-RL7 100 128 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BCPZ10-RL7 10 256 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH5 AD5142BCPZ100-RL7 100 256 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH6 AD5142WBCPZ10-RL7 10 256 SPI −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DN0 AD5142BRUZ10 10 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BRUZ100 100 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BRUZ10-RL7 10 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142WBRUZ10-RL7 10 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 AD5142BRUZ100-RL7 100 256 SPI −40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD5142DBZ Evaluation Board 1 Z = RoHS Compliant Part. 2 The evaluation board is shipped with the 10 kΩ R resistor option; however, the board is compatible with all of the available resistor value options. AB 3 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD5122W and AD5142W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. C | Page 30 of 32

Data Sheet AD5122/AD5142 NOTES Rev. C | Page 31 of 32

AD5122/AD5142 Data Sheet NOTES ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10880-0-5/17(C) Rev. C | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD5122BRUZ100 AD5142BRUZ100 AD5122BCPZ100-RL7 AD5142BCPZ100-RL7 AD5142BRUZ10 AD5122BRUZ10 AD5142BCPZ10-RL7 AD5122BCPZ10-RL7 AD5142BRUZ100-RL7 AD5142BRUZ10-RL7 AD5122WBRUZ10-RL7 AD5142WBCPZ10-RL7 AD5142WBRUZ10-RL7 AD5122WBCPZ10-RL7