Fully Accurate, 16-Bit, Unbuffered V , Quad SPI OUT Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP AD5066 FEATURES Total unadjusted error for the part is <0.8 mV. Zero code error for the part is 0.05 mV typically. Low power quad 16-bit nanoDAC, ±1 LSB INL Low total unadjusted error of ±0.1 mV typically The AD5066 contains a power-down feature that reduces the Low zero code error of 0.05 mV typically current consumption of the device to typically 400 nA at 5 V Individually buffered reference pins and provides software selectable output loads while in power- 2.7 V to 5.5 V power supply down mode. Specified over full code range of 0 to 65535 The outputs of all DACs can be updated simultaneously using Power-on reset to zero scale or midscale the hardware LDAC function, with the added functionality of Per channel power-down with 3 power-down functions user software selectable DAC channels to update simultaneously. Hardware LDAC with software LDAC override function There is also an asynchronous CLR that clears all DACs to a CLR function to programmable code software-selectable code—0 V, midscale, or full scale. Small 16-lead TSSOP PRODUCT HIGHLIGHTS APPLICATIONS 1. Quad channel available in 16-lead TSSOP, ±1 LSB INL. Process control 2. Individually buffered voltage reference pins. Data acquisition systems 3. TUE = ±0.8 mV max and zero code error = 0.1 mV max. Portable battery-powered instruments 4. High speed serial interface with clock speeds up to 50 MHz. Digital gain and offset adjustment 5. Three power-down modes available to the user. Programmable voltage and current sources 6. Reset to known output voltage (zero scale or midscale). GENERAL DESCRIPTION Table 1. Related Devices The AD5066 is a low power, 16-bit quad-channel, unbuffered Part No. Description voltage output nanoDAC® offering relative accuracy specifica- AD5666 Quad,16-bit buffered DAC,16 LSB INL, TSSOP tions of ±1 LSB INL with individual reference pins and can AD5025/AD5045/AD50651 Dual,12-/14-/16-bit buffered nanoDAC, operate from a single 2.7 V to 5.5 V supply. The AD5066 also TSSOP offers a differential accuracy specification of ±1 LSB DNL. AD5024/AD5044/AD50641 Quad 16-bit nanoDAC, TSSOP Reference buffers are also provided on-chip. The part uses a AD50621 Single, 16-bit nanoDAC, SOT-23 versatile 3-wire, low power Schmitt trigger serial interface that AD50631 Single, 16-bit nanoDAC, MSOP operates at clock rates up to 50 MHz and is compatible with AD5061 Single,16-bit nanoDAC, ±4 LSB INL, SOT-23 standard SPI®, QSPI™, MICROWIRE™, and most DSP interface AD5040/AD50601 14-/16-bit nanoDAC, SOT-23 standards. The AD5066 incorporates a power-on reset circuit 1 ±1 LSB INL that ensures the DAC output powers up to zero scale or midscale and remains there until a valid write to the device takes place. FUNCTIONAL BLOCK DIAGRAM VDD VREFAVREFB AD5066 LDAC REINGPISUTTER REGDIASCTER DAC A VOUTA SCLK REINGPISUTTER REGDIASCTER DAC B VOUTB SYNC INTLEORGFIACCE REINGPISUTTER REGDIASCTER DAC C VOUTC REINGPISUTTER REGDIASCTER DAC D VOUTD DIN POWER-ON RESET POWER-DOWN LOGIC LDAC CLR POR VREFCVREFD GND 06845-001 Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.

AD5066 TABLE OF CONTENTS Features .............................................................................................. 1 DAC Architecture....................................................................... 15 Applications ....................................................................................... 1 Reference Buffer ......................................................................... 15 General Description ......................................................................... 1 Serial Interface ............................................................................ 15 Product Highlights ........................................................................... 1 Input Shift Register .................................................................... 15 Functional Block Diagram .............................................................. 1 Power-On Reset .......................................................................... 17 Revision History ............................................................................... 2 Clear Code Register ................................................................... 18 Specifications ..................................................................................... 3 LDAC Function ........................................................................... 18 AC Characteristics ........................................................................ 4 Power Supply Bypassing and Grounding ................................ 19 Timing Characteristics ................................................................ 5 Microprocessor Interfacing ....................................................... 19 Absolute Maximum Ratings ............................................................ 6 Applications Information .............................................................. 21 ESD Caution .................................................................................. 6 Using a Reference as a Power Supply ....................................... 21 Pin Configuration and Function Descriptions ............................. 7 Bipolar Operation....................................................................... 21 Typical Performance Characteristics ............................................. 8 Using the AD5066 with a Galvanically Isolated Interface .... 21 Terminology .................................................................................... 14 Outline Dimensions ....................................................................... 22 Theory of Operation ...................................................................... 15 Ordering Guide .......................................................................... 22 Digital-to-Analog Converter .................................................... 15 REVISION HISTORY 8/10—Rev. 0 to Rev. A Change to Minimum SYNC High Time, Single Channel Update Parameter, Table 4 ............................................... 5 7/09—Revision 0: Initial Version Rev. A | Page 2 of 24

AD5066 SPECIFICATIONS V = 2.7 V to 5.5 V, 2.0 V ≤ V A, V B, V C, V D ≤ V − 0.4 V, all specifications T to T , unless otherwise noted. DD REF REF REF REF DD MIN MAX Table 2. A Grade1 B Grade1 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE2 Resolution 16 16 Bits Relative Accuracy (INL) ±0.5 ±4 ±0.5 ±1 LSB T = −40°C to +105°C A ±0.5 ±4 ±0.5 ±2 T = −40°C to +125°C A Differential Nonlinearity (DNL) ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error (TUE) ±0.1 ±0.8 ±0.1 ±0.8 mV V = 2.7 V, V = 2 V DD REF Zero-Code Error 0.05 0.1 0.05 0.1 mV All 0s loaded to the DAC register Zero-Code Error Drift3 ±0.5 ±0.5 µV/°C Full-Scale Error ±0.01 ±0.05 ±0.01 ±0.05 % FSR All 1s loaded to the DAC register Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR Gain Error Drift3 ±0.5 ±0.5 ppm ppm of FSR/°C DC Crosstalk3 1 5 1 5 μV Due to single-channel full-scale output change 5 25 5 25 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS3 Output Voltage Range 0 V 0 V V REF REF DC Output Impedance (Normal 8 8 kΩ Output impedance tolerance ± 10% Mode) DC Output Impedance DAC in power-down mode Output Connected to 100 kΩ 100 100 kΩ Output impedance tolerance ± 20 kΩ Network Output Connected to 1 kΩ 1 1 kΩ Output impedance tolerance ± 400 Ω Network Power-Up Time4 2.9 2.9 µs DC PSRR −120 −120 dB V ± 10%, DAC = full scale DD REFERENCE INPUTS Reference Input Range 2 V − 0.4 2 V − 0.4 V DD DD Reference Current 0.002 ±1 0.002 ±1 µA Per DAC channel Reference Input Impedance 40 40 MΩ Per DAC channel LOGIC INPUTS3 Input Current5 ±1 ±1 µA Input Low Voltage, V 0.8 0.8 V INL Input High Voltage, V 2.2 2.2 V INH Pin Capacitance 4 4 pF POWER REQUIREMENTS V 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V DD DD DAC active, excludes load current I V = V and V = GND DD IH DD IL Normal Mode6 2.5 3 2.5 3 mA All Power-Down Modes7 0.4 0.4 µA 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 Linearity calculated using a code range of 0 to 65,535; output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Time taken to exit power-down mode and enter normal mode, 32nd clock edge to 90% of DAC midscale value, output unloaded. 5 Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale. 6 Interface inactive. All DACs active. DAC outputs unloaded. 7 All four DACs powered down. Rev. A | Page 3 of 24

AD5066 AC CHARACTERISTICS V = 2.7 V to 5.5 V, 2.0 V ≤ V A, V B, V C, V D ≤ V − 0.4 V all specifications T to T , unless otherwise noted. DD REF REF REF REF DD MIN MAX Table 3. Parameter1, 2 Min Typ Max Unit Conditions/Comments3 DYNAMIC PERFORMACE Output Voltage Settling Time 7.5 10 µs ¼ to ¾ scale settling to ±2 LSB, single channel update, output unloaded Output Voltage Settling Time 12 15 µs ¼ to ¾ scale settling to ±2 LSB, all channel update, output unloaded Slew Rate 1.7 V/µs Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry Reference Feedthrough −70 dB V = 3 V ± 0.5 V p-p, frequency = 60 Hz to 20 MHz REF Digital Feedthrough 0.02 nV-sec Digital Crosstalk 1.7 nV-sec Analog Crosstalk 3.7 nV-sec DAC-to-DAC Crosstalk 5.4 nV-sec Total Harmonic Distortion −83 dB V = 3 V ± 0.2 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 30 nV/√Hz DAC code = 0x8000, 1 kHz 25 nV/√Hz DAC code = 0x8000, 10 kHz Output Noise 4.7 μV p-p 0.1 Hz to 10 Hz 1 Temperature range is −40°C to +125°C, typical at +25°C. 2 See the Terminology section. 3 Guaranteed by design and characterization; not production tested. Rev. A | Page 4 of 24

AD5066 TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2, V = 2.7 V to R F DD IL IH DD 5.5 V, all specifications T to T , unless otherwise noted. See Figure 2. MIN MAX Table 4. Parameter1 Symbol Min Typ Max Unit SCLK Cycle Time t 20 ns 1 SCLK High Time t 10 ns 2 SCLK Low Time t 10 ns 3 SYNC to SCLK Falling Edge Set-Up Time t 17 ns 4 Data Set-Up Time t 5 ns 5 Data Hold Time t 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t 5 30 ns 7 Minimum SYNC High Time t 8 Single Channel Update 3 µs All Channel Update 8 µs SYNC Rising Edge to SCLK Fall Ignore t 17 ns 9 LDAC Pulse Width Low t 20 ns 10 SCLK Falling Edge to LDAC Rising Edge t 20 ns 11 CLR Pulse Width Low t 10 ns 12 SCLK Falling Edge to LDAC Falling Edge t 10 ns 13 CLR Pulse Activation Time t 10.6 µs 14 1 Maximum SCLK frequency is 50 MHz. Guaranteed by design and characterization; not production tested. t1 t9 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB31 DB0 t13 t10 LDAC1 t11 LDAC2 CLR t12 VOUT t14 12ASYSNYNCCHHRORONNOOUSUSLDLDACACUUPDPADATETEMMOODDE.E. 06845-003 Figure 2. Serial Write Operation Rev. A | Page 5 of 24

AD5066 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings A may cause permanent damage to the device. This is a stress Table 5. rating only; functional operation of the device at these or any Parameter Rating other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Exposure to absolute Digital Input Voltage to GND −0.3 V to V + 0.3 V DD maximum rating conditions for extended periods may affect V x to GND −0.3 V to V + 0.3 V OUT DD device reliability. V x to GND −0.3 V to V + 0.3 V REF DD Operating Temperature Range Industrial −40°C to +125°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (T ) +150°C JMAX TSSOP Package Power Dissipation (T − T )/θ JMAX A JA θ Thermal Impedance 150.4°C/W JA Reflow Soldering Peak Temperature SnPb 240°C Pb-Free 260°C Rev. A | Page 6 of 24

AD5066 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 16 SCLK SYNC 2 15 DIN VDD 3 14 GND VREFB 4 AD5066 13 VOUTB TOP VIEW VREFA 5 (Not to Scale) 12 VOUTD VOUTA 6 11 VREFD VOUTC 7 10 CLR POR 8 9 VREFC 06845-004 Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Load DAC. Logic input. This is used to update the DAC register and, consequently, the analog outputs. When tied permanently low, the addressed DAC register is updated on the falling edge of the 32nd clock. If LDAC is held high during the write cycle, the addressed DAC input shift register is updated but the output is held off until the falling edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device. 3 V Power Supply Input. The AD5066 can be operated from 2.7 V to 5.5 V. Decouple the supply with a 10 µF DD capacitor in parallel with a 0.1 µF capacitor to GND. 4 V B External Reference Voltage Input for DAC B. REF 5 V A External Reference Voltage Input for DAC A. REF 6 V A Unbuffered Analog Output Voltage from DAC A. OUT 7 V C Unbuffered Analog Output Voltage from DAC C. OUT 8 POR Power-On Reset Pin. Tying this pin to GND powers the DAC outputs to zero scale on power-up. Tying this pin to V powers the DAC outputs to midscale. DD 9 V C External Reference Voltage Input for DAC C. REF 10 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the CLR code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 11 V D External Reference Voltage Input for DAC D. REF 12 V D Unbuffered Analog Output Voltage from DAC D. OUT 13 V B Unbuffered Analog Output Voltage from DAC B. OUT 14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. A | Page 7 of 24

AD5066 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 0.5 0.4 0.2 0.3 MAXINL 0.1 0.2 B) R (LS 0 SB) 0.1 L ERRO––00..21 INL (L–0.10 MIN INL N I –0.2 –0.3 VDD = 5V –0.3 –0.4 VTAR E=F 2=5 °4C.096V –0.4 TVAD D= =2 55°VC –0.5 –0.5 0 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06845-105 2 RE3FERENCEVOLTAGE4(V) 5 06845-108 Figure 4. INL Error vs. Code Figure 7. INL vs. Reference Input Voltage 0.3 0.5 VDD = 5V VREF = 4.096V 0.4 0.2 TA = 25°C 0.3 0.1 0.2 B) S R (L 0 SB) 0.1 MAXDNL NL ERRO–0.1 DNL (L–0.10 MIN DNL D –0.2 –0.2 –0.3 –0.3 VDD = 5.5V –0.4 TA = 25°C –0.40 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06845-106 –0.52 RE3FERENCEVOLTAGE4(V) 5 06845-109 Figure 5. DNL Error vs. Code Figure 8. DNL vs. Reference Input Voltage 0.03 100 0.02 80 R (mV) 0.01 R (µV) 60 RO 0 RO 40 R R MAX TUE D E –0.01 D E 20 E E ST –0.02 ST 0 U U ADJ –0.03 ADJ –20 N N TOTAL U –––000...000654 VTVADR DE=F = 2= 55 °4VC.096V TOTAL U –––864000 TVAD D= =2 55°.5CV MIN TUE –0.070 10,000 20,000 30,C00O0DE40,000 50,000 60,000 06845-107 –1002 RE3FERENCE VOLTAGE4 (V) 5 06845-110 Figure 6. Total Unadjusted Error vs. Code Figure 9. Total Unadjusted Error vs. Reference Input Voltage Rev. A | Page 8 of 24

AD5066 1.2 0.010 1.0 0.8 0.005 0.6 R) 0.4 S ERROR (%F 0 DNL (LSB) –00..220 MAX DNL AIN –0.4 MIN DNL G –0.005 –0.6 VDD = 5.5V –0.8 VVDRDEF = = 5 4V.096V TA = 25°C –1.0 –0.0102 RE3FERENCEVOLTAGE4(V) 5 06845-111 –1.2–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 06845-114 Figure 10. Gain Error Vs. Reference Input Voltage Figure 13. DNL vs. Temperature 0.10 100 0.09 80 ROR (mV) 000...000678 D ERROR (µV) 246000 MAX TUE R E SCALE E 00..0045 NADJUST –200 MIN TUE RO- 0.03 L U –40 E A Z 0.02 TVAD D= =2 55°.5CV TOT –60 VDD = 5V 0.01 –80 VREF = 4.096V 0 –100 2 RE3FERENCE VOLTAGE4 (V) 5 06845-112 –40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 06845-115 Figure 11. Zero-Code Error Vs. Reference Input Voltage Figure 14. Total Unadjusted Error vs. Temperature 1.2 50 1.0 40 MAX INL 0.8 30 0.6 20 0.4 V) µ B) 0.2 R ( 10 S O INL (L–0.02 MIN INL LE ERR–100 –0.4 CA S–20 –0.6 O- R E–30 –0.8 Z –1.0 VVDRDEF = = 5 4V.096V –40 VVDRDEF = = 5 4V.096V –1.2–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 06845-113 –50–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 06845-116 Figure 12. INL vs. Temperature Figure 15. Zero-Code Error vs. Temperature Rev. A | Page 9 of 24

AD5066 0.0020 7 VDD = 5V 0.0015 DAC OUTPUT UNLOADED 6 TA = 25°C 0.0010 R) 5 S F 0.0005 % ROR ( 0 HITS4 ER 3 N –0.0005 AI G 2 –0.0010 –0.0015 VVDRDEF = = 5 4V.096V 1 –0.0020–40 –20 0 T2E0MPER4A0TURE6 (0°C) 80 100 120 06845-117 0 2.45 2.50 IDD 2P.O55WER-UP 2(m.60A) 2.65 2.70 06845-120 Figure 16. Gain Error vs. Temperature Figure 19. I Histogram V = 5.5 V DD DD 0.010 60 VDD = 5V TA = 25°C DAC OUTPUT UNLOADED 50 +125°C IDD POWERDOWN 0.005 +25°C IDD POWERDOWN R) 40 –40°CIDD POWERDOWN S F % OR ( 0 FULL-SCALEERROR TS30 R HI R E 20 GAINERROR –0.005 VVDRDEF = = 5 4V.096V 10 TA = 25°C –0.0102.7 3.2 3.7 VDD 4(V.2) 4.7 5.2 06845-118 0 0.2 0.4IDD POWER0.D6OWN (µA) 0.8 1.0 06845-139 Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage Figure 20. I Power-Down Histogram DD 20 5 VDD = 5.5V VREF = 4.096V TA = 25°C 4 15 V) µ or ( LE Err10 mA) 3 O-SCA I (DD 2 R ZE VDD = 5V 5 VREF = 4.096V TA = 25°C 1 02.7 3.7 VDD (V) 4.7 06845-119 00 10,000 20,000 3D0A,0C0 0COD4E0,000 50,000 60,000 06845-121 Figure 18. Zero-Code Error vs. Supply Voltage Figure 21. I vs. Code DD Rev. A | Page 10 of 24

AD5066 5 3.5 VDD = 5.5V VREF = 4.096V 1/4 TO 3/4 TA = 25°C 4 CODE = MIDSCALE 3.0 I (mA)DD 3 OLTAGE (V) 22..05 V 2 UT 1.5 P UT 3/4 TO 1/4 O 1.0 1 VVDREDF = = 4 4.5.0V96V 0.5 OUTPUT AMPLIFIER = AD797 TA = 25°C DAC LOAD = 9pF 0–40 –20 0 T20EMPER4A0TURE6 (0°C) 80 100 120 06845-122 00 1 2 3 4TIME5 (µs) 6 7 8 9 10 06845-125 Figure 22. I vs. Temperature Figure 25. Settling Time DD 5 VREF = 4.096V TA = 25°C VDD CODE = MIDSCALE 4 VREF 3 A) m (D D I 2 VOUT 1 VREF = 4.096V TA = 25°C 02.7 3.0 3.5SUPPLY4 .V0OLTAGE4 (.V5) 5.0 5.5 06845-123 CCHH13 22..0000VV CH2 2.00V MT 1 03.00.02m0%s A CH1 640mV 06845-126 Figure 23. I vs. Supply Voltage Figure 26. POR to 0 V DD 10 VVDRDEF = = 5 4.5.0V96V VDD TA = 25°C 8 VREF 6 A) m ( D D I 4 VOUT 2 VDD = 5.5V VREF = 4.096V 00 1 DIG2ITAL INPUT3 VOLTAG4E (V) 5 6 06845-124 CCHH13 22..0000VV CH2 2.00V MT 1 03.00.02m0%s A CH1 640mV 06845-127 Figure 24. I vs. Digital Input Voltage Figure 27. POR to MS DD Rev. A | Page 11 of 24

AD5066 15 CH1 = SCLK VDD = 5V 10 VREF = 4.096V TA = 25°C 1 V) m E ( 5 D U T PLI 0 M CH2 = VOUT VDD = 5V H A POWER-UP TO MIDSCALE C OUTPUT UNLOADED LIT –5 G 2 –10 –15 CH1 5V CH2 500mV MT 2 µ55s% A CH2 1.2V 06845-128 –2 0 2 TIME4 (µs) 6 8 10 06845-131 Figure 28. Exiting PD to MS Figure 31. Digital Crosstalk 15 20 15 VDD = 5V 10 VREF = 4.096V TA = 25°C V) V) 10 m m DE ( 5 DE ( 5 U U T T PLI 0 PLI 0 M M A A CH CH –5 T –5 T GLI VDD = 5V GLI–10 VREF = 4.096V –10 TA = 25°C CODE = 0x8000 TO 0x7FFF –15 OUTPUT UNLOADED WITH 5kΩ AND 200pF –15 –20 –2 0 2 TIME4 (µs) 6 8 10 06845-129 –2 0 2 TIME4 (µs) 6 8 10 06845-132 Figure 29. Glitch Figure 32. DAC-to-DAC Crosstalk 15 4 VDD = 5V 3 10 VREF = 4.096V TA = 25°C mV) V) 2 MPLITUDE ( 50 VOLTAGE (µ 10 CH A PUT –1 T –5 T GLI OU–2 –10 VDD = 5V –3 VREF = 4.096V TA = 25°C –15 –4 –2 0 2 TIME4 (µs) 6 8 10 06845-130 0 1 2 3 T4ime (S5econd6s) 7 8 9 10 06845-133 Figure 30. Analog Crosstalk Figure 33. 1/f Noise Rev. A | Page 12 of 24

AD5066 0 VDD= 5V, CH1 PEAK TO PEAK –10 TA= 25ºC 155mV DAC LOADED WITH MIDSCALE –20 VREF = 3.0V ± 200mV p-p VOUT –30 B) L (d –40 E EV –50 L UT –60 O V –70 LAST SCLK –80 –1–09005 10 20 FREQUE3N0CY (kHz) 40 50 5506845-016 CH1 50.0mV CH2 5.00V MT 4 .90.08µ00s% VTVAADR DEC=F H= 2= 255 °4V C . 0 916.8V0V 06845-137 Figure 34. Total Harmonic Distortion Figure 37. Glitch Upon Entering Power Down CH1 PEAK TO PEAK 159mV CLR VOUT VOUT LAST SCLK VDD = 5V VREF = 4.096V TA = 25°C CH1 5.00V CH2 2.00V MT 2 .1000.m20s% A CH1 1.80V 06845-135 CH1 50.0mV CH2 5.00V MT 4 .90.08µ00s% A CH2 1.80V 06845-138 Figure 35. Hardware CLR Figure 38. Glitch Upon Exiting Power Down 3.0 2.8 1/4 TO 3/4 2.6 V)2.4 E ( AG2.2 T L O2.0 V T U1.8 P UT 3/4 TO 1/4 O1.6 1.4 VDD = 4.5V VREF = 4.096V 1.2 TA = 25°C 1.0 1.5 1.6 1.7 1.8 1T.I9ME (µ2s) 2.1 2.2 2.3 2.4 06845-136 Figure 36. Slew Rate Rev. A | Page 13 of 24

AD5066 TERMINOLOGY DC Crosstalk Relative Accuracy or Integral Nonlinearity (INL) DC crosstalk is the dc change in the output level of one DAC in Relative accuracy or INL is a measure of the maximum response to a change in the output of another DAC. It is measured deviation in LSBs from a straight line passing through the with a full-scale output change on one DAC (or soft power-down endpoints of the DAC transfer function. Figure 4, Figure 5, and power-up) while monitoring another DAC kept at midscale. and Figure 6 show typical INL vs. code plots. It is expressed in microvolts. Differential Nonlinearity (DNL) Reference Feedthrough DNL is the difference between the measured change and the Reference feedthrough is the ratio of the amplitude of the signal ideal 1 LSB change between any two adjacent codes. A specified at the DAC output to the reference input when the DAC output differential nonlinearity of ±1 LSB maximum ensures mono- is not being updated (that is, LDAC is high). It is expressed in tonicity. Figure 7, Figure 8, and Figure 9 show typical DNL vs. code plots. decibels. Zero-Code Error Digital Feedthrough Zero-code error is a measure of the output error when zero Digital feedthrough is a measure of the impulse injected into code (0x0000) is loaded into the DAC register. Ideally, the the analog output of a DAC from the digital input pins of the output should be 0 V. The zero-code error is always positive in device but is measured when the DAC is not being written to the AD5066, because the output of the DAC cannot go below (SYNC held high). It is specified in nanovolts per second and 0 V. Zero-code error is expressed in millivolts. Figure 17 shows measured with one simultaneous DIN and SCLK pulse loaded a typical zero-code error vs. supply voltage plot. to the DAC. Gain Error Digital Crosstalk Gain error is a measure of the span error of the DAC. It is the Digital crosstalk is the glitch impulse transferred to the output deviation in slope of the DAC transfer characteristic from the of one DAC at midscale in response to a full-scale code change ideal, expressed as a percentage of the full-scale range. (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in Gain Error Drift nanovolts per second. Gain error drift is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale Analog Crosstalk range)/°C. Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is Zero-Code Error Drift measured by loading one of the input registers with a full-scale Zero-code error drift is a measure of the change in zero-code code change (all 0s to all 1s or vice versa) while keeping LDAC error with a change in temperature. It is expressed in microvolts high and then pulsing LDAC low and monitoring the output of per degrees Celsius. the DAC whose digital code has not changed. The area of the Full-Scale Error glitch is expressed in nanovolts per second. Full-scale error is a measure of the output error when a full- DAC-to-DAC Crosstalk scale code (0xFFFF) is loaded into the DAC register. Ideally, the DAC-to-DAC crosstalk is the glitch impulse transferred to the output should be V − 1 LSB. Full-scale error is expressed as a REF output of one DAC due to a digital code change and subsequent percentage of the full-scale range. output change of another DAC. This includes both digital and Digital-to-Analog Glitch Impulse analog crosstalk. It is measured by loading one of the DACs Digital-to-analog glitch impulse is the impulse injected into the with a full-scale code change (all 0s to all 1s or vice versa) with analog output when the input code in the DAC register changes LDAC low and monitoring the output of another DAC. The state. It is normally specified as the area of the glitch in nanovolts energy of the glitch is expressed in nanovolts per second. per second and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to Total Harmonic Distortion (THD) 0x8000). See Figure 28. THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as DC Power Supply Rejection Ratio (PSRR) the reference for the DAC, and the THD is a measure of the DC PSRR indicates how the output of the DAC is affected by harmonics present on the DAC output. It is measured in changes in the supply voltage. DC PSRR is the ratio of the decibels. change in V to a change in V for full-scale output of the OUT DD DAC. It is measured in decibels. Rev. A | Page 14 of 24

AD5066 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER SERIAL INTERFACE The AD5066 is a quad 16-bit, serial input, voltage output The AD5066 has a 3-wire serial interface (SYNC, SCLK, and nanoDAC. The part operates from supply voltages of 2.7 V to DIN) that is compatible with SPI, QSPI, MICROWIRE, and 5.5 V. Data is written to the AD5066 in a 32-bit word format via most DSP interface standards. See Figure 2 for a timing diagram a 3-wire serial interface. The AD5066 incorporates a power-on of a typical write sequence. reset circuit to ensure the DAC output powers up to a known INPUT SHIFT REGISTER output state. The devices also have a software power-down mode that reduces the typical current consumption to typically 400 nA. The input shift register is 32 bits wide (see Figure 40). The first four bits are don’t cares. The next four bits are the command Because the input coding to the DAC is straight binary, the ideal bits, C3 to C0 (see Table 7), followed by the 4-bit DAC address output voltage when using an external reference is given by bits, A3 to A0 (see Table 8), and finally the bit data-word. The  D  data-word comprises of a 16-bit input code followed by four don’t V V   OUT REFIN 2N  care bits (see Figure 40). These data bits are transferred to the Input register on the 32nd falling edge of SCLK. Commands can where: be executed on individually selected DAC channels or on all DACs. D is the decimal equivalent of the binary code that is loaded to the DAC register (0 to 65,535). Table 7. Command Definitions N is the DAC resolution. Command DAC ARCHITECTURE C3 C2 C1 C0 Description The DAC architecture of the AD5066 consists of two matched 0 0 0 0 Write to Input Register n DAC sections. A simplified circuit diagram is shown in 0 0 0 1 Transfer contents of Input Register n to Figure 39. The four MSBs of the 16-bit data word are decoded DAC Register n to drive 15 switches, E1 to E15. Each of these switches connects 0 0 1 0 Write to Input Register n and update all DAC Registers one of 15 matched resistors to either GND or the V buffer REF 0 0 1 1 Write to Input Register n and update output. The remaining 12 bits of the data word drive the S0 to DAC Register n S11 switches of a 12-bit voltage mode R-2R ladder network. 0 1 0 0 Power down/power up DAC VOUT 0 1 0 1 Load clear code register 2R 2R 2R 2R 2R 2R 2R 0 1 1 0 Load LDAC register S0 S1 S11 E1 E2 E15 0 1 1 1 Reset (power-on reset) VREF 1 0 0 0 Reserved 1 0 0 1 Reserved 12-BIT R-2R LADDER FOUINRST MOESG 1BM5s E EDNQETUCSAOLDED 06845-005 1 1 1 1 Reserved Table 8. DAC Input Register Address Bits Figure 39. DAC Ladder Structure Address (n) REFERENCE BUFFER A3 A2 A1 A0 Selected DAC Channel The AD5066 operates with an external reference. Each of the 0 0 0 0 DAC A four on-board DACs has a dedicated voltage reference pin that 0 0 0 1 DAC B is buffered. The reference input pin has an input range of 2 V 0 0 1 0 DAC C to V − 0.4 V. This input voltage is then used to provide a 0 0 1 1 DAC D DD buffered reference for the DAC core. 1 1 1 1 All DACs DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 DB15DB14DB13DB12DB11DB10DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X DATA BITS COMMAND BITS ADDRESS BITS 06845-007 Figure 40. Input Shift Register Content Rev. A | Page 15 of 24

AD5066 When Bit DB9 and Bit DB8 in the control register are set to 0, The write sequence begins by bringing the SYNC line low. the part is configured in normal mode with its normal power Bringing the SYNC line low enables the DIN and SCLK input consumption of 2.5 mA at 5 V. However, for the three power- buffers. Data from the DIN line is clocked into the 32-bit shift down modes, the supply current falls to 0.4 µA if all the channels register on the falling edge of SCLK. The serial clock frequency are powered down. Not only does the supply current fall, but can be as high as 50 MHz, making the AD5066 compatible with the output pin is also internally switched from the output of the high speed DSPs. On the 32nd falling clock edge, the last data bit DAC to a resistor network of known values. This has the advantage is clocked in, and the programmed function is executed, that is, that the output impedance of the part is known while the part a change in the input register contents (see Table 8) and/or a is in power-down mode. There are three different options: the change in the mode of operation. At this stage, the SYNC line output is connected internally to GND through either a 1 kΩ or can be kept low or be brought high. In either case, it must be a 100 kΩ resistor, or it is left open-circuited (three-state). The brought high for a minimum of 2 μs (single-channel update, see output stage is illustrated in Figure 41. the t parameter in Table 4) before the next write sequence so 8 that a falling edge of SYNC can initiate the next write sequence. DAC VOUT Idle SYNC high between write sequences for even lower power operation of the part. SYNC Interrupt POWER-DOWN CIRCUITRY RESISTOR Ilena ast n 3o2r mfalalli nwgr eitdeg seesq oufe SnCceL, Kth, ea nSdY NthCe DlinAeC i si sk uepptd laotwed f oorn a tth e NETWORK 06845-008 32nd falling edge. However, if SYNC is brought high before the Figure 41. Output Stage During Power-Down Mode 32nd falling edge, this acts as an interrupt to the write sequence. The bias generator, DAC core, and other associated linear The input shift register is reset, and the write sequence is seen circuitry are shut down when all channels are powered down. as invalid. Neither an update of the DAC register contents nor a However, the contents of the DAC register are unaffected when change in the operating mode occurs (see Figure 42). in power-down mode. The time to exit power-down mode is Power-Down Modes typically 2.9 µs (see Figure 27). The AD5066 can be configured through software, in one of Table 9. Modes of Operation four different modes: normal mode (default) and three separate DB9 DB8 Operating Mode power-down modes (see Table 9). Any or all DACs can be 0 0 Normal operation powered down. Command 0100 is reserved for the power- Power-down modes down function (see Table 7). These power-down modes are 0 1 1 kΩ to GND software-programmable by setting two bits, Bit DB9 and 1 0 100 kΩ to GND Bit DB8, in the input shift register. Table 9 shows how the state 1 1 Three-state of the bits corresponds to the mode of operation of the device. Any or all DACs (DAC A to DAC D) can be powered down to the selected mode by setting the corresponding four bits (DB3, DB2, DB1, DB0) to 1. See Table 10 for the contents of the input shift register during power-down/power-up operation. SCLK SYNC DIN DB31 DB0 DB31 DB0 SYNC HINIGVHA LBIEDF WORRIET E3 2SNEDQ FUAELNLCINEG: EDGE OUTPUT UPVDAALTIDE SW ORINT ET HSEE Q32UNEDN FCAEL:LING EDGE 06845-017 Figure 42. SYNC Interrupt Facility Rev. A | Page 16 of 24

AD5066 POWER-ON RESET where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software The AD5066 contains a power-on reset circuit that controls executable reset function that resets the DAC to the power-on the output voltage during power-up. By connecting the POR reset code. Command 0111 is reserved for this reset function pin low, the AD5066 output powers up to 0 V; by connecting (see Table 7). Any events on LDAC or CLR during power-on the POR pin high, the AD5066 output powers up to midscale. reset are ignored. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications Table 10. 32-Bit Input Shift Register Contents for Power-Up/Power-Down Function MSB LSB DB31 to DB23 to DB10 to DB4 to DB28 DB27 DB26 DB25 DB24 DB20 DB19 DB9 DB8 DB7 DB3 DB2 DB1 DB0 X 0 1 0 0 X X PD1 PD0 X DAC D DAC C DAC B DAC A Don’t Command bits (C2 to C0) Address bits Don’t Power-down Don’t Power-down/power-up channel cares (A3 to A0)— cares mode cares selection—set bit to 1 to select don’t cares Rev. A | Page 17 of 24

AD5066 CLEAR CODE REGISTER Synchronous LDAC: LDAC is held permanently low. After new data is read, the DAC registers are updated on the falling edge The AD5066 has a hardware CLR pin that is an asynchronous of the 32nd SCLK pulse, provided LDAC is held low. clear input. The CLR input is falling edge sensitive. Bringing the CLR line low clears the contents of the input register and the Asynchronous LDAC: LDAC is held high then pulsed low to DAC registers to the data contained in the user-configurable update. The outputs are not updated at the same time that the CLR register and sets the analog outputs accordingly (see input registers are written to. When LDAC is pulsed low, the Table 11). This function can be used in system calibration to DAC registers are updated with the contents of the input load zero scale, midscale, or full scale to all channels together. registers. These clear code values are user-programmable by setting two Command 0001, 0010 and 0011 (see Table 7) update the DAC bits, Bit DB1 and Bit DB0, in the control register (see Table 11). Register/Registers, regardless of the level of the LDAC pin The default setting clears the outputs to 0 V. Command 0101 is Software LDAC Function reserved for loading the clear code register (see Table 7). Writing to the DAC using Command 0110 loads the 4-bit Table 11. Clear Code Register LDAC register (DB3 to DB0). The default for each channel is DB1 (CR1) DB0 (CR0) Clears to Code 0; that is, the LDAC pin works normally. Setting the bits to 1 0 0 0x0000 updates the DAC channel regardless of the state of the hardware 0 1 0x8000 LDAC pin, so that it effectively sees the hardware LDAC pin 1 0 0xFFFF as being tied low (see Table 12 for the LDAC register mode of 1 1 No operation operation.) This flexibility is useful in applications where the user wants to simultaneously update select channels while the The part exits clear code mode on the 32nd falling edge of the remainder of the channels are synchronously updating. next write to the part. If CLR is activated during a write sequence, the write is aborted. Table 12. Load LDAC Register The CLR pulse activation time (the falling edge of CLR to when LDAC Bits (DB3 to LDAC the output starts to change) is typically 10.6 µs. See Table 13 for DB0) Pin LDAC Operation contents of the input shift register during the loading clear code 0 1/0 Determined by LDAC pin register operation. 1 X1 DAC channels update, overrides the LDAC LDAC FUNCTION pin; DAC channels see LDAC as 0 Hardware LDAC Pin 1 X = don’t care. The outputs of all DACs can be updated simultaneously using The LDAC register gives the user extra flexibility and control the hardware LDAC pin, as shown in Figure 2. There are two over the hardware LDAC pin (see Table 14). Setting the LDAC methods of using the hardware LDAC pin: synchronously bits (DB0 to DB3) to 0 for a DAC channel means that this (LDAC permanently low) and asynchronously (LDAC pulsed). channel’s update is controlled by the hardware LDAC pin. Table 13. 32-Bit Input Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0 X 0 1 0 1 X X X X X 1/0 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Clear code register (CR1 to CR0) Table 14. 32-Bit Input Shift Register Contents for LDAC Overwrite Function MSB LSB DB31 DB4 to DB28 DB27 DB26 DB25 DB24 DB23 to DB20 to DB19 DB3 DB2 DB1 DB0 X 0 1 1 0 X X DAC D DAC C DAC B DAC A Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Setting LDAC bit to 1 override LDAC pin Rev. A | Page 18 of 24

AD5066 POWER SUPPLY BYPASSING AND GROUNDING AD5066 to 68HC11/68L11 Interface When accuracy is important in a circuit, it is helpful to carefully Figure 44 shows a serial interface between the AD5066 and the consider the power supply and ground return layout on the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 board. The printed circuit board containing the AD5066 should drives the SCLK of the AD5066, and the MOSI output drives have separate analog and digital sections. If the AD5066 is in a DIN of the DAC. A port line (PC7) drives the SYNC signal. system where other devices require an AGND-to-DGND con- 68HC11/68L11* AD5066* nection, make the connection at one point only and as close as possible to the AD5066. PC7 SYNC Bypass the power supply to the AD5066 with 10 µF and 0.1 µF capacitors. The capacitors should be physically as close as SCK SCLK possible to the device, with the 0.1 µF capacitor, ideally, right up atygpaein. sItt itsh eim dpeovrictea.n Tt hthea 1t 0th µeF 0 c.1ap µaFc ictaoprsa cairteo rth hea tsa lnotwal uefmfe cbteivaed *ADDITIONAL MPOINSSI OMITTED DFIONR CLARITY. 06845-010 Figure 44. AD5066 to 68HC11/68L11 Interface series resistance and low effective series inductance, typical of common ceramic types of capacitors. This 0.1 µF capacitor The setup conditions for correct operation of this interface are provides a low impedance path to ground for high frequencies as follows: The 68HC11/68L11 is configured with its CPOL bit caused by transient currents due to internal logic switching. as 0, and the CPHA bit as 1. When data is being transmitted to The power supply line should have as large a trace as possible to the DAC, the SYNC line is taken low (PC7). When the 68HC11/ provide a low impedance path and reduce glitch effects on the 68L11 is configured as described previously, data appearing on supply line. Shield the clocks and other fast switching digital the MOSI output is valid on the falling edge of SCK. Serial data signals from other parts of the board by digital ground. Avoid from the 68HC11/68L11 is transmitted in 8-bit bytes with only crossover of digital and analog signals if possible. When traces eight falling clock edges occurring in the transmit cycle. Data is cross on opposite sides of the board, ensure that they run at transmitted MSB first. To load data to the AD5066, PC7 is left right angles to each other to reduce feedthrough effects through low after the first eight bits are transferred, and a second serial the board. The best board layout technique is the microstrip write operation is performed to the DAC. PC7 is taken high at technique, where the component side of the board is dedicated the end of this procedure. to the ground plane only, and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. MICROPROCESSOR INTERFACING AD5066 to Blackfin® ADSP-BF53X Interface Figure 43 shows a serial interface between the AD5066 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multipro- cessor communications. Using SPORT0 to connect to the AD5066, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5066, TSCLK0 drives the SCLK of the parts, and TFS0 drives SYNC. ADSP-BF53x* AD5066* TFS0 SYNC DT0PRI DIN *ADDITIONATSLC PLINKS0 OMITTED SFCOLRK CLARITY. 06845-009 Figure 43. AD5066 to Blackfin ADSP-BF53X Interface Rev. A | Page 19 of 24

AD5066 AD5066 to 80C51/80L51 Interface 80C51/80L51* AD5066* Figure 45 shows a serial interface between the AD5066 and the 80C51/80L51 microcontroller. The setup for the interface is as P3.3 SYNC follows: TxD of the 80C51/80L51 drives SCLK of the AD5066, TxD SCLK RxD drives DIN on the AD5066, and a bit-programmable pin on the port (P3.3) drives the SYNC signal. When data is to be RxD DIN transmitted to the AD5066, P3.3 is taken low. The 80C51/80L51 *ADDITIONAL PINS OMITTED FOR CLARITY. 06845-011 transmit data in 8-bit bytes only; thus, only eight falling clock Figure 45. AD5066 to 80C512/80L51 Interface edges occur in the transmit cycle. To load data to the DAC, P3.3 AD5066 to MICROWIRE Interface is left low after the first eight bits are transmitted, and a second, third, and fourth write cycle is initiated to transmit the second, Figure 46 shows an interface between the AD5066 and any third, and fourth byte of data. P3.3 is taken high following the MICROWIRE-compatible device. Serial data is clocked into completion of this cycle. The 80C51/80L51 output the serial the AD5066 on the falling edge of the SCLK. data in a format that has the LSB first. The AD5066 must MICROWIRE* AD5066* receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. CS SYNC SK DIN *ADDITIONAL PISNOS OMITTED FOR CLSACRLITKY. 06845-012 Figure 46. AD5066 to MICROWIRE Interface Rev. A | Page 20 of 24

AD5066 APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY R2 = 10kΩ Because the supply current required by the AD5066 is extremely +5V R1 = 10kΩ low, an alternative option is to use a voltage reference to supply +5.5V the required voltage to the parts (see Figure 47). This is espe- +5V AD820/ ±5V OP295 cially useful if the power supply is quite noisy or if the system VREF VREF VOUT supply voltages are at some value other than 5 V or 3 V, for VDD example, 15 V. The voltage reference outputs a steady supply 10µF 0.1µF AD5066 –5V voltage for the AD5066. If the low dropout REF195 is used, it must supply 2.5 mA of current to the AD5066 with no load on the output of t1h5Ve DAC. SERIAL3- WINITREERFACE 06845-014 Figure 48. Bipolar Operation with the AD5066 5V 4.5V REF195 REF194 USING THE AD5066 WITH A GALVANICALLY ISOLATED INTERFACE VDD VREF SYNC In process control applications in industrial environments, S3E-WRIIRAEL SCLK AD5066 VOUTx = 0V TO 4.5V it is often necessary to use a galvanically isolated interface to INTERFACE DIN protect and isolate the controlling circuitry from any hazardous 06845-013 cthoem DmAoCn -ims foudnec tvioolntaingge.s itChoatu cpalenr ®o cpcruovr iidne tsh ies oalraetaio wn hiner eex cess Figure 47. REF195 as a Power Supply to the AD5066 of 2.5 kV. The AD5066 uses a 3-wire serial logic interface, so BIPOLAR OPERATION the ADuM1300 three-channel digital isolator provides the required isolation (see Figure 49). The power supply to the The AD5066 has been designed for single-supply operation, part also needs to be isolated, which is done by using a but a bipolar output range is also possible using the circuit in transformer. On the DAC side of the transformer, a 5 V Figure 48. The circuit gives an output voltage range of ±5 V. regulator provides the 5 V supply required for the AD5066. Rail-to-rail operation at the amplifier output is achieved using an AD8638 or AD8639 the output amplifier. 5V REGULATOR The output voltage for any input code can be calculated as POWER 10µF 0.1µF follows:   D  R1+R2 R2 V =V × × −V ×  O  DD 65,536  R1  DD R1 VDD SCLK VIA VOA SCLK where: D = the input code in decimal (0 to 65,535). ADuM1300 AD5066 VDD = 5 V. SDI VIB VOB SYNC VOUTx R1 = R2 = 10 kΩ. 10×D VO =65,536 −5V DATA VIC VOC DIN GND Tsphoins disi nagn toou atp −u5t vVo lotuagtpeu rta, nagned o 0fx ±F5F FVF, w coitrhr e0sxp0o0n0d0i ncogr troe -a 06845-015 Figure 49. AD5066 with a Galvanically Isolated Interface +5 V output. Rev. A | Page 21 of 24

AD5066 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 50. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeter ORDERING GUIDE Package Power-On Model1 Temperature Range Package Description Option Reset to Code Accuracy Resolution AD5066BRUZ −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 16 bits AD5066BRUZ-REEL7 −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±1 LSB INL 16 bits AD5066ARUZ −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 16 bits AD5066ARUZ-REEL7 −40°C to +125°C 16-Lead TSSOP RU-16 Zero ±4 LSB INL 16 bits 1 Z = RoHS Compliant Part. Rev. A | Page 22 of 24

AD5066 NOTES Rev. A | Page 23 of 24

AD5066 NOTES ©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06845-0-8/10(A) Rev. A | Page 24 of 24