Fully Accurate, 12-/14-/16-Bit, Dual, V OUT nanoDAC SPI Interface, 4.5 V to 5.5 V in a TSSOP Data Sheet AD5025/AD5045/AD5065 FEATURES ence buffer is provided on chip. The AD5025/AD5045/AD5065 incorporate a power-on reset circuit that ensures the DAC output Low power dual 12-/14-/16-bit DAC, ±1 LSB INL powers up zero scale or midscale and remains there until a valid Individual voltage reference pins write takes place to the device. The AD5025/AD5045/AD5065 Rail-to-rail operation contain a power-down feature that reduces the current consump- 4.5 V to 5.5 V power supply tion of the device to typically 400 nA at 5 V and provides software Power-on reset to zero scale or midscale selectable output loads while in power-down mode. The parts are Power down to 400 nA @ 5 V put into power-down mode over the serial interface. Total unad- 3 power-down functions justed error for the parts is <2.5 mV. The parts exhibit very low Per channel power-down glitch on power-up. The outputs of all DACs can be updated Low glitch upon power-up Hardware power-down lockout capability simultaneously using the LDAC function, with the added Hardware LDAC with software LDAC override function functionality of user-selectable DAC channels to simultaneously CLR function to programmable code update. There is also an asynchronous CLR that clears all DACs SDO daisy-chaining option to a software-selectable code—0 V, midscale, or full scale. The 14-lead TSSOP parts also feature a power-down lockout pin, PDL, which can be used to prevent the DAC from entering power-down under any APPLICATIONS circumstances over the serial interface. Process controls PRODUCT HIGHLIGHTS Data acquisition systems Portable battery-powered instruments 1. Dual channel available in a 14-lead TSSOP package with Digital gain and offset adjustment individual voltage reference pins. Programmable voltage and current sources 2. 12-/14-/16-bit accurate, ±1 LSB INL. Programmable attenuators 3. Low glitch on power-up. 4. High speed serial interface with clock speeds up to 50 MHz. GENERAL DESCRIPTION 5. Three power-down modes available to the user. The AD5025/AD5045/AD5065 are low power, dual 12-/14-/16-bit 6. Reset to known output voltage (zero scale or midscale). buffered voltage output nanoDAC® DACs offering relative accuracy 7. Power-down lockout capability. specifications of ±1 LSB INL with individual reference pins, and can operate from a single 4.5 V to 5.5 V supply. The AD5025/ Table 1. Related Devices AD5045/AD5065 also offer a differential accuracy specification of Part No. Description ±1 LSB. The parts use a versatile 3-wire, low power Schmitt AD5666 Quad,16-bit buffered DAC, 16 LSB INL, TSSOP trigger serial interface that operates at clock rates up to 50 MHz AD5024/AD5044/AD5064 Quad 16-bit nanoDAC, 1 LSB INL, TSSOP AD5062/AD5063 16-bit nanoDAC, 1 LSB INL, MSOP and is compatible with standard SPI®, QSPI™, MICROWIRE™, AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23 and DSP interface standards. The reference for the AD5025/ AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, SOT-23 AD5045/AD5065 are supplied from an external pin and a refer- FUNCTIONAL BLOCK DIAGRAM POR VDD VREFA VREFB LDAC SCLK REINGPISUTTER REGDIASCTER DACA BUFFER VOUTA SYNC INTERFACE LOGIC DIN REINGPISUTTER REGDIASCTER DACB BUFFER VOUTB LDAC POWER-DOWN SDO PDL CLR AD5025/AD5045/AD5065 LOGICGND 06844-001 Figure 1. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5025/AD5045/AD5065 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Register .............................................................................. 17 Applications ....................................................................................... 1 Standalone Mode ........................................................................ 19 General Description ......................................................................... 1 SYNC Interrupt .......................................................................... 19 Product Highlights ........................................................................... 1 Daisy-Chaining ........................................................................... 19 Functional Block Diagram .............................................................. 1 Power-On Reset and Software Reset ....................................... 20 Revision History ............................................................................... 2 Power-Down Modes .................................................................. 20 Specifications ..................................................................................... 3 Clear Code Register ................................................................... 21 AC Characteristics ........................................................................ 4 LDAC Function ........................................................................... 21 Timing Characteristics ................................................................ 5 Power-Down Lockout ................................................................ 22 Absolute Maximum Ratings ............................................................ 7 Power Supply Bypassing and Grounding ................................ 22 ESD Caution .................................................................................. 7 Microprocessor Interfacing ....................................................... 23 Pin Configuration and Function Descriptions ............................. 8 Applications Information .............................................................. 24 Typical Performance Characteristics ............................................. 9 Using a Reference as a Power Supply for the Terminology .................................................................................... 15 AD5025/AD5045/AD5065 ....................................................... 24 Theory of Operation ...................................................................... 17 Bipolar Operation Using the AD5025/AD5045/AD5065 ..... 24 Digital-to-Analog Converter .................................................... 17 Using the AD5025/AD5045/AD5065 with a Galvanically Isolated Interface ................................................. 24 DAC Architecture ....................................................................... 17 Outline Dimensions ....................................................................... 25 Reference Buffer ......................................................................... 17 Ordering Guide .......................................................................... 25 Output Amplifier ........................................................................ 17 Serial Interface ............................................................................ 17 REVISION HISTORY 8/2016—Rev. 0 to Rev. A Change to Minimum SYNC High Times (Single Channel Update) Parameter and Minimum SYNC High Time (All Channel Update) Parameter, Table 4 ............................................. 5 10/2008—Revision 0: Initial Version Rev. A | Page 2 of 25

Data Sheet AD5025/AD5045/AD5065 SPECIFICATIONS V = 4.5 V to 5.5 V, R = 5 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V , unless otherwise specified. All specifications T to DD L L REFIN DD MIN T , unless otherwise noted. MAX Table 2. B Grade1 A Grade1, 2 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments STATIC PERFORMANCE3 Resolution AD5065 16 16 Bits AD5045 14 AD5025 12 Relative Accuracy AD5065 ±0.4 ±1 ±0.5 ±4 LSB T = −40°C to +105°C A AD5065 +0.4 ±2 ±0.5 ±4 T = −40°C to +125°C A AD5045 ±0.1 ±0.5 LSB T = −40°C to +105°C A AD5045 ±0.1 ±1 T = −40°C to +125°C A AD5025 ±0.05 ±0.25 LSB T = −40°C to +105°C A AD5025 ±0.05 ±0.5 T = −40°C to +125°C A Differential Nonlinearity ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error ±0.2 ±2.5 ±0.2 ±2.5 mV V = 2.5 V; V = 5.5 V REF DD Offset Error ±0.2 ±1.8 ±0.2 ±1.8 mV Code 512 (AD5065), Code 128 (AD5045), Code 32 (AD5025) loaded to DAC register Offset Error Drift4 ±2 ±2 µV/°C Full-Scale Error ±0.01 ±0.07 ±0.01 ±0.07 % FSR All 1s loaded to DAC register, VREF < VDD Gain Error ±0.005 ±0.05 ±0.005 ±0.05 % FSR Gain Temperature Coefficient4 ±1 ±1 ppm Of FSR/°C DC Crosstalk4 40 40 µV Due to single channel full-scale output change, R = 5 kΩ to GND or V L DD 40 40 µV/mA Due to load current change 40 40 µV Due to powering down (per channel) OUTPUT CHARACTERISTICS4 Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 1 1 nF R = 5 kΩ, R = 100 kΩ, and R = ∞ L L L DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 100 kΩ Output impedance tolerance ± 400 Ω 100 kΩ Network Output Connected to 1 1 kΩ Output impedance tolerance ± 20 Ω 1 kΩ Network Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero-scale, output shorted to V DD Power-Up Time 4.5 4.5 µs Time to exit power-down mode to normal mode of AD5024/AD5044/ AD5064, 32nd clock edge to 90% of DAC midscale value, output unloaded DC PSRR −92 −92 dB VDD ± 10%, DAC = full scale, VREF < VDD REFERENCE INPUTS Reference Input Range 2.2 V 2.2 V V DD DD Reference Current 35 50 35 50 µA Per DAC channel Reference Input Impedance 120 120 kΩ Rev. A | Page 3 of 25

AD5025/AD5045/AD5065 Data Sheet B Grade1 A Grade1, 2 Parameter Min Typ Max Min Typ Max Unit Conditions/Comments LOGIC INPUTS Input Current5 ±1 ±1 µA Input Low Voltage, V 0.8 0.8 V INL Input High Voltage, V 2.2 2.2 V INH Pin Capacitance4 4 4 pF LOGIC OUTPUTS (SDO)3, 4 Output Low Voltage, V 0.4 0.4 V I = 2 mA OL SINK Output High Voltage, V V − 1 V − 1 I = 2 mA OH DD DD SOURCE High Impedance Leakage ±0.002 ±1 ±0.002 ±1 μA Current4 High Impedance Output 7 7 pF Capacitance POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V DD I 6 DAC active, excludes load current DD Normal Mode 2.2 2.7 2.2 2.7 mA V = V and V = GND IH DD IL All Power-Down Modes7 0.4 2 0.4 2 µA T = −40°C to +105°C A 30 30 µA T = −40°C to +125°C A 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 A grade offered in AD5065 only. 3 Linearity calculated using a reduced code range—AD5065: Code 512 to Code 65,024; AD5045: Code 128 to Code 16,256; AD5025: Code 32 to Code 4064. Output unloaded. 4 Guaranteed by design and characterization; not production tested. 5 Current flowing into or out of individual digital pins. 6 Interface inactive. All DACs active. DAC outputs unloaded. 7 Both DACs powered down. AC CHARACTERISTICS V = 4.5 V to 5.5 V, R = 5 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V . All specifications T to T , unless otherwise noted. DD L L REFIN DD MIN MAX Table 3. Parameter1 Min Typ Max Unit Conditions/Comments2 Output Voltage Settling Time 5.8 8 µs ¼ to ¾ scale settling to ±1 LSB, R = 5 kΩ single-channel update L including DAC calibration sequence Output Voltage Settling Time 10.7 13 µs ¼ to ¾ scale settling to ±1 LSB, R = 5 kΩ all channel update including L DAC calibration sequence Slew Rate 1.5 V/µs Digital-to-Analog Glitch 4 nV-sec 1 LSB change around major carry Impulse3 Reference Feedthrough3 −90 dB V = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz REF SDO Feedthrough 0.07 nV-sec Daisy-chain mode; SDO load is 10 pF Digital Feedthrough3 0.1 nV-sec Digital Crosstalk3 1.9 nV-sec Analog Crosstalk3 1.2 nV-sec DAC-to-DAC Crosstalk3 2.1 nV-sec Multiplying Bandwidth3 340 kHz V = 3 V ± 0.86 V p-p REF Total Harmonic Distortion3 −80 dB V = 3 V ± 0.86 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, 1 kHz 60 nV/√Hz DAC code = 0x8400, 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 Temperature range is −40°C to + 125°C, typical at 25°C. 3 See the Terminology section. Rev. A | Page 4 of 25

Data Sheet AD5025/AD5045/AD5065 TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 3 and R F DD IL IH Figure 4. V = 4.5 V to 5.5 V. All specifications T to T , unless otherwise noted. DD MIN MAX Table 4. Parameter Symbol Min Typ Max Unit SCLK Cycle Time t 1 20 ns 1 SCLK High Time t 10 ns 2 SCLK Low Time t 10 ns 3 SYNC to SCLK Falling Edge Setup Time t 16.5 ns 4 Data Setup Time t 5 ns 5 Data Hold Time t 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t 0 30 ns 7 Minimum SYNC High Time (Single Channel Update) t 3 µs 8 Minimum SYNC High Time (All Channel Update) t 8 µs 8 SYNC Rising Edge to SCLK Fall Ignore t 17 ns 9 LDAC Pulse Width Low t 20 ns 10 SCLK Falling Edge to LDAC Rising Edge t 20 ns 11 CLR Pulse Width Low t 10 ns 12 SCLK Falling Edge to LDAC Falling Edge t 10 ns 13 CLR Pulse Activation Time t 10.6 µs 14 SCLK Rising Edge to SDO Valid t 2, 3 22 ns 15 SCLK Falling Edge to SYNC Rising Edge t 2 5 30 ns 16 SYNC Rising Edge to SCLK Rising Edge t 2 8 ns 17 SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (Single Channel Update) t 2 2 µs 18 SYNC Rising Edge to LDAC/CLR/PDL Falling Edge (All Channel Update) t 2 4 µs 18 PDL Minimum Pulse Width t 20 ns 19 1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested. 2 Daisy-chain mode only. 3 Measured with the load circuit of Figure 2. t15 determines the maximum SCLK frequency in daisy-chain mode. Circuit and Timing Diagrams 2mA IOL TO OUTPUT VOH (MIN) + VOL (MAX) PIN 2 CL 50pF 2mA IOH 06844-002 Figure 2. Load Circuit for Digital Output (SDO) Timing Specifications Rev. A | Page 5 of 25

AD5025/AD5045/AD5065 Data Sheet t1 t9 SCLK t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB31 DB0 t13 t10 LDAC1 t11 LDAC2 t12 CLR t14 VOUT t19 PDL 12ASYSNYCNHCRHORONNOOUUS SL DLDAACC U UPDPDAATET EM MOODDE.E. 06844-003 Figure 3. Serial Write Operation SCLK 32 64 t17 t8 t4 t16 SYNC t5 t6 DIN DB31 DB0 DB31 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t15 SDO DB31 DB0 UNDEFINED INPUT WORD FOR DAC N t18 t10 LDAC1 t18 t12 CLR t18 t19 1IFP IND LDAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY. 06844-004 Figure 4. Daisy-Chain Timing Diagram Rev. A | Page 6 of 25

Data Sheet AD5025/AD5045/AD5065 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Table 5. Ratings may cause permanent damage to the product. This is a Parameter Rating stress rating only; functional operation of the product at these V to GND −0.3 V to +7 V DD or any other conditions above those indicated in the operational Digital Input Voltage to GND −0.3 V to V + 0.3 V DD section of this specification is not implied. Operation beyond V A or V B to GND −0.3 V to V + 0.3 V OUT OUT DD the maximum operating conditions for extended periods may V A or V B to GND −0.3 V to V + 0.3 V REF REF DD affect product reliability. Operating Temperature Range, Industrial −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (T ) 150°C ESD CAUTION JMAX Power Dissipation (T − T )/θ JMAX A JA θ Thermal Impedance 150.4°C/W JA Reflow Soldering Peak Temperature SnPb 240°C Pb-Free 260°C Rev. A | Page 7 of 25

AD5025/AD5045/AD5065 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS LDAC 1 14 SCLK SYNC 2 13 DIN AD5025/ VDD 3 AD5045/ 12 PDL VREFA 4 AD5065 11 GND VOUTA 5 (NToOt Pto V SIEcaWle) 10 VOUTB POR 6 9 VREFB SDO 7 8 CLR 06844-005 Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can be tied permanently low in standalone mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low. The LDAC pin should be used in asynchronous LDAC update mode, as shown in Figure 3, and the LDAC pin must be brought high after pulsing. This allows all DAC outputs to simultaneously update. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 V Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled DD with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 4 V A DAC A Reference Input. This is the reference voltage input pin for DAC A. REF 5 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 6 POR Power-On Reset Pin. Tying this pin to GND powers up the part to 0 V. Tying this pin to V powers up DD the part to midscale. 7 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 8 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 9 V B DAC B Reference Input. This is the reference voltage input pin for DAC B. REF 10 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 11 GND Ground Reference Point for All Circuitry on the Part. 12 PDL The PDL pin is used to ensure hardware shutdown lockout of the device under any circumstance. A Logic 1 at the PLO pin causes the device to behave as normal. The user may successfully enter software power-down over the serial interface while Logic 1 is applied to the PDL pin. If a Logic 0 is applied to this pin, it ensures that the device cannot enter software power-down under any circumstances. If the device had previously been placed in software power-down mode, a high-to- low transition at the PDL pin causes the DAC(s) to exit power-down and output a voltage corresponding to the previous code in the DAC register before the device entered software power-down. 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. 14 SCLK Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. A | Page 8 of 25

Data Sheet AD5025/AD5045/AD5065 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 INL (LSB) –00..220 DNL (LSB) –00..220 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.0512 16,640 DA3C2 ,C76O8DE 48,896 65,024 06844-019 –1.0512 16,640 DA3C2 ,C76O8DE 48,896 65,024 06844-022 Figure 6. AD5065 INL Figure 9. AD5065 DNL 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 B) 0.2 B) 0.2 S S L (L 0 L (L 0 N N I –0.2 D –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 –1.00 512 1024 1536DAC20 C4O8DE2560 3072 3584 4096 06844-020 –1.00 4096 DAC81 C9O2DE 12,288 16,384 06844-023 Figure 7. AD5045 INL Figure 10. AD5045 DNL 1.0 1.00 0.8 0.75 0.6 0.50 0.4 0.25 B) 0.2 B) NL (LS 0 NL (LS 0 I –0.2 D –0.25 –0.4 –0.50 –0.6 –0.75 –0.8 –1.00 512 1024 1536DAC20 C4O8DE2560 3072 3584 4096 06844-021 –1.000 4096 DAC81 C9O2DE 12,288 16,384 06844-024 Figure 8. AD5025 INL Figure 11. AD5025 DNL Rev. A | Page 9 of 25

AD5025/AD5045/AD5065 Data Sheet 0.20 1.2 TA = 25°C 1.0 0.15 0.8 0.10 0.6 0.05 V) 0.4 mV) R (m 0.2 MAX TUE ERROR @ VDD = 5.5V E ( 0 RO 0 TU –0.05 E ER –0.2 MIN TUE ERROR @ VDD = 5.5V U T –0.4 –0.10 –0.6 –0.15 –0.8 –1.0 –0.20512 16,640 DA3C2 ,C76O8DE 48,896 65,024 06844-025 –1.22.0 2.5 3.R0EFERE3.N5CE VO4L.T0AGE (V4).5 5.0 5.5 06844-028 Figure 12. Total Unadjusted Error (TUE) vs. DAC Code Figure 15. Total Unadjusted Error (TUE) vs. Reference Input Voltage 1.6 0.015 1.4 TA = 25°C 1.2 0.010 1.0 DAC A 0.8 R (LSB) 000...246 MAX INL ERROR @ VDD = 5.5V R (%FSR) 0.005 RRO –0.20 RRO 0 DAC B NL E –0.4 MIN INL ERROR @ VDD = 5.5V AIN E–0.005 I –0.6 G –0.8 –1.0 –0.010 –1.2 –1.4 VVDREDF= = 5 4.5.0V96V –1.62.0 2.5 3.R0EFERE3.N5CE VO4L.T0AGE (V4).5 5.0 5.5 06844-026 –0.015–60 –40 –20 0 TE2M0PERA40TURE6 0(°C) 80 100 120 140 06844-029 Figure 13. INL vs. Reference Input Voltage Figure 16. Gain Error vs. Temperature 1.6 0.6 1.4 TA = 25°C 0.5 VVDREDF= = 5 4.5.0V96V 1.2 1.0 0.4 0.8 SB) 00..46 R (mV) 00..32 DNL ERROR (L –––0000....64202 MMINA XD NDLN LE RERROROR R@ @ V DVDD D= =5 .55.V5V OFFSET ERRO –00..011 DAC B DAC A –0.8 –0.2 –1.0 –1.2 –0.3 –1.4 –1.62.0 2.5 3.R0EFERE3.N5CE VO4L.T0AGE (V4).5 5.0 5.5 06844-027 –0.4–60 –40 –20 0 TE2M0PERA40TURE6 0(ºC) 80 100 120 140 06844-030 Figure 14. DNL vs. Reference Input Voltage Figure 17. Offset Error vs. Temperature Rev. A | Page 10 of 25

Data Sheet AD5025/AD5045/AD5065 0.2 5.0 4.5 4.0 0.1 V) 3.5 %FSR) GAIN ERROR LTAGE ( 3.0 VTAD D= =2 55ºVC, VREF = 4.096V ERROR ( 0 FULL-SCALE ERROR TPUT VO 22..05 13OA//NU44 DTSS PCC2U0AA0TLLp EELFOTTTAOOOD 31EG//44DN SSDWCCIAATLLHEE 5kΩ U O 1.5 –0.1 1.0 0.5 –0.24.50 4.75 VD5D.0 0(V) 5.25 5.50 06844-031 00 2 4 6TIME (µs)8 10 12 14 06844-038 Figure 18. Gain Error and Full-Scale Error vs. Supply Voltage Figure 21. Settling Time and Typical Output Slew Rate 0.12 POR 0.09 V) m R ( O R ER 0.06 1 T E S F F O VOUT 0.03 3 04.50 4.75 VD5D.0 0(V) 5.25 5.50 06844-032 CH1 2V CH3 2V MT 2 m20s.4% A CH1 2.52V 06844-039 Figure 19. Offset Error Voltage vs. Supply Voltage Figure 22. Power-On Reset to 0 V 16 14 12 10 S T 1 HI 8 6 4 3 2 00 1.0 1.I1DD POWE1.R2 UP (mA1).3 1.4 1.5 06844-064 CH1 2V CH3 2V MT 2 m20s.4% A CH1 2.52V 06844-040 Figure 20. IDD Histogram, VDD = 5.0 V Figure 23. Power-On Reset to Midscale Rev. A | Page 11 of 25

AD5025/AD5045/AD5065 Data Sheet 7 CH1 = SCLK VDD = 5V, VREF = 4.096V 6 TA = 25°C 5 1 V) 4 m E ( 3 D U T 2 LI P CH2 = VOUT VDD = 5V AM 1 POWER-UP TO MIDSCALE CH 0 T 2 GLI –1 –2 –3 CH1 5V CH2 500mV MT 2 µ55s% A CH2 1.2V 06844-041 –40 2.5 TIM5E.0 (μs) 7.5 10.0 06844-044 Figure 24. Exiting Power-Down to Midscale Figure 27. DAC-to-DAC Crosstalk 6 VDD = 5V, VREF= 4.096V 5 TA = 25ºC DAC LOADED WITH MIDSCALE 4 V) m E ( 3 D U T 2 V LI DI AMP 1 1μV/ H TC 0 LI G –1 –2 –30 2.5 TIM5E.0 (μs) 7.5 10.0 06844-042 4s/DIV 06844-045 Figure 25. Digital-to-Analog Glitch Impulse Figure 28. 0.1 Hz to 10 Hz Output Noise Plot 7 0 6 TVAD D= =2 55ºVC, VREF = 4.096V –10 TVADD= =2 55ºVC, DAC LOADED WITH MIDSCALE 5 –20 VREF = 3.0V ± 200mV p-p V) 4 m –30 LITUDE ( 32 EL (dB) –40 P V –50 M 1 E CH A 0 LOUT –60 T V GLI –1 –70 –2 –80 –3 –90 –40 2.5 TIM5E.0 (μs) 7.5 10.0 06844-043 –1005 10 20 FREQUE3N0CY (kHz) 40 50 55 06844-046 Figure 26. Analog Crosstalk Figure 29. Total Harmonic Distortion Rev. A | Page 12 of 25

Data Sheet AD5025/AD5045/AD5065 24 0.0010 VDD = 5V, VREF = 3.0V CODE = MIDSCALE 22 TA = 25°C 0.0008 VDD = 5V, VREF = 4.096V 20 0.0006 μs) 18 0.0004 TIME ( 16 GE (V) 0.0002 G 14 A SETTLIN 1120 ∆VOLT–0.00020 VDD = 5.5V –0.0004 8 6 –0.0006 4 –0.0008 0 1 2 3 CA4PACIT5ANCE 6(nF) 7 8 9 10 06844-047 –25 –20 –15 –10 –5CURR0ENT 5(mA)10 15 20 25 30 06844-051 Figure 30. Settling Time vs. Capacitive Load Figure 33. Typical Output Load Regulation 0.10 CODE = MIDSCALE 0.08 VDD = 5V, VREF = 4.096V CLR 0.06 1 0.04 V) 0.02 (UT 0 O 2 VOUT ∆V –0.02 –0.04 –0.06 –0.08 CH1 5V CH2 2V MT21µ1s% A CH1 2.5V 06844-048 –0.10–25 –20 –15 –10 –5 IO0UT (m5A) 10 15 20 25 30 06844-052 Figure 31. Hardware CLR Figure 34. Typical Current Limiting Plot 10 0 VOUT CH1 295mV p-p –10 B) d ON ( –20 TI A U N –30 E T T A –40 CH A CH B –50 CH C CH D SCLK 3dB POINT –6010 100FREQUENCY (kHz1)000 10000 06844-049 CH1 50mV CH2 5V MT48µ.s6% A CH2 1.2V 06844-053 Figure 32. Multiplying Bandwidth Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, No Load Rev. A | Page 13 of 25

AD5025/AD5045/AD5065 Data Sheet VOUT CH1 200mV p-p CH1 170mV p-p VOUT SCLK SCLK CH1 50mV CH2 5V MT48µ.s6% A CH2 1.2V 06844-054 CH1 20mV CH2 5V MT48µ.s6% A CH2 1.2V 06844-056 Figure 36. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Figure 38. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, 5 kΩ/200 pF Load 5 kΩ/200 pF Load CH1 129mV p-p 1 VOUT PDL VOUT 2 CH1 20mV CH2 5V SCLK MT48µ.s6% A CH2 1.2V 06844-055 CH1 5.00V CH2 1V M1µs A CH1 2.5V 06844-068 Figure 37. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Figure 39. PDL Activation Time Load Rev. A | Page 14 of 25

Data Sheet AD5025/AD5045/AD5065 TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse For the DAC, relative accuracy, or integral nonlinearity (INL), is Digital-to-analog glitch impulse is the impulse injected into the a measure of the maximum deviation in LSBs from a straight analog output when the input code in the DAC register changes line passing through the endpoints of the DAC transfer state. It is normally specified as the area of the glitch in nanovolt- function. Figure 6, Figure 7, and Figure 8 show plots of typical seconds and is measured when the digital input code is changed INL vs. code. by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 25. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the DC Power Supply Rejection Ratio (PSRR) measured change and the ideal 1 LSB change between any two PSRR indicates how the output of the DAC is affected by changes adjacent codes. A specified differential nonlinearity of ±1 LSB in the supply voltage. PSRR is the ratio of the change in V to OUT maximum ensures monotonicity. This DAC is guaranteed mono- a change in V for full-scale output of the DAC. It is measured DD tonic by design. Figure 9, Figure 10, and Figure 11 show plots of in decibels. V is held at 2.5 V, and V is varied ±10%. REF DD typical DNL vs. code. Measured with V < V . REF DD Offset Error DC Crosstalk Offset error is a measure of the difference between the actual DC crosstalk is the dc change in the output level of one DAC in V and the ideal V , expressed in millivolts in the linear response to a change in the output of another DAC. It is measured OUT OUT region of the transfer function. Offset error is measured on the with a full-scale output change on one DAC (or soft power-down part with Code 512 (AD5065), Code 128 (AD5045), and Code 32 and power-up) while monitoring another DAC kept at midscale. (AD5025) loaded into the DAC register. It can be negative or It is expressed in microvolts. positive and is expressed in millivolts. DC crosstalk due to load current change is a measure of the Offset Error Drift impact that a change in load current on one DAC has to another Offset error drift is a measure of the change in offset error with DAC kept at midscale. It is expressed in microvolts per milliamp. a change in temperature. It is expressed in microvolts per degree Reference Feedthrough Celsius. Reference feedthrough is the ratio of the amplitude of the signal Gain Error at the DAC output to the reference input when the DAC output Gain error is a measure of the span error of the DAC. It is the is not being updated (that is, LDAC is high). It is expressed in deviation in slope of the DAC transfer characteristic from the decibels. ideal, expressed as a percentage of the full-scale range. Digital Feedthrough Gain Temperature Coefficient Digital feedthrough is a measure of the impulse injected into Gain error drift is a measure of the change in gain error with the analog output of a DAC from the digital input pins of the changes in temperature. It is expressed in parts per million of device but is measured when the DAC is not being written to full-scale range per degree Celsius. Measured with VREF < VDD. (SYNC held high). It is specified in nanovolt-seconds. It is Full-Scale Error measured with one simultaneous data and clock pulse loaded Full-scale error is a measure of the output error when full-scale to the DAC. code (0xFFFF) is loaded into the DAC register. Ideally, the Digital Crosstalk output should be VDD − 1 LSB. Full-scale error is expressed as a Digital crosstalk is the glitch impulse transferred to the output percentage of the full-scale range. of one DAC at midscale in response to a full-scale code change (all 0s to all 1s or vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nanovolt-seconds. Rev. A | Page 15 of 25

AD5025/AD5045/AD5065 Data Sheet Analog Crosstalk Multiplying Bandwidth Analog crosstalk is the glitch impulse transferred to the output The amplifiers within the DAC have a finite bandwidth. The of one DAC due to a change in the output of another DAC. It is multiplying bandwidth is a measure of this. A sine wave on the measured by loading one of the input registers with a full-scale reference (with full-scale code loaded to the DAC) appears on code change (all 0s to all 1s or vice versa) while keeping LDAC the output. The multiplying bandwidth is the frequency at high, and then pulsing LDAC low and monitoring the output of which the output amplitude falls to 3 dB below the input. the DAC whose digital code has not changed. The area of the Total Harmonic Distortion (THD) glitch is expressed in nanovolt-seconds. Total harmonic distortion is the difference between an ideal DAC-to-DAC Crosstalk sine wave and its attenuated version using the DAC. The sine DAC-to-DAC crosstalk is the glitch impulse transferred to the wave is used as the reference for the DAC, and the THD is a output of one DAC due to a digital code change and subsequent measure of the harmonics present on the DAC output. It is output change of another DAC. This includes both digital and measured in decibels. analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s or vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nanovolt-seconds. Rev. A | Page 16 of 25

Data Sheet AD5025/AD5045/AD5065 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER OUTPUT AMPLIFIER The AD5025/AD5045/AD5065 are single 12-/14-/16-bit, serial The on-chip output buffer amplifier can generate rail-to-rail input, voltage output DACs. The parts operate from supply voltages voltages on its output, which gives an output range of 0 V to of 4.5 V to 5.5 V. Data is written to the AD5025/AD5045/AD5065 V . The amplifier is capable of driving a load of 5 k Ωn i DD in a 32-bit word format via a 3-wire serial interface. The AD5025/ parallel with 200 pF to GND. The slew rate is 1.5 V/µs with a ¼ AD5045/AD5065 incorporate a power-on reset circuit that ensures to ¾ scale settling time of 13 µs. the DAC output powers up to a known output state. The devices SERIAL INTERFACE also have a software power-down mode that reduces the typical The AD5025/AD5045/AD5065 have a 3-wire serial interface current consumption to typically 400 nA. (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and Because the input coding to the DAC is straight binary, the ideal MICROWIRE interface standards as well as most DSPs. See output voltage when using an external reference is given by Figure 3 for a timing diagram of a typical write sequence. V =V × D  INPUT REGISTER OUT REFIN 2N  The AD5025/AD5045/AD5065 input register is 32 bits wide where: (see Figure 41). The first four bits are don’t cares. The next four D is the decimal equivalent of the binary code that is loaded to bits are the command bits, C3 to C0 (see Table 8), followed by the DAC register (0 to 65,535 for the 16-bit AD5065). the 4-bit DAC address bits, A3 to A0 (see Table 7) and finally N is the DAC resolution. the data bits. These data bits comprise the 12-bit, 14-bit, or 16-bit DAC ARCHITECTURE input code, followed by eight, six, or four don’t care bits for the AD5025/AD5045/AD5065, respectively (see Figure 41, Figure 42, The DAC architecture of the AD5025/AD5045/AD5065 consists and Figure 43). These data bits are transferred to the DAC of two matched DAC sections. A simplified circuit diagram is register on the 32nd falling edge of SCLK. shown in Figure 40. The four MSBs of the 16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches Table 7. Address Commands connects one of 15 matched resistors to either GND or a VREF Address (n) Selected DAC buffer output. The remaining 12 bits of the data-word drive A3 A2 A1 A0 Channel Switch S0 to Switch S11 of a 12-bit voltage mode R-2R ladder 0 0 0 0 DAC A network. 0 0 1 1 DAC B VOUT 0 0 0 1 Reserved 2R 2R 2R 2R 2R 2R 2R 0 0 1 0 Reserved S0 S1 S11 E1 E2 E15 1 1 1 1 Both DACs VREF Table 8. Command Definitions Command 12-BIT R-2R LADDER FOU15R EMQSUBAsL D SEECGOMDEENDT ISNTO 06844-006 C3 C2 C1 C0 Description Figure 40. DAC Ladder Structure 0 0 0 0 Write to Input Register n1 0 0 0 1 Update DAC Register n1 REFERENCE BUFFER 0 0 1 0 Write to Input Register n, update all The AD5025/AD5045/AD5065 operate with an external reference. (software LDAC) Each DAC has a dedicated voltage reference pin and an on-chip 0 0 1 1 Write to and update DAC Channel n1 reference buffer. The reference input pin has an input range of 0 1 0 0 Power down/power up DAC 2.5 V to VDD. This input voltage is then used to provide a 0 1 0 1 Load clear code register buffered reference for the DAC core. 0 1 1 0 Load LDAC register 0 1 1 1 Reset (power-on reset) 1 0 0 0 Set up DCEN register (daisy-chain enable) 1 0 0 1 Reserved 1 1 1 1 Reserved 1 See Table 7. Rev. A | Page 17 of 25

AD5025/AD5045/AD5065 Data Sheet DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS 06844-007 Figure 41. AD5065 Input Register Content DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X DATA BITS COMMAND BITS ADDRESS BITS 06844-008 Figure 42. AD5045 Input Register Content DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X DATA BITS COMMAND BITS ADDRESS BITS 06844-009 Figure 43. AD5025 Input Register Content Rev. A | Page 18 of 25

Data Sheet AD5025/AD5045/AD5065 STANDALONE MODE mode is enabled by setting a bit (DB1) in the DCEN register. The default setting is standalone mode, where DB1 = 0. The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 32-bit shift register on the Table 9 shows how the state of the bit corresponds to the mode falling edge of SCLK. The serial clock frequency can be as high of operation of the device. as 50 MHz, making the AD5025/AD5045/AD5065 compatible Table 9. DCEN (Daisy-Chain Enable) Register with high speed DSPs. On the 32nd falling clock edge, the last DB1 DB0 Description data bit is clocked in and the programmed function is executed, 0 X Standalone mode (default) that is, a change in DAC register contents and/or a change in 1 X DCEN mode the mode of operation. The SYNC line must be brought high within 30 ns of the 32nd falling edge of SCLK. In either case, it The SCLK is continuously applied to the input register when must be brought high for a minimum of 1.9 µs before the next SYNC is low. If more than 32 clock pulses are applied, the data write sequence so that a falling edge of SYNC can initiate the next ripples out of the input shift register and appears on the SDO write sequence. Because the SYNC buffer draws more current line. This data is clocked out on the rising edge of SCLK and is when V = V than it does when V = 0 V, SYNC should be valid on the falling edge. By connecting this line to the DIN IN DD IN idled low between write sequences for even lower power input on the next DAC in the chain, a multiDAC interface is operation of the part. As mentioned previously, however, SYNC constructed. Each DAC in the system requires 32 clock pulses; therefore, the total number of clock cycles must equal 32N, must be brought high again just before the next write sequence. where N is the total number of devices in the chain. SYNC INTERRUPT If SYNC is taken high before 32N clocks are clocked into the In a normal write sequence, the SYNC line is kept low for at part, it is considered an invalid frame and the data is discarded. least 32 falling edges of SCLK, and the DAC is updated on the When the serial transfer to all devices is complete, SYNC is 32nd falling edge. However, if SYNC is brought high before the taken high. This prevents any further data from being clocked 32nd falling edge, this acts as an interrupt to the write sequence. into the input register. The input register is reset, and the write sequence is seen as invalid. The serial clock can be continuous or a gated clock. A continuous Neither an update of the DAC register contents nor a change in SCLK source can be used only if SYNC can be held low for the the operating mode occurs (see Figure 44). correct number of clock cycles. In gated clock mode, a burst DAISY-CHAINING clock containing the exact number of clock cycles must be used, For systems that contain several DACs, or where the user wishes to and SYNC must be taken high after the final clock to latch the data. read back the DAC contents for diagnostic purposes, the SDO In daisy-chain mode, the LDAC pin cannot be tied permanently pin can be used to daisy-chain several devices together and low. The LDAC pin must be used in asynchronous LDAC update provide serial readback. mode, as shown in Figure 3. The LDAC pin must be brought The daisy-chain mode is enabled through a software executable high after pulsing. This allows all DAC outputs to simultaneously daisy-chain enable (DCEN) command. Command 1000 is update. reserved for this DCEN function (see Table 8). The daisy-chain SCLK SYNC DIN DB31 DB0 DB31 DB0 SYNC HINIGVHA LBIEDF WORRIET E32 SNEDQ FUAELNLCINEG: EDGE VALID WORNIT TEH SEE 3Q2UNEDN FCAEL,L OINUGT PEUDTG UEPDATES 06844-010 Figure 44. SYNC Interrupt Facility Table 10. 32-Bit Input Register Contents for Daisy-Chain Enable MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0 X 1 0 0 0 X X X X X 1/0 X Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares DCEN register Rev. A | Page 19 of 25

AD5025/AD5045/AD5065 Data Sheet POWER-ON RESET AND SOFTWARE RESET current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. The AD5025/AD5045/AD5065 contain a power-on reset (POR) This has the advantage that the output impedance of the part is circuit that controls the output voltage during power-up. By known while the part is in power-down mode. There are three connecting the POR pin low, the AD5025/AD5045/AD5065 different options. The output is connected internally to GND output powers up to zero scale. Note that this is outside the through either a 1 kΩ or a 100 kΩ resistor, or it is left open- linear region of the DAC; by connecting the POR pin high, the circuited (three-state). The output stage is illustrated in Figure 45. AD5025/AD5045/AD5065 output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications DAC AMPLIFIER VOUT where it is important to know the state of the output of the DAC while it is in the process of powering up. There is also a software executable reset function that resets the DAC to the power-on reset code selected by the POR pin. Command 0111 is reserved POWER-DOWN CIRCUITRY RESISTOR fPoOr tWhisE rRe-sDet OfuWncNtio Mn (OseDe ETSab le 8). NETWORK 06844-011 Figure 45. Output Stage During Power-Down The AD5025/AD5045/AD5065 contain four separate modes The bias generator, output amplifier, resistor string, and other of operation. Command 0100 is reserved for the power-down associated linear circuitry are shut down when the power-down function (see Table 8). These modes are software-programmable mode is activated. However, the contents of the DAC register are by setting two bits, Bit DB9 and Bit DB8, in the input register (see unaffected when in power-down. The time to exit power-down Table 12). Table 11 shows how the state of the bits corresponds is typically 4.5 µs for V = 5 V (see Figure 24). to the mode of operation of the device. DD Either or both DACs (DAC A and DAC B) can be powered down Table 11. Modes of Operation to the selected mode by setting the corresponding bits (DB3 and DB9 DB8 Operating Mode DB0) to 1. See Table 12 for the contents of the input register 0 0 Normal operation, power-down modes during power-down/power-up operation. 0 1 1 kΩ to GND Any combination of DACs can be powered up by setting PD1 = 0 1 0 100 kΩ to GND and PD0 = 0 (normal operation). The output powers up to the 1 1 Three-state value in the input register (LDAC low) or to the value in the When both Bit DB9 and Bit DB8 in the input register are set to 0, DAC register before powering down (LDAC high). the part works normally with its normal power consumption of 2.2 mA at 5 V. However, for the three power-down modes, the supply current falls to 0.4 µV at 5 V. Not only does the supply Table 12. 32-Bit Input Register Contents for Power-Up/Power-Down Function MSB LSB DB31 DB10 DB4 to to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB9 DB8 DB7 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 X DAC DAC DAC DAC A B B A Don’t Command bits (C2 to C0) Address bits (A3 to A0)—don’t Don’t Power-down Don’t Power-down/power-up channel cares cares cares mode cares selection—set bits to 1 to select Rev. A | Page 20 of 25

Data Sheet AD5025/AD5045/AD5065 CLEAR CODE REGISTER LDAC FUNCTION The AD5025/AD5045/AD5065 have a hardware CLR pin that Hardware LDAC Pin is an asynchronous clear input. The CLR input is falling edge sensi- The outputs of all DACs can be updated simultaneously using tive. Bringing the CLR line low clears the contents of the input the hardware LDAC pin. The LDAC pin can be used in register and the DAC registers to the data contained in the user- synchronous or asynchronous mode, as shown in Figure 3. configurable CLR register, and sets the analog outputs accordingly Synchronous LDAC: LDAC is held low. After new data is read, (see Table 13). This function can be used in system calibration the DAC registers are updated on the falling edge of the 32nd to load zero scale, midscale, or full scale to all channels together. SCLK pulse. LDAC can be permanently low or pulsed in These clear code values are user-programmable by setting two standalone mode. LDAC cannot be tied permanently low in bits, Bit DB1 and Bit DB0, in the input register (see Table 13). The default setting clears the outputs to 0 V. Command 0101 is daisy-chain mode. reserved for loading the clear code register (see Table 8). Asynchronous LDAC: LDAC is held high and pulsed. The outputs are not updated at the same time that the input registers are Table 13. Clear Code Register written to. When LDAC goes low, the DAC registers are updated Clear Code Register with the contents of the input register. DB1 (CR1) DB0 (CR0) Clears to Code Software LDAC Function 0 0 0x0000 0 1 0x8000 Alternatively, the outputs of all DACs can be updated simulta- 1 0 0xFFFF neously using the software LDAC function by writing to Input 1 1 No operation Register n (see Table 7) and updating all DAC registers. The part exits clear code mode on the 32nd falling edge of the Command 0010 is reserved for this software LDAC function. next write to the part. If CLR is activated during a write sequence, The LDAC register gives the user extra flexibility and control the write is aborted. over the hardware LDAC pin (see Table 16). Setting the LDAC The CLR pulse activation time, the falling edge of CLR to when bit register (DB0 to DB3) to 0 for a DAC channel means that the output starts to change, is typically 10.6 µs (see Figure 31). this channel update is controlled by the hardware LDAC pin. If DB0 or DB3 is set to 1, this channel updates synchronously. See Table 14 for contents of the input register during the loading clear code register operation. The part effectively sees the hardware LDAC pin as being tied low (see Table 15 for the LDAC register mode of operation). This flexibility is useful in applications where the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. Table 14. 32-Bit Input Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2 to DB19 DB1 DB0 X 0 1 0 1 X X X X X 1/0 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Clear code register (CR1 to CR0) Table 15. LDAC Overwrite Definitions Load DAC Register LDAC Bits (DB3 and DB0) LDAC Pin LDAC Operation 0 1, 0 Determined by LDAC pin. 1 X1 DAC channels update, overrides the LDAC pin. DAC channels see LDAC as 0. 1 X = don’t care. Table 16. 32-Bit Input Register Contents for LDAC Overwrite Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB4 to DB19 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC B X X DAC A Don’t cares Command bits (C3 to C0) Address bits (A3 to A0)—don’t cares Don’t cares Set LDAC bits to 1 to override LDAC pin Rev. A | Page 21 of 25

AD5025/AD5045/AD5065 Data Sheet POWER-DOWN LOCKOUT The user is recommended to hardwire the pin to a logic high or low, thereby either enabling or disabling the feature. The AD5025/AD5045/AD5065 contain a digital input pin, PDL. When activated, the power-down lockout pin (PDL) disables POWER SUPPLY BYPASSING AND GROUNDING software shutdown under any circumstances. The user should When accuracy is important in a circuit, it is helpful to carefully hardwire the PDL pin to a logic low (thus preventing subsequent consider the power supply and ground return layout on the board. software power-down) or logic high (the part can be placed in The printed circuit board (PCB) containing the AD5025/AD5045/ power-down mode over the serial interface). If the user transitions AD5065 should have separate analog and digital sections. If the the PDL pin from logic high to a logic low during a valid write AD5025/AD5045/AD5065 are in a system where other devices sequence, the device responds immediately and the current require an AGND-to-DGND connection, the connection should write sequence is aborted. Note the following PDL features. be made at one point only. This ground point should be as close as possible to the AD5025/AD5045/AD5065. PDL During a Write Sequence Bypass the power supply to the AD5025/AD5045/AD5065 with If a PDL is generated (that is, a high-to-low transition) while a 10 µF and 0.1 µF capacitors. The capacitors should physically be valid write sequence is ongoing, the write is aborted. The user as close as possible to the device, with the 0.1 µF capacitor must rewrite the current write command again. ideally right up against the device. The 10 µF capacitors are the PDL While DACs in Power-Down Mode tantalum bead type. It is important that the 0.1 µF capacitor has low effective series resistance (ESR) and low effective series If a PDL is generated while the DAC(s) are in power-down inductance (ESI), which is typical of common ceramic types of mode, the DAC(s) come out of power-down (that is, all power- capacitors. This 0.1 µF capacitor provides a low impedance path down bits are reset to 0000) to the last voltage output correspond- to ground for high frequencies caused by transient currents due ing to the last valid stored DAC value. While PDL remains active, to internal logic switching. software power-down is disabled. The power supply line should have as large a trace as possible to PDL Low to High Transition provide a low impedance path and reduce glitch effects on the After PDL is taken from a low to a high state, all DAC channels supply line. Shield clocks and other fast switching digital signals remain in normal mode, and the user must reissue a software from other parts of the board by digital ground. Avoid crossover power-down command to the control register to power down of digital and analog signals if possible. When traces cross on the required channels. opposite sides of the board, ensure that they run at right angles Transitioning PDL from a low to a high disables the feature to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique, immediately. where the component side of the board is dedicated to the If PDL and CLR are generated at the same time, the CLR signal ground plane only and the signal traces are placed on the solder causes the DAC register to change as per the clear code register, side. However, this is not always possible with a 2-layer board. and the DACs come out of power-down. If PDL, CLR, and LDAC are generated at the same time, CLR has higher precedence over LDAC and PDL. Rev. A | Page 22 of 25

Data Sheet AD5025/AD5045/AD5065 MICROPROCESSOR INTERFACING AD5025/AD5045/AD5065 to 80C51/80L51 Interface AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Figure 48 shows a serial interface between the AD5025/AD5045/ Interface AD5065 and the 80C51/80L51 microcontroller. The setup for Figure 46 shows a serial interface between the AD5025/AD5045/ the interface is as follows: TxD of the 80C51/80L51 drives SCLK AD5065 and the Blackfin® ADSP-BF53x microprocessor. The of the AD5025/AD5045/AD5065, and RxD drives the serial ADSP-BF53x processor family incorporates two dual-channel data line of the part. The SYNC signal is again derived from a synchronous serial ports, SPORT1 and SPORT0, for serial and bit-programmable pin on the port. In this case, Port Line P3.3 is multiprocessor communications. Using SPORT0 to connect to used. When data is to be transmitted to the AD5025/AD5045/ the AD5025/AD5045/AD5065, the setup for the interface is AD5065, P3.3 is taken low. The 80C51/80L51 transmits data in as follows: DT0PRI drives the DIN pin of the AD5025/AD5045/ 8-bit bytes only; thus, only eight falling clock edges occur in the AD5065, and TSCLK0 drives the SCLK of the parts. The SYNC is transmit cycle. To load data to the DAC, P3.3 is lept low after driven from TFS0. the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high ADSP-BF53x* AD5025/ following the completion of this cycle. The 80C51/80L51 outputs AD5045/ AD5065* the serial data in LSB-first format. The AD5025/AD5045/AD5065 TFS0 SYNC must receive data with the MSB first. The 80C51/80L51 transmit routine should take this into account. DT0PRI DIN 80C51/80L51* AD5025/ *ADDITIONATSLC PLINKS0 OMITTED SFCOLRK CLARITY. 06844-012 AADD55006455*/ Figure 46. AD5025/AD5045/AD5065 to Blackfin ADSP-BF53x Interface P3.3 SYNC AD5025/AD5045/AD5065 to 68HC11/68L11 Interface TxD SCLK FAiDgu5r0e6 457 asnhdo wths ea 6s8erHiaCl i1n1t/e6r8faLc1e1 b emtwicereonc othnet rAoDlle5r0. 2S5C/AKD o5f 0th45e / *ADDITIONAL PRINxDS OMITTED FOR CLDAIRNITY. 06844-014 68HC11/68L11 drives the SCLK of the AD5025/AD5045/AD5065, Figure 48. AD5025/AD5045/AD5065 to 80C51/80L51 Interface and the MOSI output drives the serial data line of the DAC. AD5025/AD5045/AD5065 to MICROWIRE Interface 68HC11/68L11* AD5025/ Figure 49 shows an interface between the AD5025/AD5045/ AD5045/ AD5065* AD5065 and any MICROWIRE-compatible device. Serial data is PC7 SYNC shifted out on the falling edge of the serial clock and is clocked into the AD5025/AD5045/AD5065 on the rising edge of SCLK. SCK SCLK *ADDITIONAL MPOINSSI OMITTED DFIONR CLARITY. 06844-013 MICROWIRE* AAADDD555000624555*// Figure 47. AD5025/AD5045/AD5065 to 68HC11/68L11 Interface CS SYNC The SYNC signal is derived from a port line (PC7). The setup SK DIN cTohned 6it8iHonCs1 f1o/r6 c8oLr1r1e cits ocpoenrfaigtiuorne do fw tihthis iitnst CerPfaOcLe abriet aass 0fo, lalnowd sit: s *ADDITIONAL PISNOS OMITTED FOR CLSACRLITKY. 06844-015 CPHA bit as 1. When data is being transmitted to the DAC, the Figure 49. AD5025/AD5045/AD5065 to MICROWIRE Interface SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5025/AD5045/ AD5065, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. A | Page 23 of 25

AD5025/AD5045/AD5065 Data Sheet APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY FOR This is an output voltage range of ±5 V, with 0x0000 corre- THE AD5025/AD5045/AD5065 sponding to a −5 V output, and 0xFFFF corresponding to a +5 V output. Because the supply current required by the AD5025/AD5045/ R2 = 10kΩ AD5065 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see Figure 50). +5V +5V R1 = 10kΩ This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or AD820/ ±5V OP295 3 V, for example, 15 V. The voltage reference outputs a steady VDD VOUT supply voltage for the AD5025/AD5045/AD5065. If the low 10µF 0.1µF AD5025/ dropout REF195 is used, it must supply 500 µA of current to AD5045/ –5V AD5065 the AD5025/AD5045/AD5065 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also needs t(ow istuhp ap l5y kthΩe lcouardr eonnt tthoe t hDeA lCoa odu. tTphuet )t oist al current required SERIAL3- IWNITREERFACE 06844-017 Figure 51. Bipolar Operation with the AD5025/AD5045/AD5065 500 µA + (5 V/5 kΩ) = 1.5 mA USING THE AD5025/AD5045/AD5065 WITH A The load regulation of the REF195 is typically 2 ppm/mA, GALVANICALLY ISOLATED INTERFACE which results in a 3 ppm (15 µV) error for the 1.5 mA current drawn from it. This corresponds to a 0.196 LSB error. In process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect 15V and isolate the controlling circuitry from any hazardous common- 5V REF195 mode voltages that can occur in the area where the DAC is functioning. iCoupler® provides isolation in excess of 2.5 kV. The AD5025/AD5045/AD5065 use a 3-wire serial logic interface, VDD SYNC so the ADuM1300 three-channel digital isolator provides the S3E-WRIIRAEL SCLK AADD55002455// VOUTx = 0V TO 5V required isolation (see Figure 52). The power supply to the part INTERFACE DIN AD5065 also needs to be isolated, which is achieved by using a transformer. 06844-016 O5 Vn tshuep DpAlyC r esqiduei roefd t hfoer t rtahnes AfoDrm50er2, 5a/ 5A VD 5r0eg4u5l/aAtoDr5 p0r6o5v.i des the Figure 50. REF195 as Power Supply to the AD5025/AD5045/AD5065 5V BIPOLAR OPERATION USING THE REGULATOR AD5025/AD5045/AD5065 POWER 10µF 0.1µF The AD5025/AD5045/AD5065 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 51. The circuit gives an output voltage range of VDD ±5 V. Rail-to-rail operation at the amplifier output is achievable SCLK VIA VOA SCLK AD5025/ using an AD820 or an OP295 as the output amplifier. ADuM1300 AD5045/ AD5065 The output voltage for any input code can be calculated as SDI VIB VOB SYNC VOUTx follows:   D  R1+R2 R2 V =V × × −V ×  DATA VIC VOC DIN O  DD 65,536  R1  DD R1 GND where D represents the input code in decimal (0 to 65,535). 06844-018 With V = 5 V, R1 = R2 = 10 kΩ, Figure 52. AD5025/AD5045/AD5065 with a Galvanically Isolated Interface DD 10×D V =  −5V O 65,536 Rev. A | Page 24 of 25

Data Sheet AD5025/AD5045/AD5065 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 4.30 BSC 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.A20X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 53. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Package Model1 Temperature Range Package Description Option Accuracy Resolution AD5025BRUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±0.25 LSB INL 12 bits AD5025BRUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.25 LSB INL 12 bits AD5045BRUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±0.5 LSB INL 14 bits AD5045BRUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±0.5 LSB INL 14 bits AD5065ARUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±4 LSB INL 16 bits AD5065ARUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±4 LSB INL 16 bits AD5065BRUZ −40°C to +125°C 14-Lead TSSOP RU-14 ±1 LSB INL 16 bits AD5065BRUZ-REEL7 −40°C to +125°C 14-Lead TSSOP RU-14 ±1 LSB INL 16 bits 1 Z = RoHS Compliant Part. ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06844-0-8/16(A) Rev. A | Page 25 of 25