Fully Accurate, 12-/14-/16-Bit V nanoDAC, Quad, OUT SPI Interface, 4.5 V to 5.5 V in TSSOP Data Sheet AD5024/AD5044/AD5064 FEATURES FUNCTIONAL BLOCK DIAGRAMS Low power quad 12-/14-/16-bit DAC, ±1 LSB INL VDD VREFIN AD5064-1 Pin compatible and performance upgrade to AD5666 Individual and common voltage reference pin options LDAC REINGPISUTTER REGDIASCTER DAC A BUFFER VOUTA SCLK Rail-to-rail operation INTERFACE REINGPISUTTER REGDIASCTER DAC B BUFFER VOUTB 4.5 V to 5.5 V power supply SYNC LOGIC AND Power-on reset to zero scale or midscale DIN RESGHISIFTTER REINGPISUTTER REGDIASCTER DAC C BUFFER VOUTC 3 power-down functions and per-channel power-down REINGPISUTTER REGDIASCTER DAC D BUFFER VOUTD SDO HCLaRrd fwunacreti oLDn AtoC pwriotghr saomftmwaabrele L cDoAdCe override function LDACCLR PORWPEEOSRRE-TON POWLEGORNG-DDICOWN 06803-064 SDO daisy-chaining option Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666 14-/16-lead TSSOP VDD VREFAVREFB Internal reference buffer and internal output amplifier AD5024/ AD5044/ APPLICATIONS AD5064 LDAC REINGPISUTTER REGDIASCTER DAC A BUFFER VOUTA SCLK PDraotcae ascsq cuoinstitriooln systems SYNC ILNROTEGSEGHIRCISIFF TAATENCRDE RREEIINNGGPPIISSUUTTTTEERR RREEGGDDIIAASSCCTTEERR DDAACC BC BBUUFFFFEERR VVOOUUTTBC Portable battery-powered instruments DIN REINGPISUTTER REGDIASCTER DAC D BUFFER VOUTD Digital gain and offset adjustment PPrrooggrraammmmaabbllee vaottletanguea taonrds current sources LDACCLR PORWPEEOSRRE-TON VREFCVREFD POWLEGORNG-DDICOWN 06803-001 Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD5024/AD5044/AD5064/AD5064-1 are low power, quad 1. Quad channel available in 14-/16-lead TSSOPs. 12-/14-/16-bit buffered voltage output nanoDAC® converters 2. 16-bit accurate, 1 LSB INL. that offer relative accuracy specifications of 1 LSB INL and 1 LSB 3. High speed serial interface with clock speeds up to 50 MHz. DNL with the AD5024/AD5044/AD5064 individual reference 4. Reset to known output voltage (zero scale or midscale). pin and the AD5064-1 common reference pin options. The Table 1. Related Devices AD5024/AD5044/AD5064/AD5064-1 can operate from a single Device No. Description 4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1 also offer a differential accuracy specification of ±1 LSB. The AD5666 Quad,16-bit buffered DAC, 16 LSB INL, TSSOP devices use a versatile 3-wire, low power Schmitt trigger serial AD5025/AD5045/AD5065 Dual, 16-bit buffered DACs, interface that operates at clock rates up to 50 MHz and is compati- 1 LSB INL, TSSOP ble with standard SPI, QSPI™, MICROWIRE, and DSP interface AD5062, AD5063 16-bit nanoDAC, 1 LSB INL, SOT-23, standards. Integrated reference buffers and output amplifiers are MSOP also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1 AD5061 16-bit nanoDAC, 4 LSB INL, SOT-23 incorporate a power-on reset circuit that ensures the DAC AD5040/AD5060 14-/16-bit nanoDAC, 1 LSB INL, output powers up to zero scale or midscale and remains there SOT-23 until a valid write takes place to the device. The AD5024/AD5044/ AD5064/AD5064-1 contain a power-down feature that reduces the current consumption of the device to typically 400 nA at 5 V and provides software selectable output loads while in power- down mode. Total unadjusted error for the devices is <2 mV. Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD5024/AD5044/AD5064 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Output Amplifier ........................................................................ 19  Applications ....................................................................................... 1  Serial Interface ............................................................................ 19  Functional Block Diagrams ............................................................. 1  Shift Register ............................................................................... 19  General Description ......................................................................... 1  Modes of Operation ................................................................... 21  Product Highlights ........................................................................... 1  Power-On Reset .......................................................................... 22  Revision History ............................................................................... 2  Power-Down Modes .................................................................. 22  Specifications ..................................................................................... 3  Clear Code Register ................................................................... 23  AC Characteristics ........................................................................ 4  LDAC Function .......................................................................... 23  Timing Characteristics ................................................................ 5  Power Supply Bypassing and Grounding ................................ 24  Absolute Maximum Ratings ............................................................ 7  Microprocessor Interfacing ....................................................... 25  ESD Caution .................................................................................. 7  Applications Information .............................................................. 26  Pin Configurations and Function Descriptions ........................... 8  Using a Reference as a Power Supply ....................................... 26  Typical Performance Characteristics ........................................... 10  Bipolar Operation....................................................................... 26  Terminology .................................................................................... 17  Using the AD5024/AD5044/AD5064/AD5064-1 with a Theory of Operation ...................................................................... 19  Galvanically Isolated Interface ................................................. 26  Digital-to-Analog Converter .................................................... 19  Outline Dimensions ....................................................................... 27  DAC Architecture ....................................................................... 19  Ordering Guide .......................................................................... 28  Reference Buffer ......................................................................... 19  REVISION HISTORY 6/2016—Rev. F to Rev. G Changes to Timing Characteristics Section and Table 4 .............. 5 Changed ADSP-BF53x to ADSP-BF527 ..................... Throughout Added Circuit and Timing Diagrams Section and Figure 3 ........ 5 Changes to Power-On Reset Section ............................................ 22 Added Figure 5 ................................................................................... 6 Changes to Figure 4 ........................................................................... 6 6/2013—Rev. E to Rev. F Added Figure 6 ................................................................................... 8 Change to Standalone Mode Section ........................................... 21 Added Table 6; Renumbered Sequentially ..................................... 8 Changed Input Shift Register to Shift Register Throughout ....... 8 5/2011—Rev. D to Rev. E Changes to Table 7 ............................................................................. 9 Changes to Table 4 ............................................................................ 5 Changes to Typical Performance Characteristics Section ........ 10 Changes to Figure 4 and Figure 5 ................................................... 6 Changes to Terminology Section ................................................. 17 Changes to Digital-to-Analog Converter Section, Reference 8/20—Rev. C to Rev. D Buffer Section, Output Amplifier Section, Serial Interface Change to Minimum SYNC High Time (Single Channel Section, Shift Register Section, and Table 8 ................................ 19 Update) Parameter, Table 4 ............................................................. 5 Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20 Added Modes of Operation Section, Daisy-Chaining Section, 5/2010—Rev. B to Rev. C Table 10, and Table 11 .................................................................... 21 Changes to Power-On Reset Section ............................................ 22 Changes to Table 13 and Power-Down Mode Section .............. 22 Changes to Table 16 ....................................................................... 24 6/2009—Rev. A to Rev. B Changes to Figure 52 to Figure 55 ................................................ 25 Changes to Figure 1 .......................................................................... 1 Changes to Bipolar Operation Section and Figure 56 to Figure 58 .......................................................................................... 26 3/2009—Rev. 0 to Rev. A Added Figure 59 ............................................................................. 27 Added 14-Lead TSSOP ...................................................... Universal Updated Outline Dimensions ....................................................... 27 Added Figure 1; Renumbered Sequentially .................................. 1 Changes to Ordering Guide .......................................................... 28 Changes to Features Section, General Description Section, Product Highlights Section, Figure 2, and Table 1 ....................... 1 8/2008—Revision 0: Initial Version Changes to Table 2 ............................................................................ 3 Rev. G | Page 2 of 28

Data Sheet AD5024/AD5044/AD5064 SPECIFICATIONS V = 4.5 V to 5.5 V, R = 5 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V , unless otherwise specified. All specifications T to DD L L REFIN DD MIN T , unless otherwise noted. MAX Table 2. B Grade1 A Grade1, 2 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE3 Resolution 16 16 Bits AD5064/AD5064-1 14 Bits AD5044 12 Bits AD5024 Relative Accuracy (INL)4 ±0.5 ±1 ±0.5 ±4 LSB AD5064/AD5064-1; T = −40°C to +105°C A ±0.5 ±2 ±0.5 ±4 LSB AD5064/AD5064-1; T = −40°C to +125°C A ±0.25 ±1 LSB AD5044 ±0.12 ±0.5 LSB AD5024 Differential Nonlinearity (DNL)4 ±0.2 ±1 ±0.2 ±1 LSB Total Unadjusted Error ±2 ±2 mV V = 2.5 V, V = 5.5 V REF DD Offset Error4, 5 ±0.2 ±1.8 ±0.2 ±1.8 mV Offset Error Temperature ±2 ±2 μV/°C Coefficient4, 6 Full-Scale Error4 ±0.01 ±0.07 ±0.01 ±0.07 % FSR All 1s loaded to DAC register, V < V REF DD Gain Error4 ±0.005 ±0.05 ±0.005 ±0.05 % FSR V < V REF DD Gain Temperature Coefficient4, 6 ±1 ±1 ppm FSR/°C DC Crosstalk4, 6 40 40 μV Due to single-channel, full-scale output change, R = 5 kΩ to GND or V L DD 40 40 μV/mA Due to load current change 40 40 μV Due to powering down (per channel) OUTPUT CHARACTERISTICS6 Output Voltage Range 0 V 0 V V DD DD Capacitive Load Stability 1 1 nF R = 5 kΩ, R =100 kΩ, and R = ∞ L L L DC Output Impedance Normal Mode 0.5 0.5 Ω Power-Down Mode Output Connected to 100 100 kΩ Output impedance tolerance ± 20 kΩ 100 kΩ Network Output Connected to 1 1 kΩ Output impedance tolerance ± 400 Ω 1 kΩ Network Short-Circuit Current 60 60 mA DAC = full scale, output shorted to GND 45 45 mA DAC = zero scale, output shorted to V DD Power-Up Time7 4.5 4.5 μs DC PSRR −92 −92 dB V ± 10%, DAC = full scale, V < V DD REF DD REFERENCE INPUTS Reference Input Range 2.2 V 2.2 V V DD DD Reference Current 35 50 35 50 μA Per DAC channel; individual reference option 140 160 140 160 μA Single reference option Reference Input Impedance 120 120 kΩ Individual reference option 32 32 kΩ Single reference option LOGIC INPUTS Input Current8 ±1 ±1 μA Input Low Voltage, V 0.8 0.8 V INL Input High Voltage, V 2.2 2.2 V INH Pin Capacitance6 4 4 pF Rev. G | Page 3 of 28

AD5024/AD5044/AD5064 Data Sheet B Grade1 A Grade1, 2 Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS (SDO)9 Output Low Voltage, V 0.4 0.4 V I = 2 mA OL SINK Output High Voltage, V V − 1 V − 1 I = 2 mA OH DD DD SOURCE High Impedance Leakage ±0.002 ±1 ±0.002 ±1 μA Current High Impedance Output 7 7 pF Capacitance6 POWER REQUIREMENTS V 4.5 5.5 4.5 5.5 V DAC active, excludes load current DD I 10 V = V , V = GND, Code = midscale DD IH DD IL Normal Mode 4 6 4 6 mA All Power-Down Modes11 0.4 2 0.4 2 μA T = −40°C to +105°C A 30 30 μA T = −40°C to +125°C A 1 Temperature range is −40°C to +125°C, typical at 25°C. 2 A grade offered in AD5064 only. 3 Linearity and total unadjusted error are calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded. 4 See the Terminology section. 5 Offset error calculated using a reduced code range—AD5064/AD5064-1: Code 512 to Code 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Code 4064. Output unloaded 6 Guaranteed by design and characterization; not production tested. 7 Time to exit power-down mode to normal mode; 32nd clock edge to 90% of DAC midscale value, output unloaded. 8 Current flowing into individual digital pins. VDD = 5.5 V; VREF = 4.096 V; Code = midscale. 9 AD5064-1 only. 10 Interface inactive. All DACs active. DAC outputs unloaded. 11 All four DACs powered down. AC CHARACTERISTICS V = 4.5 V to 5.5 V, R = 5 kΩ to GND, C = 200 pF to GND, 2.5 V ≤ V ≤ V . All specifications T to T , unless otherwise DD L L REFIN DD MIN MAX noted. Table 3. Parameter1, 2 Min Typ Max Unit Test Conditions/Comments3 Output Voltage Settling Time 5.8 8 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, R = 5 kΩ, L single-channel update 10.7 13 μs ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, R = 5 kΩ, all channel L update Slew Rate 1.5 V/μs Digital-to-Analog Glitch Impulse 3 nV-sec 1 LSB change around major carry Reference Feedthrough −90 dB V = 3 V ± 0.86 V p-p, frequency = 100 Hz to 100 kHz REF Digital Feedthrough 0.1 nV-sec Digital Crosstalk 1.9 nV-sec Analog Crosstalk 2 nV-sec DAC-to-DAC Crosstalk 3.5 nV-sec AC Crosstalk 6 nV-sec Multiplying Bandwidth 340 kHz V = 3 V ± 0.86 V p-p REF Total Harmonic Distortion −80 dB V = 3 V ± 0.2 V p-p, frequency = 10 kHz REF Output Noise Spectral Density 64 nV/√Hz DAC code = 0x8400, frequency = 1 kHz 60 nV/√Hz DAC code = 0x8400, frequency = 10 kHz Output Noise 6 μV p-p 0.1 Hz to 10 Hz 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range is −40°C to +125°C, typical at 25°C. Rev. G | Page 4 of 28

Data Sheet AD5024/AD5044/AD5064 TIMING CHARACTERISTICS All input signals are specified with t = t = 1 ns/V (10% to 90% of V ) and timed from a voltage level of (V + V )/2. See Figure 4 and R F DD IL IH Figure 5. V = 4.5 V to 5.5 V. All specifications T to T , unless otherwise noted. DD MIN MAX Table 4. Parameter1 Symbol Min Typ Max Unit SCLK Cycle Time t 20 ns 1 SCLK High Time t 10 ns 2 SCLK Low Time t 10 ns 3 SYNC to SCLK Falling Edge Setup Time t 17 ns 4 Data Setup Time t 5 ns 5 Data Hold Time t 5 ns 6 SCLK Falling Edge to SYNC Rising Edge t 5 30 ns 7 Minimum SYNC High Time (Single Channel Update) t 3 μs 8 Minimum SYNC High Time (All Channel Update) t 8 μs 8 SYNC Rising Edge to SCLK Fall Ignore t 17 ns 9 LDAC Pulse Width Low t 20 ns 10 SCLK Falling Edge to LDAC Rising Edge t 20 ns 11 CLR Minimum Pulse Width Low t 10 ns 12 SCLK Falling Edge to LDAC Falling Edge t 10 ns 13 CLR Pulse Activation Time t 10.6 μs 14 SCLK Rising Edge to SDO Valid t 2, 3 22 ns 15 SCLK Falling Edge to SYNC Rising Edge t 2 5 ns 16 SYNC Rising Edge to SCLK Rising Edge t 2 8 ns 17 SYNC Rising Edge to LDAC/CLR Falling Edge (Single Channel Update) t 2 2 μs 18 SYNC Rising Edge to LDAC/CLR Falling Edge (All Channel Update) t 2 8 μs 18 Power-up Time4 4.5 μs 1 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 5.5 V. Guaranteed by design and characterization; not production tested. 2 Daisy-chain mode only. 3 Measured with the load circuit of Figure 3. t15 determines the maximum SCLK frequency in daisy-chain mode. AD5064-1 only. 4 Time to exit power-down mode to normal mode of AD5024/AD5044/AD5064/AD5064-1, 32nd clock edge to 90% of DAC midscale value, with output unloaded. Circuit and Timing Diagrams 2mA IOL TO OUTPUT VOH (MIN) + VOL (MAX) PIN 2 CL 50pF 2mA IOH 06803-002 Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications Rev. G | Page 5 of 28

AD5024/AD5044/AD5064 Data Sheet t 1 t 9 SCLK t8 t4 t3 t2 t7 SYNC t 6 t 5 DIN DB31 DB0 t t 10 13 LDAC1 t 11 LDAC2 t CLR 12 VOUT t14 12ASYSNYNCCHHRROONONOUSU SL DLADCAC U PUDPDAATET EM MOODED.E. 06803-003 Figure 4. Serial Write Operation SCLK 32 64 t 17 t t 8 4 t16 SYNC t 5 t 6 DIN DB31 DB0 DB31 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N + 1 t 15 SDO DB31 DB0 UNDEFINED INPUT WORD FOR DAC N t 18 t 10 LDAC1 t 18 t 12 CLR 1IF IN DAISY-CHAIN MODE, LDAC MUST BE USED ASYNCHRONOUSLY. 06803-004 Figure 5. Daisy-Chain Timing Diagram Rev. G | Page 6 of 28

Data Sheet AD5024/AD5044/AD5064 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a Table 5. stress rating only; functional operation of the product at these Parameter Rating or any other conditions above those indicated in the operational V to GND −0.3 V to +7 V DD section of this specification is not implied. Operation beyond Digital Input Voltage to GND −0.3 V to V + 0.3 V DD the maximum operating conditions for extended periods may V to GND −0.3 V to V + 0.3 V OUT DD affect product reliability. V to GND −0.3 V to V + 0.3 V REF DD Operating Temperature Range Industrial −40°C to +125°C ESD CAUTION Storage Temperature Range −65°C to +150°C Junction Temperature (T ) 150°C JMAX TSSOP Power Dissipation (T − T )/θ JMAX A JA θJA Thermal Impedance 113°C/W Reflow Soldering Peak Temperature Pb-Free 260°C Rev. G | Page 7 of 28

AD5024/AD5044/AD5064 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS LDAC 1 14 SCLK SYNC 2 13 DIN VDD 3 12 GND AD5064-1 VOUTA 4 11 VOUTB TOP VIEW VOUTC 5 (Not to Scale) 10 VOUTD POR 6 9 CLR VREFIN 7 8 SDO 06803-065 Figure 6. 14-Lead TSSOP (RU-14) Table 6. 14-Lead TSSOP (RU-14) Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. When daisy-chain mode is enabled, this pin cannot be tied permanently low; the LDAC pin should be used in asynchronous LDAC update mode, as shown in Figure 5, and the LDAC pin must be brought high after pulsing. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 V Power Supply Input. These devices can be operated from 4.5 V to 5.5 V, and the supply should be DD decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 5 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 6 POR Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to V DD powers up all four DACs to midscale. 7 V This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D. REFIN 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 9 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 10 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 11 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 12 GND Ground Reference Point for All Circuitry on the Device. 13 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the falling edge of the serial clock input. 14 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. G | Page 8 of 28

Data Sheet AD5024/AD5044/AD5064 LDAC 1 16 SCLK SYNC 2 15 DIN VDD 3 AD5024/ 14 GND AD5044/ VREFB 4 AD5064 13 VOUTB VREFA 5 TOP VIEW 12 VOUTD VOUTA 6 (Not to Scale) 11 VREFD VOUTC 7 10 CLR POR 8 9 VREFC 06803-005 Figure 7. 16-Lead TSSOP (RU-16) Pin Configuration Table 7. 16-Lead TSSOP (RU-16) Pin Function Descriptions Pin No. Mnemonic Description 1 LDAC LDAC can be operated in two modes, asynchronously and synchronously, as shown in Figure 4. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode. 2 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. 3 V Power Supply Input. These devices can be operated from 4.5 V to 5.5 V, and the supply should be DD decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND. 4 V B DAC B Reference Input. This is the reference voltage input pin for DAC B. REF 5 V A DAC A Reference Input. This is the reference voltage input pin for DAC A. REF 6 V A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. OUT 7 V C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. OUT 8 POR Power-On Reset. Tying this pin to GND powers up the device to 0 V. Tying this pin to V powers up the DD device to midscale. 9 V C DAC C Reference Input. This is the reference voltage input pin for DAC C. REF 10 CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored. When CLR is activated, the input register and the DAC register are updated with the data contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V. 11 V D DAC D Reference Input. This is the reference voltage input pin for DAC D. REF 12 V D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. OUT 13 V B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. OUT 14 GND Ground Reference Point for All Circuitry on the Device. 15 DIN Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the falling edge of the serial clock input. 16 SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz. Rev. G | Page 9 of 28

AD5024/AD5044/AD5064 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 0.8 VVTADR DE=F = 2= 55 °4VC.096V 0.8 VVTADR DE=F = 2= 55 °4VC.096V 0.6 0.6 0.4 0.4 INL (LSB) –00..220 DNL (LSB) –00..202 –0.4 –0.4 –0.6 –0.6 ––10..08 06803-019 ––01..80 06803-022 512 16,640 32,768 48,896 65,024 512 16,640 32,768 48,896 65,024 DAC CODE DAC CODE Figure 8. AD5064/AD5064-1 INL Figure 11. AD5064/AD5064-1 DNL 1.0 1.0 VDD = 5V VDD = 5V 0.8 VREF = 4.096V 0.8 VREF = 4.096V TA = 25°C TA = 25°C 0.6 0.6 0.4 0.4 INL (LSB) –00..202 DNL (LSB) –00..202 –0.4 –0.4 –0.6 –0.6 ––10..08 06803-020 ––10..08 06803-023 0 512 1024 1536 2048 2560 3072 3584 4096 0 4096 8192 12,288 16,384 DAC CODE DAC CODE Figure 9. AD5044 INL Figure 12. AD5044 DNL 1.0 1.00 VDD = 5V VDD = 5V 0.8 TVAR E=F 2=5 °4C.096V 0.75 VTAR E=F 2=5 °4C.096V 0.6 0.50 0.4 0.25 INL (LSB) –00..202 DNL (LSB)–0.250 –0.4 –0.50 –0.6 ––10..08 06803-021 ––10..0705 06803-024 0 512 1024 1536 2048 2560 3072 3584 4096 0 4096 8192 12,288 16,384 DAC CODE DAC CODE Figure 10. AD5024 INL Figure 13. AD5024 DNL Rev. G | Page 10 of 28

Data Sheet AD5024/AD5044/AD5064 0.20 1.2 VDD = 5V TA = 25°C 0.15 VTAR E=F 2=5 °4C.096V 01..80 0.10 0.6 0.4 0.05 mV) mV) 0.2 MAX TUE @ VDD = 5.5V TUE ( 0 TUE ( –0.20 MIN TUE @ VDD = 5.5V –0.05 –0.4 –0.10 –0.6 –0.15 –0.8 –0.20 06803-025 ––11..20 06803-028 512 16,640 32,768 48,896 65,024 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DAC CODE REFERENCE VOLTAGE (V) Figure 14. Total Unadjusted Error (TUE) Figure 17. TUE vs. Reference Input Voltage 1.6 0.015 1.4 TA = 25°C 1.2 0.010 1.0 DAC A 0.8 ROR (LSB) 000...2460 MAX INL ERROR @ VDD = 5.5V ROR (%FSR) 0.0050 DAC B DAC D R –0.2 R E E INL ––00..64 MIN INL ERROR @ VDD = 5.5V GAIN –0.005 DAC C –0.8 –1.0 –0.010 –––111...642 06803-026 –0.015 VVDREDF= = 5 4.5.0V96V 06803-029 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –60 –40 –20 0 20 40 60 80 100 120 140 REFERENCE VOLTAGE (V) TEMPERATURE (°C) Figure 15. INL vs. Reference Input Voltage Figure 18. Gain Error vs. Temperature 1.6 0.6 1.4 TA = 25°C VDD= 5.5V 1.2 0.5 DAC C VREF = 4.096V 1.0 0.4 0.8 0.6 V) 0.3 B) m R (LS 00..24 MAX DNL ERROR @ VDD = 5.5V ROR ( 0.2 DAC D O 0 R 0.1 R E NL ER ––00..42 MIN DNL ERROR @ VDD = 5.5V FSET 0 D –0.6 OF –0.1 –0.8 DAC A –0.2 –1.0 DAC B –––111...642 06803-027 ––00..43 06803-030 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 –60 –40 –20 0 20 40 60 80 100 120 140 REFERENCE VOLTAGE (V) TEMPERATURE (ºC) Figure 16. DNL vs. Reference Input Voltage Figure 19. Offset Error vs. Temperature Rev. G | Page 11 of 28

AD5024/AD5044/AD5064 Data Sheet 0.2 10 VREF = 4.096V VDD = 5.5V TA = 25°C TVAR E=F 2=5 °4C.096 8 0.1 R) S 6 %F GAIN ERROR mA) OR ( 0 (DD RR I 4 E FULL-SCALE ERROR –0.1 2 –0.24.50 4.75 VD5D.0 0(V) 5.25 5.5006803-031 00 10,000 20,000 30D,0A0C0 CO40D,E000 50,000 60,000 70,000 06803-034 Figure 20. Gain Error and Full-Scale Error vs. Supply Voltage Figure 23. Supply Current vs. Code 0.12 10 VREF = 4.096V VDD = 5.5V TA = 25°C VREF = 4.096 CODE = MIDSCALE 8 0.09 V) m R ( 6 O A) R m T ER 0.06 (DD E I 4 S F F O 0.03 2 0 06803-032 0 4.50 4.75 VD5D.0 0(V) 5.25 5.50 –40 –20 0 2T0EMPE4R0ATURE6 0(°C) 80 100 120 06803-035 Figure 21. Offset Error Voltage vs. Supply Voltage Figure 24. Supply Current vs. Temperature 40 10 MEAN: 4.11699 35 SLIDM: I0T.S0:5 4L4O4W03: 3 HIGH: 4.3 TVVADR DE=F = 2= 55 °4.5C.0V96 CPk: LOW: 6.84 HIGH: 1.12 8 30 VREF = 4.096V TA = 25°C CODE = MIDSCALE 25 6 A) S m HIT 20 (D D I 4 15 10 2 5 0 0 3.9 4.0IDDPOWER4-.U1P (mA) 4.2 4.3 06803-033 4.5 4.6 4.7 4.8SUP4P.9LY V5O.0LTAG5.E1 (V)5.2 5.3 5.4 5.5 06803-036 Figure 22. IDD Histogram, VDD = 5.0 V Figure 25. Supply Current vs. Supply Voltage Rev. G | Page 12 of 28

Data Sheet AD5024/AD5044/AD5064 10 VDD = 5.5V VREF = 4.096V VREF = 4.096 TA = 25°C TA = 25°C OUTPUT UNLOADED VDD 8 6 A) m 1 (DD DAC A I 4 3 2 0 06803-040 0 1 DIGIT2AL INPUT V3OLTAGE (V4) 5 06803-037 CH1 2V CH3 2V MT 2 m20s.4% A CH1 2.52V Figure 26. Supply Current vs. Digital Input Voltage Figure 29. Power-On Reset to Midscale 5.0 CH1 = SCLK 4.5 4.0 1 V) 3.5 E ( AG 3.0 VDD = 5V, VREF = 4.096V OLT 2.5 1T/A4 =S C25AºLCETO 3/4 SCALE UT V 2.0 3O/U4 TSPCUATL ELOTAOD 1E/4D SWCIATLHE 5kΩ CH2 = VOUT PVODDW =E 5RV-UP TO MIDSCALE TP AND 200pFTO GND OUTPUT UNLOADED U O 1.5 2 1.0 0.05 06803-038 06803-041 0 2 4 6 8 10 12 14 CH1 5V CH2 500mV M2µs A CH2 1.2V TIME (µs) T 55% Figure 27. Settling Time Figure 30. Exiting Power-Down to Midscale 6 VREF = 4.096V VDD = 5V TA = 25°C 5 VREF = 4.096V VDD CODE = 0x8000 TOTA 0 =x 72F5F°CF 4 OUTPUT UNLOADED WITH 5kΩ V) AND 200pF m E ( 3 D U T 2 1 PLI M 1 A H TC 0 DAC A LI 3 G –1 06803-039 ––32 06803-042 CH1 2V CH3 2V M2ms A CH1 2.52V 0 2.5 5.0 7.5 10.0 T 20.4% TIME (μs) Figure 28. Power-On Reset to 0 V Figure 31. Digital-to-Analog Glitch Impulse Rev. G | Page 13 of 28

AD5024/AD5044/AD5064 Data Sheet 7 0 VDD = 5V, VREF = 4.096V VDD= 5V, 6 TA = 25ºC –10 TA= 25ºC DAC LOADED WITH MIDSCALE 5 –20 VREF = 3.0V ± 200mV p-p V) 4 m –30 E ( 3 B) D d –40 TCH AMPLITU 120 V LEVEL (OUT ––6500 GLI –1 –70 –2 –80 ––34 06803-043 –1–0900 06803-046 0 2.5 5.0 7.5 10.0 5 10 20 30 40 50 55 TIME (μs) FREQUENCY (kHz) Figure 32. Analog Crosstalk Figure 35. Total Harmonic Distortion 7 24 VDD = 5V, VREF = 4.096V VDD = 5V, VREF = 3.0V 6 TA = 25°C 22 TA = 25°C 1/4 SCALE TO 3/4 SCALE 5 WITHIN ±1LSB 20 V) 4 PLITUDE (m 32 G TIME (μs) 111864 M 1 N CH A 0 TTLI 12 GLIT –1 SE 10 –2 8 ––43 06803-044 46 06803-047 0 2.5 5.0 7.5 10.0 0 1 2 3 4 5 6 7 8 9 10 TIME (μs) CAPACITANCE (nF) Figure 33. DAC-to-DAC Crosstalk Figure 36. Settling Time vs. Capacitive Load VDD = 5V, VREF= 4.096V TA = 25ºC DAC LOADED WITH MIDSCALE CLR 1 V DI V/ μ 1 DAC A 2 06803-045 VVTADR DE=F = 2= 55 º4VC.096V 06803-048 4s/DIV CH1 5V CH2 2V M2µs A CH1 2.5V T11% Figure 34. 0.1 Hz to 10 Hz Output Noise Plot Figure 37. Hardware CLR Rev. G | Page 14 of 28

Data Sheet AD5024/AD5044/AD5064 10 0.10 CODE = MIDSCALE 0.08 VDD = 5V, VREF = 4.096V 0 0.06 B) –10 0.04 d ATION ( –20 (V)UT 0.020 ENU –30 ∆VO–0.02 T T A –40 –0.04 CH A CH B –0.06 ––6500 CC3dHHB CD POINT 06803-049 ––00..1008 06803-052 10 100 1000 10000 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 FREQUENCY (kHz) IOUT (mA) Figure 38. Multiplying Bandwidth Figure 41. Typical Current Limiting Plot 5.0 TA = 25°C 4.5 VDD = 5V, VREF = 4.096V DAC A 295mV p-p 4.0 V) 3.5 E ( AG 3.0 VDD = 5V, VREF = 4.096V LT TA= 25°C O 2.5 1/4 SCALETO 3/4 SCALE V T 3/4 SCALETO 1/4 SCALE U 2.0 OUTPUT LOADED WITH 5kΩ P T AND 200pFTO GND U O 1.5 1.0 0.05 06803-050 06803-053 0 2 4 6 8 10 12 14 CH1 50mV CH2 5V M4µs A CH2 1.2V TIME (µs) T8.6% Figure 39. Typical Output Slew Rate Figure 42. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, No Load 00..00001008 CVDODD =E 5=V M, VIDRSECF A=L 4E.096V TVAD D= =2 55°VC, VREF = 4.096V DAC A 200mV p-p 0.0006 0.0004 V) E ( 0.0002 G A LT 0 O V ∆–0.0002 –0.0004 ––00..00000068 06803-051 SCLK 06803-054 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 CH1 50mV CH2 5V M4µs A CH2 1.2V T8.6% CURRENT (mA) Figure 43. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, Figure 40. Typical Output Load Regulation 5 kΩ/200 pF Load Rev. G | Page 15 of 28

AD5024/AD5044/AD5064 Data Sheet VDD = 5V,VREF = 4.096V TA = 25°C TA = 25°C VDD = 5V, VREF = 4.096V DAC A 129mV p-p DAC A 170mV p-p SCLK 06803-055 SCLK 06803-056 CH1 20mV CH2 5V M4µs A CH2 1.2V CH1 20mV CH2 5V M4µs A CH2 1.2V T8.6% T8.6% Figure 44. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, Figure 45. Glitch Upon Exiting Power-Down (1 kΩ to GND) to Zero Scale, No Load 5 kΩ/200 pF Load Rev. G | Page 16 of 28

Data Sheet AD5024/AD5044/AD5064 TERMINOLOGY Relative Accuracy (INL) DC Power Supply Rejection Ratio (PSRR) For the DAC, relative accuracy, or integral nonlinearity (INL), PSRR indicates how the output of the DAC is affected by changes is a measure of the maximum deviation in LSBs from a straight in the supply voltage. PSRR is the ratio of the change in V to OUT line passing through the endpoints of the DAC transfer function. a change in V for full-scale output of the DAC. It is measured DD Figure 8, Figure 9, and Figure 10 show plots of typical INL vs. code. in decibels. V is held at 2.5 V, and V is varied by ±10%. REF DD Measured with V < V . Differential Nonlinearity (DNL) REF DD DNL is the difference between the measured change and the DC Crosstalk ideal 1 LSB change between any two adjacent codes. A specified DC crosstalk is the dc change in the output level of one DAC in differential nonlinearity of ±1 LSB maximum ensures monoto- response to a change in the output of another DAC. It is measured nicity. This DAC is guaranteed monotonic by design. Figure 11, with a full-scale output change on one DAC (or soft power-down Figure 12, and Figure 13 show plots of typical DNL vs. code. and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts. Offset Error Offset error is a measure of the difference between the actual DC crosstalk due to load current change is a measure of the V and the ideal V , expressed in millivolts in the linear impact that a change in load current on one DAC has to another OUT OUT region of the transfer function. Offset error is calculated using DAC kept at midscale. It is expressed in microvolts per milliamp. a reduced code range—AD5064/AD5064-1: Code 512 to Code Reference Feedthrough 65,024; AD5044: Code 128 to Code 16,256; AD5024: Code 32 to Reference feedthrough is the ratio of the amplitude of the signal Code 4064, with output unloaded. Offset error can be negative or at the DAC output to the reference input when the DAC output positive and is expressed in millivolts. is not being updated (that is, LDAC is high). It is expressed in Gain Error decibels. Gain error is a measure of the span error of the DAC. It is the Digital Feedthrough deviation in slope of the DAC transfer characteristic from the Digital feedthrough is a measure of the impulse injected into ideal, expressed as a percentage of the full-scale range. the analog output of a DAC from the digital input pins of the Offset Error Temperature Coefficient device, but it is measured when the DAC is not being written Offset error temperature coefficient is a measure of the change to (SYNC held high). It is specified in nanovolt-seconds and in offset error with a change in temperature. It is expressed in measured with one simultaneous data and clock pulse loaded microvolts per degree Celsius. to the DAC. Gain Temperature Coefficient Digital Crosstalk Gain error drift is a measure of the change in gain error with Digital crosstalk is the glitch impulse transferred to the output changes in temperature. It is expressed in parts per million of of one DAC at midscale in response to a full-scale code change full-scale range per degree Celsius. (all 0s to all 1s or vice versa) in the input register of another Full-Scale Error DAC. It is measured in standalone mode and is expressed in Full-scale error is a measure of the output error when full-scale nanovolt-seconds. code (0xFFFF) is loaded into the DAC register. Ideally, the Analog Crosstalk output should be VREF − 1 LSB. Full-scale error is expressed as a Analog crosstalk is the glitch impulse transferred to the output percentage of the full-scale range. Measured with VREF < VDD. of one DAC due to a change in the output of another DAC. It is Digital-to-Analog Glitch Impulse measured by loading one of the input registers with a full-scale Digital-to-analog glitch impulse is the impulse injected into the code change (all 0s to all 1s or vice versa) while keeping LDAC analog output when the input code in the DAC register changes high, and then pulsing LDAC low and monitoring the output of state. It is normally specified as the area of the glitch in nanovolt- the DAC whose digital code has not changed. The area of the seconds and is measured when the digital input code is changed glitch is expressed in nanovolt-seconds. by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 31. Rev. G | Page 17 of 28

AD5024/AD5044/AD5064 Data Sheet DAC-to-DAC Crosstalk (with full-scale code loaded to the DAC) appears on the output. DAC-to-DAC crosstalk is the glitch impulse transferred to the The multiplying bandwidth, expressed in kilohertz, is the output of one DAC due to a digital code change and subsequent frequency at which the output amplitude falls to 3 dB below output change of another DAC. This includes both digital and the input. analog crosstalk. It is measured by loading one of the DACs Total Harmonic Distortion (THD) with a full-scale code change (all 0s to all 1s or vice versa) with Total harmonic distortion is the difference between an ideal LDAC low and monitoring the output of another DAC. The sine wave and its attenuated version using the DAC. The sine energy of the glitch is expressed in nanovolt-seconds. wave is used as the reference for the DAC, and the THD is a Multiplying Bandwidth measure of the harmonics present on the DAC output. It is The multiplying bandwidth is a measure of the finite bandwidth measured in decibels. of the amplifiers within the DAC. A sine wave on the reference Rev. G | Page 18 of 28

Data Sheet AD5024/AD5044/AD5064 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER OUTPUT AMPLIFIER The AD5024/AD5044/AD5064/AD5064-1 are single 12-/14-/ The output buffer amplifier can generate rail-to-rail voltages 16-bit, serial input, voltage output DACs with an individual on its output, which gives an output range of 0 V to V . The DD reference pin. The AD5064-1 model (see the Ordering Guide) amplifier is capable of driving a load of 5 kΩ in parallel with is a 16-bit, serial input, voltage output DAC that is identical to 200 pF to GND. The slew rate is 1.5 V/μs with a ¼ to ¾ scale other AD5064 models but with a single reference pin for all settling time of 5.8 μs. DACs. The devices operate from supply voltages of 4.5 V to 5.5 V. SERIAL INTERFACE Data is written to the AD5024/AD5044/AD5064/AD5064-1 in a The AD5024/AD5044/AD5064/AD5064-1 have a 3-wire serial 32-bit word format via a 3-wire serial interface. The AD5024/ interface (SYNC, SCLK, and DIN) that is compatible with SPI, AD5044/AD5064/AD5064-1 incorporate a power-on reset circuit that ensures that the DAC output powers up to a known output QSPI, and MICROWIRE interface standards as well as most state. The devices also have a software power-down mode that DSPs. See Figure 4 for a timing diagram of a typical write reduces the typical current consumption to typically 400 nA. sequence. The AD5064-1 model contains an SDO pin to allow the user to daisy-chain multiple devices together (see the Daisy- Because the input coding to the DAC is straight binary, the ideal Chaining section). output voltage when using an external reference is given by SHIFT REGISTER  D  VOUT VREFIN 2N  The AD5024/AD5044/AD5064/AD5064-1 shift register is 32 bits wide. The first four bits are don’t cares. The next four bits are the where: command bits, C3 to C0 (see Table 8), followed by the 4-bit D is the decimal equivalent of the binary code that is loaded to DAC address bits, A3 to A0 (see Table 9), and finally the bit the DAC register (0 to 65,535 for the 16-bit AD5064). data-word. The data-word comprises 12-bit, 14-bit, or 16-bit input N is the DAC resolution. code, followed by eight, six, or four don’t care bits for the AD5024, DAC ARCHITECTURE AD5044, and AD5064/AD5064-1, respectively (see Figure 47, Figure 48, and Figure 49). These data bits are transferred to the The DAC architecture of the AD5064 consists of two matched DAC register on the 32nd falling edge of SCLK. Commands can be DAC sections. A simplified circuit diagram is shown in Figure 46. executed on individually selected DAC channels or on all DACs. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of Table 8. Command Definitions 15 matched resistors to either GND or the V buffer output. REF Command The remaining 12 bits of the data-word drive the S0 to S11 C3 C2 C1 C0 Description switches of a 12-bit voltage mode R-2R ladder network. 0 0 0 0 Write to Input Register n VOUT 0 0 0 1 Update DAC Register n 2R 2R 2R 2R 2R 2R 2R 0 0 1 0 Write to Input Register n, update all (software LDAC) S0 S1 S11 E1 E2 E15 0 0 1 1 Write to and update DAC Channel n VREF 0 1 0 0 Power down/power up DAC 0 1 0 1 Load clear code register 12-BIT R-2R LADDER FOU15R EMQSUBAsL D SEECGOMDEENDT ISNTO 06803-006 00 11 11 10 RLoeasedt L(DpoAwC erre-goinst reers et) Figure 46. DAC Ladder Structure 1 0 0 0 Set up DCEN register1 (daisy-chain enable) REFERENCE BUFFER 1 0 0 1 Reserved 1 1 1 1 Reserved The AD5024/AD5044/AD5064/AD5064-1 operate with an exter- nal reference. For most models, each DAC has a dedicated voltage 1 Available in the AD5064-1 14-lead TSSOP only. reference pin. The AD5064-1 model has a single voltage reference Table 9. Address Commands pin for all DACs. The reference input pin has an input range of 2.2 V to V . This input voltage is then buffered internally to Address (n) DD provide a reference for the DAC core. A3 A2 A1 A0 Selected DAC Channel 0 0 0 0 DAC A 0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 1 1 1 1 All DACs Rev. G | Page 19 of 28

AD5024/AD5044/AD5064 Data Sheet DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X DATA BITS COMMAND BITS ADDRESS BITS 06803-009 Figure 47. AD5024 Shift Register Content DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X DATA BITS COMMAND BITS ADDRESS BITS 06803-008 Figure 48. AD5044 Shift Register Content DB31 (MSB) DB0 (LSB) X X X X C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X DATA BITS COMMAND BITS ADDRESS BITS 06803-007 Figure 49. AD5064/AD5064-1 Shift Register Content SCLK SYNC DIN DB31 DB0 DB31 DB0 SYNC HINIGVHA LBIEDF WORRIET E32 SNEDQ FUAELNLCINEG: EDGE VALID WORNIT TEH SEE 3Q2UNEDN FCAEL,L OINUGT PEUDTG UEPDATES 06803-010 Figure 50. SYNC Interrupt Facility Rev. G | Page 20 of 28

Data Sheet AD5024/AD5044/AD5064 MODES OF OPERATION reserved for this DCEN function (see Table 8). The daisy-chain mode is enabled by setting Bit DB1 in the DCEN register. The There are three main modes of operation: standalone mode default setting is standalone mode, where DB1 = 0. where a single device is used, daisy-chain mode for a system that contains several DACs, and power-down mode when the Table 10 shows how the state of the bit corresponds to the mode supply current falls to 0.4 μA at 5 V. of operation of the device. Standalone Mode Table 10. DCEN (Daisy-Chain Enable) Register The write sequence begins by bringing the SYNC line low. Data DB1 DB0 Description from the DIN line is clocked into the 32-bit shift register on the 0 X Standalone mode (default) falling edge of SCLK. The serial clock frequency can be as high 1 X DCEN mode as 50 MHz, making the AD5024/AD5044/AD5064/AD5064-1 The SCLK is continuously applied to the shift register when compatible with high speed DSPs. On the 32nd falling clock edge, SYNC is low. If more than 32 clock pulses are applied, the data the last data bit is clocked in and the programmed function is ripples out of the shift register and appears on the SDO line. executed, that is, an LDAC-dependent change in DAC register This data is clocked out on the rising edge of SCLK and is valid contents and/or a change in the mode of operation. At this on the falling edge. By connecting this line to the DIN input on stage, the SYNC line can be kept low or be brought high. In the next DAC in the chain, a daisy-chain interface is constructed. either case, it must be brought high for a minimum of 3 μs Each DAC in the system requires 32 clock pulses; therefore, the (single channel, see Table 4, t parameter) before the next write 8 total number of clock cycles must equal 32N, where N is the sequence so that a falling edge of SYNC can initiate the next total number of devices that are updated. If SYNC is taken high write sequence. SYNC should be idled at rails between write at a clock that is not a multiple of 32, it is considered an invalid sequences for even lower power operation of the device. frame and the data is discarded. SYNC Interrupt When the serial transfer to all devices is complete, SYNC is In a normal write sequence, the SYNC line is kept low for at taken high. This prevents any further data from being clocked least 32 falling edges of SCLK, and the DAC is updated on the into the shift register. 32nd falling edge. However, if SYNC is brought high before the In daisy-chain mode, the LDAC pin cannot be tied permanently 32nd falling edge, this acts as an interrupt to the write sequence. low. The LDAC pin must be used in asynchronous LDAC update The write sequence is seen as invalid. Neither an update of the mode, as shown in Figure 5. The LDAC pin must be brought DAC register contents nor a change in the operating mode high after pulsing. This allows all DAC outputs to simulta- occurs (see Figure 50). neously update. Daisy-Chaining The serial clock can be continuous or a gated clock. A continuous For systems that contain several DACs the SDO pin can be SCLK source can be used only if SYNC can be held low for the used to daisy-chain several devices together and provide serial correct number of clock cycles. In gated clock mode, a burst readback. clock containing the exact number of clock cycles must be used, The daisy-chain mode is enabled through a software executable and SYNC must be taken high after the final clock to latch the data. daisy-chain enable (DCEN) command. Command 1000 is Table 11. 32-Bit Shift Register Contents for Daisy-Chain Enable MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 1 0 0 0 X X X X X 1/0 X Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares DCEN register Rev. G | Page 21 of 28

AD5024/AD5044/AD5064 Data Sheet POWER-ON RESET Table 12. Modes of Operation DB9 DB8 Operating Mode The AD5024/AD5044/AD5064/AD5064-1 contain a power-on 0 0 Normal operation reset circuit that initializes the registers to their default values Power-down modes: and controls the output voltage during power-up. By connecting 0 1 1 kΩ to GND the POR pin low, the AD5024/AD5044/AD5064/AD5064-1 1 0 100 kΩ to GND output powers up to zero scale. Note that this is outside the 1 1 Three-state linear region of the DAC; by connecting the POR pin high, the AD5024/AD5044/AD5064/AD5064-1 output powers up to Any or all DACs (DAC D to DAC A) can be powered down to midscale. The output remains powered up at this level until a the selected mode by setting the corresponding four bits (DB3, valid write sequence is made to the DAC. This is useful in DB2, DB1, DB0) to 1. See Table 13 for the contents of the shift applications where it is important to know the state of the register during power-down/power-up operation. output of the DAC while it is in the process of powering up. When both Bit DB9 and Bit D8 in the shift register are set to 0, There is also a software executable reset function that resets the the device works normally with its normal power consumption DAC to the power-on reset code. Command 0111 is designated of 4 mA at 5 V. However, for the three power-down modes, the for this reset function (see Table 8). Any events on LDAC or supply current falls to 0.4 μA at 5 V. Not only does the supply CLR during power-on reset are ignored. The power-on reset current fall, but the output stage is also internally switched from circuit is triggered when V passes 2.6 V approximately and DD the output of the amplifier to a resistor network of known values. takes 50 μs to complete. No writes to the AD5024/AD5044/ This has the advantage that the output impedance of the device AD5064/AD5064-1 should take place during this time. is known while the device is in power-down mode. There are To prevent unintended operation during power-up, control the three different power-down options. The output is connected digital input signals (SYNC, SCLK, DIN, LDAC, and CLR) while internally to GND through either a 1 kΩ or a 100 kΩ resistor, or the power supply is ramping. Control these signals by using pull- it is left open-circuited (three-state). The output stage is illustrated up resistors connected to V or GND. For applications that do in Figure 51. DD not require the hardware LDAC or CLR functions, the LDAC pin and the CLR pin can be tied directly to GND. For applications with a slow V ramp time (for example, more than 2 ms to 3 ms), it is DAC AMPLIFIER VOUT DD recommended that a software reset command is written when the power supplies have reached their final value. POWER-DOWN MODES POCWIRECRU-IDTORWYN RESISTOR Tsehpea rAaDte5 p0o2w4/eAr-Ddo5w04n4 m/AoDde5s0. 6C4o/mADm5a0n6d4 0-110 c0o ins tdaeinsi gthnraeteed for Figure 51. Output Stage During PowNEerT-WDOowRKn 06803-011 the power-down function (see Table 8). These power-down The bias generator, output amplifier, resistor string, and other modes are software-programmable by setting two bits, Bit DB9 associated linear circuitry are shut down when the power-down and Bit DB8, in the shift register. Table 12 shows how the state of mode is activated. However, the contents of the DAC register the bits corresponds to the mode of operation of the device. are unaffected when in power-down. The DAC register can be updated while the device is in power-down mode. The time to exit power-down is typically 4.5 μs for VDD = 5 V (see Figure 30). Table 13. 32-Bit Shift Register Contents for Power-Up/Power-Down Function MSB LSB DB31 DB19 DB7 to to to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10 DB9 DB8 DB4 DB3 DB2 DB1 DB0 X 0 1 0 0 X X X X X PD1 PD0 X DAC D DAC C DAC B DAC A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Power- Don’t Power-down/power-up channel cares don’t cares cares down mode cares selection—set bit to 1 to select Rev. G | Page 22 of 28

Data Sheet AD5024/AD5044/AD5064 CLEAR CODE REGISTER Synchronous LDAC: After new data is read, the DAC registers are updated on the falling edge of the 32nd SCLK pulse, provided The AD5024/AD5044/AD5064/AD5064-1 have a hardware CLR pin that is an asynchronous clear input. The CLR input is LDAC is held low. falling edge sensitive. Bringing the CLR line low clears the Asynchronous LDAC: The outputs are not updated at the same contents of the input register and the DAC registers to the data time that the input registers are written to. When LDAC is contained in the user-configurable CLR register and sets the pulsed low, the DAC registers are updated with the contents of analog outputs accordingly (see Table 14). This function can be the input registers. used in system calibration or reset to load zero scale, midscale, Software LDAC Function or full scale to all channels together. Note that zero scale and full Alternatively, the outputs of all DACs can be updated simulta- scale are outside the linear region of the DAC. These clear code values are user-programmable by setting two bits, Bit DB1 and neously or individually using the software LDAC function by Bit DB0, in the shift register (see Table 14). The default setting writing to Input Register n and updating all DAC registers. clears the outputs to 0 V. Command 0101 is designated for Command 0010 is reserved for this software LDAC function. loading the clear code register (see Table 8). Writing to the DAC using Command 0110 loads the 4-bit LDAC register (DB3 to DB0). The default for each channel Table 14. Clear Code Register is 0; that is, the LDAC pin works normally. Setting the bits to 1 DB1 (CR1) DB0 (CR0) Clears to Code updates the DAC channel regardless of the state of the hardware 0 0 0x0000 LDAC pin, so that it effectively sees the hardware LDAC pin as 0 1 0x8000 being tied low (see Table 15 for the LDAC register mode of 1 0 0xFFFF operation.) This flexibility is useful in applications where the 1 1 No operation user wants to simultaneously update select channels while the The device exits clear code mode on the 32nd falling edge of the remainder of the channels are synchronously updating. next write to the device. If hardware CLR pin is activated Table 15. LDAC Overwrite Definition during a write sequence, the write is aborted. Load LDAC Register The CLR pulse activation time, which is the falling edge of CLR LDAC Bits to when the output starts to change, is typically 10.6 μs. See (DB3 to DB0) LDAC Pin LDAC Operation Table 16 for contents of the shift register while loading the clear 0 1 or 0 Determined by the LDAC pin. code register. 1 X1 DAC channels update, overrides LDAC FUNCTION the LDAC pin. DAC channels see LDAC as 0. Hardware LDAC Pin 1 X = don’t care. The outputs of all DACs can be updated simultaneously using the hardware LDAC pin, as shown in Figure 4. LDAC can be The LDAC register gives the user extra flexibility and control permanently low or pulsed. There are two methods of using the over the hardware LDAC pin (see Table 17). Setting the LDAC hardware LDAC pin, synchronously and asynchronously. bits (DB0 to DB3) to 0 for a DAC channel means that the update of this channel is controlled by the hardware LDAC pin. Table 16. 32-Bit Shift Register Contents for Clear Code Function MSB LSB DB31 to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 to DB2 DB1 DB0 X 0 1 0 1 X X X X X 1/0 1/0 Don’t cares Command bits (C3 to C0) Address bits (A3 to A0) Don’t cares Clear code register (CR1 to CR0) Table 17. 32-Bit Shift Register Contents for LDAC Overwrite Function MSB LSB DB31 to DB19 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 to DB4 DB3 DB2 DB1 DB0 X 0 1 1 0 X X X X X DAC D DAC C DAC B DAC A Don’t Command bits (C3 to C0) Address bits (A3 to A0)— Don’t Setting LDAC bits to 1 overrides LDAC pin cares don’t cares cares Rev. G | Page 23 of 28

AD5024/AD5044/AD5064 Data Sheet POWER SUPPLY BYPASSING AND GROUNDING The power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the When accuracy is important in a circuit, it is helpful to carefully supply line. Clocks and other fast switching digital signals should consider the power supply and ground return layout on the board. be shielded from other parts of the board by digital ground. Avoid The printed circuit board (PCB) containing the AD5024/AD5044/ crossover of digital and analog signals, if possible. When traces AD5064/AD5064-1 should have separate analog and digital cross on opposite sides of the board, ensure that they run at right sections. If the AD5024/AD5044/AD5064/AD5064-1 are in angles to each other to reduce feedthrough effects through the a system where other devices require an AGND-to-DGND board. The best board layout technique is the microstrip tech- connection, the connection should be made at one point only. nique, where the component side of the board is dedicated to the This ground point should be as close as possible to the ground plane only and the signal traces are placed on the solder AD5024/AD5044/AD5064/AD5064-1. side. However, this is not always possible with a 2-layer board. The power supply to the AD5024/AD5044/AD5064/AD5064-1 should be bypassed with 10 μF and 0.1 μF capacitors. The capaci- tors should be as physically close as possible to the device, with the 0.1 μF capacitor ideally right up against the device. The 10 μF capacitors are the tantalum bead type. It is important that the 0.1 μF capacitor have low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 μF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. Rev. G | Page 24 of 28

Data Sheet AD5024/AD5044/AD5064 MICROPROCESSOR INTERFACING AD5024/AD5044/AD5064/AD5064-1 to 80C51/80L51 Interface AD5024/AD5044/AD5064/AD5064-1 to Blackfin ADSP-BF527 Interface Figure 54 shows a serial interface between the AD5024/AD5044/ AD5064/AD5064-1 and the 80C51/80L51 microcontroller. The Figure 52 shows a serial interface between the AD5024/ setup for the interface is as follows: TxD of the 80C51/80L51 AD5044/AD5064/AD5064-1 and the Blackfin® ADSP-BF527 drives SCLK of the AD5024/AD5044/AD5064/AD5064-1, and microprocessor. The ADSP-BF527 processor incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for RxD drives the serial data line of the device. The SYNC signal is serial and multiprocessor communications. Using SPORT0 to again derived from a bit-programmable pin on the port. In this connect to the AD5024/AD5044/AD5064/AD5064-1, the setup case, Port Line P3.3 is used. When data is to be transmitted to the for the interface is as follows: DT0PRI drives the DIN pin of the AD5024/AD5044/AD5064/AD5064-1, P3.3 is taken low. The AD5024/AD5044/AD5064/AD5064-1, and TSCLK0 drives the 80C51/80L51 transmit data in 8-bit bytes only; thus, only eight SCLK of the devices. The SYNC pin is driven from TFS0. falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, ADSP-BF527* AD5024/ and a second write cycle is initiated to transmit the second byte of AD5044/ AD5064/ data. P3.3 is taken high following the completion of this cycle. AD5064-1* The 80C51/80L51 output the serial data in a format that has the TFS0 SYNC LSB first. The AD5024/AD5044/AD5064/AD5064-1 must DT0PRI DIN receive data with the MSB first. The 80C51/80L51 transmit TSCLK0 SCLK routine should take this into account. *ADDITIONAL PINS OMITTED FOR CLARITY. 06803-012 80C51/80L51* AD5024/ Figure 52. AD5024/AD5044/AD5064/AD5064-1 to Blackfin AD5044/ ADSP-BF527 Interface AD5064/ AD5064-1* AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 P3.3 SYNC Interface TxD SCLK Figure 53 shows a serial interface between the AD5024/AD5044/ RxD DIN ASCDK5 0o6f 4t/hAe D685H06C41-11 /a6n8dL 1th1e d 6r8ivHesC t1h1e/ 6S8CLL1K1 omf itchreo cAoDnt5r0o2ll4e/r . *ADDITIONAL PINS OMITTED FOR CLARITY. 06803-014 Figure 54. AD5024/AD5044/AD5064/AD5064-1 to 80C512/80L51 Interface AD5044/AD5064/AD5064-1, and the MOSI output drives the AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE serial data line of the DAC. Interface 68HC11/68L11* AD5024/ Figure 55 shows an interface between the AD5024/AD5044/ AD5044/ AD5064/ AD5064/AD5064-1 and any MICROWIRE-compatible device. AD5064-1* Serial data is shifted out on the falling edge of the serial clock and is PC7 SYNC clocked into the AD5024/AD5044/AD5064/AD5064-1 on the SCK SCLK rising edge of the SCLK. MOSI DIN *ADDITIONAL PINS OMITTED FOR CLARITY. 06803-013 MICROWIRE* AADD55002444// Figure 53. AD5024/AD5044/AD5064/AD5064-1 to 68HC11/68L11 Interface AD5064/ AD5064-1* The SYNC signal is derived from a port line (PC7). The setup CS SYNC conditions for correct operation of this interface are as follows: SK DIN The 68HC11/68L11 is configured with its CPOL bit as 0, and its SO SCLK CSYPNHCA lbinite a iss 1ta. kWenh elonw d a(PtaC i7s )b. eWinhge tnr atnhsem 6i8tHteCd 1to1 /t6h8eL D11A iCs , the *ADDITIONAL PINS OMITTED FOR CLARITY. 06803-015 Figure 55. AD5024/AD5044/AD5064/AD5064-1 to MICROWIRE Interface configured as described previously, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5024/AD5044/ AD5064, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. Rev. G | Page 25 of 28

AD5024/AD5044/AD5064 Data Sheet APPLICATIONS INFORMATION USING A REFERENCE AS A POWER SUPPLY This is an output voltage range of ±5 V, with 0x0000 corre- sponding to a −5 V output, and 0xFFFF corresponding to a Because the supply current required by the AD5024/AD5044/ +5 V output. AD5064/AD5064-1 is extremely low, an alternative option is to R2 = 10kΩ use a voltage reference to supply the required voltage to the devices (see Figure 56). This is especially useful if the power supply is +5V quite noisy or if the system supply voltages are at some value +5V R1 = 10kΩ oa tshteera dthya snu 5p pVl y( fvoor letaxgame fpolre ,t 1h5e VA)D. T50h2e 4v/oAltDag5e0 r4e4fe/AreDnc5e0 o6u4t/p uts VREF 5V VREFA AADD88663389/ ±5V VDD VOUTA AD5064-1. If the low dropout REF195 is used, it must supply 10µF 0.1µF AD5024/ 3 mA of current to the AD5024/AD5044/AD5064/AD5064-1, AD5044/ –5V AD5064/ with no load on the output of the DAC. When the DAC output is AD5064-1 loaded, the REF195 also needs to supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is 3 mA + (5 V/5 kΩ) = 4 mA SERIAL3- IWNITREERFACE 06803-017 The load regulation of the REF195 is typically 2 ppm/mA, Figure 57. Bipolar Operation which results in a 3 ppm (15 µV) error for the 4 mA current USING THE AD5024/AD5044/AD5064/AD5064-1 drawn from it. This corresponds to a 0.196 LSB error. WITH A GALVANICALLY ISOLATED INTERFACE 15V In process control applications in industrial environments, it 5V is often necessary to use a galvanically isolated interface to REF195 protect and isolate the controlling circuitry from any hazardous common-mode voltages that can occur in the area where the VDD S3E-WRIIRAEL SSYCNLCK AADD55002444// VOUT = 0V TO 5V D2.A5 CkV i.s Tfuhnec AtiDon5i0n2g4. /iACDou5p0l4e4r/®A pDro5v0id64es/A isDol5a0ti6o4n- 1in u seex cae 3ss- wofir e INTERFACE AD5064/ DIN AD5064-1 serial logic interface, so the ADuM1300 three-channel digital 06803-016 ipsoowlaetor rs uppropvlyid teos t thhee d reevqiucier eadls ois onleaetdiosn t o(s beee iFsiogluatreed 5, 8w).h Tichhe is Figure 56. REF195 as a Power Supply to the AD5024/AD5044/AD5064/AD5064-1 done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the BIPOLAR OPERATION AD5024/AD5044/AD5064/AD5064-1. The AD5024/AD5044/AD5064/AD5064-1 have been designed for single-supply operation, but a bipolar output range is also 5V REGULATOR possible using the circuit shown in Figure 57. The circuit gives an POWER 10µF 0.1µF output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD8638 or an AD8639 as the output amplifier. VDD Assuming VDD = VREF, the output voltage for any input code can SCLK VIA VOA SCLK AD5024/ be calculated as follows: AD5044/ ADuM1300 AD5064/   D  R1+R2 R2 AD5064-1 VOUT =VDD×65,536× R1 −VDD×R1 SDI VIB VOB SYNC VOUTx where D represents the input code in decimal (0 to 65,535). DATA VIC VOC DIN With VDD = 5 V, R1 = R2 = 10 kΩ, GND V =10×D −5V 06803-018 OUT 65,536 Figure 58. AD5024/AD5044/AD5064/AD5064-1 with a Galvanically Isolated Interface Rev. G | Page 26 of 28

Data Sheet AD5024/AD5044/AD5064 OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.A20X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 59. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 60. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. G | Page 27 of 28

AD5024/AD5044/AD5064 Data Sheet ORDERING GUIDE Model1 Temperature Range Accuracy Resolution Package Description Package Option AD5024BRUZ −40°C to +125°C ±0.5 LSB INL 12 Bits 16-Lead TSSOP RU-16 AD5024BRUZ-REEL7 −40°C to +125°C ±0.5 LSB INL 12 Bits 16-Lead TSSOP RU-16 AD5044BRUZ −40°C to +125°C ±1 LSB INL 14 Bits 16-Lead TSSOP RU-16 AD5044BRUZ-REEL7 −40°C to +125°C ±1 LSB INL 14 Bits 16-Lead TSSOP RU-16 AD5064ARUZ-1 −40°C to +125°C ±4 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064ARUZ-1REEL7 −40°C to +125°C ±4 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064BRUZ-1 −40°C to +125°C ±1 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064BRUZ-1REEL7 −40°C to +125°C ±1 LSB INL 16 Bits 14-lead TSSOP RU-14 AD5064BRUZ −40°C to +125°C ±1 LSB INL 16 Bits 16-Lead TSSOP RU-16 AD5064BRUZ-REEL7 −40°C to +125°C ±1 LSB INL 16 Bits 16-Lead TSSOP RU-16 EVAL-AD5064-1EBZ 14-Lead TSSOP Evaluation Board EVAL-AD5064EBZ 16-Lead TSSOP Evaluation Board 1 Z = RoHS Compliant Part. ©2008–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06803-0-6/16(G) Rev. G | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD5064-1EBZ EVAL-AD5064EBZ AD5064BRUZ-1REEL7 AD5044BRUZ-REEL7 AD5024BRUZ AD5024BRUZ-REEL7 AD5044BRUZ AD5064ARUZ-1REEL7 AD5064BRUZ-REEL7 AD5064BRUZ AD5064ARUZ-1 AD5064BRUZ-1