a Variable Resolution, Resolver-to-Digital Converter AD2S83 FEATURES FUNCTIONAL BLOCK DIAGRAM Tracking R/D Converter High Accuracy Velocity Output REFERENCE I/P OFFSET ADJUST High Max Tracking Rate 1040 RPS (10 Bits) HF FILTER C3 +12V R9 –12V 44-Lead PLCC Package 10-, 12-, 14-, or 16-Bit Resolution Set by User C1 R2 R3 R8 Ratiometric Conversion R1 C2 BANDWIDTH SELECTION Stabilized Velocity Reference R4 Dynamic Performance Set by User AC ERROR O/P INTEGRATOR C5 DEMOD I/P R5 Industrial Temperature Range O/P SIN A1 C4 APPLICATIONS GSNIGD S SWEIGTCMHEINNTG R – 2R DAC A3 SEPNHSAISTIEVE INTEGRATOR VELOCITY DC and AC Servo Motor Control COS A2 DETECTOR O/P SIGNAL Process Control GND AD2S83 R6 TRACKING NRoubmoetricicsal Control of Machine Tools RCILPOPCLKE 16-BIT UP/DOWN COUNTER VCI/OP RSEALTEECTION Axis Control +12V OUTPUT DATA LATCH V TCROA N+ S DFAERTA C7 –12V LOGIC VCO O/P R7 3K3 DATASC1SC2ENABLE BYTE 5V DIG BUSYDIRECTION INHIBIT C6 LOAD 16 SELECT GND 390pF DATA BITS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD2S83 is a monolithic 10-, 12-, 14-, or 16-bit tracking High Accuracy Velocity Output. A precision analog velocity resolver-to-digital converter. signal with a typical linearity of ±0.1% and reversion error less than ±0.3% is generated by the AD2S83. The provision of this The converter allows users to select their own resolution and dynamic signal removes the need for mechanical tachogenerators used in performance with external components. The converter allows users to servo systems to provide loop stabilization and speed control. select the resolution to be 10, 12, 14, or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) Resolution Set by User. Two control pins are used to select when set to 10-bit resolution. the resolution of the AD2S83 to be 10, 12, 14 or 16 bits allow- ing optimum resolution for each application. The AD2S83 converts resolver format input signals into a paral- lel natural binary digital word using a ratiometric tracking con- Ratiometric Tracking Conversion. This technique provides version method. This ensures high noise immunity and tolerance continuous output position data without conversion delay. It of long leads allowing the converter to be located remote from also provides noise immunity and tolerance of harmonic distor- the resolver. tion on the reference and input signals. The position output from the converter is presented via 3-state Dynamic Performance Set by the User. By selecting external output pins which can be configured for operations with 8- or resistor and capacitor values the user can determine band- 16-bit bus. BYTE SELECT, ENABLE and INHIBIT pins width, maximum tracking rate and velocity scaling of the ensure easy data transfer to 8- and 16-bit data bus, and outputs converter to match the system requirements. The component are provided to allow for cycle or pitch counting in external values are easy to select using the free component selection counters. software design aid. A precise analog signal proportional to velocity is also available MODELS AVAILABLE and will replace a tachogenerator. Information on the models available is given in the Ordering The AD2S83 operates over reference frequencies in the range Guide. 0 Hz to 20,000 Hz. REV.E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD2S83–SPECIFICATIONS ((cid:1)V = (cid:1)12 V dc (cid:1) 5%; V = 5 V dc (cid:1) 10%; T = –40(cid:3)C to +85(cid:3)C) S L A Parameter Conditions Min Typ Max Unit SIGNAL INPUTS (SIN, COS) Frequency1 0 20,000 Hz Voltage Level 1.8 2.0 2.2 V rms Input Bias Current 60 150 nA Input Impedance 1.0 MΩ REFERENCE INPUT (REF) Frequency 0 20,000 Hz Voltage Level 1.0 8.0 V pk Input Bias Current 60 150 nA Input Impedance 1.0 MΩ PERFORMANCE Repeatability 1 LSB Allowable Phase Shift (Signals to Reference) –10 +10 Degree Max Tracking Rate 10 Bits 1040 rps 12 Bits 260 rps 14 Bits 65 rps 16 Bits 16.25 rps Bandwidth User Selectable ACCURACY Angular Accuracy A, I (cid:1)8 +1 LSB arc min Monotonicity Guaranteed Monotonic Missing Codes (16-Bit Resolution) A, I 4 Codes VELOCITY SIGNAL LINEARITY2, 3, 4 AD2S83AP 0 kHz–500 kHz –40°C to +85°C ±0.15 (cid:1)0.25 % FSR 0.5 MHz–1 MHz –40°C to +85°C ±0.25 (cid:1)1.0 % FSR AD2S83IP 0 kHz–500 kHz –40°C to +85°C ±0.25 (cid:1)0.5 % FSR 0.5 MHz–1 MHz –40°C to +85°C ±0.25 (cid:1)1.0 % FSR Reversion Error AD2S83AP –40°C to +85°C ±0.5 (cid:1)1.0 % O/P AD2S83IP –40°C to +85°C ±1.0 (cid:1)1.5 % O/P DC Zero Offset5 ±3 mV Gain Scaling Accuracy ±1.5 (cid:1)3 % FSR Output Voltage 1 mA Load ±8 V Dynamic Ripple Mean Value 1.0 % rms O/P INPUT/OUTPUT PROTECTION Analog Inputs Overvoltage Protection ±8 V Analog Outputs Short Circuit O/P Protection ±5.6 ±8 ±10.4 mA DIGITAL POSITION Resolution 10, 12, 14, and 16 Bits Output Format Bidirectional Natural Binary Load 3 LSTTL INHIBIT6 Sense Logic LO to INHIBIT Time to Stable Data 240 390 490 ns ENABLE6 Logic LO Enables Position Output Logic HI Outputs in High ENABLE6/Disable Time Impedance State 35 110 ns BYTE SELECT6 Sense Logic HI MS Byte DB1–DB8 Logic LO LS Byte DB1–DB8 Time to Data Available 60 140 ns SHORT CYCLE INPUTS Internally Pulled High via 100 kΩ to +V S SC1 SC2 0 0 10-Bit Resolution 0 1 12-Bit Resolution 1 0 14-Bit Resolution 1 1 16-Bit Resolution –2– REV. E

AD2S83 Parameter Conditions Min Typ Max Unit COMPLEMENT Internally Pulled High via 100 kΩ to +V . Logic LO to Activate; S No Connect for Normal Operation DATA LOAD Sense Internally Pulled High via 100 kΩ 150 300 ns to +V . Logic LO Allows S Data to be Loaded into the Counters from the Data Lines BUSY6, 7 Sense Logic HI When Position O/P Changing Width 150 350 ns Load Use Additional Pull-Up (See Figure 2) 1 LSTTL DIRECTION6 Sense Logic HI Counting Up Logic LO Counting Down Max Load 3 LSTTL RIPPLE CLOCK6 Sense Logic HI All 1s to All 0s All 0s to All 1s Width Dependent on Input Velocity 300 ns Reset Before Next Busy Load 3 LSTTL DIGITAL INPUTS Input High Voltage, V INHIBIT, ENABLE 2.0 V IH DB1–DB16, Byte Select ±V = ±11.4 V, V = 5.0 V S L Input Low Voltage, V INHIBIT, ENABLE 0.8 V IL DB1–DB16, Byte Select ±V = ±12.6 V, V = 5.0 V S L DIGITAL INPUTS Input High Current, I INHIBIT, ENABLE (cid:1)100 µA IH DB1–DB16 ±V = ±12.6 V, V = 5.5 V S L Input Low Current, I INHIBIT, ENABLE (cid:1)100 µA IL DB1–DB16, Byte Select ±V = ±12.6 V, V = 5.5 V S L DIGITAL INPUTS Low Voltage, V ENABLE = HI 1.0 V IL SC1, SC2, DATA LOAD ±V = ±12.0 V, V = 5.0 V S L Low Current, I ENABLE = HI –400 µA IL SC1, SC2, DATA LOAD ±V = ±12.0 V, V = 5.0 V S L DIGITAL OUTPUTS High Voltage, V DB1–DB16 2.4 V OH RIPPLE CLK, DIR ±V = ±12.0 V, V = 4.5 V S L I = 100 µA OH Low Voltage, V DB1–DB16 0.4 V OL RIPPLE CLK, DIR ±V = ±12.0 V, V = 5.5 V S L I = 1.2 mA OL NOTES 1Angular accuracy is not guaranteed <50 Hz reference frequency. 2Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz. 3Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.” 4Worst case reversion error at temperature extremes. 5Velocity output offset dependent on value for R6. 6Refer to timing diagram. 7Busy pulse guaranteed up to a VCO rate of 900kHz. All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. REV. E –3–

AD2S83–SPECIFICATIONS ((cid:1)V = (cid:1)12 V dc (cid:1) 5%; V = 5 V dc (cid:1) 10%; T = –40(cid:3)C to +85(cid:3)C) S L A Parameter Conditions Min Typ Max Unit THREE-STATE LEAKAGE DB1–DB16 Only Current I ±V = ±12.0 V, V = 5.5 V (cid:1)20 µA L S L V = 0 V OL ±V = ±12.0 V, V = 5.5 V (cid:1)20 µA S L V = 5.0 V OH RATIO MULTIPLIER AC Error Output Scaling 10 Bit 177.6 mV/Bit 12 Bit 44.4 mV/Bit 14 Bit 11.1 mV/Bit 16 Bit 2.775 mV/Bit PHASE SENSITIVE DETECTOR Output Offset Voltage 12 mV Gain In Phase w.r.t. REF –0.882 –0.9 –0.918 V rms/V dc In Quadrature w.r.t. REF ±0.02 V rms/V dc Input Bias Current 60 150 nA Input Impedance 1.0 MΩ Input Voltage ±8 V INTEGRATOR Open-Loop Gain At 10 kHz 57 60 63 dB Dead Zone Current (Hysteresis) 90 100 110 nA/LSB Input Offset Voltage 1 5 mV Input Bias Current 60 150 nA Output Voltage Range (cid:1)8 V VCO Maximum Rate 1.1 MHz VCO Rate +ve DIR 8.25 8.50 8.75 kHz/µA –ve DIR 8.25 8.50 8.75 kHz/µA VCO Power Supply Sensitivity Rate +V +0.5 %/V S –V –0.5 %/V S Input Offset Voltage 3 mV Input Bias Current 12 50 nA Input Bias Current Tempco +0.22 nA/°C Linearity of Absolute Rate AD2S83AP 0 kHz–500 kHz ±0.15 (cid:1)0.25 % FSR 0.5 MHz–1 MHz ±0.25 (cid:1)1.0 % FSR AD2S83IP 0 kHz–500 kHz ±0.25 (cid:1)0.5 % FSR 0.5 MHz–1 MHz ±0.25 (cid:1)1.0 % FSR Reversion Error AD2S83AP ±0.5 (cid:1)1.0 % Output AD2S83IP ±1.0 (cid:1)1.5 % Output POWER SUPPLIES Voltage Levels +V +11.4 +12.6 V S –V –11.4 –12.6 V S +V +4.5 +5 +V V L S Current ±I ±V @ ±12 V ±12 (cid:1)23 mA S S ±I ±V @ ±12.6 V ±19 (cid:1)30 mA S S ±I +V @ ±5.0 V ±0.5 (cid:1)1.5 mA L L All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. ORDERING GUIDE Temperature Package Package Model Range Accuracy Description Option AD2S83AP –40°C to +85°C 8 arc min Plastic Leaded Chip Carrier P-44A AD2S83IP –40°C to +85°C 8 arc min Plastic Leaded Chip Carrier P-44A –4– REV. E

AD2S83 ABSOLUTE MAXIMUM RATINGS1 (with respect to GND) PIN FUNCTION DESCRIPTIONS +V 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V dc S –V 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –13 V dc Pin S +V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +V Nos. Mnemonic Description L S Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 1 DEMOD O/P Demodulator Output SIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –V S 2 REFERENCE I/P Reference Signal Input COS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –V S 3 AC ERROR O/P Ratio Multiplier Output Any Logical Input . . . . . . . . . . . . . . . . . . –0.4 V dc to +V dc L Demodulator Input . . . . . . . . . . . . . . . . . . . . . . . +13 V to –V 4 COS Cosine Input S Integrator Input . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –V 5 ANALOG GND Power Ground S VCO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 V to –VS 6 SIGNAL GND Resolver Signal Ground Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW 7 SIN Sine Input Operating Temperature 8 +V Positive Power Supply Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C S Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C 10–25 DB1–DB16 Parallel Output Data Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C 26 +VL Logic Power Supply 27 ENABLE Logic HI—Output Data Pins in CAUTION 1Absolute Maximum Ratings are those values beyond which damage to the device High Impedance State may occur. Logic LO—Presents Active Data 2Correct polarity voltages must be maintained on the +V and –V pins. to the Output Pins S S RECOMMENDED OPERATING CONDITIONS 28 BYTE SELECT Logic HI—Most Significant Byte to Power Supply Voltage (+V , –V ) . . . . . . . . . . ±12 V dc ± 5% DB1–DB8 Power Supply Voltage V .S . . . .S . . . . . . . . . . . . +5 V dc ± 10% Logic LO—Least Significant Byte L to DB1–DB8 Analog Input Voltage (SIN and COS) . . . . . . . 2 V rms ± 10% 30 INHIBIT Logic LO Inhibits Data Transfer Analog Input Voltage (REF) . . . . . . . . . . . . . . 1 V to 8 V peak to Output Latches Signal and Reference Harmonic Distortion . . . . . . 10% (max) PhaseShiftBetweenSignalandReference . . . ±10 Degrees(max) 31 DIGITAL GND Digital Ground Ambient Operating Temperature Range 32, 33 SC2–SC1 Select Converter Resolution Industrial (AP, IP) . . . . . . . . . . . . . . . . . . . –40°C to +85°C 34 DATA LOAD Logic LO DB1–DB16 Inputs Logic HI DB1–DB16 Outputs PIN CONFIGURATION 35 COMPLEMENT Active Logic LO 36 BUSY Converter Busy, Data not Valid SIGNAL GND ANALOG GND COS I/P AC ERROR O/P REF I/P DEMOD O/P DEMOD I/P INTEGRATOR I/P INTEGRATOR O/P VCO O/P VCO I/P 3387 RDIIPRPELCET CIOLNOCK LWIPCnoohphsgauiiitnlctiegv SSeeBsitPug afnustreyoals mlDHe R WeI1ofsith nateoetnis oA CDnllo i0rnesvc eotrirto eVnri cOoefu Vtperusta 6 5 4 3 2 1 44 43 42 41 40 39 –V Negative Power Supply S SIN I/P 7 PIDINE N1TIFIER 39 –VS 40 VCO I/P VCO Input +VS 8 38 RIPPLE CLOCK 41 VCO O/P VCO Output NC 9 37 DIRECTION (MSB) DB110 36 BUSY 42 INTEGRATOR O/P Integrator Output DB211 AD2S83 35 COMP 43 INTEGRATOR I/P Integrator Input DB312 TOP VIEW 34 DATA LOAD 44 DEMOD I/P Demodulator Input (Not to Scale) DB413 33 SC1 DB514 32 SC2 DB615 31 DIGITAL GND DB716 30 INHIBIT DB8 17 29 NC 18 19 20 21 22 23 24 25 26 27 28 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 +VL ABLE LECT NC = NO CONNECT (LSB) EN YTE SE B CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD2S83 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE REV. E –5–

AD2S83 Bit Weight Table When more than one converter is used on a card, separate de- coupling capacitors should be used for each converter. Binary Resolution Degrees Minutes Seconds The resolver connections should be made to the SIN and COS Bits (N) (NN) /Bit /Bit /Bit inputs, REFERENCE INPUT and SIGNAL GROUND as 0 1 360.0 21600.0 1296000.0 shown in Figure 11 and described in the Connecting the 1 2 180.0 10800.0 648000.0 Resolver section. 2 4 90.0 5400.0 324000.0 3 8 45.0 2700.0 162000.0 The two signal ground wires from the resolver should be joined 4 16 22.5 1350.0 81000.0 at the SIGNAL GROUND pin of the converter to minimize the coupling between the sine and cosine signals. For this reason it 5 32 11.25 675.0 40500.0 is also recommended that the resolver is connected using indi- 6 64 5.625 337.5 20250.0 vidually screened twisted pair cables with the sine, cosine and 7 128 2.8125 168.75 10125.0 8 256 1.40625 84.375 5062.5 reference signals twisted separately. 9 512 0.703125 42.1875 2531.25 SIGNAL GROUND and ANALOG GROUND are connected 10 1024 0.3515625 21.09375 1265.625 internally. ANALOG GROUND and DIGITAL GROUND 11 2048 0.1757813 10.546875 632.8125 must be connected externally and as close to the converter as 12 4096 0.0878906 5.273438 316.40625 possible. 13 8192 0.0439453 2.636719 158.20313 The external components required should be connected as 14 16384 0.0219727 1.318359 79.10156 shown in Figure 1. 15 32768 0.0109836 0.659180 39.55078 16 65536 0.0054932 0.329590 19.77539 CONVERTER RESOLUTION 17 131072 0.0027466 0.164795 9.88770 Two major areas of the AD2S83 specification can be selected by 18 262144 0.0013733 0.082397 4.94385 the user to optimize the total system performance. The resolu- tion of the digital output is set by the logic state of the inputs CONNECTING THE CONVERTER SC1 and SC2 to be 10, 12, 14 or 16 bits; and the dynamic char- The power supply voltages connected to +V and –V pins acteristics of bandwidth and tracking rate are selected by the S S should be +12 V dc and –12 V dc and must not be reversed. choice of external components. The voltage applied to V can be +5 V dc to +V . L S The choice of the resolution will affect the values of R4 and R6 It is recommended that the decoupling capacitors are connected which scale the inputs to the integrator and the VCO respec- in parallel between the power lines +V , –V and ANALOG tively (see Component Selection section). If the resolution is S S GROUND adjacent to the converter. Recommended values are changed, then new values of R4 and R6 must be switched into 100 nF (ceramic) and 10 µF (tantalum). Also capacitors of the circuit. 100 nF and 10 µF should be connected between +V and L Note: When changing resolution under dynamic conditions, do DIGITAL GROUND adjacent to the converter. it when the BUSY is low, i.e., when data is not changing. REFERENCE I/P OFFSET ADJUST R9 HF FILTER C3 +12V –12V R3 R8 C1 R2 C2 BANDWIDTH R1 SELECTION R4 AC ERROR O/P INTEGRATOR C5 I/P DEMOD R5 O/P SIN A1 C4 PHASE SIG GND VELOCITY SEGMENT R - 2R DAC A3 SENSITIVE INTEGRATOR SIGNAL COS A2 SWITCHING DETECTOR O/P GND AD2S83 R6 TRACKING RIPPLE VCO RATE CLOCK 16-BIT UP/DOWN COUNTER I/P SELECTION VCO + DATA C7 +12V TRANSFER 150pF OUTPUT DATA LATCH LOGIC –12V VCO O/P R7 3K3 DATA SC1 SC2 ENABLE BYTE 5V DIG BUSYDIRECTION INHIBIT C6 LOAD 16 DATA BITS SELECT GND 390pF Figure 1.Connection Diagram –6– REV. E

AD2S83 CONVERTER OPERATION The direction of input rotation is indicated by the DIRECTION When connected in a circuit such as shown in Figure 10, the (DIR) logic output. This direction data is always valid in advance AD2S83 operates as a tracking resolver-to-digital converter. of a RIPPLE CLOCK pulse and, as it is internally latched, only The output will automatically follow the input for speeds up to changing state (1 LSB min change in input) with a correspond- the selected maximum tracking rate. No convert command is ing change in direction. necessary as the conversion is automatically initiated by each Both the RIPPLE CLOCK pulse and the DIRECTION data LSB increment, or decrement, of the input. Each LSB change of are unaffected by the application of the INHIBIT. The static the converter initiates a BUSY pulse. positional accuracy quoted is the worst case error that can occur The AD2S83 is remarkably tolerant of input amplitude and over the full operating temperature excluding the effects of frequency variation because the conversion depends only on the offset signals at the INTEGRATOR INPUT (which can be ratio of the input signals. Consequently there is no need for trimmed out—see Figure 1), and with the following conditions: accurate, stable oscillator to produce the reference signal. The input signal amplitudes are within 10% of the nominal; phase inclusion of the phase sensitive detector in the conversion loop shift between signal and reference is less than 10 degrees. ensures high immunity to signals that are not phase or frequency These operating conditions are selected primarily to establish a coherent or are in quadrature with the reference signal. repeatable acceptance test procedure which can be traced to national standards. In practice, the AD2S83 can be used well SIGNAL CONDITIONING outside these operating conditions providing the above points The amplitude of the SINE and COSINE signal inputs should are observed. be maintained within 10% of the nominal values if full perfor- mance is required from the velocity signal. VELOCITY SIGNAL The digital position output is relatively insensitive to amplitude The tracking converter technique generates an internal signal at variation. Increasing the input signal levels by more than 10% the output of the integrator (INTEGRATOR OUTPUT) that is will result in a loss in accuracy due to internal overload. Reduc- proportional to the rate of change of the input angle. This is a ing levels will result in a steady decline in accuracy. With the dc analog output referred to as the VELOCITY signal. signal levels at 50% of the correct value, the angular error will It is recommended that the velocity output be buffered. increase to an amount equivalent to 1.3 LSB. At this level the repeatability will also degrade to 2 LSB and the dynamic response The sense is positive for an increasing angular input and nega- will also change, since the dynamic characteristics are propor- tive for decreasing angular input. The full-scale velocity output tional to the signal level. is ±8 V dc. The output velocity scaling and tracking rate are a function of the resolution of the converter; this is summarized The AD2S83 will not be damaged if the signal inputs are below. applied to the converter without the power supplies and/or the reference. Max Tracking Nominal Scaling Res Rate (rps) (rps/V dc) REFERENCE INPUT The amplitude of the reference signal applied to the converter’s 10 1040 130 input is not critical, but care should be taken to ensure it is kept 12 260 32.5 within the recommended operating limits. 14 65 8.125 The AD2S83 will not be damaged if the reference is supplied to 16 16.25 2.03 the converter without the power supplies and/or the signal (Velocity O/P = ±8 V dc nominal) inputs. The output velocity can be suitably scaled and used to replace a conventional DC tachogenerator. For more detailed information HARMONIC DISTORTION see the AD2S83 as a Silicon Tachogenerator section. The amount of harmonic distortion allowable on the signal and reference lines is 10%. DC ERROR SIGNAL Square waveforms can be used but the input levels should be The signal at the output of the phase sensitive detector adjusted so that the average value is 1.9 V rms. (For example, a (DEMODULATOR OUTPUT) is the signal to be nulled by square wave should be 1.9 V peak.) Triangular and sawtooth the tracking loop and is, therefore, proportional to the error waveforms should have a amplitude of 2 V rms. between the input angle and the output digital angle. As the Note: The figure specified of 10% harmonic distortion is for converter is a Type 2 servo loop, the demodulator output signal calibration convenience only. will increase if the output fails to track the input for any reason. This is an indication that the input has exceeded the maximum POSITION OUTPUT tracking rate of the converter or, due to some internal or exter- The resolver shaft position is represented at the converter out- nal malfunction, the converter is unable to reach a null. By con- put by a natural binary parallel digital word. As the digital posi- necting two external comparators, this voltage can be used as a tion output of the converter passes through the major carries, “built-in-test.” i.e., all “1s” to all “0s” or the inverse, a RIPPLE CLOCK (RC) logic output is initiated indicating that a revolution or a pitch of the input has been completed. REV. E –7–

AD2S83 COMPONENT SELECTION 4. Maximum Tracking Rate (R6) The following instructions describe how to select the external The VCO input resistor R6 sets the maximum tracking rate components for the converter in order to achieve the required of the converter and hence the velocity scaling as at the max bandwidth and tracking rate. In all cases the nearest “preferred tracking rate, the velocity output will be 8 V. value” component should be used, and a 5% tolerance will not Decide on your maximum tracking rate, “T,” in revolutions degrade the overall performance of the converter. Care should per second. When setting the value for R6, it should be be taken that the resistors and capacitors will function over the remembered that the linearity of the velocity output is required operating temperature range. The components should specified across 0 kHz–500 kHz and 500 kHz–1000 kHz. be connected as shown in Figure 1. The following conversion can be used to determine the Free PC compatible software is available to help users select the corresponding rps: optimum component values for the AD2S83, and display the transfer gain, phase and small step response. VCO Rate(Hz) rps= N For more detailed information and explanation, see the Circuit 2 Functions and Dynamic Performance section. Note that “T” must not exceed the maximum tracking rate 1. HF Filter (R1, R2, C1, C2) or 1/16 of the reference frequency. The function of the HF filter is to remove any dc offset and to reduce the amount of noise present on the signal inputs to 6.81×1010 the AD2S83, reaching the Phase Sensitive Detector and R6= Ω affecting the outputs. R1 and C2 may be omitted—in which T ×n case R2 = R3 and C1 = C3, calculated below—but their use where n = bits per revolution is particularly recommended if noise from switch mode = 1,024 for 10 bits resolution power supplies and brushless motor drive is present. = 4,096 for 12 bits Values should be chosen so that = 16,384 for 14 bits = 65,536 for 16 bits 15kΩ≤R1=R2≤56kΩ 5. Closed-Loop Bandwidth Selection (C4, C5, R5) 1 a. Choose the closed-loop bandwidth (f ) required C1=C2= BW 2πR1f ensuring that the ratio of reference frequency to band- REF width does not exceed the following guidelines: and f = Reference Frequency (Hz) REF Resolution Ratio of Reference Frequency/Bandwidth 10 2.5 : 1 This filter gives an attenuation of three times at the input to 12 4 : 1 the phase sensitive detector. 14 6 : 1 2. Gain Scaling Resistor (R4) (See Phase Sensitive Demodula- 16 7.5 : 1 tor section.) Typical values may be 100 Hz for a 400 Hz reference fre- If R1, C2 are used: quency and 500 Hz to 1000 Hz for a 5 kHz reference frequency. E 1 R4= DC × Ω 100×10−9 3 b. Select C4 so that 21 C4= F where 100 × 10–9 = current/LSB R6× f 2 If R1, C2 are not used: BW E with R6 in Ω and f , in Hz selected above. R4= DC Ω BW 100×10–9 c. C5 is given by where E = 160 × 10–3 for 10 bits resolution C 5=5×C4 DC = 40 × 10–3 for 12 bits d. R5 is given by = 10 × 10–3 for 14 bits 4 = 2.5 × 10–3 for 16 bits R5= Ω 2×π× f ×C5 = Scaling of the DC ERROR in volts/LSB BW 3. AC Coupling of Reference Input (R3, C3) 6. VCO Phase Compensation Select R3 and C3 so that there is no significant phase shift at The following values of C6 and R7 should be connected as the reference frequency. That is, close as possible to the VCO output, Pin 41. R3=100kΩ C 6=390 pF, R7=3.3kΩ 7. VCO Optimization 1 C3> F To optimize the performance of the VCO a capacitor, C7, R3× fREF should be placed across the VCO input and output, Pins 40 with R3 in Ω. and 41. C7=150 pF –8– REV. E

AD2S83 8. Offset Adjust BYTE SELECT Input Offsets and bias currents at the integrator input can cause an The BYTE SELECT input selects the byte of the position data additional positional offset at the output of the converter of to be presented at the data output DB1 to DB8. The least sig- 1 arc minute typical, 5.3 arc minutes maximum. If this can be nificant byte will be presented on data output DB9 to DB16 tolerated, then R8 and R9 can be omitted from the circuit. (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S83 If fitted, the following values of R8 and R9 should be used: is used with a resolution less than 16 bits the unused data lines R8=4.7MΩ,R9=1MΩ potentiometer are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data To adjust the zero offset, ensure the resolver is disconnected output DB1 and DB8. A logic “LO” will present the least sig- and all the external components are fitted. Connect the nificant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will COS pin to the REFERENCE INPUT and the SIN pin to duplicate data outputs 9 to 16. the SIGNAL GROUND and with the power and reference applied, adjust the potentiometer to give all “0s” on the The operation of the BYTE SELECT has no effect on the con- digital output bits. version process of the converter. The potentiometer may be replaced with select on test resistors if preferred. RIPPLE CLOCK As the output of the converter passes through the major carry, i.e., all “1s” to all “0s” or the converse, a positive going edge on DATA TRANSFER the RIPPLE CLOCK (RC) output is initiated indicating that a To transfer data the INHIBIT input should be used. The data revolution, or a pitch, of the input has been completed. will be valid 490 ns after the application of a logic “LO” to the INHIBIT. This is regardless of the time when the INHIBIT is The minimum pulsewidth of the ripple clock is 300 ns. RIPPLE applied and allows time for an active BUSY to clear. By using CLOCK is normally set high before a BUSY pulse and resets the ENABLE input the two bytes of data can be transferred before the next positive going edge of the next BUSY pulse. after which the INHIBIT should be returned to a logic “HI” The only exception to this is when DIR changes while the state to enable the output latches to be updated. RIPPLE CLOCK is high. Resetting of the RIPPLE clock will BUSY Output only occur if the DIR remains stable for two consecutive posi- The validity of the output data is indicated by the state of the tive BUSY pulse edges. BUSY output. When the input to the converter is changing, the If the AD2S83 is being used in a pitch and revolution counting signal appearing on the BUSY output is a series of pulses at application, the ripple and busy will need to be gated to prevent TTL level. A BUSY pulse is initiated each time the input moves false decrement or increment (see Figure 2). by the analog equivalent of one LSB and the internal counter is incremented or decremented. RIPPLE CLOCK is unaffected by INHIBIT. INHIBIT Input 5V The INHIBIT logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does 10k(cid:4) 1k(cid:4) not interrupt the operation of the tracking loop. Releasing the TO COUNTER INHIBIT automatically generates a BUSY pulse to refresh the IN4148 (CLOCK) RIPPLE 2N3904 output data. CLOCK 0V 5V ENABLE Input The ENABLE input determines the state of the output data. A 5K1 logic “HI” maintains the output data pins in the high imped- IN4148 BUSY ance condition, and the application of a logic “LO” presents the data in the latches to the output pins. The operation of the NOTE: DO NOT USE ABOVE CCT WHEN INHIBIT IS LOW. ENABLE has no effect on the conversion process. Figure 2.Diode Transistor Logic N and Gate REV. E –9–

AD2S83 BUSY VH t 1 RIPPLE CLOCK VL t2 VH t4 VH t3 DATA t5 VL INHIBIT VH t 6 VH t DIR 7 VL t 8 t 9 INHIBIT VL ENABLE VL t10 VH VZ DATA t11 VL SEBLEYCTET VL VH VH DATA t12 t13 VL Figure 3.Digital Timing Parameter T * T * Condition MIN MAX t 150 350 BUSY WIDTH V –V 1 H H t 10 25 RIPPLE CLOCK V to BUSY V 2 H H t 470 580 RIPPLE CLOCK V to Next BUSY V 3 L H t 16 45 BUSY V to DATA V 4 H H t 3 25 BUSY V to DATA V 5 H L t 70 140 INHIBIT V to BUSY V 6 H H t 485 625 MIN DIR V to BUSY V 7 H H t 515 670 MIN DIR V to BUSY V 8 H H t – 490 INHIBIT V to DATA STABLE 9 L t 40 110 ENABLE V to DATA V 10 L H t 35 110 ENABLE V to DATA V 11 L L t 60 140 BYTE SELECT V to DATA STABLE 12 L t 60 125 BYTE SELECT V to DATA STABLE 13 H *ns –10– REV. E

AD2S83 DIRECTION Output CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE The DIRECTION (DIR) output indicates the direction of the The AD2S83 allows the user great flexibility in choosing the input rotation. Any change in the state of DIR precedes the dynamic characteristics of the resolver-to-digital conversion to corresponding BUSY, DATA and RIPPLE CLOCK updates. ensure the optimum system performance. The characteristics DIR can be considered as an asynchronous output and can are set by the external components shown in Figure 1. The make multiple changes in state between two consecutive LSB Component Selection section explains how to select desired update cycles. This occurs when the direction of rotation of the maximum tracking rate and bandwidth values. The following input changes but the magnitude of the rotation is less than 1 LSB. paragraphs explain in greater detail the circuit of the AD2S83 and the variations in the dynamic performance available to the COMPLEMENT user. The COMPLEMENT input is an active low input and is inter- Loop Compensation nally pulled to +V via 100 kΩ. S The AD2S83 (connected as shown in Figure 1) operates as a Strobing DATA LOAD and COMPLEMENT pins to logic LO Type 2 tracking servo loop where the VCO/counter combination will set the logic HI bits of the AD2S83 counter to a LO state. and Integrator perform the two integration functions inherent in Those bits of the applied data which are logic LO will not a Type 2 loop. change the corresponding bits in the AD2S83 counter. Additional compensation in the form of a pole/zero pair is For Example: required to stabilize the loop. Initial Counter State 1 0 1 0 1 This compensation is implemented by the integrator compo- Applied Data Word 1 1 0 0 0 nents (R4, C4, R5, C5). Counter State after DATA LOAD 1 1 0 0 0 The overall response the converter is that of a unity gain second Initial Counter State 1 0 1 0 1 order low-pass filter, with the angle of the resolver as the input Applied Data Word 1 1 0 0 0 and the digital position data as the output. Counter State after DATA LOAD and Complement 0 0 1 0 1 The AD2S83 does not have to be connected as tracking con- In order to read the counter following a DATA LOAD, the verter, parts of the circuit can be used independently. This is procedure below should be followed: particularly true of the Ratio Multiplier which can be used as a control transformer. (For more information contact Motion 1. Place outputs in high impedance state (ENABLE = HI). Control Applications.) 2. Present data to pins. A block diagram of the AD2S83 is given in Figure 4. 3. Pull DATA LOAD and COMPLEMENT pins to ground. 4. Wait 100 ns. 5. Remove data from pins. 6. Remove outputs from high impedance state (ENABLE = LO). 7. Read outputs. R5 C5 AC ERROR C4 SIN (cid:5) SIN (cid:7)t RATIO PHASE R4 SENSITIVE COS (cid:5) SIN (cid:7)t MULTIPLIER A, SIN ((cid:5)–(cid:6)) SIN (cid:7)t DEMODULATOR INTEGRATOR DIGITAL CLOCK (cid:6) R6 DIRECTION VCO VELOCITY Figure 4.Functional Diagram REV. E –11–

AD2S83 Ratio Multiplier Phase Sensitive Demodulator The ratio multiplier is the input section of the AD2S83. This The phase sensitive demodulator is effectively ideal and devel- compares the signal from the resolver (angle θ) to the digital ops a mean dc output at the DEMODULATOR OUTPUT (angle φ) held in the counter. Any difference between these pin of two angles results in an analog voltage at the AC ERROR ±2 2 OUTPUT. This circuit function has historically been called a π ×(DEMODULATOR INPUT rmsvoltage) “Control Transformer” as it was originally performed by an electromechanical device known by that name. for sinusoidal signals in phase or antiphase with the reference The AC ERROR signal is given by (for a square wave the DEMODULATOR OUTPUT voltage A1 sin (θ–φ) sin ωt will equal the DEMODULATOR INPUT). This provides a where ω = 2 π f signal at the DEMODULATOR OUTPUT which is a dc level REF proportional to the positional error of the converter. f = reference frequency REF DC Error Scaling= 160 mV/bit (10-bit resolution) A1 = the gain of the ratio multiplier stage = 14.5. = 40 mV/bit (12-bit resolution) So for 2 V rms inputs signals = 10 mV/bit (14-bit resolution) AC ERROR output in volts/(bit of error) = 2.5 mV/bit (16-bit resolution) When the tracking loop is closed, this error is nulled to zero 360 =2×sin  ×A1 unless the converter input angle is accelerating.  n  Integrator where n = bits per rev The integrator components (R4, C4, R5, C5) are external to the = 1,024 for 10-bit resolution AD2S83 to allow the user to determine the optimum dynamic = 4,096 for 12-bit resolution characteristics for any given application. The Component = 16,384 for 14-bit resolution Selection section explains how to select components for a = 65,536 for 16-bit resolution chosen bandwidth. giving an AC ERROR output Since the output from the integrator is fed to the VCO INPUT, = 178 mV/bit @ 10-bit resolution it is proportional to velocity (rate of change of output angle) and = 44.5 mV/bit @ 12-bit resolution can be scaled by selection of R6, the VCO input resistor. This is = 11.125 mV/bit @ 14-bit resolution explained in the Voltage Controlled Oscillator (VCO) section = 2.78 mV/bit @ 16-bit resolution below. The ratio multiplier will work in exactly the same way whether To prevent the converter from “flickering” (i.e., continually the AD2S83 is connected as a tracking converter or as a control toggling by ±1 bit when the quantized digital angle, φ, is not an transformer, where data is preset into the counters using the exact representation of the input angle, θ) feedback is internally DATA LOAD pin. applied from the VCO to the integrator input to ensure that the HF Filter VCO will only update the counter when the error is greater than The AC ERROR OUTPUT may be fed to the PSD via a simple or equal to 1 LSB. In order to ensure that this feedback “hys- ac coupling network (R2, C1) to remove any dc offset at this teresis” is set to 1 LSB the input current to the integrator must point. Note, however, that the PSD of the AD2S83 is a wide- be scaled to be 100 nA/bit. Therefore, band demodulator and is capable of aliasing HF noise down to DC Error Scaling (mV/bit ) within the loop bandwidth. This is most likely to happen where R4= the resolver is situated in particularly noisy environments, and 100(nA/bit) the user is advised to fit a simple HF filter R1, C2 prior to the Any offset at the input of the integrator will affect the accuracy phase sensitive demodulator. of the conversion as it will be treated as an error signal and The attenuation and frequency response of a filter will affect the offset the digital output. One LSB of extra error will be added loop gain and must be taken into account in deriving the loop for each 100 nA of input bias current. The method of adjusting transfer function. The suggested filter (R1, C1, R2, C2) is out this offset is given in the Component Selection section. shown in Figure 1 and gives an attenuation at the reference frequency (f ) of three times at the input to the phase sensitive Voltage Controlled Oscillator (VCO) REF demodulator. The VCO is essentially a simple integrator feeding a pair of dc level comparators. Whenever the integrator output reaches one Values of components used in the filter must be chosen to of the comparator threshold voltages, a fixed charge is injected ensure that the phase shift at f is within the allowable signal REF into the integrator input to balance the input current. At the to reference phase shift of the converter. same time the counter is clocking either up or down, dependent on the polarity of the input current. In this way the counter is clocked at a rate proportional to the magnitude of the input current of the VCO. –12– REV. E

AD2S83 During the VCO reset period the input continues to be inte- 12 grated. The reset period is constant at 40 ns. 9 The VCO rate is fixed for a given input current by the VCO scaling factor: 6 = 8.5 kHz/µA 3 T The tracking rate in rps per µA of VCO input current can be LO found by dividing the VCO scaling factor by the number of LSB AIN P 0 changes per rev (i.e., 4096 for 12-bit resolution). G–3 The input resistor R6 determines the scaling between the con- –6 verter velocity signal voltage at the INTEGRATOR OUTPUT pin and the VCO input current. Thus to achieve a 5 V output at –9 100 rps (6000 rpm) and 12-bit resolution the VCO input cur- –12 rent must be: 0.0 0.04 0.1 0.2 0.4 1 2 (100×4096)/(8500) = 48.2 µA FREQUENCY – fBW Figure 5. Gain Plot Thus, R6 would be set to: 5/(48.2 × 10–6) = 103.7 kΩ The velocity offset voltage depends on the VCO input resistor, 180 R6, and the VCO bias current and is given by 135 Velocity Offset Voltage = R6 × (VCO bias current) 90 The temperature coefficient of this offset is given by Velocity Offset Tempco = R6 × (VCO bias current tempco) OT 45 L where the VCO bias current tempco is typically +0.22 nA/°C. E P 0 S A The maximum recommended rate for the VCO is 1.1 MHz H P–45 which sets the maximum possible tracking rate. –90 Since the minimum voltage swing available at the integrator output is ±8 V, this implies that the minimum value for R6 is –135 62 kΩ. As –180 0.0 0.04 0.1 0.2 0.4 1 2 MaxCurrent= 1.1×106 =129µA FREQUENCY – fBW 8.5×103 Figure 6.Phase Plot 8 MinValueR6= =62kΩ 129×10–6 Transfer Function By selecting components using the method outlined in the sec- tion “Component Selection,” the converter will have a critically damped time response and maximum phase margin. The Closed-Loop Transfer Function is given by: θ 14(1+ s ) OUT = N θIN (s +2.4)(s 2 + 3.4s +5.8) N N N where, s , the normalized frequency variable is given by: N 2 s sN = π f BW and f is the closed-loop 3 dB bandwidth (selected by the BW choice of external components). The acceleration constant K , is given approximately by A K =6×(f )2 sec–2 A BW The normalized gain and phase diagrams are given in Figures 5 and 6. REV. E –13–

AD2S83 The small signal step response is shown in Figure 7. The time The only effective way to compensate for dynamic loading from the step to the first peak is t , and the t is the time from effects is to introduce a 2nd order term which will provide the 1 2 the step until the converter is settled to 1 LSB. The times t and motor with an acceleration or deceleration demand signal (see 1 t are given approximately by Figure 9). 2 1 t = 1 f CONTROL BW TERMS t = 5 × R POSITION MOTOR 2 fBW 12 DEMAND + – where R = resolution, i.e., 10, 12, 14 or 16. VELOCITY ELECTRONICS t2 ACTUAL POSITION POSITION FEEDBACK ELECTRONICS SOURCE Figure 9.Position Control and Velocity Control Traditionally this would need to be implemented by using sepa- rate position and speed feedback transducers, e.g., an encoder or resolver and a dc tachogenerator. The AD2S83 can decode TIME t the resolver to provide both velocity and position information. 1 Figure 7. Small Step Response DC Tachogenerator The DC tachogenerator is a small permanent magnet dc The large signal step response (for steps greater than 5 degrees) generator. The output is a dc voltage which is proportional to applies when the error voltage exceeds the linear range of the the speed of the rotor and whose polarity is determined by the converter. direction of rotation. Physically they are similar to a resolver. Typically the converter will take three times longer to reach the Velocity Error Derivation first peak for a 179 degrees step. The velocity error is the difference between the synthesized dc In response to a velocity step, the velocity output will exhibit velocity demand derived from the actual and demand positions the same time response characteristics as outlined above for the and the feedback from the tachogenerator or the AD2S83. The position output. velocity demand is usually derived via a DAC so apart from any quantization noise it is clean. The velocity feedback, therefore, THE AD2S83 AS A SILICON TACHOGENERATOR needs to be as close to a pure dc level as possible. The errors Position Control Using the AD2S83 which determine the quality of the resultant acceleration demand The AD2S83 has been optimized for use as a feedback device to the motor are explained below. for velocity as well as position. A traditional position control Linearity loop shown below compares a demand position with an actual Linearity is the maximum deviation from the ideal straight line to derive a position error and hence a velocity demand. velocity characteristic. The line used is given by: MOTOR v = mx + c POSITION DEMAND + CONTROL where – TERMS v = velocity m = gain scaling x = dc voltage ACTUAL c = zero velocity dc offset POSITION POSITION ELECTRONICS Linearity is generally a function of the input velocity to the FEEDBACK SOURCE tachogenerator or resolver. Figure 8.Position Control Reversion Error Reversion or reversal error is an offset which is dependent on Quality of control may be reduced if the load on a motor varies the direction of rotation of the transducer; e.g., if 10 rps = dynamically. System reaction and compensation for a sudden 1.000 V dc, then –10 rps = 1.003 V dc with +0.3% reversion change in the loading depends on how rapidly the system can error and FSO = ±8 V dc. update the velocity demand to the motor. This can cause rapid acceleration of the motor until the loop updates with a new Zero Velocity DC Offset velocity demand. This is a residual dc offset present at zero input velocity. This can be externally nulled. –14– REV. E

AD2S83 Ripple Content ACCELERATION ERROR Ripple content is due to several factors. Tachogenerators suffer A tracking converter employing a Type 2 servo loop does not from ripple due to the speed of rotation, commutator segments suffer any velocity lag, however, there is an additional error due and the number of poles. The resolver/RDC combination has a to acceleration. This additional error can be defined using the predominant ripple at twice the resolver reference as a result of acceleration constant K of the converter. A the synchronous demodulator and at a frequency twice per Input Acceleration revolution due to the resolver windings mismatch. K = A ErrorinOutput Angle Motor torque pulsations which are a consequence of excessive velocity ripple have a detrimental effect upon the quality of The numerator and denominator must have consistent angular speed control in servo systems. units. For example if KA is in sec–2, then the input acceleration may be specified in degrees/sec2 and the error output in degrees. The resultant “cogging” effect will be particularly noticeable at low speed and when the motor is in the low torque region. KA does not define maximum input acceleration, only the error due to acceleration. The maximum acceleration allowable before the Other undesirable side effects such as the increase in acoustic converter loses track is dependent on the angular accuracy noise from a motor and a temperature rise in the motor stator requirements of the system. windings are possible results of the presence of torque ripple. Angular Accuracy × K = Degrees/sec2 A For more detailed information of the causes and sources of K can be used to predict the output position error for a A errors see the Velocity Errors section. given input acceleration. For example for an acceleration of 100 revs/sec2, K = 2.7 × 106 sec–2 and 12-bit resolution. A AD2S83 COMPARISON WITH DC TACHOGENERATOR Comparative tests of the AD2S83 and a dc tachogenerator were 2 Input acceleration[LSB/sec ] carried out. The tachogenerator was connected at the nondrive ErrorinLSBs = –2 end of the motor shaft with the resolver located behind the drive K [sec ] A shaft of the motor. The AD2S83 was located remotely. The AD2S83 was set up with a 200 Hz bandwidth, reference fre- 100[rev/sec2] × 212 = =0.15LSBsor47.5secondsof arc quency of 2.6 kHz and resolution of 14 bits. 2.7×106 The comparative analysis can be summarized: To determine the value of K based on the passive components A AD2S83 DC Tacho Conditions used to define the dynamics of the converter the following should be used. Linearity % 0.1 0.1 0–3600 rpm 4.04×1011 Reversion Error % FSO 0.3 0.25 K = A 2n ×R6×R4×(C4+C5) Note the typical operating range of dc tachogenerator is Where n = resolution of the converter. 0 rpm-3600 rpm. The resolver/AD2S83 combination will oper- R4, R6 in ohms ate up to speeds in excess of 10000 rpm. C5, C4 in farads. Ripple Effects The comparative analysis of the output ripple from the tacho- generator and the AD2S83 is illustrated below. Minimization of the AD2S83 output ripple is discussed in detail in the Velocity Errors section. Other Factors Other factors concerning choice of feedback source have to be addressed. On average the MTBF of a tachogenerator is 347 days as opposed to typically 8 years for a resolver. Resolvers are relatively insensitive to temperature whereas a tachogenerator will be specified up to a maximum of 100°C with a ±0.1%/°C (above 25°C) degradation in output voltage. The brushless resolver requires no preventative maintenance; the brushes on a tachogenerator, however, will require periodic checking. REV. E –15–

AD2S83 SOURCES OF ERRORS VELOCITY ERRORS Integrator Offset Some “ripple” or noise will always be present in the velocity Additional inaccuracies in the conversion of the resolver signals signal. Velocity signal ripple is caused by, or related to, the will result from an offset at the input to the integrator. This following parameters. The resulting effects are generally addi- offset will be treated as an error signal. The resulting angular tive. This means diagnosis needs to be an iterative process in error will typically be 1 arc minute over the operating tempera- order to define the source of the error. ture range. 1.0 Reference Frequency A description of how to adjust the zero offset is given in the A ripple content at the reference frequency is superimposed Component Selection section; the circuit required is shown in on the velocity signal output. The amplitude depends on Figure 1. the loop bandwidth. This error is a function of a dc offset at the input to Phase Sensitive Demodulator (PSD). Differential Phase Shift Phase shift between the sine and cosine signals from the resolver 2.0 Resolver Inaccuracies is known as differential phase shift and can cause static error. Impedance mismatch occur in the sine and cosine windings Some differential phase shift will be present on all resolvers as a of the resolver. These give rise to differential phase shift result of coupling. A small resolver residual voltage (quadrature between the sine and cosine inputs to the RDC and varia- voltage) indicates a small differential phase shift. Additional tions in the resolver output amplitudes. phase shift can be introduced if the sine channel wires and the 2.1 Sine and Cosine Amplitude Mismatch cosine channel wires are treated differently. For instance, differ- This is normally identified by the presence of asymmetrical ent cable lengths or different loads could cause differential phase ripple voltages. shift. 2.2 Differential Phase Shift between the Sine and Cosine Inputs The additional error caused by differential phase shift on the The frequency of this ripple is usually twice the input veloc- input signals approximates to ity, and the amplitude is proportional to the magnitude of Error = 0.53 a × b arc minutes the velocity signal. The phase shift is normally induced through the connections from the resolver to the converter. where a = differential phase shift (degrees). Maintaining equal lengths of screened twisted pair cable b = signal to reference phase shift (degrees). from the resolver to the AD2S83 will reduce the effects of This error can be minimized by choosing a resolver with a small resistive imbalance, and therefore, reduce differential phase residual voltage, ensuring that the sine and cosine signals are shift. handled identically and removing the reference phase shift (see 3.0 LSB Update Ripple the Connecting the Resolver section). By taking these precau- LSB update noise occurs as the resolver rotates and the tions the extra error can be made insignificant. digital outputs of the RDC are updated. For a correctly Most resolvers exhibit a phase shift between the signal and the scaled loop, this ripple component has a magnitude of reference. This phase shift will, however, give rise under approximately 2 mV peak at 16-bit resolution. dynamic conditions to an additional error defined by: 3.1 Ripple due to the LSB rate given by: Shaft Speed(rps)×Phase Shift(Degrees) LSB rate = N × Reference Frequency =ErrorDegrees The PSD generates sums and differences of all its compo- ReferenceFrequency nent input frequencies, so when the LSB update rate is an multiple of the reference frequency, a beat frequency is Under static operating conditions phase shift between the refer- generated. The magnitude of this ripple is a function of the ence and the signal lines alone will not theoretically affect the LSB weighting, i.e., ripple is less at 16 bits. converter’s static accuracy. 4.0 Torque Ripple For example, for a phase shift of 20 degrees, a shaft rotation of Torque ripple is a phenomenon associated with motors. An 22 rps and a reference frequency of 5 kHz, the converter will ac motor naturally exhibits a sinusoidal back emf. In an exhibit an additional error of: ideal system the current fed to the motor should, in order 22×20 =0.088Degrees to cancel, also be sinusoidal. In practice the current is often 5000 trapezoidal. Consequently, the output torque from the motor will not be smooth and torque ripple is created. If the load- This effect can be eliminated by placing a phase shift in the ing on a motor is constant, the velocity of the motor shaft reference to the converter equivalent to the phase shift in the will vary as a result of the cyclic variation of motor torque. resolver (see the Connecting the Resolver section). The variation in velocity then appears on the velocity Note: Capacitive and inductive crosstalk in the signal and reference output as ripple. This is not an error but a true velocity leads and wiring can cause similar problems. variation in the system. –16– REV. E

AD2S83 Offset Errors 1 PHASE LEAD = ARC TAN PHASE LAG = ARC TAN 2(cid:8)fRC The limiting factor in the measuring of low or “creep” speeds is 2(cid:8)fRC the level of dc offset present at zero velocity. The zero velocity C R dc offset at the output of the AD2S83 is a function of the input R C bias current to the VCO and the value for the input resistor R6. See “Circuit Functions and Dynamic Performance VCO.” PHASE SHIFT CIRCUITS The offset can be minimized by reducing the maximum tracking Figure 10. Phase Shift Circuits rate so reducing the value for R6. Offset is a function of tracking rate and therefore resolution; the dc offset is lowest at 16 bits. TYPICAL CIRCUIT CONFIGURATION To increase the dynamic range of the velocity dynamic resolu- Figure 11 shows a typical circuit configuration for the AD2S83 tion switching can be employed. (Contact MCG Applications with 12-bit resolution. Values of the external components have for more information.) been chosen for a reference frequency of 5 kHz and a maximum tracking rate of 260 rps with a bandwidth of 520 Hz. Placing the CONNECTING THE RESOLVER values for R4, R6, C4, and C5 in the equation for K gives a A The recommended connection circuit is shown in Figure 11. value of 1.65 × 106. The resistors are 0.125 W, 5% tolerance In cases where the reference phase relative to the input signals preferred values. The capacitors are 100 V ceramic, 10% toler- from the resolver requires adjustment, this can be easily ance components. achieved by varying the value of the resistor R2 of the HF filter For signal and reference voltages greater than 2 V rms a simple (see Figure 1). voltage divider circuit of resistors can be used to generate the Assume that R1 = R2 = R and C1 = C2 = C correct signal level at the converter. Care should be taken to ensure that the ratios of the resistors between the sine signal line 1 and ground and the cosine signal line and ground are the same. and Reference Frequency = . 2πRC Any difference will result in an additional position error. For more information on resistive scaling of SIN, COS, and By altering the value of R2, the phase of the reference relative to REFERENCE converter inputs refer to the application note, the input signals will change in an approximately linear manner “Circuit Applications of the 2S81 and 2S80 Resolver-to-Digital for phase shifts of up to 10 degrees. Converters.” Increasing R2 by 10% introduces a phase lag of two degrees. Decreasing R2 by 10% introduces a phase lead of two degrees. R9 1M(cid:4) R8 C2 R2 4.7M(cid:4) 10C03nF R1030k(cid:4) 2.2nF 15k(cid:4) REFERENCE INPUT C1 VELOCITY 2.2nF R6 R4 C4 R5 C5 O/P 100nF R1 62k(cid:4) 130k(cid:4) 1.2nF 200k(cid:4) 6.2nF 15k(cid:4) COS HIGH C7 RESOLVER REF LOW 150pF R7 C6 SIGNAL COS LOW 3.3k(cid:4) 390pF 100nF SIN LOW 6 5 4 3 2 1 44 43 42 41 40 SIN HIGH 7 39 –12V +12V 8 38 RIPPLE CLOCK 9 37 DIRECTION MSB 10 36 BUSY 11 35 COMPLEMENT AD2S83 12 TOP VIEW 34 DATA LOAD (Not to Scale) DATA 13 33 OUTPUT 14 32 SC2 0V 15 31 16 30 INHIBIT 17 29 18 19 20 21 22 23 24 25 26 27 28 SB 5V LE TECT NOTE: R7, C6 AND C7 SHOULD BE CONNECTED AS L + B YE CLOSE AS POSSIBLE TO THE CONVERTER PINS. DATA OUTPUT NA BEL SIGNAL SCREENS SHOULD BE CONNECTED TO PIN 5. E S Figure 11.Typical Circuit Configuration REV. E –17–

AD2S83 APPLICATIONS OTHER PRODUCT Control Transformer AD2S90. Low-cost resolver-to-digital converter with outputs The ratio multiplier of the AD2S83 can be used independently which emulate optical encoders and a serial output for absolute of the loop integrators as a control transformer. In this mode, position information. Unlike the AD2S83, the AD2S90 requires the resolver inputs θ are multiplied by a digital angle φ, any no external components to operate. The AD2S90 is built on difference between φ and θ will be represented by the AC LC2MOS and packaged in a 20-lead PLCC. ERROR output as Sin ωt sin (θ–φ) or the DEMOD output AD2S80A/AD2S81A/AD2S82A. Monolithic resolver-to-digital as sin (θ–φ). To use the AD2S83 in this mode refer to the converter. The AD2S80/AD2S82A offer selectable 10, 12, 14, “Control Transformer” application note. 16 bits of resolution. The AD2S81A has 12-bit resolution. All devices have user selectable dynamics. The AD2S80A is available in 40-lead DDIP, 44-lead LCC and is qualified to MIL-STD- 883B REV. E. The is available in a 44-lead PLCC, and the AD2S81A in a 28-lead DDIP. –18– REV. E

AD2S83 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Leaded Chip Carrier (PLCC) (P-44A) 0.180 (4.57) 0.165 (4.19) E) 0.048 (1.21) 00..004482 ((11..2017)) 00..005462 ((11..4027)) 00..002155 ((00..6338)) 00 (rev. 0.042 (1.07) 7 6 PIN 1 4039 10/ IDENTIFIER 0(B1.S0.2C570) 00..6539 ((1164..0909)) –1.5– c TOP VIEW 0.021 (0.53) 06 (PINS DOWN) 0.013 (0.33) 00 0 C 0.032 (0.81) 0.026 (0.66) 17 29 18 28 0.020 0.040 (1.01) (0.50R) 00..665560 ((1166..6561))SQ 0.025 (0.64) 0.110 (2.79) 0.695 (17.65) SQ 0.085 (2.16) 0.685 (17.40) A. S. U. N D I E T N RI P REV. E –19–

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