Low Cost, 14-Bit, Dual Channel Synchro/Resolver-to-Digital Converter Data Sheet AD2S44 FEATURES The core of each conversion is performed by state-of-the-art mono- Low per-channel cost lithic, integrated circuits manufactured by the Analog Devices, Inc., 32-lead DIL hybrid package proprietary BiMOS II process, which combines the advantages of 2.6 arc minute accuracy low power CMOS digital logic with bipolar linear circuits. The 14-bit resolution use of these ICs keeps the internal component count low and Built-in test ensures high reliability. Independent reference inputs The built-in test (BIT) facility can be used in failsafe systems to High tracking rate provide an indication of whether the converter is tracking APPLICATIONS accurately. Gimbal/gyro control systems Each channel incorporates a high accuracy differential condi- Robotics tioning circuit for signal inputs providing more than 74 dB of Engine controllers common-mode rejection. Options are available for both synchro Coordinate conversion and resolver format inputs. The converter output is via a three-state Military servo control systems transparent latch allowing data to be read without interruption Fire control systems Avionic systems of the converter operation. The A/B and OE control lines select Antenna monitoring the channel and present the digital position to the common CNC machine tooling data outputs. GENERAL DESCRIPTION The AD2S44 also features independent reference inputs where different reference frequencies can be used for each channel. The AD2S44 is a 14-bit dual channel, continuous tracking synchro/ resolver-to-digital converter. It has been designed specifically All components are 100% tested at −55°C, +25°C, and +125°C. for applications where space, weight, and cost are at a premium. Devices are processed to high reliability screening standards Each 32-lead hybrid device contains two independent Type II servo and receive further levels of testing and screening to ensure loop tracking converters. The ratiometric conversion technique high levels of reliability. employed provides excellent noise immunity and tolerance of long lead lengths. FUNCTIONAL BLOCK DIAGRAM RHI (A) REFERENCE RLO (A) CONDITIONER +VS S1 (A) HIGH SS32 ((AA)) CORSENYSNDOCITHLIOVRENORE/R MUSSLINPT/EICPEOLDISER ERARMOPR DSEEPTNHESACISTTEIOV-ER INTEGRATOR VCO CUOP-UDNOTWENR –GVNSD S4 (A) BIT BUILT-IN TEST THREE- A/B AD2S44 DETECTION STATE OE OUTPUT DB1 (MSB) LATCHES TO DB14 (LSB) S1 (B) HIGH SS32 ((BB)) CORSENYSNDOCITHLIOVRENORE/R SSINP/ECEODS ERARMOPR DSEEPTNHESACISTTEIOV-ER INTEGRATOR VCO CUOP-UDNOTWENR S4 (B) MULTIPLIER RRLHOI ((BB)) CROENFDEIRTEIONNCEER 02947-001 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©1989–2011 Analog Devices, Inc. All rights reserved.

AD2S44 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Output Enable (OE) ......................................................................8  Applications ....................................................................................... 1  Built-In Test (BIT) .........................................................................8  General Description ......................................................................... 1  Scaling for Nonstandard Signals .................................................9  Functional Block Diagram .............................................................. 1  Dynamic Performance ..................................................................9  Table of Contents .............................................................................. 2  Acceleration Error .........................................................................9  Revision History ............................................................................... 2  Reliability ..................................................................................... 10  Specifications ..................................................................................... 3  Processing for High Reliability (B Suffix) ............................... 10  Absolute Maximum Ratings ............................................................ 5  Other Products ........................................................................... 10  ESD Caution .................................................................................. 5  Outline Dimensions ....................................................................... 11  Pin Configuration and Function Descriptions ............................. 6  Ordering Guide .......................................................................... 11  Theory of Operation ........................................................................ 7  Ordering Information ................................................................ 11  Connecting the Converter ........................................................... 7  Channel Select (A/B) ................................................................... 7  REVISION HISTORY 10/11—Rev. A to Rev. B Changes to Processing for High Reliability Section and Other Products Section ................................................................. 10 Changes to Figure 1 .......................................................................... 1 Updated Outline Dimensions ....................................................... 11 Changes to Figure 3 .......................................................................... 7 Changes to Ordering Guide .......................................................... 11 08/08—Rev. 0 to Rev. A Changes to Ordering Information ............................................... 11 Updated Format ................................................................ Universal 10/89—Revision 0: Initial Version Changes to Specifications Section .................................................. 3 Changes to Absolute Maximum Ratings Section ......................... 5 Deleted Standard Processing Section ............................................. 7 Rev. B | Page 2 of 12

Data Sheet AD2S44 SPECIFICATIONS V = ±15 V at T = 25°C, unless otherwise noted. S A Table 1. Parameter Min Typ Max Unit Test Conditions/Comments PERFORMANCE Accuracy1 AD2S44-UMB2 −4.0 +4.0 Arc minutes −55°C to +125°C −2.6 +2.6 Arc minutes −25°C to +85°C AD2S44-TMB2 −4.0 +4.0 Arc minutes −55°C to +125°C Tracking Rate 20 Rev/sec Resolution (1 LSB = 1.3 Arc Minutes) 14 Bits Output coding parallel natural binary Repeatability 1 LSB Signal/Reference Frequency 400 2600 Hz Bandwidth 100 Hz SIGNAL INPUTS Signal Voltage 11.8 or 90 V rms See the Ordering Information section Input Impedance 90 V Signal 200 kΩ Resistive tolerance ±2% 11.8 V Signal 26 kΩ Common-Mode Rejection 74 dB Common-Mode Range 90 V Signal ±250 V dc 11.8 V Signal ±60 V dc REFERENCE INPUTS Reference Voltage 26 or 115 V rms See the Ordering Information section Input Impedance 115 V 270 kΩ Resistive tolerance ±5% 26 V 270 kΩ Common-Mode Range 115 V ±210 V dc 26 V ±210 V dc ACCELERATION CONSTANT 62,000 sec–2 STEP RESPONSE Large Step1, 2 63 75 ms 179° to 1 LSB of error Small Step1, 2 25 30 ms 2° to 1 LSB of error POWER LINES +V = +15 V1, 2 75 80 mA Quiescent condition S –V = −15 V1, 2 40 45 mA Quiescent condition S Power Dissipation 1.7 1.9 W Quiescent condition DIGITAL INPUTS OE V 0.7 V dc I = 5 µA IL IL V 2.0 V dc I = 5 µA IH IH A/B V 0.7 V dc I = 1.2 mA IL IL V 2.0 V dc I = –60 µA IH IH DIGITAL OUTPUTS (DB1 to DB14) V 1, 2 0.4 V dc I = 1.2 mA OL IL V 1, 2 2.4 V dc I = 60 µA OH OH Three-State Leakage Current ±40 µA Drive Capability 3 LSTTL loads Rev. B | Page 3 of 12

AD2S44 Data Sheet Parameter Min Typ Max Unit Test Conditions/Comments DATA TRANSFER See Figure 6 Time to Data Stable (After Negative Edge of OE 640 ns t S or Change of Level of A/B) Time to Data in High Impedance State 200 ns t R (After Positive Edge of OE) Time for Repetitive Strobing of Selected Channel 200 ns t P BUILT-IN TEST OUTPUT (BIT) Sense Active low Low = error condition V 0.4 V dc I = 3.2 mA OL OL V 2.4 V dc I = −160 µA OH OH Drive Capability 8 LSTTL loads Error Condition Set 55 LSB Error Condition Cleared 45 LSB 1 Specified overtemperature range, −55°C to +125°C, and for: (a) ±10% signal and reference amplitude variation; (b) ±10% signal and reference harmonic distortion; (c) ±5% power supply variation; and (d) ±10% variation in reference frequency. 2 These parameters are 100% tested at nominal values of power supplies, input signal voltages, and operating frequency. All other parameters are guaranteed by design, not tested. Rev. B | Page 4 of 12

Data Sheet AD2S44 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress +VS to GND +17.25 V dc rating only; functional operation of the device at these or any –VS to GND −17.25 V dc other conditions above those indicated in the operational Any Logic Input to GND +6.0 V dc (maximum) section of this specification is not implied. Exposure to absolute Any Logic Input to GND −0.4 V dc (minimum) maximum rating conditions for extended periods may affect Maximum Junction Temperature 150°C device reliability. S1, S2, S3, S4 Pins (Line-to-Line)1 ESD CAUTION 90 V Option ±600 V dc 11.8 V Option ±80 V dc S1, S2, S3, S4 Pins to GND 90 V Option ±600 V dc 11.8 V Option ±80 V dc R Pins to R Pins HI LO 26 V, 115 V Options ±600 V dc R Pins to R Pins to GND HI LO 26 V, 115 V Options ±600 V dc Storage Temperature Range −65°C to +150°C Operating Temperature Range −55°C to +125°C 1 On synchro input options, line-to-line voltage refers to the differential voltages of S2 (A)/S2 (B) to S1 (A)/S1 (B), S1 (A)/S1 (B) to S3 (A)/S3 (B), and S3 (A)/S3 (B) to S2 (A)/S2 (B). On resolver input options, line-to-line levels refer to the S1 (A)/ S1 (B) to S3 (A)/S3 (B) and S2 (A)/S2 (B) to S4 (A)/S4 (B) voltages. Rev. B | Page 5 of 12

AD2S44 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB8 1 32 DB7 DB9 2 31 DB6 DB10 3 30 DB5 DB11 4 29 DB4 DB12 5 28 DB3 DB13 6 27 DB2 DB14 (LSB) 7 26 DB1 (MSB) OE 8 TAODP2 VSIE4W4 25 +VS A/B 9 (Not to Scale) 24 –VS BIT 10 23 GND RLO (A) 11 22 RLO (B) RHI (A) 12 21 RHI (B) S4 (A) 13 20 S4 (B) S3 (A) 14 19 S3 (B) SS12 ((AA)) 1156 1187 SS12 ((BB)) 02947-003 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 to 7 DB8 to DB14 (LSB) Parallel Output Data Bits. 8 OE Output Enable Input. 9 A/B Channel A or Channel B Select Input. 10 BIT Built-In Test Error Output. 11 R (A) Input Pin for Channel A Reference Low. LO 12 R (A) Input Pin for Channel A Reference High. HI 13 to 16 S4 (A) to S1 (A) Channel A Input Signal. 17 to 20 S1 (B) to S4 (B) Channel B Input Signal. 21 R (B) Input Pin for Channel B Reference High. HI 22 R (B) Input Pin for Channel B Reference Low. LO 23 GND Power Supply Ground. This pin is electrically connected to the case. 24 –V Negative Power Supply. S 25 +V Positive Power Supply. S 26 to 32 DB1 (MSB) to DB7 Parallel Output Data Bits. Rev. B | Page 6 of 12

Data Sheet AD2S44 THEORY OF OPERATION The AD2S44 operates on a tracking principle. The output digital A phase sensitive detector, integrator, and voltage-controlled word continually tracks the position of the synchro/resolver oscillator (VCO) form a closed-loop system that seeks to null sin shaft without the need for external convert commands and (θ − ϕ). When this is accomplished, the word state of the up-down status wait loops. As the transducer moves through a position counter (ϕ) equals the synchro/resolver shaft angle (θ), to within equivalent to the least significant bit weighting, the output the rated accuracy of the converter. digital word is updated. CONNECTING THE CONVERTER Each channel is identical in operation, sharing power supply The power supply voltages connected to −V and +V are to be S S and output pins. Both channels operate continuously and ±15 V and cannot be reversed. independently of each other. The digital output from either It is suggested that a parallel combination of a ceramic 100 nF channel is available after switching the channel select and capacitor and a tantalum 6.8 µF capacitor be placed from each output enable inputs. of the supply pins to GND. If the device is a synchro-to-digital converter, the 3-wire synchro The pin marked GND is connected electrically to the case and output is connected to the S1, S2, and S3 pins on the unit, and is to be taken to 0 V potential in the system. a solid-state Scott T input conditioner converts these signals into resolver format given by The digital output is taken from Pin 26 to Pin 32 and from Pin 1 to Pin 7. Pin 26 is the MSB, and Pin 7 is the LSB. V = K E sin ωt sin θ 1 0 The reference connections are made to the R pins and the R V = K E sin ωt cos θ HI LO 2 0 pins. In the case of a synchro, the signals are connected to the where: S1, S2, and S3 pins, according to the following convention: θ is the angle of the synchro shaft. E = E sin ωt sin θ E sin ωt is the reference signal. S1−S3 RLO−RHI 0 K is the transformation ratio of the input signal conditioner. E = E sin ωt sin (θ − 120°) S3−S2 RLO−RHI If the unit is a resolver-to-digital converter, the 4-wire resolver E = E sin ωt sin (θ – 240°) S2−S1 RLO−RHI output is connected directly to the S1, S2, S3, and S4 pins on For a resolver, the signals are connected to the S1, S2, S3, and S4 the unit. pins, according to the following convention: To understand the conversion process, assume that the current E = E sin ωt sin θ S1−S3 RLO−RHI word state of the up-down counter is ϕ. V is multiplied by cos ϕ, 1 E = E sin ωt cos θ and V is multiplied by sin ϕ to give the following: S2−S4 RLO−RHI 2 CHANNEL SELECT (A/B) K E sin ωt sin θ cos ϕ 0 K E sin ωt cos θ sin ϕ A/B is the channel select input. A Logic 1 selects Channel A, and 0 a Logic 0 selects Channel B. Data becomes valid 640 ns after A/B These signals are subtracted by the error amplifier to give is toggled. Timing information is shown in Figure 4 and Figure 5. K E sin ωt (sin θ cos ϕ − cos θ sin ϕ) 0 or K E sin ωt sin (θ − ϕ) 0 RHI (A) REFERENCE RLO (A) CONDITIONER +VS V1 SSS123 (((AAA))) CORSENYSNDOCITHLIOVRENORE/R MUSSLIHNPTI/EIGCPEHOLDISER ERARMOPR DSEEPTNHESACISTTEIVO-ER INTEGRATOR VCO CUOP-UDNOTWERN –GVNSD S4 (A) V2 BIT BUILT-IN TEST THREE- A/B AD2S44 DETECTION STATE OE OUTPUT LATCHES DB1 (MSB) TO DB14 (LSB) S1 (B) SS32 ((BB)) CORSENYSNDOCITHLIOVRENORE/R MUSSLIHNPTI/EIGCPEHOLDISER ERARMOPR DSEEPTNHESACISTTEIVO-ER INTEGRATOR VCO CUOP-UDNOTWERN S4 (B) RRLHOI ((BB)) CROENFDEIRTEIONNCEER 02947-010 Figure 3. Functional Block Diagram Rev. B | Page 7 of 12

AD2S44 Data Sheet OUTPUT ENABLE (OE) BUILT-IN TEST (BIT) OE is the output enable input; the signal is active low. When set The BIT is the built-in test error output, which provides an over- to Logic 1, DB1 to DB14 are in high impedance state. When OE velocity or fault indication signal for the channel selected via A/B. is set to Logic 0, DB1 to DB14 represent the angle of the transducer The error voltage of each channel is continuously monitored. When shaft to within the stated accuracy of the converter (see bit weights the error exceeds ±50 bits for the currently selected channel, the in Table 4). Data becomes valid 640 ns after the OE is switched. BIT output goes low, indicating that an error greater than approx- Timing information is shown in Figure 4 and Figure 5 and imately one angular degree exists, and the data is, therefore, invalid. detailed in Table 1. The BIT signal has a built-in hysteresis; that is, the error required to set the BIT is greater than the error required for it to be cleared. Table 4. Bit Weight Bit No. Weight (Degrees) The BIT is set when the error exceeds 55 LSBs and is cleared when 1 (MSB) 180.0000 the error goes below 45 LSBs. This mode of operation guarantees 2 90.0000 that the BIT does not flicker when the error threshold is crossed. 3 45.0000 The BIT is valid for the selected channel approximately 50 ns after 4 22.5000 the change in the state of A/B. In most instances, the error condi- 5 11.2500 tion that sets the BIT must persist for at least one period of the 6 5.6250 reference signal prior to the BIT responding to the condition. 7 2.8125 8 1.4063 Table 5. BIT Output Faults 9 0.7031 Condition Description 10 0.3516 Power-Up Transient The BIT returns to a logic high state after 11 0.1758 Response the AD2S44 position output synchronizes 12 0.0879 with the angle input to within 1°. 13 0.0439 Normally, the BIT is low at power-up for 14 ( LSB) 0.0220 a period less than or equal to the large signal step response settling time of the AD2S44 after the ±V supplies have S stabilized to within 5% of their final values. OE Step Input > 1° The BIT returns to a logic high state after the selected channel of the AD2S44 has settled to within 1° of the input angle resulting from an instantaneous step. A/B Excessive Velocity The BIT is driven to a logic low if the maximum tracking rate of the AD2S44 is exceeded (20 rps typical). tS tS tR Signal Failure The BIT may be driven to a logic low state if DBAITTAS CHANNEL B CHANNEL A all signal voltages to the selected channel (1 TO 14) VALID* VALID* are lost. *CDOUNRVINEGR TCEHRA NDNAETAL OVAULTIPDU.T IS INHIBITED FROM UPDATES 02947-005 CFaoinluvreer ter/System tAon tyr afaciklu trhee t ihnaptu cta suysnecsh trhoe/ rAeDso2lSv4e4r taon gfaleil s Figure 4. Repetitive Reading of One Channel drives the BIT to a logic low. This may include, but is not limited to, acceleration conditions, poor supply voltage regulation, or excessive noise on the signal connections. OE tP A/B tS tR DATA DATA DATA BITS VALID* VALID* (1 TO 14) *CDOUNRVINEGR TCEHRA NDNAETAL OVAULTIPDU.T IS INHIBITED FROM UPDATES 02947-004 Figure 5. Alternative Reading of Each Channel Rev. B | Page 8 of 12

Data Sheet AD2S44 SCALING FOR NONSTANDARD SIGNALS The gain and phase diagrams are shown in Figure 7 and Figure 8. A feature of these converters is that the signal and reference inputs 6 can be resistively scaled to accommodate nonstandard input signal 3 and reference voltages that are outside the nominal ±10% limits of the converter. Using this technique, it is possible to use a standard 0 converter with a personality card in systems where a wide range of input and reference voltages are encountered. dB) –3 N ( The accuracy of the converter is affected by the matching accu- AI G –6 racies of resistors used for external scaling. For resolver format options, it is critical that the value of the resistors on the S1 (A)/ –9 S1 (B) to S3 (A)/S3 (B) signal input pair be precisely matched to tthhee Sth4r (eAe )r/eSs4is t(oBr)s toon S 2th (eA S)1/S, S22 (,B a)n idn pSu3t p pinaisr m. Fuosrt sbyen mchartcoh oepdt. iIonn s, ––1152 02947-007 10 100 general, a 0.1% mismatch between resistor values contributes an FREQUENCY (Hz) additional 1.7 arc minutes of error to the conversion. In addition, Figure 7. Gain Plot imbalances in resistor values can greatly reduce the common- mode rejection ratio of the signal inputs. 180 To calculate the values of the external scaling resistors, add 135 2.222 kΩ for each volt of signal in series with the S1, S2, S3, and S4 pins (no resistor is required on the S4 pins for synchro options) 90 and add 3 kΩ extra per volt of reference in series with the RLO ees) 45 pins and the RHI pins. egr DYNAMIC PERFORMANCE E (D 0 S A H –45 P θIN Figure 6. TKSra2ansfer Fu11n c++t ssioTTn12 of AD2S4θ4O UT 02947-006 ––11–839050 02947-008 The transfer function of the converter is as follows: 10 100 FREQUENCY (Hz) Open-loop transfer function Figure 8. Phase Plot θ K 1+sT ACCELERATION ERROR OUT = a × 1 θIN s2 1+sT2 A tracking converter employing a Type II servo loop does not suffer any velocity lag. However, there is an additional error Closed-loop transfer function due to acceleration. This error is defined using the acceleration θOUT = 1+sT1 constant (Ka) of the converter θ 1+sT +s2 K +s3T K K = Input Acceleration/Error in Output Angle IN 1 a 2 a a The numerator and denominator must have consistent angular where: units. For example, if K is expressed in sec–2, the input accelera- a Ka = 62000 sec–2. tion is to be specified in degrees/sec2 and the output angle error is T = 0.0061 sec. to be specified in degrees. Alternatively, the angular unit of measure 1 can also be in units such as radians, arc minutes, or LSBs. T = 0.001 sec. 2 Rev. B | Page 9 of 12

AD2S44 Data Sheet K does not define maximum acceleration; it defines only the PROCESSING FOR HIGH RELIABILITY (B SUFFIX) a error due to acceleration. The maximum acceleration of which As a part of the high reliability manufacturing procedure, all the AD2S44 keeps track is approximate to 5 × K = 310,000°/sec2 a converters receive the processing shown in Table 6. or about 800 revolutions/sec2. Table 6. K can be used to predict the output position error due to input a acceleration. For example, an acceleration of 50 revolutions/sec2 Process1 Conditions with K = 62,000 is calculated using the following equation: Precap Visual Inspection MIL-STD-883, Method 2017 a Temperature Cycling 10 cycles, –65°C to +150°C LSB Constant Acceleration 5000 Gs, Y1 plane Input Acceleration  Interim Electrical Tests @ 25°C ErrorsinLSBs= sec2 = Operating Burn In 160 hours @ 125°C [ ] K sec−2 Seal Test, Fine and Gross MIL-STD-883, Method 1014 a Final Electrical Test Performed at T , T , T MIN AMB MAX  rev  LSB External Visual Inspection MIL-STD-883, Method 2009 50 ×214  sec2  rev  =13.2LSBs 1 Test and screening data supplied by request. [ ] 62,000sec−2 OTHER PRODUCTS Analog Devices manufactures many other products concerned RELIABILITY with the conversion of synchro/resolver data, such as the The reliability of these products is very high due to the extensive SDC/RDC1740 series and the AD2S80A series. use of custom chip circuits that decrease the active component Hybrid count. Calculations of the MTBF figure under various environ- mental conditions are available upon request from Analog The SDC/RDC1740 is a hybrid synchro/resolver-to-digital Devices. converter with internal isolating micro transformers. Monolithic Figure 9 shows the MTBF in years vs. case temperature for Naval Sheltered conditions calculated in accordance with the The AD2S80A series are ICs performing resolver-to-digital Mil-Hdbk-217E. conversion with accuracies up to ±2 arc minutes and 16-bit 100 resolution. s) ar F (Ye 10 B T M 1 02947-009 25 45 65 85 105 125 TEMPERATURE (°C) Figure 9. MTBF vs. Temperature Rev. B | Page 10 of 12

Data Sheet AD2S44 OUTLINE DIMENSIONS 1.728 (43.89) MAX 32 17 1.102 (27.99) 1.079 (27.41) 1 16 PIN 1 0.025 (0.64) INDICATOR 0.225 (5.72) (NOTE 1) 0.015 (0.38) MAX 0.192 (4.88) 0.206 (5.23) 0.015 (0.38) 0.152 (3.86) 0.186 (4.72) 0.008 (0.20) 0.910 (23.11) 0.025 (0.64) 0.120 (3.05) 0.890 (22.61) MIN 0.100 (2.54) MAX BSC 0.070 (1.78) 0.023 (0.58) 0.030 (0.76) 0.014 (0.36) NOTES: 1. INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE. 2. CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 10. 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] (DH-32E) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model Temperature Range Package Description Package Option AD2S44–TM11B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E AD2S44–TM12B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E AD2S44–TM18B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E AD2S44–UM18B −55°C to +125°C 32-Lead Bottom-Brazed Ceramic DIP for Hybrid [BBDIP_H] DH-32E ORDERING INFORMATION When ordering, the converter part numbers are to be suffixed by AD2S44- XM Y Z B a two-letter code defining the accuracy grade, and a two digit numeric code defining the signal/reference voltage and frequency. HIGH-REL PROCESSING All the standard options, and their option codes, are shown in Z = 0* SIGNAL, 2V REFERENCE, 2V RESOLVER Z = 1 SIGNAL, 11.8V REFERENCE, 26V SYNCHRO Figure 11. For nonstandard configurations, contact Analog Z = 2 SIGNAL, 90V REFERENCE, 115V SYNCHRO BASEPART Z = 3* SIGNAL, 11.8V REFERENCE, 11.8V RESOLVER Devices. NUMBER Z = 4* SIGNAL, 26V REFERENCE, 26V RESOLVER BASE PART Z = 8 SIGNAL, 11.8V REFERENCE, 26V RESOLVER For example, the AD2S44–TM12B is the correct part number Y = 1 400Hz TO 2.6kHz REFERENCE FREQUENCY for a component that operates with 90 V signal, 115 V reference X = U –55°C TO +125°C OPERATING TEMPERATURE synchro format inputs and yields a ±4.0 arc minutes accuracy RANGE ±4.0 ARC MIN ACCURACY over the −55°C to +125°C temperature range processed to high ±2.6 ARC MIN ACCURACY (–25°C TO +85°C) reliability standards. X = T –55°C TO +125°C OPERATING TEMPERATURE RANGE±4.0 ARC MIN ACCURACY X = S* –55°C TO +125°C OPERATING TEMPERATURE *MODEL IS OBSOLETEAND NO L O N G E R RAAVNAGILEA±B5L.2E .ARC MIN ACCURACY 02947-002 Figure 11. Rev. B | Page 11 of 12

AD2S44 Data Sheet NOTES ©1989–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02947-0-10/11(B) Rev. B | Page 12 of 12