Variable Resolution, 10-Bit to 16-Bit R/D Converter with Reference Oscillator AD2S1210 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete monolithic resolver-to-digital converter REFERENCE PINS CRYSTAL 3125 rps maximum tracking rate (10-bit resolution) ±2.5 arc minutes of accuracy 10-/12-/14-/16-bit resolution, set by user EXCITATION REFERENCE VOLTAGE INTERNAL OUTPUTS OSCILLATOR REFERENCE CLOCK Parallel and serial 10-bit to 16-bit data ports (DAC) GENERATOR Absolute position and velocity outputs System fault detection SYNTHETIC AD2S1210 REFERENCE Programmable fault detection thresholds Differential inputs ADC Incremental encoder emulation INPUTS TYPE II FAULT FAULT FROM TRACKING LOOP DETECTION DETECTION Programmable sinusoidal oscillator on-board RESOLVER OUTPUTS ADC Compatible with DSP and SPI interface standards 5 V supply with 2.3 V to 5 V logic interface POSITION VELOCITY CONFIGURATION −40°C to +125°C temperature rating REGISTER REGISTER REGISTER DATA I/O ADCP aPnLdIC aAc sTeIrOvoN mS otor control EMEOUNULCTAOPTDUIOETRNS ENCODEREMULATION MULTIPLEXER Encoder emulation DATA BUS OUTPUT Electric power steering EInletecgtrriact veedh sitcalerste r generators/alternators RESET DATA I/O 07467-001 Figure 1. Automotive motion sensing and control GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD2S1210 is a complete 10-bit to 16-bit resolution tracking 1. Ratiometric tracking conversion. The Type II tracking loop resolver-to-digital converter, integrating an on-board program- provides continuous output position data without mable sinusoidal oscillator that provides sine wave excitation conversion delay. It also provides noise immunity and for resolvers. tolerance of harmonic distortion on the reference and input signals. The converter accepts 3.15 V p-p ± 27% input signals, in the range 2. System fault detection. A fault detection circuit can sense of 2 kHz to 20 kHz on the sine and cosine inputs. A Type II loss of resolver signals, out-of-range input signals, input servo loop is employed to track the inputs and convert the input signal mismatch, or loss of position tracking. The fault sine and cosine information into a digital representation of the detection threshold levels can be individually programmed input angle and velocity. The maximum tracking rate is 3125 rps. by the user for optimization within a particular application. 3. Input signal range. The sine and cosine inputs can accept differential input voltages of 3.15 V p-p ± 27%. 4. Programmable excitation frequency. Excitation frequency is easily programmable to a number of standard frequencies between 2 kHz and 20 kHz. 5. Triple format position data. Absolute 10-bit to 16-bit angular position data is accessed via either a 16-bit parallel port or a 4-wire serial interface. Incremental encoder emulation is in standard A-quad-B format with direction output available. 6. Digital velocity output. 10-bit to 16-bit signed digital velocity accessed via either a 16-bit parallel port or a 4-wire serial interface. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.

AD2S1210 TABLE OF CONTENTS Features .............................................................................................. 1 LOS Threshold Register ............................................................ 21 Applications ....................................................................................... 1 DOS Overrange Threshold Register ........................................ 21 Functional Block Diagram .............................................................. 1 DOS Mismatch Threshold Register ......................................... 21 General Description ......................................................................... 1 DOS Reset Maximum and Minimum Threshold Registers . 22 Product Highlights ........................................................................... 1 LOT High Threshold Register .................................................. 22 Revision History ............................................................................... 2 LOT Low Threshold Register ................................................... 22 Specifications ..................................................................................... 3 Excitation Frequency Register .................................................. 22 Timing Specifications .................................................................. 6 Control Register ......................................................................... 22 Absolute Maximum Ratings ............................................................ 8 Software Reset Register ............................................................. 23 ESD Caution .................................................................................. 8 Fault Register .............................................................................. 23 Pin Configuration and Function Descriptions ............................. 9 Digital interface .............................................................................. 24 Typical Performance Characteristics ........................................... 11 SOE Input .................................................................................... 24 Resolver Format Signals ................................................................. 15 SAMPLE Input............................................................................ 24 Theory of Operation ...................................................................... 16 Data Format ................................................................................ 24 Resolver to Digital Conversion ................................................. 16 Parallel Interface ......................................................................... 24 Fault Detection Circuit .............................................................. 16 Serial Interface ............................................................................ 28 On-Board Programmable Sinusoidal Oscillator .................... 18 Incremental Encoder Outputs .................................................. 31 Synthetic Reference Generation ............................................... 18 Supply Sequencing and Reset ................................................... 31 Configuration of AD2S1210 ......................................................... 20 Circuit Dynamics ........................................................................... 32 Modes of Operation ................................................................... 20 Loop Response Model ............................................................... 32 Register Map .................................................................................... 21 Sources of Error .......................................................................... 33 Position Register ......................................................................... 21 Outline Dimensions ....................................................................... 34 Velocity Register ......................................................................... 21 Ordering Guide .......................................................................... 34 REVISION HISTORY 2/10—Rev. 0 to Rev. A Changes to Typical Performance Characteristics Section ... 11, 12 Changes to Ordering Guide .......................................................... 34 8/08—Revision 0: Initial Version Rev. A | Page 2 of 36

AD2S1210 SPECIFICATIONS AV = DV = 5.0 V ± 5%, CLKIN = 8.192 MHz ± 25%, EXC, EXC frequency = 10 kHz to 20 kHz (10-bit); 6 kHz to 20 kHz (12-bit); DD DD 3 kHz to 12 kHz (14-bit); 2 kHz to 10 kHz (16-bit); T = T to T ; unless otherwise noted.1 A MIN MAX Table 1. Parameter Min Typ Max Unit Conditions/Comments SINE, COSINE INPUTS2 Voltage Amplitude 2.3 3.15 4.0 V p-p Sinusoidal waveforms, differential SIN to SINLO, COS to COSLO Input Bias Current 8.25 μA V = 4.0 V p-p, CLKIN = 8.192 MHz IN Input Impedance 485 kΩ V = 4.0 V p-p, CLKIN = 8.192 MHz IN Phase Lock Range −44 +44 Degrees Sine/cosine vs. EXC output, Control Register D3 = 0 Common-Mode Rejection ±20 arc sec/V 10 Hz to 1 MHz, Control Register D4 = 0 ANGULAR ACCURACY3 Angular Accuracy ±2.5 + 1 LSB ±5 + 1 LSB arc min B, D grades ±5 + 1 LSB ±10 + 1 LSB arc min A, C grades Resolution 10, 12, 14, 16 Bits No missing codes Linearity INL 10-bit ±1 LSB B, D grades ±2 LSB A, C grades 12-bit ±2 LSB B, D grades ±4 LSB A, C grades 14-bit ±4 LSB B, D grades ±8 LSB A, C grades 16-bit ±16 LSB B, D grades ±32 LSB A, C grades Linearity DNL ±0.9 LSB Repeatability ±1 LSB VELOCITY OUTPUT Velocity Accuracy4 10-bit ±2 LSB B, D grades, zero acceleration ±4 LSB A, C grades, zero acceleration 12-bit ±2 LSB B, D grades, zero acceleration ±4 LSB A, C grades, zero acceleration 14-bit ±4 LSB B, D grades, zero acceleration ±8 LSB A, C grades, zero acceleration 16-bit ±16 LSB B, D grades, zero acceleration ±32 LSB A, C grades, zero acceleration Resolution5 9, 11, 13, 15 Bits DYNAMNIC PERFORMANCE Bandwidth 10-bit 2000 6500 Hz 2900 5300 Hz CLKIN = 8.192 MHz 12-bit 900 2800 Hz 1200 2200 Hz CLKIN = 8.192 MHz 14-bit 400 1500 Hz 600 1200 Hz CLKIN = 8.192 MHz 16-bit 100 350 Hz 125 275 Hz CLKIN = 8.192 MHz Rev. A | Page 3 of 36

AD2S1210 Parameter Min Typ Max Unit Conditions/Comments Tracking Rate 10-bit 3125 rps CLKIN = 10.24 MHz 2500 CLKIN = 8.192 MHz 12-bit 1250 rps CLKIN = 10.24 MHz 1000 CLKIN = 8.192 MHz 14-bit 625 rps CLKIN = 10.24 MHz 500 CLKIN = 8.192 MHz 16-bit 156.25 rps CLKIN = 10.24 MHz 125 CLKIN = 8.192 MHz Acceleration Error 10-bit 30 arc min At 50,000 rps2, CLKIN = 8.192 MHz 12-bit 30 arc min At 10,000 rps2, CLKIN = 8.192 MHz 14-bit 30 arc min At 2500 rps2, CLKIN = 8.192 MHz 16-bit 30 arc min At 125 rps2, CLKIN = 8.192 MHz Settling Time 10° Step Input 10-bit 0.6 0.9 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz 12-bit 2.2 3.1 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz 14-bit 6.5 9.0 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz 16-bit 27.5 40 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz Settling Time 179° Step Input 10-bit 1.5 2.2 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz 12-bit 4.75 6.0 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz 14-bit 10.5 14.7 ms To settle to within ±2 LSB , CLKIN = 8.192 MHz 16-bit 45 66 ms To settle to within ±2 LSB, CLKIN = 8.192 MHz EXC, EXC OUTPUTS Voltage 3.2 3.6 4.0 V p-p Load ±100 μA, typical differential output (EXC to EXC) = 7.2 V p-p Center Voltage 2.40 2.47 2.53 V Frequency 2 20 kHz EXC/EXC DC Mismatch 30 mV EXC/EXC AC Mismatch 100 mV THD −58 dB First five harmonics VOLTAGE REFERENCE REFOUT 2.40 2.47 2.53 V ±I = 100 μA OUT Drift 100 ppm/°C PSRR −60 dB CLKIN, XTALOUT6 V Voltage Input Low 0.8 V IL V Voltage Input High 2.0 V IH LOGIC INPUTS V Voltage Input Low 0.8 V V = 2.7 V to 5.25 V IL DRIVE 0.7 V V = 2.3 V to 2.7 V DRIVE V Voltage Input High 2.0 V V = 2.7 V to 5.25 V IH DRIVE 1.7 V V = 2.3 V to 2.7 V DRIVE I Low Level Input Current (Non 10 μA IL Pull-Up) IIL Low Level Input Current (Pull-Up) 80 μA RES0, RES1, RD, WR/FSYNC, A0, A1, and RESET pins I High Level Input Current −10 μA IH LOGIC OUTPUTS V Voltage Output Low 0.4 V V = 2.3 V to 5.25 V OL DRIVE V Voltage Output High 2.4 V V = 2.7 V to 5.25 V OH DRIVE 2.0 V V = 2.3 V to 2.7 V DRIVE I High Level Three-State Leakage −10 μA OZH I Low Level Three-State Leakage 10 μA OZL Rev. A | Page 4 of 36

AD2S1210 Parameter Min Typ Max Unit Conditions/Comments POWER REQUIREMENTS AV 4.75 5.25 V DD DV 4.75 5.25 V DD V 2.3 5.25 V DRIVE POWER SUPPLY I 12 mA AVDD I 35 mA DVDD I 2 mA OVDD 1 Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C. 2 The voltages, SIN, SINLO, COS, and COSLO, relative to AGND, must always be between 0.15 V and AVDD − 0.2 V. 3 All specifications within the angular accuracy parameter are tested at constant velocity, that is, zero acceleration. 4 The velocity accuracy specification includes velocity offset and dynamic ripple. 5 For example when RES0 = 0 and RES1 = 1, the position output has a resolution of 12 bits. The velocity output has a resolution of 11 bits with the MSB indicating the direction of rotation. In this example, with a CLKIN frequency of 8.192 MHz the velocity LSB is 0.488 rps, that is, 1000 rps/(211). 6 The clock frequency of the AD2S1210 can be supplied with a crystal, an oscillator, or directly from a DSP/microprocessor digital output. When using a single-ended clock signal directly from the DSP/microprocessor, the XTALOUT pin should remain open circuit and the logic levels outlined under the logic inputs parameter in Table 1 apply. Rev. A | Page 5 of 36

AD2S1210 TIMING SPECIFICATIONS AV = DV = 5.0 V ± 5%, T = T to T unless otherwise noted.1 DD DD A MIN MAX, Table 2. Parameter Description Limit at T , T Unit MIN MAX f Frequency of clock input 6.144 MHz min CLKIN 10.24 MHz max t Clock period ( = 1/f ) 98 ns min CK CLKIN 163 ns max t A0 and A1 setup time before RD/CS low 2 ns min 1 t Delay CS falling edge to WR/FSYNC rising edge 22 ns min 2 t Address/data setup time during a write cycle 3 ns min 3 t Address/data hold time during a write cycle 2 ns min 4 t Delay WR/FSYNC rising edge to CS rising edge 2 ns min 5 t Delay CS rising edge to CS falling edge 10 ns min 6 t Delay between writing address and writing data 2 × t + 20 ns min 7 CK t A0 and A1 hold time after WR/FSYNC rising edge 2 ns min 8 t Delay between successive write cycles 6 × t + 20 ns min 9 CK t Delay between rising edge of WR/FSYNC and falling edge of RD 2 ns min 10 t Delay CS falling edge to RD falling edge 2 ns min 11 t Enable delay RD low to data valid in configuration mode 12 V = 4.5 V to 5.25 V 37 ns min DRIVE V = 2.7 V to 3.6 V 25 ns min DRIVE V = 2.3 V to 2.7 V 30 ns min DRIVE t RD rising edge to CS rising edge 2 ns min 13 t Disable delay RD high to data high-Z 16 ns min 14A t Disable delay CS high to data high-Z 16 ns min 14B t Delay between rising edge of RD and falling edge of WR/FSYNC 2 ns min 15 t SAMPLE pulse width 2 × t + 20 ns min 16 CK t Delay from SAMPLE before RD/CS low 6 × t + 20 ns min 17 CK t Hold time RD before RD low 2 ns min 18 t Enable delay RD/CS low to data valid 19 V = 4.5 V to 5.25 V 17 ns min DRIVE V = 2.7 V to 3.6 V 21 ns min DRIVE V = 2.3 V to 2.7 V 33 ns min DRIVE t RD pulse width 6 ns min 20 t A0 and A1 set time to data valid when RD/CS low 21 V = 4.5 V to 5.25 V 36 ns min DRIVE V = 2.7 V to 3.6 V 37 ns min DRIVE V = 2.3 V to 2.7 V 29 ns min DRIVE t Delay WR/FSYNC falling edge to SCLK rising edge 3 ns min 22 t Delay WR/FSYNC falling edge to SDO release from high-Z 23 V = 4.5 V to 5.25 V 16 ns min DRIVE V = 2.7 V to 3.6 V 26 ns min DRIVE V = 2.3 V to 2.7 V 29 ns min DRIVE t Delay SCLK rising edge to DBx valid 24 V = 4.5 V to 5.25 V 24 ns min DRIVE V = 2.7 V to 3.6 V 18 ns min DRIVE V = 2.3 V to 2.7 V 32 ns min DRIVE t SCLK high time 0.4 × t ns min 25 SCLK t SCLK low time 0.4 × t ns min 26 SCLK t SDI setup time prior to SCLK falling edge 3 ns min 27 t SDI hold time after SCLK falling edge 2 ns min 28 Rev. A | Page 6 of 36

AD2S1210 Parameter Description Limit at T , T Unit MIN MAX t Delay WR/FSYNC rising edge to SDO high-Z 15 ns min 29 t Delay from SAMPLE before WR/FSYNC falling edge 6 × t + 20 ns ns min 30 CK t Delay CS falling edge to WR/FSYNC falling edge in normal mode 2 ns min 31 t A0 and A1 setup time before WR/FSYNC falling edge 2 ns min 32 t33 A0 and A1 hold time after WR/FSYNC falling edge2 In normal mode, A0 = 0, A1 = 0/1 24 × t + 5 ns ns min CK In configuration mode, A0 = 1, A1 = 1 8 × t + 5 ns ns min CK t Delay WR/FSYNC rising edge to WR/FSYNC falling edge 10 ns min 34 f Frequency of SCLK input SCLK V = 4.5 V to 5.25 V 20 MHz DRIVE V = 2.7 V to 3.6 V 25 MHz DRIVE V = 2.3 V to 2.7 V 15 MHz DRIVE 1 Temperature ranges are as follows: A, B grades: –40°C to +85°C; C, D grades: –40°C to +125°C. 2 A0 and A1 should remain constant for the duration of the serial readback. This may require 24 clock periods to read back the 8-bit fault information in addition to the 16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles. Rev. A | Page 7 of 36

AD2S1210 ABSOLUTE MAXIMUM RATINGS Table 3. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress AV to AGND, DGND −0.3 V to +7.0 V rating only; functional operation of the device at these or any DD DV to AGND, DGND −0.3 V to +7.0 V other conditions above those indicated in the operational DD V to AGND, DGND −0.3 V to AV section of this specification is not implied. Exposure to absolute DRIVE DD AVDD to DVDD −0.3 V to +0.3 V maximum rating conditions for extended periods may affect AGND to DGND −0.3 V to +0.3 V device reliability. Analog Input Voltage to AGND −0.3 V to AV + 0.3 V DD ESD CAUTION Digital Input Voltage to DGND −0.3 V to V + 0.3 V DRIVE Digital Output Voltage to DGND −0.3 V to V + 0.3 V DRIVE Analog Output Voltage Swing −0.3 V to AV + 0.3 V DD Input Current to Any Pin Except Supplies1 ±10 mA Operating Temperature Range (Ambient) A, B Grades −40°C to +85°C C, D Grades −40°C to +125°C Storage Temperature Range −65°C to +150°C θ Thermal Impedance2 54°C/W JA θ Thermal Impedance2 15°C/W JA RoHS-Compliant Temperature, Soldering 260(−5/+0)oC Reflow ESD 2 kV HBM 1 Transient currents of up to 100 mA do not cause latch-up. 2 JEDEC 2S2P standard board. Rev. A | Page 8 of 36

AD2S1210 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RES0 REFOUT REFBYP COS COSLOAVDD SINLO SIN AGND EXC EXC A0 48 47 46 45 44 43 42 41 40 39 38 37 RES1 1 36 A1 CS 2 PIN 1 35 DOS RD 3 34 LOT WR/FSYNC 4 33 RESET DGND 5 AD2S1210 32 DIR DVDD 6 TOP VIEW 31 NM CLKIN 7 (Not to Scale) 30 B XTALOUT 8 29 A SOE 9 28 DB0 SAMPLE 10 27 DB1 DB15/SDO 11 26 DB2 DB14/SDI 12 25 DB3 13 14 15 16 17 18 19 20 21 22 23 24 DB13/SCLK DB12 DB11 DB10 DB9VDRIVE DGND DB8 DB7 DB6 DB5 DB4 07467-002 Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 RES1 Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the resolution of the AD2S1210 to be programmed. Refer to the Configuration of AD2S1210 section. 2 CS Chip Select. Active low logic input. The device is enabled when CS is held low. 3 RD Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output enable for the parallel data outputs, DB15 to DB0. The output buffer is enabled when CS and RD are held low. When the SOE pin is low, the RD pin should be held high. 4 WR/FSYNC Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input enable for the parallel data inputs, DB7 to DB0. The input buffer is enabled when CS and WR/FSYNC are held low. When the SOE pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus. 5, 19 DGND Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1210. Refer all digital input signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 6 DV Digital Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD2S1210. The AV and DV DD DD DD voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 7 CLKIN Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of the AD2S1210. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the AD2S1210 is specified from 6.144 MHz to 10.24 MHz. 8 XTALOUT Crystal Output. When using a crystal or oscillator to supply the clock frequency to the AD2S1210, apply the crystal across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be considered a no connect pin. 9 SOE Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high. 10 SAMPLE Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity registers, after a high-to-low transition on the SAMPLE signal. The fault register is also updated after a high-to-low transition on the SAMPLE signal. 11 DB15/SDO Data Bit 15/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB15, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and WR/FSYNC. The bits are clocked out on the rising edge of SCLK. 12 DB14/SDI Data Bit 14/Serial Data Input Bus. When the SOE pin is high, this pin acts as DB14, a three-state data output pin controlled by CS and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The bits are clocked in on the falling edge of SCLK. Rev. A | Page 9 of 36

AD2S1210 Pin No. Mnemonic Description 13 DB13/SCLK Data Bit 13/Serial Clock. In parallel mode, this pin acts as DB13, a three-state data output pin controlled by CS and RD. In serial mode, this pin acts as the serial clock input. 14 to DB12 to Data Bit 12 to Data Bit 9. Three-state data output pins controlled by CS and RD. 17 DB9 18 V Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. DRIVE Decouple this pin to DGND. The voltage range on this pin is 2.3 V to 5.25 V and may be different to the voltage range at AV and DV but should never exceed either by more than 0.3 V. DD DD 20 DB8 Data Bit 8. Three-state data output pin controlled by CS and RD. 21 to DB7 to DB0 Data Bit 7 to Data Bit 0. Three-state data input/output pins controlled by CS, RD, and WR/FSYNC. 28 29 A Incremental Encoder Emulation Output A. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 30 B Incremental Encoder Emulation Output B. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 31 NM North Marker Incremental Encoder Emulation Output. Logic output. This output is free running and is valid if the resolver format input signals applied to the converter are valid. 32 DIR Direction. Logic output. This output is used in conjunction with the incremental encoder emulation outputs. The DIR output indicates the direction of the input rotation and is high for increasing angular rotation. 33 RESET Reset. Logic input. The AD2S1210 requires an external reset signal to hold the RESET input low until V is within the DD specified operating range of 4.75 V to 5.25 V. 34 LOT Loss of Tracking. Logic output. LOT is indicated by a logic low on the LOT pin and is not latched. Refer to the Loss of Position Tracking Detection section. 35 DOS Degradation of Signal. Logic output. Degradation of signal (DOS) is detected when either resolver input (sine or cosine) exceeds the specified DOS sine/cosine threshold or when an amplitude mismatch occurs between the sine and cosine input voltages. DOS is indicated by a logic low on the DOS pin. Refer to the Signal Degradation Detection section. 36 A1 Mode Select 1. Logic input. A1 in conjunction with A0 allows the mode of the AD2S1210 to be selected. Refer to the Configuration of AD2S1210 section. 37 A0 Mode Select 0. Logic input. A0 in conjunction with A1 allows the mode of the AD2S1210 to be selected. Refer to the Configuration of AD2S1210 section. 38 EXC Excitation Frequency. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation frequency register. 39 EXC Excitation Frequency Complement. Analog output. An on-board oscillator provides the sinusoidal excitation signal (EXC) and its complement signal (EXC) to the resolver. The frequency of this reference signal is programmable via the excitation frequency register. 40 AGND Analog Ground. This pin is the ground reference points for analog circuitry on the AD2S1210. Refer all analog input signals and any external reference signal to this AGND voltage. Connect the AGND pin to the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis. 41 SIN Positive Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. 42 SINLO Negative Analog Input of Differential SIN/SINLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. 43 AV Analog Supply Voltage, 4.75 V to 5.25 V. This pin is the supply voltage for all analog circuitry on the AD2S1210. The DD AV and DV voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a DD DD transient basis. 44 COSLO Negative Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. 45 COS Positive Analog Input of Differential COS/COSLO Pair. The input range is 2.3 V p-p to 4.0 V p-p. 46 REFBYP Reference Bypass. Connect reference decoupling capacitors at this pin. Typical recommended values are 10 μF and 0.01 μF. 47 REFOUT Voltage Reference Output. 48 RES0 Resolution Select 0. Logic input. RES0 in conjunction with RES1 allows the resolution of the AD2S1210 to be programmed. Refer to the Configuration of AD2S1210 section. Rev. A | Page 10 of 36

AD2S1210 TYPICAL PERFORMANCE CHARACTERISTICS T = 25°C, AV = DV = V = 5 V, SIN/SINLO = 3.15 V p-p, COS/COSLO = 3.15 V p-p, CLKIN = 8.192 MHz , unless otherwise noted. A DD DD DRIVE 9000 5000 4500 8000 4000 7000 3500 ODE6000 ODE3000 C C ER 5000 ER 2500 P P HITS 4000 HITS 2000 1500 3000 1000 2000 500 1000 0 8181 8182 8183 8184 8185 8186 8187 8188 8189CO8190DE8191 8192 8193 8194 8195 8196 8197 8198 8199 07467-003 81788179818081818182818381848185818681878188C8189OD8190E81918192819381948195819681978198819982008201 07467-006 Figure 3. Typical 16-Bit Angular Accuracy Histogram Of Codes, Figure 6. Typical 12-Bit Angular Accuracy Histogram of Codes, 10,000 Samples 10,000 Samples, Hysteresis Disabled 8000 12000 7000 10000 6000 8000 DE5000 DE O O C C HITS PER 43000000 HITS PER 64000000 2000 2000 1000 0 8181 8182 8183 8184 8185 8186 8187 8188 8189CO8190DE8191 8192 8193 8194 8195 8196 8197 8198 8199 07467-004 Figu0re 7. T5y1p0ical 12-B5i1t 1AngulaCr OA51cD2cEuSracy Hi5s1to3gram of 5C1o4des, 07467-017 Figure 4. Typical 14-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Enabled 10,000 Samples, Hysteresis Disabled 1400 12000 1200 10000 1000 CODE8000 R CODE800 PER 6000 S PE600 TS HIT HI4000 400 2000 200 0 0 2046 2047 C2O0D48ES 2049 2050 07467-005 817681778178817981808181818281838184818581868187CO8188DE818981908191819281938194819581968197819881998200 07467-018 Figure 5. Typical 14-Bit Angular Accuracy Histogram of Codes, Figure 8. Typical 10-Bit Angular Accuracy Histogram of Codes, 10,000 Samples, Hysteresis Enabled 10,000 Samples, Hysteresis Disabled Rev. A | Page 11 of 36

AD2S1210 12000 20 18 10000 16 14 E8000 s) COD gree12 R 6000 De10 PE E ( HITS 4000 ANGL 8 6 4 2000 2 0 126 127 CO12D8ES 129 130 07467-038 00 0.50 1.00 1.50 2.00TIM2E. 5(0ms)3.00 3.50 4.00 4.50 5.0007467-008 Figure 9. Typical 10-Bit Angular Accuracy Histogram of Codes, Figure 12. Typical 12-Bit 10° Step Response 10,000 Samples, Hysteresis Enabled 20 20 18 18 16 16 14 14 s) s) ee12 ee12 gr gr e e D10 D10 E ( E ( GL 8 GL 8 N N A A 6 6 4 4 2 2 00 4 8 12 16TIME2 0(ms)24 28 32 36 4007467-010 00 0.25 0.50 0.75 1.00TIM1E.2 (5ms1).50 1.75 2.00 2.25 2.5007467-007 Figure 10. Typical 16-Bit 10° Step Response Figure 13. Typical 10-Bit 10° Step Response 20 250 18 225 16 200 14 175 s) s) ee12 ee150 gr gr e e D10 D125 E ( E ( GL 8 GL100 N N A A 6 75 4 50 2 25 00 1 2 3 4TIME5 (ms)6 7 8 9 1007467-009 00 8 16 24 32TIME40 (ms)48 56 64 72 8007467-014 Figure 11. Typical 14-Bit 10° Step Response Figure 14. Typical 16-Bit 179° Step Response Rev. A | Page 12 of 36

AD2S1210 250 5 225 0 10-BIT 200 –5 175 –10 GLE (Degrees)111520050 GNITUDE (dB)–––122505 14-BIT 12-BIT N A 16-BIT A M 75 –30 50 –35 25 –40 00 2 4 6 8TIME10 (ms)12 14 16 18 2007467-013 –451 10 F1R0E0QUENCY (1Hkz) 10k 100k07467-015 Figure 15. Typical 14-Bit 179° Step Response Figure 18. Typical System Magnitude Response 250 0 10-BIT 225 –20 200 –40 175 –60 E (Degrees)115205 ASE (Degrees)–1–0800 14-BIT 12-BIT GL100 PH–120 16-BIT N A 75 –140 –160 50 –180 25 –200 00 1 2 3 4TIME5 (ms)6 7 8 9 1007467-012 1 10 F1R0E0QUENCY(1Hkz) 10k 100k 07467-016 Figure 16. Typical 12-Bit 179° Step Response Figure 19. Typical System Phase Response 250 10 225 9 200 8 s) e grees)117550 R (Degre 76 e O D125 R 5 GLE (100 G ER 4 N N A KI 75 C 3 A R 50 T 2 25 1 00 1 2TIME (ms)3 4 5 07467-011 00 500 AC1C0E0L0ERATION1 5(r0p0s2) 2000 250007467-022 Figure 17. Typical 10-Bit 179° Step Response Figure 20. Typical 16-Bit Tracking Error vs. Acceleration Rev. A | Page 13 of 36

AD2S1210 10 10 9 9 8 8 s) s) e e gre 7 gre 7 e e R (D 6 R (D 6 O O R 5 R 5 R R E E G 4 G 4 N N KI KI C 3 C 3 A A R R T 2 T 2 1 1 00 5000 10000 150A0C0CE2L00E0R0AT2I5O0N0 0(rp3s020)00 35000 40000 4500007467-021 00 200000 4A0C0C00E0LERA6T0I0O0N0 0(rps2)800000 1000000 07467-019 Figure 21. Typical 14-Bit Tracking Error vs. Acceleration Figure 23. Typical 10-Bit Tracking Error vs. Acceleration 10 9 8 s) e gre 7 e R (D 6 O R 5 R E G 4 N KI C 3 A R T 2 1 00 20000 60A0C00CELERAT10IO00N0 (0rps2) 140000 18000007467-020 Figure 22. Typical 12-Bit Tracking Error vs. Acceleration Rev. A | Page 14 of 36

AD2S1210 RESOLVER FORMAT SIGNALS Vr = Vp × sin(ωt) Vr= Vp× sin(ωt) R1 S2 S2 Va = Vs × sin(ωt) × cos(θ) R1 Va = Vs × sin(ωt) × cos(θ) θ S4 θ S4 R2 R2 S1 S3 S1 S3 Vb = Vs × sin(ωt) × sin(θ) Vb = Vs × sin(ωt) × sin(θ) (A) CLASSICAL RESOLVER (B)VARIABLE RELUCTANCE RESOLVER 07467-023 Figure 24. Classical Resolver vs. Variable Reluctance Resolver A resolver is a rotating transformer, typically with a primary The stator windings are displaced mechanically by 90° (see winding on the rotor and two secondary windings on the stator. Figure 24). The primary winding is excited with an ac reference. In the case of a variable reluctance resolver, there are no wind- The amplitude of subsequent coupling onto the stator secondary ings on the rotor, as shown in Figure 24. The primary winding windings is a function of the position of the rotor (shaft) relative to is on the stator as well as the secondary windings, but the saliency the stator. The resolver, therefore, produces two output voltages in the rotor design provides the sinusoidal variation in the (S3 − S1, S2 − S4) modulated by the sine and cosine of shaft secondary coupling with the angular position. Either way, the angle. Resolver format signals refer to the signals derived from resolver output voltages (S3 − S1, S2 − S4) have the same the output of a resolver, as shown in Equation 1. Figure 25 equations, as shown in Equation 1. illustrates the output format. S3−S1=E sinωt×sinθ 0 (1) S2−S4=E sinωt×cosθ 0 where: S2 – S4 (cos) θ is the shaft angle. Sinωt is the rotor excitation frequency. S3 – S1 E0 is the rotor excitation amplitude. (sin) R2 – R4 (REF) 0° 90° 18θ0° 270° 360°07467-024 Figure 25. Electrical Resolver Representation Rev. A | Page 15 of 36

AD2S1210 THEORY OF OPERATION RESOLVER TO DIGITAL CONVERSION Monitor=A1×sinθ×sinφ+A2×cosθ×cosφ (4) The AD2S1210 operates on a Type II tracking closed-loop where: principle. The output continually tracks the position of the A1 is the amplitude of the incoming sine signal (A1 × sinθ). resolver without the need for external conversion and wait A2 is the amplitude of the incoming cosine signal (A2 × cosθ). states. As the resolver moves through a position equivalent θ is the resolver angle. to the least significant bit weighting, the output is updated by ϕ is the angle stored in the position register. one LSB. Note that Equation 4 is shown after demodulation, with the The converter tracks the shaft angle θ by producing an output Carrier Signal sinωt removed. Also, note that for matched input angle ϕ that is fed back and compared to the input angle θ, and signal (that is, a no fault condition), A1 = A2. the resulting error between the two is driven towards 0 when When A1 = A2 and the converter is tracking (θ = ϕ), the the converter is correctly tracking the input angle. To measure monitor signal output has a constant magnitude of A1 (Monitor the error, S3 − S1 is multiplied by cosϕ and S2 − S4 is multiplied by = A1 × (sin2 θ + cos2 θ) = A1), which is independent of shaft sinϕ to give angle. When A1 ≠ A2, the monitor signal magnitude varies E0sinωt×sinθcosφ (for S3 − S1) between A1 and A2 at twice the rate of shaft rotation. The monitor signal is used as described in the following sections to E sinωt×cosθsinφ (for S2 − S4) 0 detect degradation or loss of input signals. The difference is taken, giving Loss of Signal Detection E sinωt×(sinθcosφ−cosθsinφ) (2) 0 The AD2S1210 indicates that a loss of signal (LOS) has This signal is demodulated using the internally generated occurred for four separate conditions. synthetic reference, yielding • When either resolver input (sine or cosine) falls below the E (sinθcosφ−cosθsinφ) (3) specified LOS sine/cosine threshold. This threshold is 0 defined by the user and is set by writing to the internal Equation 3 is equivalent to Esin(θ − ϕ), which is approximately 0 register, Address 0x88 (see the Register Map section). equal to E(θ − ϕ) for small values of θ − ϕ, where θ − ϕ = 0 • When any of the resolver input pins (SIN, SINLO, COS, or angular error. COSLO) are disconnected from the sensor. The value E0 (θ − ϕ) is the difference between the angular error • When any of the resolver input pins (SIN, SINLO, COS, or of the rotor and the digital angle output of the converter. COSLO) are clipping the power rail or ground rail of the A phase-sensitive demodulator, some integrators, and a compensa- AD2S1210. Refer to the Sine/Cosine Input Clipping section. tion filter form a closed-loop system that seeks to null the error • When a configuration parity error has occurred. Refer to signal. When this is accomplished, ϕ equals the Resolver Angle θ the Configuration Parity Error section. within the rated accuracy of the converter. A Type II tracking A loss of signal is caused if either of the stator windings of the loop is used so that constant velocity inputs can be tracked resolver (sine or cosine) are open circuit or have a number of without inherent error. shorted turns. LOS is indicated by both the DOS and LOT pins FAULT DETECTION CIRCUIT latching as logic low outputs. The DOS and LOT pins are reset to a no fault state when the user enters configuration mode and The AD2S1210 fault detection circuit can sense loss of resolver reads the fault register. The LOS condition has priority over signals, out-of-range input signals, input signal mismatch, or both the DOS and LOT conditions, as shown in Table 6. To loss of position tracking; however, in the event of a fault, the determine the cause of the LOS fault detection, the user must position indicated by the AD2S1210 may differ significantly read the fault register, Address 0xFF (see the Register Map section). from the actual shaft position of the resolver. When a loss of signal is detected due to the resolver inputs (sine Monitor Signal or cosine) falling below the specified LOS sine/cosine threshold, The AD2S1210 generates a monitor signal by comparing the the electrical angle through which the resolver may rotate before angle in the position register to the incoming sine and cosine the LOS can be detected by the AD2S1210 is referred to as the signals from the resolver. The monitor signal is created in a LOS angular latency. This is defined by the specified LOS sine/ similar fashion to the error signal described in the Resolver to cosine threshold set by the user and the maximum amplitude of Digital Conversion section. The incoming signals, sinθ and the input signals being applied to the AD2S1210. The worst-case cosθ, are multiplied by the sin and cos of the output angle, angular latency can be calculated as follows: respectively, and then added together. Rev. A | Page 16 of 36

AD2S1210 Angular Latency = window counter periods for the range of excitation frequencies ⎡ LOSthreshold ⎤ on the AD2S1210 are outlined in Table 5. 2×Arccos⎢ ⎥ (5) ⎢⎣maxsine/cosineamplitude⎥⎦ Table 5. Window Counter Period vs. Excitation Frequency Range, CLKIN = 8.192 MHz The preceding equation is based on the worst-case angular Number of Window error, which can be seen by the AD2S1210 before an LOS fault Excitation Frequency Internal Clock Counter Period is indicated. This occurs if one of the resolver input signals, Range Cycles (μs)1 either sine or cosine, is lost while the remaining signal is at its 2 kHz ≤ Exc Freq < 4 kHz 1065 260 peak amplitude, for example, if the sine input is lost while the 4 kHz ≤ Exc Freq < 8 kHz 554 135.25 input angle is 90°. The worst-case angular latency is twice the 8 kHz ≤ Exc Freq ≤ 20 kHz 256 62.5 worst-case angular error. Signal Degradation Detection 1 CLKIN = 8.192 MHz. The window counter period scales with clock frequency and can be calculated by multiplying the number of internal clock cycles by The AD2S1210 indicates that a degradation of signal (DOS) has the period of the internal clock frequency, that is, CLKIN/2. occurred for two separate conditions. The AD2S1210 detects an LOS or DOS due to the resolver inputs (sine or cosine) falling below or exceeding the LOS and DOS • When either resolver input (sine or cosine) exceeds the thresholds within two window counter periods. For example, specified DOS sine/cosine threshold. This threshold is with an excitation frequency of 10 kHz, a fault is detected within defined by the user and is set by writing to the internal 125 μs. A persistent fault is detected within one window counter register, Address 0x89 (see the Register Map section). period of the reading and clearing the fault register. • When the amplitudes of the input signals, sine and cosine, mismatch by more than the specified DOS sine/cosine Note that the time latency to detect the occurrence of a DOS mismatch threshold. This threshold is defined by the user mismatch fault is dependent on the speed of rotation of the and is set by writing to the internal register, Address 0x8A resolver. The worst-case time latency to detect a DOS mismatch (see the Register Map section). The AD2S1210 continuously fault is the time required for one full rotation of the resolver. stores the minimum and maximum magnitude of the moni- Loss of Position Tracking Detection tor signal in internal registers. The difference between the The AD2S1210 indicates that a loss of tracking (LOT) has minimum and maximum is calculated to determine if a occurred when DOS mismatch has occurred. The initial values for the minimum and maximum internal registers must be defined • The internal error signal of the AD2S1210 has exceeded by the user, at Address 0x8C and Address 0x8B, respectively the specified angular threshold. This threshold is defined (see the Register Map section). by the user and is set by writing to the internal register, Address 0x8D (see the Register Map section). DOS is indicated by a logic low on the DOS pin. When DOS is • The input signal exceeds the maximum tracking rate. The indicated, the output is latched low until the user enters configura- maximum tracking rate depends on the resolution defined tion mode and reads the fault register. The DOS condition has by the user and the CLKIN frequency. priority over the LOT condition, as shown in Table 6. To deter- mine the cause of the DOS fault detection, the user must read LOT is indicated by a logic low on the LOT pin and is not latched. the fault register, Address 0xFF (see the Register Map section). LOT has hysteresis and is not cleared until the internal error signal is less than the value defined in the LOT low threshold Time Latency for LOS and DOS Detection register, Address 0x8E (see the Register Map section). Note that the monitor signal is generated on the active edge of When the maximum tracking rate is exceeded, LOT is cleared the internal AD2S1210 clock. The internal clock is generated only if the velocity is less than the maximum tracking rate and by dividing the externally applied CLKIN frequency by 2; for the internal error signal is less than the value defined in the LOT example, when using a CLKIN frequency of 8.192 MHz the low threshold register. LOT can be indicated for step changes in internal AD2S1210 clock is 4.096 MHz. The AD2S1210 conti- position (such as after a RESET signal is applied to the AD2S1210). nuously stores the minimum and maximum magnitude of the It is also useful as a built-in test to indicate that the tracking monitor signal in internal registers. The values stored in these converter is functioning properly. The LOT condition has lower internal registers are compared to the LOS and DOS thresholds priority than both the DOS and LOS conditions, as shown in configured by the user at set intervals. This interval, known as Table 6. The LOT and DOS conditions cannot be indicated using the window counter period, is dependent on the excitation the LOT and DOS pins at the same time. However, both condi- frequency configured by the user. It is set to ensure that two tions are indicated separately in the fault register. To determine window counter periods include at least one full period of the the cause of the LOT fault detection, the user must read the fault excitation frequency applied to the resolver. The window register, Address 0xFF (see the Register Map section). counter period is defined in terms of internal clock cycles. The Rev. A | Page 17 of 36

AD2S1210 Table 6. Fault Detection Decoding The AD2S1210 also provides an internal synthetic reference Order of signal that is phase locked to its sine and cosine inputs. Phase Condition DOS Pin LOT Pin Priority errors between the resolver primary and secondary windings Loss of Signal (LOS) 0 0 1 can degrade the accuracy of the RDC and are compensated by Degradation of Signal (DOS) 0 1 2 this synchronous reference signal. This also compensates the Loss of Tracking (LOT) 1 0 3 phase shifts due to temperature and cabling and eliminates the No Fault 1 1 N/A need of an external preset phase compensation circuit. Sine/Cosine Input Clipping SYNTHETIC REFERENCE GENERATION The AD2S1210 indicates that a clipping error has occurred if When a resolver undergoes a high rotation rate, the RDC tends any of the resolver input pins (SIN, SINLO, COS, or COSLO) to act as an electric motor and produces speed voltages, along are clipping the power rail or ground rail of the AD2S1210. The with the ideal sine and cosine outputs. These speed voltages are clipping fault is indicated if the input amplitudes are less than in quadrature to the main signal waveform. Moreover, nonzero 0.15 V or greater then AVDD − 0.2 V for more than 4 μs. resistance in the resolver windings causes a nonzero phase shift Sine/cosine input clipping error is indicated by both the DOS and between the reference input and the sine and cosine outputs. LOT pins latching as logic low outputs. Sine/cosine input clipping The combination of speed voltages and phase shift causes a track- error is also indicated by Bit D7 of the fault register being set high. ing error in the RDC that is approximated by The DOS and LOT pins are reset to a no fault state when the RotationRate Error=PhaseShift× (6) user enters configuration mode and reads the fault register. ReferenceFrequency Configuration Parity Error To compensate for the described phase error between the resolver The AD2S1210 includes a number of user programmable registers reference excitation and the sine/cosine signals, an internal that allow the user to configure the part. Each read/write register synthetic reference signal is generated in phase with the refer- on the AD2S1210 is programmed with seven bits of informa- ence frequency carrier. The synthetic reference is derived using tion by the user. The 8th bit is reserved as a parity error bit. In the internally filtered sine and cosine signals. It is generated the event that the data within these registers becomes corrupted, by determining the zero crossing of either the sine or cosine the AD2S1210 indicates that a configuration parity error has (whichever signal is larger, to improve phase accuracy) and occurred. Configuration parity error is indicated by both the DOS evaluating the phase of the resolver reference excitation. The and LOT pins latching as logic low outputs. Configuration parity synthetic reference reduces the phase shift between the refer- error is also indicated by Bit D0 of the fault register being set ence and sine/cosine inputs to less than 10°, and operates for high. In the event that a parity error occurs, it is recommended phase shifts of ±44°. If additional phase lock range is required, that the user reset the part using the RESET pin. Bit D5 in the control register can be set to zero to expand the Phase Lock Error phase lock range to 360° (see the Control Register section). The AD2S1210 indicates that a phase lock error has occurred if CONNECTING THE CONVERTER the difference between the phase of the excitation frequency Ground is connected to the AGND and DGND pins (see and the phase of the sine and cosine signals exceeds the specified Figure 26). A positive power supply (V ) of 5 V dc ± 5% is DD phase lock range. Phase lock error is indicated by a logic low on connected to the AV and DV pins, with typical values for the DD DD the LOT pin and is not latched. Phase lock error is also indicated decoupling capacitors being 10 nF and 4.7 μF. These capacitors by Bit D1 of the fault register being set high. are then placed as close to the device pins as possible and are ON-BOARD PROGRAMMABLE SINUSOIDAL connected to both AV and DV . The V pin is connected DD DD DRIVE OSCILLATOR to the supply voltage of the microprocessor. The voltage applied to the V input controls the voltage of the parallel and serial An on-board oscillator provides the sinusoidal excitation signal DRIVE interfaces. V can be set to 5 V, 3 V, or 2.5 V. Typical values (EXC) to the resolver as well as its complemented signal (EXC). DRIVE for the V decoupling capacitors are 10 nF and 4.7 μF. DRIVE The frequency of this reference signal is programmable to a Typical values for the oscillator decoupling capacitors are 20 pF, number of standard frequencies between 2 kHz and 20 kHz. whereas typical values for the reference decoupling capacitors are The amplitude of this signal is 3.6 V p-p and is centered on 2.5 V. 10 nF and 10 μF. The reference excitation output of the AD2S1210 needs an external buffer amplifier to provide gain and the additional current to drive a resolver. Rev. A | Page 18 of 36

AD2S1210 S2 R2 Figure 27 shows a suggested buffer circuit. Capacitor C1 may be used in parallel with Resistor R2 to filter out any noise that may exist on the EXC and EXC outputs. Care should be taken when 5V S4 S3 S1 R1 selecting the cutoff frequency of this filter to ensure that phase BUFFER BUFFER shifts of the carrier caused by the filter do not exceed the phase 4.7µF 10nF CIRCUIT CIRCUIT lock range of the AD2S1210. The gain of the circuit is 10nF 10µF 48 47 46 45 44 43 42 41 40 39 38 37 T P S O D O N D C C CarrierGain=−(R2/R1)×(1/(1+R2×C1×ω)) (7) 12 REFOU REFBY CO COSLAVD SINL SI AGN EX EX 3356 and 3 34 4 33 ⎛ ⎛ R2⎞⎞ ⎛R2⎞ ⎛ 1 ⎞ V =⎜V ×⎜1+ ⎟⎟−⎜ ⎟×⎜ ⎟V (8) 10nF 4.7µF 5 DGND 32 OUT ⎝ REF ⎝ R1⎠⎠ ⎝R1⎠ ⎝1+R2×C1×ω⎠ IN 6 DVDD AD2S1210 31 5V 7 CLKIN 30 where: 8 XTALOUT 29 ω is the radian frequency of the applied signal. 9 28 V , a dc voltage, is set so that V is always a positive value, REF OUT 10 27 8.192 eliminating the need for a negative supply. MHZ 1121 DRIVE GND 2256 C1 V D 20pF 20pF 13 14 15 16 17 18 19 20 21 22 23 24 R2 12V VDRIVE 12V Figure 26. Connecting the1 A0DnF2S1210 to a4 .R7µeFsolver 07467-025 EXC/(EVXINC) (RV1REF) AD8662 VOUT In this recommended configuration, the converter introduces a fVroREmF/2 t hoeff sreets oinlv tehre. TSIhNe, sSiInNe LaOn,d C cOosSi,n aen sdi gCnOalSsL cOan s iegancahl obuet puts 5V 07467-026 connected to a different potential relative to ground if the sine Figure 27. Buffer Circuit and cosine signals adhere to the recommended specifications. A separate screened twisted pair cable is recommended for the Note that because the EXC and EXC outputs are differential, analog input pins, SIN, SINLO, COS, and COSLO. The screens there is an inherent gain of 2×. should terminate to either REFOUT or AGND. Rev. A | Page 19 of 36

AD2S1210 CONFIGURATION OF AD2S1210 MODES OF OPERATION Note that the recommended frequency range for each resolution and bandwidth, as outlined in Table 7, are defined for a clock The AD2S1210 has two modes of operation: configuration mode frequency of 8.192 MHz. The recommended excitation frequency and normal mode. The configuration mode is used to program range scales with the clock frequency of the AD2S1210. The the registers that set the excitation frequency, the resolution, default excitation frequency of the AD2S1210 is 10 kHz when and the fault detection thresholds of the AD2S1210. Configuration operated with a clock frequency of 8.192 MHz. mode is also used to read back the information in the fault register. The data in the position and velocity registers can also be read A0, A1 Inputs back while in configuration mode. The AD2S1210 can be operated The AD2S1210 allows the user to read the angular position or entirely in configuration mode or, when the initial configuration is the angular velocity data directly from the parallel outputs or completed, the part can be taken out of configuration mode and through the serial interface. The required information can be operated in normal mode. When operating in normal mode, the selected using the A0 and A1 inputs. These inputs should also data outputs can provide angular position or angular velocity be used to put the part into configuration mode. The data from data. The A0 and A1 inputs are used to determine whether the the fault register and the remaining on-chip registers can be AD2S1210 is in configuration mode and to determine whether accessed in configuration mode. the position or velocity data is supplied to the output pins, see Table 8. Table 8. Configuration Mode Settings Setting the Excitation Frequency A0 A1 Result 0 0 Normal mode—position output The excitation frequency of the AD2S1210 is set by writing a 0 1 Normal mode—velocity output frequency control word to the excitation frequency register, 1 0 Reserved Address 0x91 (see the Register Map section). 1 1 Configuration mode ( ) FCW×f ExcitationFrequency= CLKIN RES0, RES1 Inputs 215 In normal mode, the resolution of the digital output is selected where FCW is the frequency control word and f is the clock CLKIN using the RES0 and RES1 input pins. In configuration mode, frequency of the AD2S1210. the resolution is selected by setting the RES0 and RES1 bits in The specified range of the excitation frequency is from 2 kHz to the control register. When switching between normal mode and 20 kHz and can be set in increments of 250 Hz. To achieve the configuration mode, it is the responsibility of the user to ensure angular accuracy specifications in Table 1, the excitation frequency that the resolution set in the control register matches the resolution should be selected as outlined in Table 7. set by the RES0 and RES1 input pins. Failure to do so may result in incorrect data on the outputs, caused by the differences Table 7. Recommended Excitation Frequency vs. Resolution between the resolution settings. (f = 8.192 MHz) CLKIN Typical Min Excitation Max Excitation Table 9. Resolution Settings Resolution Bandwidth Frequency Frequency Resolution Position LSB Velocity LSB 10 Bits 4100 Hz 10 kHz 20 kHz RES0 RES1 (Bits) (Arc min) (rps)1 12 Bits 1700 Hz 6 kHz 20 kHz 0 0 10 21.1 4.88 14 Bits 900 Hz 3 kHz 12 kHz 0 1 12 5.3 0.488 16 Bits 250 Hz 2 kHz 10 kHz 1 0 14 1.3 0.06 1 1 16 0.3 0.004 1 CLKIN = 8.192 MHz. The velocity LSB size and maximum tracking rate scale linearly with the CLKIN frequency. Rev. A | Page 20 of 36

AD2S1210 REGISTER MAP maximum velocity that the AD2S1210 can track for each Table 10. Register Map resolution is specified in Table 1. For example, the maximum Register Register Read/Write tracking rate of the AD2S1210 at 16 bits resolution, with an Register Name Address Data Register 8.192 MHz input clock, is ±125 rps. A velocity of +125 rps Position 0x80 D15 to D8 Read only results in 0x7FFF being stored in the velocity register; a velocity 0x81 D7 to D0 Read only of −125 rps results in 0x8000 being stored in the velocity register. Velocity 0x82 D15 to D8 Read only The value stored in the velocity register is 16 bits regardless of 0x83 D7 to D0 Read only resolution. At lower resolutions, the LSBs of the 16-bit digital LOS Threshold 0x88 D7 to D0 Read/write output should be ignored. For example, at 10-bit resolution, DOS Overrange 0x89 D7 to D0 Read/write Threshold Data Bit D15 to Data Bit D6 provide valid data; D5 to D0 should DOS Mismatch 0x8A D7 to D0 Read/write be ignored. The maximum tracking rate of the AD2S1210 at Threshold 10-bit resolution with an 8.192 MHz input clock is ±2500 rps. DOS Reset Max 0x8B D7 to D0 Read/write A velocity of +2500 rps results in 0x1FF being stored in Bit D15 to Threshold Bit D6 of the velocity register; a velocity of −2500 rps results in DOS Reset Min 0x8C D7 to D0 Read/write 0x3FF being stored in Bit D15 to Bit D6 of the velocity register. In Threshold this 10-bit example, the LSB size of the velocity output is 4.88 rps. LOT High Threshold 0x8D D7 to D0 Read/write LOS THRESHOLD REGISTER LOT Low Threshold 0x8E D7 to D0 Read/write Excitation Frequency 0x91 D7 to D0 Read/write Table 13. 8-Bit Register Control 0x92 D7 to D0 Read/write Address Bit Read/Write Soft Reset 0xF0 D7 to D0 Write only 0x88 D7 to D0 Read/write Fault 0xFF D7 to D0 Read only The LOS threshold register determines the loss of signal threshold POSITION REGISTER of the AD2S1210. The AD2S1210 allows the user to set the LOS threshold to a value between 0 V and 4.82 V. The resolution of Table 11. 16-Bit Register the LOS threshold is seven bits, that is, 38 mV. Note that the MSB, Address Bit Read/Write D7, should be set to 0. The default value of the LOS threshold 0x80 D15 to D8 Read only on power-up is 2.2 V. 0x81 D7 to D0 Read only DOS OVERRANGE THRESHOLD REGISTER The position register contains a digital representation of the angular position of the resolver input signals. The values are Table 14. 8-Bit Register stored in 16-bit binary format. The value in the position register Address Bit Read/Write is updated following a falling edge on the SAMPLE input. 0x89 D7 to D0 Read/write Note that with hysteresis enabled (see the Control Register section), The DOS overrange threshold register determines the degradation at lower resolutions, the LSBs of the 16-bit digital output are set to of signal threshold of the AD2S1210. The AD2S1210 allows the zero. For example, at 10-bit resolution, Data Bit D15 to Data Bit D6 user to set the DOS overrange threshold to a value between 0 V provide valid data; D5 to D0 are set to zero. With hysteresis dis- and 4.82 V. The resolution of the DOS overrange threshold is abled, the value stored in the position register is 16 bits regardless seven bits, that is, 38 mV. Note that the MSB, D7, should be set to of resolution. At lower resolutions, the LSBs of the 16-bit digital 0. The default value of the DOS overrange threshold on power-up output can be ignored. For example, at 10-bit resolution, Data is 4.1 V. Bit D15 to Data Bit D6 provide valid data; D5 to D0 can be DOS MISMATCH THRESHOLD REGISTER ignored. VELOCITY REGISTER Table 15. 8-Bit Register Address Bit Read/Write Table 12. 16-Bit Register 0x8A D7 to D0 Read/write Address Bit Read/Write The DOS mismatch threshold register determines the signal 0x82 D15 to D8 Read only mismatch threshold of the AD2S1210. The AD2S1210 allows 0x83 D7 to D0 Read only the user to set the DOS mismatch threshold to a value between The velocity register contains a digital representation of the angular 0 V and 4.82 V. The resolution of the DOS mismatch threshold velocity of the resolver input signals. The value in the velocity is seven bits, that is, 38 mV. Note that the MSB, D7, should be register is updated following a falling edge on the sample input. set to 0.The default value of the DOS mismatch threshold on The values are stored in 16-bit, twos complement format. The power-up is 380 mV. Rev. A | Page 21 of 36

AD2S1210 DOS RESET MAXIMUM AND MINIMUM Table 19. LOT High/Low Threshold THRESHOLD REGISTERS LOT Low LOT High Resolution Range LSB Size Default Default Table 16. 8-Bit Registers (Bits) (Degrees) (Degrees) (Degrees) (Degrees) Address Bit Read/Write 10 0 to 45 0.35 2.5 12.5 0x8B D7 to D0 Read/write 12 0 to 18 0.14 1.0 5.0 14 0 to 9 0.09 0.5 2.5 0x8C D7 to D0 Read/write 16 0 to 9 0.09 0.5 2.5 The AD2S1210 continuously stores the minimum and maximum EXCITATION FREQUENCY REGISTER magnitude of the monitor signal in internal registers. The differ- ence between the minimum and maximum is calculated to Table 20. 8-Bit Register determine if a DOS mismatch has occurred. The initial values Address Bit Read/Write for the minimum and maximum internal registers must be 0x91 D7 to D0 Read/write defined by the user. When the fault register is cleared, the The excitation frequency register determines the frequency of registers that store the maximum and minimum amplitudes of the excitation outputs of the AD2S1210. A 7-bit frequency control the monitor signal are reset to the values stored in the DOS reset word is written to the register to set the excitation frequency. maximum and minimum threshold registers. The resolution of Note that the MSB, D7, should be set to 0. the DOS reset maximum and minimum thresholds is seven bits ( ) each, that is, 38 mV. Note that the MSB, D7, should be set to ExcitationFrequency×215 FCW= (9) 0.To ensure correct operation, it is recommended that the DOS f CLKIN reset minimum threshold register be set to at least 1 LSB less where FCW is the frequency control word and f is the clock than the DOS overrange threshold, and the DOS reset maximum CLKIN frequency of the AD2S1210. The specified range of the excitation threshold register be set to at least 1 LSB greater than the LOS frequency is from 2 kHz to 20 kHz and can be set in increments threshold register. The default value of the DOS reset minimum of 250 Hz. To ensure that the AD2S1210 is operated within the threshold register and the DOS reset maximum threshold specified frequency range, the frequency control word should register are 3.99 V and 2.28 V, respectively. be a value between 0x4 and 0x50. LOT HIGH THRESHOLD REGISTER For example, if the user requires an excitation frequency of 5 kHz Table 17. 8-Bit Register and has an 8.192 MHz clock frequency, the code that needs to Address Bit Read/Write be programmed is given by 0x8D D7 to D0 Read/write (5kHz×215) FCW = =14(hexadecimal) The LOT high threshold register determines the loss of position 8.192MHz tracking threshold for the AD2S1210. The LOT high threshold The default excitation frequency of the AD2S1210 on power-up is a 7-bit word. Note that the MSB, D7, should be set to 0. The is 10 kHz. range of the LOT high threshold, the LSB size, and the default value of the LOT high threshold on power-up are dependent on CONTROL REGISTER the resolution setting of the AD2S1210, and are outlined in Table 19. Table 21. 8-Bit Register Address Bit Read/Write LOT LOW THRESHOLD REGISTER 0x92 D7 to D0 Read/write Table 18. 8-Bit Register The control register is an 8-bit register that sets the AD2S1210 Address Bit Read/Write control modes. The default value of the control register on 0x8E D7 to D0 Read/write power-up is 0x7E. The LOT low threshold register determines the level of hysteresis Table 22. Control Register Bit Descriptions on the loss of position tracking fault detection. Loss of tracking Bit Description (LOT) occurs when the internal error signal of the AD2S1210 D7 Address/data bit exceeds the LOT high threshold. LOT has hysteresis and is not D6 Reserved; set to 1 cleared until the internal error signal is less than the value defined D5 Phase lock range in the LOT low threshold register. The LOT low threshold is a 0 = 360°, 1 = ±44° 7-bit word. Note that the MSB, D7, should be set to 0. The range D4 0 = disable hysteresis, 1 = enable hysteresis of the LOT high threshold, the LSB size, and the default value of D3 Set Encoder Resolution EnRES1 the LOT high threshold on power-up are dependent on the resolu- D2 Set Encoder Resolution EnRES0 tion setting of the AD2S1210, and are outlined in Table 19. D1 Set Resolution RES1 D0 Set Resolution RES0 Rev. A | Page 22 of 36

AD2S1210 Address/Data Bit Table 23. Encoder Resolution Settings The MSB of each 8-bit word written to the AD2S1210 indicates EnRES0 EnRES1 Resolution (Bits) whether the 8-bit word is a register address or data. The MSB 0 0 10 (D7) of each register address defined on the AD2S1210 is high. 0 1 12 The MSB of each data word written to the AD2S1210 is low. 1 0 14 Note that when a data word is written to the AD2S1210, the 1 1 16 MSB is internally reconfigured as a parity bit. When reading Set Resolution data from any of the read/write registers (see Table 10), the In normal mode, the resolution of the digital output is selected parity of Bit D6 to Bit D0 is recalculated and compared to the using the RES0 and RES1 input pins (see Table 9). In configuration previously stored parity bit. The MSB of the 8-bit output is used mode, the resolution is selected by setting the RES0 and RES1 to indicate whether a configuration error has occurred. If the bits in the control register. When switching between normal mode MSB is returned high, this indicates that the data read back from and configuration mode, it is the responsibility of the user to the device does not match the configuration data written to the ensure that the resolution set in the control register matches the device in the previous write cycle. resolution set by the RES0 and RES1 input pins. The default resolu- Phase Lock Range tion of the digital output on power-up is 12 bits. The phase lock range allows the AD2S1210 to compensate for SOFTWARE RESET REGISTER phase errors between the excitation frequency and the sine/cosine Table 24. 8-Bit Register inputs. The recommended mode of operation is to use the default Address Bit Read/Write phase lock range of ±44°. If additional phase lock range is required, a range of 360° can be set. However, in this mode of 0xF0 D7 to D0 Write only operation, the AD2S1210 should be reset following a loss of Addressing the software reset register, that is writing the 8-bit signal error. Failure to do so may result in a 180° error in the address, 0xF0, of the software reset register to the AD2S1210 angular output data. while in configuration mode, allows the user to initiate a soft- Hysteresis ware reset of the AD2S1210. The software reset reinitializes the excitation frequency outputs and the internal Type II tracking loop. The AD2S1210 includes a hysteresis function, ±1 LSB, between The data stored in the configuration registers is not overwritten the output of the position integrator and the input to the position by a software reset. However, it should be noted that the data in register. When operating in a noisy environment, this can be used the fault register is reset. In an application that uses two or more to prevent flicker on the LSB. On the AD2S1210, the maximum resolver-to-digital converters, which are both driven from the same tracking rate is defined by the bandwidth. Each resolution setting clock source, the software reset can be used to synchronize the is internally configured with a different bandwidth, as outlined phase of the excitation frequencies across the converters. in Table 1. The maximum tracking rate and the bandwidth are inversely proportional to the resolution, that is, the maximum FAULT REGISTER tracking rate increases as the resolution is decreased. The option Table 25. 8-Bit Register of disabling the hysteresis allows the user to oversample the Address Bit Read/Write position output and to achieve a higher resolution output within 0xFF D7 to D0 Read only the specified bandwidths through external averaging. The AD2S1210 has the ability to detect eight separate fault condi- The hysteresis function can be enabled or disabled through tions. When a fault occurs, the DOS and/or the LOT output setting Bit D4 in the control register. Hysteresis is enabled by pins are taken low. By reading the fault register, the user can default on power-up. determine the cause of the triggering of the fault detection output Set Encoder Resolution pins. Note that the fault register bits are active high, that is, the The resolution of the encoder outputs of the AD2S1210 can be fault bits are taken high to indicate that a fault has occurred. set to the same resolution as the digital output or it can also be Table 26. Fault Register Bit Descriptions set to a lower resolution. For example, when the resolution of Bit Description the AD2S1210 position outputs is set to 16 bits, the resolution D7 Sine/cosine inputs clipped of the encoder outputs may be set to 14, 12, or 10 bits. This D6 Sine/cosine inputs below LOS threshold allows the user to take advantage of the lower bandwidth and D5 Sine/cosine inputs exceed DOS overrange threshold improved performance of the 16-bit resolution setting without D4 Sine/cosine inputs exceed DOS mismatch threshold requiring external divide down of the A-quad-B encoder outputs. D3 Tracking error exceeds LOT threshold The default resolution of the encoder outputs on power-up is 16 D2 Velocity exceeds maximum tracking rate bits. Refer to the Incremental Encoder Outputs section. D1 Phase error exceeds phase lock range D0 Configuration parity error Rev. A | Page 23 of 36

AD2S1210 DIGITAL INTERFACE The angular position and angular velocity are represented by Reading from the AD2S1210 binary data and can be extracted either via a 16-bit parallel The following data can be read back from the AD2S1210: interface or via a 4-wire serial interface that operates at clock • Angular position rates of up to 25 MHz. The AD2S1210 programmable functions • Angular velocity are controlled using a set of on-chip registers. Data is written to these registers using either the serial or the parallel interface. • Fault register data • Status of on-chip registers SOE INPUT The angular position and angular velocity data can be read back The serial output enable pin, SOE, is held high to enable the in either normal mode or configuration mode. To read the parallel interface. The SOE pin is held low to enable the serial status of the fault register or the remaining on-chip registers, interface, which places Pin DB0 to Pin DB12 in the high imped- the part must be put into configuration mode. ance state. Pin DB13 is the serial clock input (SCLK), Pin DB14 Reading from the AD2S1210 in Configuration Mode is the serial data input (SDI), Pin DB15 is the serial data output (SDO), and WR/FSYNC is the frame synchronization input. To read back data stored in one of the on-chip registers, including the fault register, the user must first place the AD2S1210 into SAMPLE INPUT configuration mode using the A0 and A1 inputs. The 8-bit address The AD2S1210 operates on a Type II tracking closed-loop of the register to be read should then be written to the part, as principle. The loop continually tracks the position and velocity described in the Writing to the AD2S1210 section. This transfers of the resolver without the need for external conversion and the relevant data to the output register. The data can then be wait states. The position and velocity registers are external to read using the RD input as described previously. When reading the loop and are updated with a high-to-low transition of the back data from any of the read/write registers (see Table 10), the SAMPLE signal. This pin must be held low for at least t16 ns 8-bit word consists of the seven bits of data in the relevant register, to guarantee correct latching of the data. D6 to D0, and an error bit, D7. If the error bit is returned high, DATA FORMAT this indicates that the data read back from the device does not match the configuration data written to the device in the previous The digital angle data represents the absolute position of the write cycle. resolver shaft as a 10-bit to 16-bit unsigned binary word. The digital velocity data is a 10-bit to 16-bit twos complement word, If the user wants to read back the angular position or velocity which represents the velocity of the resolver shaft rotating in data while in configuration mode, a falling edge of the SAMPLE either a clockwise or a counterclockwise direction. input is required to update the information in the position and velocity registers. The data in these registers can then be read back PARALLEL INTERFACE by addressing the required register and reading back the data as The parallel interface is selected holding the SOE pin high. The described previously. Figure 29 shows the timing specifications to chip select pin, CS, must be held low to enable the interface. follow when reading from the configuration registers. Writing to the AD2S1210 Reading from the AD2S1210 in Normal Mode The on-chip registers of the AD2S1210 are written to, in parallel To read back position or velocity data from the AD2S1210, the mode, using an 8-bit parallel interface, D7 to D0, and the WR/ information stored in the position and velocity registers should FSYNC pin. The MSB of each 8-bit word written to the AD2S1210 first be updated using the SAMPLE input. A high-to-low transition indicates whether the 8-bit word is a register address or data. on the SAMPLE input transfers the data from the position and The MSB (D7) of each register address defined on the AD2S1210 velocity integrators to the position and velocity registers. The is high (see the Register Map section). The MSB of each data fault register is also updated on the high-to-low transition of the word written to the AD2S1210 is low. To write to one of the SAMPLE input. The status of the A0 and A1 inputs determines registers, the user must first place the AD2S1210 into configura- whether the position or velocity data is transferred to the output tion mode using the A0 and A1 inputs. Then the 8-bit address register. The CS pin must be held low to transfer the selected should be written to the AD2S1210 using Pin DB7 to Pin DB0, data to the output register. Finally, the RD input is used to read and latched using the rising edge of the WR/FSYNC input. The the data from the output register and to enable the output buffer. data can then be presented on Pin DB7 to Pin DB0 and again The output buffer is enabled when CS and RD are held low. The latched into the part using the WR/FSYNC input. Figure 28 shows data pins return to a high impedance state when RD returns to the timing specifications to follow when writng to the configura- a high state. If the user is reading data continuously, RD can be tion registers. Note that the RD input should be held high when reapplied a minimum of t ns after it was released. 20 writing to the AD2S1210. The timing requirements for the read cycle are shown in Figure 30. Note that the WR/FSYNC input should be high when RD is low. Rev. A | Page 24 of 36

AD2S1210 Clearing the Fault Register 4. The fault register should be read as described in the Reading from the AD2S1210 in Configuration Mode The LOT pin and/or the DOS pin of the AD2S1210 are taken section. low to indicate that a fault has been detected. The AD2S1210 is capable of detecting eight separate fault conditions. To determine 5. A second high-to-low transition of the SAMPLE input which condition triggered the fault indication, the user is required clears the fault indications on the DOS and/or LOT pins. to enter configuration mode and read the fault register. To reset 6. Note that in the event of a persistent fault, the fault indica- the fault indicators, an additional SAMPLE pulse is required. tors are reasserted within the specified fault time latency. This ensures that any faults that may occur between the initial Figure 31 shows the timing specifications to follow when sampling and subsequent reading of the fault register are captured. clearing the fault register. Therefore, to read and clear the fault register, the following Note that the last valid register address written to the AD2S1210 sequence of events is required: prior to exiting configuration mode is again valid when reentering 1. A high-to-low transition of the SAMPLE input. configuration mode. It is therefore recommended that when 2. The SAMPLE input should be held low for t16 ns and then initial configuration of the AD2S1210 is complete, the fault address can be returned high. should be written to the AD2S1210 before leaving configuration 3. The AD2S1210 should be put into configuration mode, mode. This simplifies the reading and clearing of the fault register that is, A0 and A1 are both set to logic high. in normal operation because it is now possible to access the position, velocity, and fault information by toggling the A0 and A1 pins without requiring additional register addressing. f CLKIN CLKIN t1 t8 t1 A0,A1 t 6 t5 t2 t t 2 2 CS t 9 t 7 WR t t 3 3 t4 t4 DB0TO DB7 ADDRESS DATA ADDRESS N12..O RTDE SSDHOONU’TL DC ABRE EH.ELD HIGH WHEN WRITINGTO THEAD2S1210. 07467-027 Figure 28. Parallel Port Write Timing—Configuration Mode Rev. A | Page 25 of 36

AD2S1210 f CLKIN CLKIN t 1 A0,A1 t2 t t14B 11 CS t t 5 13 t 15 WR t10 t12 t14A t14A RD t 4 t3 t12 DB0TO DB7 ADDRESS DATA ADDRESS DATA NOTES 1. DON’T CARE. 07467-028 Figure 29. Parallel Port Read Timing—Configuration Mode f CLKIN CLKIN t16 t16 SAMPLE t17 t6 CS t t 18 20 RD t 1 A0,A1 POSITION VELOCITY FAULT* t t t14A/t14B 19 21 DATA POSITION VELOCITY FAULT* *ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE. N1.OTESDON’T CARE. 07467-029 Figure 30. Parallel Port Read Timing Rev. A | Page 26 of 36

AD2S1210 f CLKIN CLKIN t16 t16 t16 SAMPLE t 17 CS t 2 WR t 9 RD t 1 A0,A1 CONFIGURATION t t 12 3 t t 4 14A t 19 DATA FAULTADDRESS FAULT DATA N1.OTESDON’T CARE. 07467-030 Figure 31. Parallel Port—Clear Fault Register Rev. A | Page 27 of 36

AD2S1210 SERIAL INTERFACE this indicates that the data read back from the device does not match the configuration data written to the device in the previous The serial interface is selected by holding the SOE pin low. The write cycle. AD2S1210 serial interface consists of four signals: SDO, SDI, WR/FSYNC, and SCLK. The SDI is used for transferring data To read back the angular position or velocity data while in into the on-chip registers whereas the SDO is used for accessing configuration mode, a falling edge of the SAMPLE input is data from the on-chip registers, including the position, velocity, required to update the information in the position and velocity and fault registers. SCLK is the serial clock input for the device, registers. and all data transfers (either on SDI or SDO) take place with Reading from the AD2S1210 in Normal Mode respect to this SCLK signal. WR/FSYNC is used to frame the To read back position or velocity data from the AD2S1210, the data. The falling edge of WR/FSYNC takes the SDI and SDO information stored in the position and velocity registers should lines out of a high impedance state. A rising edge on WR/FSYNC first be updated using the SAMPLE input. A high-to-low returns the SDI and SDO to a high impedance state. The CS input transition on the SAMPLE input transfers the data from the is not required for the serial interface and should be held low. position and velocity integrators to the position and velocity SDO Output registers. The fault register is also updated on the high-to-low In normal mode of operation, data is shifted out of the device as transition of the SAMPLE input. The status of the A0 and A1 a 24-bit word under the control of the serial clock input, SCLK. inputs determines whether the position or velocity data is The data is shifted out on the rising edge of SCLK. The timing transferred to the output register. diagram for this operation is shown in Figure 32. In normal mode, the output shift register is 24 bits wide. The 24-bit SDI Input word consists of 16 bits of angular data (position or velocity data) followed by the 8-bit fault register data. Data is read out MSB The SDI input is used to address the on-chip registers and as a first (Bit 23) on the SDO pin. Bit 23 through Bit 8 correspond to daisy-chain input in configuration mode. The data is shifted the angular information. The angular position data format is into the part on the falling edge of SCLK. The timing diagram unsigned binary, with all 0s corresponding to 0 degrees and all for this operation is shown in Figure 32. 1s corresponding to 360 degrees − l LSB. The angular velocity data Writing to the AD2S1210 format is twos complement binary, with the MSB representing the The on-chip registers of the AD2S1210 can be accessed using rotation direction. Bit 7 through Bit 0 correspond to the fault the serial interface. To write to one of the registers, the user information. If the user does not require the fault information, must first place the AD2S1210 into configuration mode using the WR/FSYNC can be pulled high after the16th SCLK rising edge. the A0 and A1 inputs. The 8-bit address should be written to Clearing the Fault Register the AD2S1210 using the SDI pin and latched using the rising The LOT pin and/or the DOS pin of the AD2S1210 are taken edge of the WR/FSYNC input. The data can then be presented on low to indicate that a fault has been detected. The AD2S1210 is the SDI pin and again latched into the part using the WR/FSYNC capable of detecting eight separate fault conditions. To determine input. The MSB of the 8-bit write indicates whether the 8-bit which condition triggered the fault indication, the user is required word is a register address, MSB set high, or the data to be written, to enter configuration mode and read the fault register. To reset MSB set low. Figure 33 shows the timing specifications to follow the fault indicators, an additional SAMPLE pulse is required. when writing to the configuration registers. This ensures that any faults that may occur between the initial Reading from the AD2S1210 in Configuration Mode sampling and subsequent reading of the fault register are captured. To read back data stored in one of the on-chip registers, including Therefore, to read and clear the fault register, the following the fault register, the user must first place the AD2S1210 into sequence of events is required: configuration mode using the A0 and A1 inputs. The 8-bit 1. A high-to-low transition of the SAMPLE input. address of the register to be read should then be written to the 2. Hold the SAMPLE input low for t ns and then it can be 16 part, as described in the Writing to the AD2S1210 section. returned high. This transfers the relevant data to the output register. 3. Put the AD2S1210 into configuration mode, that is, A0 and In configuration mode, the output shift register is eight bits A1 are both set to logic high. wide. Data is shifted out of the device as an 8-bit word under 4. Read the fault register as described in the Reading from the the control of the serial clock input, SCLK. The timing diagram AD2S1210 in Configuration Mode section. for this operation is shown in Figure 34. When reading back 5. A second high-to-low transition of the SAMPLE input data from any of the read/write registers (see Table 10), the 8-bit clears the fault indications on the DOS and/or LOT pins. word consists of the seven bits of data in the relevant register, Note that in the event of a persistent fault, the fault indicators D6 to D0, and an error bit, D7. If the error bit is returned high, are reasserted within the specified fault time latency. Rev. A | Page 28 of 36

AD2S1210 WR/FSYNC t22 fSCLK t29 t 25 SCLK t23 t24 t26 SDO MSB LSB t t SDI MSB 27 28 LSB 07467-031 Figure 32. Serial Interface Timing Diagram f CLKIN CLKIN t t 1 t 1 8 A0, A1 t 5 t 2 CS t2 t7 t9 WR/FSYNC SDI ADDRESS DATA NEW ADDRESS SDO OLD DATA OLD DATA COPY OF DATA N1.OTESDON’T CARE. 07467-032 Figure 33. Serial Interface Write Timing—Configuration Mode f CLKIN CLKIN A0, A1 t6 t2 t1 t5 t5 CS t 2 WR/FSYNC SDI ADDRESS 1 ADDRESS 2 ADDRESS 3 SDO OLD DATA DATA 1 DATA 2 N1.OTEDSON’T CARE. 07467-033 Figure 34. Serial Interface Read Timing—Configuration Mode Rev. A | Page 29 of 36

AD2S1210 f CLKIN CLKIN t t 16 16 SAMPLE t 30 t 6 CS t 31 t 34 WR/FSYNC t 32 t 33 A0, A1 POSITION VELOCITY FAULT* t 29 t 23 SDO POSITION VELOCITY FAULT* *ASSUMES FAULT REGISTER ADDRESS WRITTEN TO PART BEFORE EXITING CONFIGURATION MODE. N1.OTESDON’T CARE. 07467-034 Figure 35. Serial Interface Read Timing Rev. A | Page 30 of 36

AD2S1210 INCREMENTAL ENCODER OUTPUTS SUPPLY SEQUENCING AND RESET The A, B, and NM incremental encoder emulation outputs are The AD2S1210 requires an external reset signal to hold the free running and are valid if the resolver format input signals RESET input low until V is within the specified operating DD applied to the converter are valid. range of 4.5 V to 5.5 V. The AD2S1210 can be configured to emulate a 256-line, a The RESET pin must be held low for a minimum of 10 μs after 1024-line, a 4096-line, or a 16,384-line encoder. For example, V is within the specified range (shown as t in Figure 37). DD RST if the AD2S1210 is configured for 12-bit resolution, one revolu- Applying a RESET signal to the AD2S1210 initializes the output tion produces 1024 A and B pulses. Pulse A leads Pulse B for position to a value of 0x000 (degrees output through the parallel, increasing angular rotation (that is, clockwise direction). serial, and encoder interfaces) and causes LOS to be indicated The resolution of the encoder emulation outputs of the AD2S1210 (LOT and DOS pins pulled low), as shown in Figure 37. is generally configured to match the resolution of the digital output. Failure to apply the correct power-up/reset sequence may result However, the encoder emulation outputs of the AD2S1210 can also in an incorrect position indication. be configured to have a lower resolution than the digital outputs. After a rising edge on the RESET input, the device must be allowed For example, if the AD2S1210 is configured for 16-bit resolu- at least t ms (see Figure 37) for the internal circuitry to stabil- tion, then the encoder emulation outputs can also be configured TRACK ize and the tracking loop to settle to the step change of the input for 14-bit, 12-bit, or 10-bit resolution. However, the resolution position. For the duration of t fault indications may occur of the encoder emulation outputs cannot be higher than the TRACK on the LOT and DOS pins due to the step response caused by resolution of the digital output. If the AD2S1210 is configured the RESET. The duration of t is dependent on the converter such that the resolution of the encoder emulation outputs is TRACK resolution as outlined in Table 27. After t , the fault register higher than the resolution of the digital outputs, the AD2S1210 TRACK should be read and cleared as outlined in the Clearing the Fault internally overrides this configuration. In this event, the resolu- Register section. The time required to read and clear the fault tion of the encoder outputs is set to match the resolution of the register is indicated as t , and is defined by the interface digital outputs. The resolution of the encoder emulation outputs FAULT speed of the DSP/microprocessor used in the application. (Note can be programmed by writing to Bit D3 and Bit D2 of the that if position data is acquired via the encoder outputs, these control register. can be monitored during t .) TRACK The north marker pulse is generated as the absolute angular position passes through zero. The north marker pulse width Table 27. t vs. Resolution (f = 8.192 MHz) TRACK CLKIN is set internally for 90° and is defined relative to the A cycle. Resolution (Bits) t (ms) TRACK Figure 36 details the relationship between A, B, and NM. 10 10 12 20 A 14 25 16 60 B VDD 4.75V t RST RESET t NM 07467-035 TRACK tFAULT Figure 36. A, B, and NM Timing for Clockwise Rotation SAMPLE The inclusion of A and B outputs allows the AD2S1210 with LOT VALID resolver solution to replace optical encoders directly without OUTPUT the need to change or upgrade existing application software. DOS DATA 07457-036 Figure 37. Power Supply Sequencing and Reset Rev. A | Page 31 of 36

AD2S1210 CIRCUIT DYNAMICS LOOP RESPONSE MODEL RDC closed-loop transfer function ERROR G(z) (ACCELERATION) VELOCITY H(z)= (13) 1+G(z) θIN k1 × k2 1 –c z–1 11 –– bazz––11 1 –c z–1 θOUT The closed-loop magnitude and phase responses are that of a – second-order low-pass filter (see Figure 11 and Figure 12). Sin/Cos LOOKUP 07467-037 Ttioo nc oisn vpeerrtf oGrm(z)e din btoy sthueb sst-iptulatnineg, athne i nfovlelroswe ibnigli neqeuara ttiroann sffoorr zm: a - Figure 38. RDC System Response Block Diagram 2 The RDC is a mixed-signal device that uses two ADCs to digitize +s signals from the resolver and a Type II tracking loop to convert z= t (14) 2 these to digital position and velocity words. −s t The first gain stage consists of the ADC gain on the sine/cosine where t is the sampling period (1/4.096 MHz ≈ 244 ns). inputs and the gain of the error signal into the first integrator. The first integrator generates a signal proportional to velocity. Substitution yields the open-loop transfer function, G(s). The compensation filter contains a pole and a zero that are used s2t2 t(1+a) to provide phase margin and reduce high frequency noise gain. 1+st+ 1+s× k1×k2(1−a) 4 2(1−a) The second integrator is the same as the first and generates the G(s)= × × (15) a−b s2 t(1+b) position output from the velocity signal. The sin/cos lookup has 1+s× 2(1−b) unity gain. The values for the k1, k2, a, b, and c parameters are outlined in Table 28. This transformation produces the best matching at low frequencies (f < f ). At such frequencies (within the closed-loop The following equations outline the transfer functions of the SAMPLE bandwidth of the AD2S1210), the transfer function can be individual blocks as shown in Figure 38, which then combine to simplified to form the complete RDC system loop response. K 1+st Integrator1 and Integrator2 transfer function G(s)≅ a × 1 (16) s2 1+st c 2 I(z)= (10) 1−z−1 where: Compensation filter transfer function t(1+a) t = 1 2(1−a) 1−az−1 C(z)= (11) 1−bz−1 t = t(1+b) 2 2(1−b) RDC open-loop transfer function k1×k2(1−a) G(z)=k1×k2×I(z)2×C(z) (12) K = a a−b Solving for each value gives t, t, and K as outlined in Table 29. 1 2 a Table 28. RDC System Response Parameters Parameter Description 10-bit resolution 12-bit resolution 14-bit resolution 16-bit resolution k1 (nominal) ADC gain 1.8/2.5 1.8/2.5 1.8/2.5 1.8/2.5 k2 Error gain 6 × 106 × 2π 18 × 106 × 2π 82 x 106 × 2π 66 × 106 × 2π a Compensator zero coefficient 8187/8192 4095/4096 8191/8192 32,767/32,768 b Compensator pole coefficient 509/512 4085/4096 16,359/16,384 32,757/32,768 c Integrator gain 1/1,024,000 1/4,096,000 1/16,384,000 1/65,536,000 Rev. A | Page 32 of 36

AD2S1210 SOURCES OF ERROR Table 29. Loop Transfer Function Parameters vs. Resolution (f = 8.192 MHz) Acceleration CLKIN Resolution (Bits) t1 (ms) t2 (ms) Ka (sec−2) A tracking converter employing a Type II servo loop does not 10 0.4 42 39.6 × 106 have a lag in velocity. There is, however, an error associated 12 1 91 6.5 × 106 with acceleration. This error can be quantified using the 14 2 160 1.6 × 106 acceleration constant (K) of the converter. a 16 8 728 92.7 × 103 Input Acceleration K = (18) Note that the closed-loop response is described as a Tracking Error G(s) H(s)= (17) Conversely, 1+G(s) InputAcceleration By converting the calculation to the s-domain, it is possible to Tracking Error= (19) K quantify the open-loop dc gain (K). This value is useful to a a calculate the acceleration error of the loop (see the Sources of The units of the numerator and denominator must be consistent. Error section). The maximum acceleration of the AD2S1210 is defined by the maximum acceptable tracking error in the users application. The step response to a 10° input step is shown in Figure 10, For example, if the maximum acceptable tracking error is 5°, Figure 11, Figure 12, and Figure 13. The step response to a 179° then the maximum acceleration is defined as the acceleration that input step is shown in Figure 14, Figure 15, Figure 16, and creates an output position error of 5° (that is, when LOT is Figure 17. In response to a step change in velocity, the indicated). AD2S1210 exhibits the same response characteristics as it does for a step change in position. An example of how to calculate the maximum acceleration in a 12-bit application with a maximum tracking error of 5° is Figure 18 and Figure 19 in the Typical Performance Characteristics section show the magnitude and phase responses of the AD2S1210 K (sec−2)×5° MaximumAcceleration= a ≅ 90,300 rps2 for each resolution setting. 360(°/rev) (20) Figure 20 to Figure 23 in the Typical Performance Characteristics section show the tracking error vs. acceleration response of the AD2S1210 for each resolution setting. Rev. A | Page 33 of 36

AD2S1210 OUTLINE DIMENSIONS 9.20 0.75 9.00 SQ 1.60 0.60 MAX 8.80 0.45 48 37 1 36 PIN 1 7.20 1.45 TOP VIEW 7.00 SQ 1.40 0.20 (PINS DOWN) 6.80 0.09 1.35 7° 3.5° 12 25 00..1055 SPELAANTEING 0C.O08PLA0°NARITY VIEW A 0.5103 240.27 BSC 0.22 LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BBC 051706-A Figure 39. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range Package Description Package Option AD2S1210ASTZ −40°C to +85°C 48-Lead LQFP ST-48 AD2S1210BSTZ −40°C to +85°C 48-Lead LQFP ST-48 AD2S1210CSTZ −40°C to +125°C 48-Lead LQFP ST-48 AD2S1210DSTZ −40°C to +125°C 48-Lead LQFP ST-48 AD2S1210WDSTZ2 −40°C to +125°C 48-Lead LQFP ST-48 AD2S1210WDSTZRL72 −40°C to +125°C 48-Lead LQFP ST-48 EVAL-AD2S1210EDZ Evaluation Board 1 Z = RoHS Compliant Part. 2 Qualified for Automotive. Rev. A | Page 34 of 36

AD2S1210 NOTES Rev. A | Page 35 of 36

AD2S1210 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07467-0-2/10(A) Rev. A | Page 36 of 36

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: AD2S1210ASTZ AD2S1210ASTZ-RL7 AD2S1210DSTZ AD2S1210BSTZ AD2S1210SST-EP-RL7 AD2S1210WDSTZRL7 AD2S1210CSTZ AD2S1210WDSTZ AD2S1210SSTZ-EPRL7