12-Bit R/D Converter with Reference Oscillator AD2S1200 FEATURES GENERAL DESCRIPTION Complete monolithic R/D converter The AD2S1200 is a complete 12-bit resolution tracking resolver- Parallel and serial 12-bit data ports to-digital converter, integrating an on-board programmable System fault detection sinusoidal oscillator that provides sine wave excitation for Absolute position and velocity outputs resolvers. An external 8.192 MHz crystal is required to provide Differential inputs a precision time reference. This clock is internally divided to ±11 arc minutes of accuracy generate a 4.096 MHz clock to drive all the peripherals. 1,000 rps maximum tracking rate, 12-bit resolution The converter accepts 3.6 V p-p ± 10% input signals, in the Incremental encoder emulation (1,024 pulses/rev) range of 10 kHz to 20 kHz on the Sin and Cos inputs. A Type II Programmable sinusoidal oscillator on-board servo loop is employed to track the inputs and convert the input Compatible with DSP and SPI® interface standards Sin and Cos information into a digital representation of the 204.8 kHz square wave output input angle and velocity. The bandwidth of the converter is set Single-supply operation (5.00 V ± 5%) internally to 1.7 kHz with an external 8.192 MHz crystal. The −40°C to +125°C temperature rating maximum tracking rate is 1,000 rps. 44-lead LQFP package 4 kV ESD protection FUNCTIONAL BLOCK DIAGRAM CLKIN REFBYP REFOUT FS1 FS2 XTALOUT (8.192MHz) AD2S1200 VOLTAGE (4.096MHz) INCTLEORCNKAL REFERENCE GENERATOR EXC REFERENCE OSCILLATOR (204.8kHz) EXC (DAC) CLOCK CPO DIVIDER RSEYFNETRHEENTCICE INDFICAAUTLOTRS DOS SinLO LOT Sin ADC ERROR MONITOR MONITOR CALCULATION/ ANGLEθ SIGNAL ERROR DEMODULATOR ERROR CosLO MONITOR ADC Cos DIGITAL FILTER ANGLEφ AB EEMNUCLOADTEIORN INPTOEGSIRTAIOTNOR INVTEELGORCAITTYOR DIR NM POSITION REGISTER VELOCITY REGISTER SAMPLE MULTIPLEXER CS DATA BUS OUTPUT RD RESET RDVEL SOE DSBO11 SDCBL1K0 DB9–DB0 04406-0-001 Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.

AD2S1200 APPLICATIONS • Triple Format Position Data: Absolute 12-bit angular binary position data accessed either via a 12-bit parallel Electric power steering port or via a 3-wire serial interface. Incremental encoder Electric vehicles emulation in standard A QUAD B format, with direction Integrated starter generator/alternator output is available. Encoder emulation Automotive motion sensing and control • Digital Velocity Output: 12-bit signed digital velocity, twos complement format, accessed either via a 12-bit PRODUCT HIGHLIGHTS parallel port or via a 3-wire serial interface. • Complete Resolver-to-Digital Interface: The AD2S1200 • Programmable Excitation Frequency: Excitation fre- provides the complete solution for digitizing resolver quency easily programmable to 10 kHz, 12 kHz, 15 kHz, or signals (12-bit resolution) with on-board programmable 20 kHz by using the frequency select pins. sinusoidal oscillator. • Ratiometric Tracking Conversion: This technique • System Fault Detection: A fault detection circuit will detect any loss of resolver signals, out of range input provides continuous output position data without signals, input signal mismatch, or loss of position tracking. conversion delay. It also provides noise immunity and tolerance of harmonic distortion on the reference and input signals. Rev. 0 | Page 2 of 24

AD2S1200 TABLE OF CONTENTS AD2S1200–Specifications................................................................4 Incremental Encoder Outputs...................................................16 Absolute Maximum Ratings............................................................6 On-Board Programmable Sinusoidal Oscillator.....................16 ESD Caution..................................................................................6 Supply Sequencing and Reset....................................................17 Pin Configuration and Function Descriptions.............................7 Charge Pump Output.................................................................17 Resolver Format Signals...................................................................8 Circuit Dynamics............................................................................18 Principle of Operation......................................................................9 AD2S1200 Loop Response Model............................................18 Fault Detection Circuit.................................................................9 Sources of Error..........................................................................19 Connecting the Converter.........................................................11 Clock Requirements...................................................................20 Absolute Position and Velocity Output....................................12 Connecting to the DSP...............................................................20 Parallel Interface..........................................................................12 Outline Dimensions........................................................................21 Serial Interface.............................................................................14 Ordering Guide...........................................................................21 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 3 of 24

AD2S1200 AD2S1200–SPECIFICATIONS Table 1. (AV = DV = 5.0 V ± 5% @ −40°C to +125°C CLKIN 8.192 MHz, unless otherwise noted.) DD DD Parameter Min Typ Max Unit Conditions/Comments Sin, Cos INPUTS1 Voltage 3.24 3.6 3.96 V p-p Sinusoidal waveforms, differential inputs Input Bias Current 2 µA V = 3.96 V p-p IN Input Impedance 1.0 MΩ V = 3.96 V p-p IN Common Mode Volts 100 mV Peak CMV @ SinLO, CosLO, with respect to REFOUT @ 10 kHz Phase Lock Range −45 +45 Degrees Sin/Cos vs. EXC output ANGULAR ACCURACY Angular Accuracy ±11 arc min Zero acceleration Y Grade ±22 arc min Zero acceleration W Grade Resolution 12 Bits Guaranteed no missing codes Linearity INL 2 LSB Zero acceleration, 0 to 1,000 rps Linearity DNL 0.3 LSB Guaranteed monotonic Repeatability 1 LSB Hysteresis 1 LSB VELOCITY OUTPUT Velocity Accuracy 2 LSB Zero acceleration Resolution 11 Bits Linearity 1 LSB Guaranteed by design 2 LSB max Offset 0 1 LSB Zero acceleration Dynamic Ripple 1 LSB Zero acceleration DYNAMIC PERFORMANCE Bandwidth 1,500 1,700 2,000 Hz Fixed Tracking Rate 1,000 rps Guaranteed by design. Tested to 800 rps. Acceleration Error 30 arc min At 10,000 rps2 Settling Time 179° Step Input 4.72 5.0 ms To within stated accuracy Settling Time 179° Step Input 3.7 3.8 ms To within one degree EXC, EXC OUTPUTS Voltage 3.34 3.6 3.83 V p-p Load ±100 µA Center Voltage 2.39 2.47 2.52 V Frequency 10 kHz FS1 = high, FS2 = high 12 kHz FS1 = high, FS2 = low 15 kHz FS1 = low, FS2 = high 20 kHz FS1 = low, FS2 = low EXC/EXC DC Mismatch 35 mV THD −60 −55 dB First five harmonics FAULT DETECTION BLOCK LOS Sin/Cos Threshold 2.86 2.92 3.0 V p-p DOS and LOT go low when Sin or Cos fall below threshold. Angular Accuracy (Worst Case) 45 Degrees LOS indicated before angular output error exceeds limit (3.96 V p-p input signal and 2.9 V LOS threshold). Angular Latency (Worst Case) 90 Degrees Maximum electrical rotation before LOS is indicated (3.96 V p-p input signal and 2.9 V LOS threshold). Time Latency 125 µs 1 The voltages Sin, SinLO, Cos, and CosLO relative to AGND must always be between 0.2 V and AVDD. Rev. 0 | Page 4 of 24

AD2S1200 Parameter Min Typ Max Unit Conditions/Comments FAULT DETECTION BLOCK (CONT.) DOS Sin/Cos Threshold 4.0 4.09 4.2 V p-p DOS goes low when Sin or Cos exceeds threshold. Sin/Cos Mismatch 385 420 mV DOS latched low when Sin/Cos amplitude mismatch exceeds the threshold. Angular Accuracy (Worst Case) 30 Degrees DOS indicated before angular output error exceeds limit. Angular Latency (Worst Case) 60 Degrees Maximum electrical rotation before DOS is indicated. Time Latency 125 µs LOT Tracking Threshold 5 Degrees LOT goes low when internal error signal exceeds threshold. Guaranteed by design. Time Latency 1.1 ms Hysteresis 4 Degrees Guaranteed by design VOLTAGE REFERENCE REFOUT 2.39 2.47 2.52 V ±IOUT = 100 µA Drift 70 ppm/°C PSRR −60 dB CHARGE PUMP OUTPUT (CPO) Frequency 204.8 kHz Square wave output Duty Cycle 50 % POWER SUPPLY I Dynamic 18 mA DD ELECTRICAL CHARACTERISTICS V Voltage Input Low 0.8 V IL V Voltage Input High 2.0 V IH V Voltage Output Low 0.4 V 2 mA load OL V Voltage Output High 4.0 V −1 mA load OH I Low Level Input Current 10 µA IL I High Level Input Current −10 µA IH I High Level Three-State Leakage −10 µA OZH I Low Level Three-State Leakage 10 µA OZL Rev. 0 | Page 5 of 24

AD2S1200 ABSOLUTE MAXIMUM RATINGS Table 2. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress Supply Voltage (VDD) −0.3 V to +7.0 V rating only; functional operation of the device at these or any Supply Voltage (AVDD) −0.3 V to + 7.0 V other conditions above those indicated in the operational Input Voltage −0.3 V to VDD + 0.3 V sections of this specification is not implied. Exposure to Output Voltage Swing −0.3 V to VDD + 0.3 V absolute maximum ratings for extended periods may affect Operating Temperature Range (Ambient) −40°C to +125°C device reliability. Storage Temperature Range −65°C to +150°C Lead Temperature Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24

AD2S1200 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T P REFOU REFBY AGND Cos CosLO AVDD SinLO Sin AGND EXC EXC 44 43 42 41 40 39 38 37 36 35 34 DVDD 1 33 RESET RD 2 32 FS2 CS 3 31 FS1 SAMPLE 4 30 LOT RDVEL 5 AD2S1200 29 DOS SOE 6 TOP VIEW 28 DIR (Not to Scale) DB11/SO 7 27 NM DB10/SCLK 8 26 B DB9 9 25 A DDBB87 1101 2243 CDPGOND 04406-0-002 12 13 14 15 16 17 18 19 20 21 22 6 5 4 3 D D 2 1 0 T N DB DB DB DB DGN DVD DB DB DB ALOU CLKI XT Figure 2. Pin Configuration 44-Lead Low Profile Quad Flat Package [LQFP] (ST-44) Table 3. Pin Function Descriptions Pin No. Pin Name Pin Type Pin No. Pin Name Pin Type 1 DV Supply 27 NM Output DD 2 RD Input 28 DIR Output 3 CS Input 29 DOS Output 4 SAMPLE Input 30 LOT Output 5 RDVEL Input 31 FS1 Input 32 FS2 Input 6 SOE Input 33 RESET Input 7 DB11/SO Output 34 EXC Output 8 DB10/SCLK Input, output 35 EXC Output 9–15 DB9–DB3 Output 16 DGND Ground 36 AGND Ground 17 DV Supply 37 Sin Input DD 18–20 DB2–DB0 Output 38 SinLO Input 21 XTALOUT Output 39 AVDD Supply 22 CLKIN Input 40 CosLO Input 23 DGND Ground 41 Cos Input 24 CPO Output 42 AGND Ground 25 A Output 43 REFBYP Input 26 B Output 44 REFOUT Output Rev. 0 | Page 7 of 24

AD2S1200 RESOLVER FORMAT SIGNALS Vr = Vp× Sin(ϖt) Vr = Vp× Sin(ϖt) R1 S2 S2 Va = Vs× Sin(ϖt)× Cos(θ) R1 Va = Vs× Sin(ϖt)× Cos(θ) θ S4 θ S4 R2 R2 S1 S3 S1 S3 (AV)b C =L AVsSS× ISCiAnL(ϖ Rt)E×S SOiLnV(θE)R (B) VARIVAbB =L EV sR×E LSUinC(ϖTtA)N×C SEin R(θE)SOLVER 04406-0-003 Figure 3. Classical Resolver vs. Variable Reluctance Resolver A resolver is a rotating transformer typically with a primary The stator windings are displaced mechanically by 90° (see winding on the rotor and two secondary windings on the stator. Figure 3). The primary winding is excited with an ac reference. In the case of a variable reluctance resolver, there are no wind- The amplitude of subsequent coupling onto the stator secon- ings on the rotor as shown in Figure 3. The primary winding is dary windings is a function of the position of the rotor (shaft) on the stator as well as the secondary windings, but the saliency relative to the stator. The resolver, therefore, produces two in the rotor design provides the sinusoidal variation in the output voltages (S3–S1, S2–S4) modulated by the SinE and secondary coupling with the angular position. Either way, the CoSinE of shaft angle. Resolver format signals refer to the resolver output voltages (S3–S1, S2–S4) will have the same signals derived from the output of a resolver as shown in equations as shown in Equation 1. Equation 1. Figure 4 illustrates the output format. S3−S1=E Sinωt×Sinθ 0 S2−S4=E Sinωt×Cosθ 0 θ=ShaftAngle S2 TO S4 (Cos) Sinωt=RotorExcitationFrequency E =RotorExcitation Amplitude 0 S3 TO S1 (Sin) Equation 1. R2 TO R4 (REF) 04406-0-004 0° 90° 180° 270° 360° θ Figure 4. Electrical Resolver Representation Rev. 0 | Page 8 of 24

AD2S1200 PRINCIPLE OF OPERATION The AD2S1200 operates on a Type II tracking closed-loop FAULT DETECTION CIRCUIT principle. The output continually tracks the position of the The AD2S1200 fault detection circuit will detect loss of resolver resolver without the need for external convert and wait states. signals, out of range input signals, input signal mismatch, or loss As the resolver moves through a position equivalent to the least of position tracking. In these cases, the position indicated by the significant bit weighting, the output is updated by one LSB. AD2S1200 may differ significantly from the actual shaft position of the resolver. The converter tracks the shaft angle θ by producing an output angle ϕ that is fed back and compared to the input angle θ, and Monitor Signal the resulting error between the two is driven towards 0 when The AD2S1200 generates a monitor signal by comparing the the converter is correctly tracking the input angle. To measure angle in the position register to the incoming Sin and Cos the error, S3–S1 is multiplied by Cosϕ and S2–S4 is multiplied signals from the resolver. The monitor signal is created in a by Sinϕ to give similar fashion to the error signal described in the Principle of Operation section. The incoming signals Sinθ and Cosθ are E Sinωt×SinθCosφ S1toS3 0 multiplied by the Sin and Cos of the output angle, respectively, E Sinωt×CosθSinφ S2toS4 0 and then added together as shown below: The difference is taken, giving Monitor=A1×SinθxSinφ+A2×Cosθ×Cosφ E Sinωt×(SinθCosφ−CosθSinφ) 0 Equation 4. Equation 2. Where A1 is the amplitude of the incoming Sin signal (A1 × This signal is demodulated using the internally generated Sinθ), A2 is the amplitude of the incoming Cos signal (A2 × synthetic reference, yielding Cosθ), θ is the resolver angle, and ϕ is the angle stored in the position register. Note that Equation 4 is shown after demodula- E (SinθCosφ−CosθSinφ) 0 tion, with the carrier signal Sinωt removed. Also note that for Equation 3. matched input signal (i.e., no-fault condition), A1 = A2. Equation 3 is equivalent to E Sin (θ − ϕ), which is 0 When A1 = A2 and the converter is tracking (θ = ϕ), the approximately equal to E (θ − ϕ) for small values of θ − ϕ, 0 monitor signal output has a constant magnitude of A1 (Monitor where θ − ϕ = angular error. = A1 × (Sin2 θ + Cos2 θ) = A1), independent of shaft angle. The value E (θ − ϕ) is the difference between the angular error When A1 ≠ A2, the monitor signal magnitude varies between 0 of the rotor and the converter’s digital angle output. A1 and A2 at twice the rate of shaft rotation. The monitor signal is used as described in the following sections to detect A phase-sensitive demodulator, integrators, and a compensation degradation or loss of input signals. filter form a closed-loop system that seeks to null the error Loss of Signal Detection signal. When this is accomplished, ϕ equals the resolver angle θ Loss of signal (LOS) is detected when either resolver input (Sin within the rated accuracy of the converter. A Type II tracking or Cos) falls below the specified LOS Sin/Cos threshold by loop is used so that constant velocity inputs can be tracked comparing the monitor signal to a fixed minimum value. LOS is without inherent error. indicated by both DOS and LOT latching as logic low outputs. For more information about the operation of the converter, see The DOS and LOT pins are reset to the no fault state by a rising the Circuit Dynamics section. edge of SAMPLE. The LOS condition has priority over both the DOS and LOT conditions, as shown in Table 4. LOS is indicated within 45° of angular output error worst case. Rev. 0 | Page 9 of 24

AD2S1200 Signal Degradation Detection Responding to a Fault Condition Degradation of signal (DOS) is detected when either resolver If any fault condition (LOS, DOS, or LOT) is indicated by the input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold AD2S1200, the output data must be presumed to be invalid. by comparing the monitor signal to a fixed maximum value. This means that even if a RESET or SAMPLE pulse releases the DOS is also detected when the amplitude of the input signals fault condition, the output data may be corrupted, even though a fault may not be immediately indicated after the RESET/ Sin and Cos mismatch by more than the specified DOS Sin/ SAMPLE event. As discussed earlier, there are some fault Cos mismatch by continuously storing the minimum and conditions with inherent latency. If the device fault is cleared, maximum magnitude of the monitor signal in internal registers, there could be some latency in the resolver’s mechanical and calculating the difference between the minimum and position before the fault condition is re-indicated. maximum. DOS is indicated by a logic low on the DOS pin, and is not latched when the input signals exceed the maximum When a fault is indicated, all output pins will still provide data, input level. When DOS is indicated due to mismatched signals, although the data may or may not be valid. The fault condition the output is latched low until a rising edge of SAMPLE resets will not force the parallel, serial, or encoder outputs to a known the stored minimum and maximum values. The DOS condition state. However, a new startup sequence is recommended only has priority over the LOT condition, as shown in Table 4. DOS after a LOS fault has been indicated. is indicated within 30° of angular output error worst case. Response to specific fault conditions is a system-level Loss of Position Tracking Detection requirement. The fault outputs of the AD2S1200 indicate that Loss of tracking (LOT) is detected for three separate conditions: the device has sensed a potential problem with either the internal or external signals of the AD2S1200. It is the • When the internal error signal of the AD2S1200 has responsibility of the system designer to implement the exceeded 5° appropriate fault-handling schemes within the control hardware • When the input signal exceeds the maximum tracking rate and/or algorithm of a given application based on the indicated of 60,000 rpm (1,000 rps) fault(s) and the velocity or position data provided by the AD2S1200. • When the internal position (at the position integrator) False Null Condition differs from the external position (at the position register) Resolver-to-digital converters that employ Type II tracking by more than 5° loops based on the error equation (Equation 3) presented in the LOT is indicated by a logic low on the LOT pin, and is not Principle of Operation section can suffer from a condition latched. LOT has a 4° hysteresis, and is not cleared until the known as “false null.” This condition is caused by a metastable internal error signal or internal/external position mismatch is solution to the error equation when θ − ϕ = 180°. The less than 1°. When the maximum tracking rate is exceeded, LOT AD2S1200 is not susceptible to this condition because its is cleared when both the velocity is less than 1,000 rps and the hysteresis is implemented externally to the tracking loop. internal/external position mismatch is less than 1°. LOT can be Because of the loop architecture chosen for the AD2S1200, the indicated for step changes in position (such as after a RESET internal error signal always has some movement (1 LSB per signal is applied to the AD2S1200), or for accelerations clock cycle), and so, in a metastable state, the converter will >~85,000 rps2. LOT is useful as a built-in test (BIT) that the always move to an unstable condition within one clock cycle, tracking converter is functioning properly. The LOT condition causing the tracking loop to respond to the false null condition has lower priority than both the DOS and LOS conditions as as if it were a 180° step change in input position (the response shown in Table 4. The LOT and DOS conditions cannot be time is the same as specified in Dynamic Performance section indicated at the same time. of Table 1). Therefore, it is impossible to enter the metastable condition any time after the startup sequence as long as the Table 4. Fault Detection Decoding resolver signals are valid. However, in a case of a loss of signal, a Condition DOS LOT Priority full reset is recommended to avoid the possibility of a false null condition. The response to the false null condition has been Loss of Signal 0 0 1 included in the value of t provided in the Supply Degradation of Signal 0 1 2 TRACK Sequencing and Reset section. Loss of Tracking 1 0 3 No Fault 1 1 Rev. 0 | Page 10 of 24

AD2S1200 CONNECTING THE CONVERTER The gain of the buffer depends on the type of resolver used. Refer to Figure 5. Ground should be connected to the AGND Since the specified excitation output amplitudes are matched to pin and DGND pin. Positive power supply V = +5 V dc ± 5% the specified Sin/Cos input amplitudes, the gain of the buffer is DD should be connected to the AV pin and DV pin. Typical determined by the attenuation of the resolver. DD DD values for the decoupling capacitors are 10 nF and 4.7 µF, In this recommended configuration, the converter introduces a respectively. These capacitors should be placed as close to the V /2 offset in the Sin, Cos signals coming from the resolver. device pins as possible, and should be connected to both AV REF DD Of course, the SinLO and CosLO signals may be connected to a and DV . If desired, the reference oscillator frequency can be DD different potential relative to ground, as long as the Sin and Cos changed from the nominal value of 10 kHz using FS1 and FS2. signals respect the recommended specifications. Note that since Typical values for the oscillator decoupling capacitors are 20 pF. the EXC/EXC outputs are differential, there is an inherent gain Typical values for the reference decoupling capacitors are 10 µF of 2×. and 0.01 µF, respectively. S2 R2 For example, if the primary to secondary turns ratio is 2:1, the buffer will have unity gain. Likewise, if the turns ratio is 5:1, the R1 gain of the buffer should be 2.5×. Figure 6 suggests a buffer S6 S3 S1 circuit. The gain of the circuit is 4.7µF 5V BUFFER BUFFER CIRCUIT CIRCUIT Gain=−(R2/R1) 10nF   R2 R2  10nF 10µF and V =V ×1+ − ×V  OUT  REF  R1 R1 IN 44 43 42 41 40 39 38 37 36 35 34 V is set so that V is always a positive value, eliminating the P D s O D O n D C C REF OUT 5V 1 DVDD EFBY AGN Co CosL AVD SinL Si AGN EX EX 33 RESET need for a negative supply. 2 R 32 12V 3 31 4 30 R2 2.7kΩ 5 29 12V 12V 6 AD2S1200 28 33Ω EXC/EXC R1 VOUT 7 27 (VIN) 8 26 (VREF) 33Ω 9 25 2.7kΩ 1101 DGND DVDD DGND 2243 5V 442Ω 1.24kΩ 04406-0-006 12 13 14 15 16 17 18 19 20 21 22 Figure 6. Buffer Circuit 5V 8.912 MHz Separate screened twisted cable pairs are recommended for 4.7µF 10nF analog inputs Sin/SinLO and Cos/CosLO. The screens should 20pF 20pF 04406-0-005 tsepremciifnieadte, atno R8.E1F92O MUTH. zT ocr aycshtaiel vme uthste b dey unsaemd.i c performance Figure 5. Connecting the AD2S1200 to a Resolver Rev. 0 | Page 11 of 24

AD2S1200 ABSOLUTE POSITION AND VELOCITY OUTPUT integrators, respectively, to the position and velocity registers following a high-to-low transition on the SAMPLE pin. The The angular position and angular velocity are represented by binary data and can be extracted either via a 12-bit parallel RDVEL polarity pin selects which register from the position or interface or a 3-wire serial interface that operates at clock rates the velocity registers is transferred to the output register. The CS up to 25 MHz. The chip select pin, CS, must be held low to pin must be held low to transfer the selected data register to the enable the device. Angular position and velocity can be selected output register. Finally, the RD input is used to read the data using a dedicated polarity input, RDVEL. from the output register and to enable the output buffer. The timing requirements for the read cycle are shown in Figure 7. SOE Input SAMPLE Input The serial output enable pin, SOE, is held high to enable the Data is transferred from the position and velocity integrators, parallel interface. The SOE pin is held low to enable the serial respectively, to the position and velocity registers following a interface, which places pins (DB0–DB9) in the high impedance high-to-low transition on the SAMPLE signal. This pin must be state, while DB11 is the serial output (SO), and DB10 is the held low for at least t ns to guarantee correct latching of the serial clock input (SCLK). 1 data. RD should not be pulled low before this time since data Data Format would not be ready. The converter will continue to operate The digital angle signal represents the absolute position of the during the read process. Also, a rising edge of SAMPLE resets resolver shaft as a 12-bit unsigned binary word. The digital the internal registers that contain the minimum and maximum velocity signal is a 12-bit twos complement word, which magnitude of the monitor signal. represents the velocity of the resolver shaft rotating in either a CS Input clockwise or a counterclockwise direction. The device will be enabled when CS is held low. Finally, the RD input is used to read the data from the output RDVEL Input register and to enable the output buffer. The timing requirements for the read cycle are illustrated in Figure 7. RDVEL input is used to select between the angular position and SAMPLE Input velocity registers as shown in Figure 7. RDVEL is held high for angular position and low for angular velocity. The RDVEL pin Data is transferred from the position and velocity integrators must be set (stable) at least t ns before the RD pin is pulled low. respectively to the position and velocity registers following a 4 high to low transition of the SAMPLE signal. This pin must be RD Input held low for at least t1 ns to guarantee correct latching of the The 12-bit data bus lines are normally in a high impedance data. RD should not be pulled low before this time. Also, a state. The output buffer is enabled when CS and RD are held rising edge of SAMPLE resets the internal registers that contain low. A falling edge of the RD signal transfers data to the output the minimum and maximum magnitude of the monitor signal. buffer. The selected data is made available to the bus to be read within t ns of the RD pin going low. The data pins will return to PARALLEL INTERFACE 6 high impedance state when the RD returns to high state, within The angular position and angular velocity are available on the t ns. If the user is reading data continuously, RD can be AD2S1200 in two 12-bit registers, which can be accessed via the 7 reapplied a minimum of t ns after it was released. 12-bit parallel port. The parallel interface is selected holding the 5 SOE pin high. Data is transferred from the velocity and position Rev. 0 | Page 12 of 24

AD2S1200 t CK CLKIN t1 t1 SAMPLE t 2 CS t 3 t 3 RD t5 t5 RDVEL t4 t4 DATA POS VEL DON'T CARE t6 t7 t6 t7 04406-0-007 Figure 7. Parallel Port Read Timing Table 5. Parallel Port Timing Parameter Description Min Typ Max t Clock Period (= 1/8.192 MHz) ~122 ns CK t SAMPLE Pulse Width 2 × t + 20 ns 1 CK t Delay from SAMPLE before RD/CS Low 6 × t + 20 ns 2 CK t RD Pulse Width 18 ns 3 t Set Time RDVEL before RD/CS Low 5 ns 4 t Hold Time RDVEL after RD/CS Low 7 ns 5 t Enable Delay RD/CS Low to Data Valid 12 ns 6 t Disable Delay RD/CS Low to Data High Z 18 ns 7 Rev. 0 | Page 13 of 24

AD2S1200 SERIAL INTERFACE SAMPLE Input The angular position and angular velocity are available on the Data is transferred from the position and velocity integrators, AD2S1200 in two 12-bit registers. These registers can be respectively, to the position and velocity registers following a accessed via a 3-wire serial interface, SO, RD, and SCLK, that high-to-low transition on the SAMPLE signal. This pin must be operates at clock rates up to 25 MHz and is compatible with SPI held low for at least t ns to guarantee correct latching of the 1 and DSP interface standards. The serial interface is selected by data. RD should not be pulled low before this time since data holding low the SOE pin. Data from the position and velocity would not be ready. The converter will continue to operate integrators are first transferred to the position and velocity during the read process. registers, using the SAMPLE pin. The RDVEL polarity pin CS Input selects which register from the position or the velocity registers The device will be enabled when CS is held low. is transferred to the output register. The CS pin must be held low to transfer the selected data register to the output register. RD Input Finally, the RD input is used to read the data that will be The 12-bit data bus lines are normally in a high impedance clocked out of the output register and will be available on the state. The output buffer is enabled when CS and RD are held serial output pin, SO. When the serial interface is selected, DB11 low. The RD input is an edge-triggered input that acts as frame is used as the serial output pin, SO, and DB10 is used as the synchronization signal and output enable. A falling edge of the serial clock input, SCLK, while pins DB0–DB9 are placed in the RD signal transfers data to the output buffer and data will be high impedance state. The timing requirements for the read available on the serial output pin, SO. RD must be held low for t cycle are described in Figure 8. 9 before the data is valid on the outputs. After RD goes low, the SO Output serial data will be clocked out of the SO pin on the falling edges The output shift register is 16-bit wide. Data is shifted out of the of the SCLK (after a minimum of t ns): the MSB will be 10 device as a 16-bit word under the control of the serial clock already available at the SO pin on the very first falling edge of input, SCLK. The timing diagram for this operation is shown in the SCLK. Each other bit of the data word will be shifted out on Figure 8. The 16-bit word consists of 12 bits of angular data the rising edge of SCLK and will be available at the SO pin on (position or velocity depending on RDVEL input), one RDVEL the falling edge of SCLK for the next 15 clock pulses. status bit and three status bits, a parity bit, degradation of signal The high-to-low transition of RD must happen during the high bit, and loss of tracking bit. Data is read out MSB first (bit 15) time of the SCLK to avoid MSB being shifted on the first rising on the SO pin. Bit 15 through bit 4 correspond to the angular edge of the SCLK and lost. RD may rise high after the falling information. The angular position data format is unsigned edge of the last bit transmitted. Subsequent negative edges binary, with all zeros corresponding to 0 degrees and all ones greater than the defined word length will clock zeros from the corresponding to 360 degrees –l LSB. The angular velocity data format instead is twos complement binary, with the MSB data output if RD remains in a low state. If the user is reading representing the rotation direction. Bit 3 is the RDVEL status data continuously, RD can be reapplied a minimum of t5 ns after bit, 1 indicating position and 0 indicating velocity. Bit 2 is DOS, it is released. the degradation of signal flag (refer to the Fault Detection RDVEL Input Circuit section). Bit 1 is LOT, the loss of tracking flag (refer to RDVEL input is used to select between the angular position and the Fault Detection Circuit section). Bit 0 is PAR, the parity bit: velocity registers. RDVEL is held high for angular position and both position and velocity data are odd parity format; the data low for angular velocity. The RDVEL pin must be set (stable) at read out will always contain an odd number of logic highs (1s). least t ns before the RD pin is pulled low. 4 Rev. 0 | Page 14 of 24

AD2S1200 t CK CLKIN t1 t1 SAMPLE t 2 CS t 3 t 3 RD t5 t5 RDVEL t4 t4 t 6 t6 t7 t7 SO POS VEL t 8 RD t SCLK SCLK t10 t11 SO MSB MSB–1 LSB RDVEL DOS LOT PAR t9 04406-0-008 Figure 8. Serial Port Read Timing Table 6. Serial Port Timing Parameter Description Min Typ Max t MSB Read Time from RD/CS to SCLK 15 ns t 8 SCLK t Enable Time RD/CS to DB Valid 12 ns 9 t Delay SCLK to DB Valid 14 ns 10 t Disable Time RD/CS to DB High Z 18 ns 11 t Serial Clock Period (25 MHz Max) 40 ns SCLK Rev. 0 | Page 15 of 24

AD2S1200 INCREMENTAL ENCODER OUTPUTS At 12 bits, the PPR = 1,024. Therefore, the maximum speed, n, The incremental encoder emulation outputs A, B, and NM are of the AD2S1200 is free running and are always valid, providing that valid resolver 60×1,024,000 format input signals are applied to the converter. n= =60000rpm 1,024 The AD2S1200 emulates a 1024-line encoder. Relating this to converter resolution means one revolution produces 1,024 A, B To get a maximum speed of 60,000 rpm, an external crystal of pulses. A leads B for increasing angular rotation (i.e., clockwise 8.192 MHz has to be chosen in order to produce an internal direction). The addition of the DIR output negates the need for CLOCKOUT equal to 4.096 MHz. external A and B direction decode logic. The DIR output This compares favorably with encoder specifications where f MAX indicates the direction of the input rotation and it is high for is specified from 20 kHz (photo diodes) to 125 kHz (laser increasing angular rotation. DIR can be considered as an based) depending on the light system used. A 1,024 line laser- asynchronous output and can make multiple changes in state based encoder will have a maximum speed of 7,300 rpm. between two consecutive LSB update cycles. This occurs when the direction of rotation of the input changes but the magnitude The inclusion of A, B outputs allows the AD2S1200 plus of the rotation is less than 1 LSB. resolver solution to replace optical encoders directly without the need to change or upgrade existing application software. The north marker pulse is generated as the absolute angular position passes through zero. The north marker pulse width is ON-BOARD PROGRAMMABLE SINUSOIDAL set internally for 90° and is defined relative to the A cycle. OSCILLATOR Figure 9 details the relationship between A, B, and NM. An on-board oscillator provides the sinusoidal excitation signal (EXC) to the resolver as well as its complemented signal (EXC). A The frequency of this reference signal is programmable to four standard frequencies (10 kHz, 12 kHz, 15 kHz, or 20 kHz) using the FS1 and FS2 pins (see Table 7). FS1 and FS2 have internal pull- ups, so the default frequency is 10 kHz. The amplitude of this B signal is centered on 2.5 V and has an amplitude of 3.6 V p-p. NM 04406-0-009 TFraebqleu e7n. c Eyx Sceitlaetcitoionn F (rkeHqzu)e ncy SelFeSc1ti on FS2 Figure 9. A, B, and NM Timing for Clockwise Rotation 10 1 1 12 1 0 Unlike incremental encoders, the AD2S1200 encoder output is 15 0 1 not subject to error specifications such as cycle error, eccentric- 20 0 0 ity, pulse and state width errors, count density, and phase ϕ. The maximum speed rating, n, of an encoder is calculated from its The reference output of the AD2S1200 will need an external maximum switching frequency, f , and its pulses per revo- MAX buffer amplifier to provide gain and the additional current to lution (PPR). drive a resolver. Refer to Figure 6 for a suggested buffer circuit. 60×f n= MAX The AD2S1200 also provides an internal synchronous reference PPR signal that is phase locked to its Sin and Cos inputs. Phase The AD2S1200 A, B pulses are initiated from XTALOUT, which errors between the resolver primary and secondary windings has a frequency of 4.096 MHz. The equivalent encoder could degrade the accuracy of the RDC and are compensated by switching frequency is this synchronous reference signal. This also compensates the phase shifts due to temperature and cabling and eliminates the 1/4×4.096MHz=1.024MHz(4Updates=1Pulse) need of an external preset phase compensation circuits. Rev. 0 | Page 16 of 24

AD2S1200 Synthetic Reference Generation After a rising edge on the RESET input, the device must be When a resolver undergoes a high rotation rate, the RDC tends allowed at least 20 ms (tTRACK) as shown in Figure 10 for internal to act as an electric motor and produces speed voltages, along circuitry to stabilize and the tracking loop to settle to the step with the ideal Sin and Cos outputs. These speed voltages are in change in input position. After tTRACK, a SAMPLE pulse must be quadrature to the main signal waveform. Moreover, nonzero applied, releasing the LOT and DOT pins to the state deter- resistance in the resolver windings causes a non-zero phase shift mined by the fault detection circuitry and providing valid between the reference input and the Sin and Cos outputs. The position data at the parallel and serial outputs (note that if combination of speed voltages and phase shift causes a tracking position data is being acquired via the encoder outputs, they error in the RDC that is approximated by may be monitored during tTRACK). RotationRate The RESET pin is internally pulled up. Error=PhaseShift× ReferenceFrequency VDD 4.75V To compensate for the described phase error between the resolver reference excitation and the Sin/Cos signals, an internal ttRRSSTT synthetic reference signal is generated in phase with the refer- RESET tTRACK ence frequency carrier. The synthetic reference is derived using the internally filtered Sin and Cos signals. It is generated by SAMPLE determining the zero crossing of either the Sin or Cos (which- ever signal is larger, to improve phase accuracy) and evaluating LOT the phase of the resolver reference excitation. The synthetic VALID reference reduces the phase shift between the reference and OUTPUT DATA Sin/Cos inputs to less than 10°, and will operate for phase shifts DOS of ±45°. 04406-0-010 SUPPLY SEQUENCING AND RESET Figure 10. Power Supply Sequencing and Reset The AD2S1200 requires an external reset signal to hold the RESET input low until V is within the specified operating CHARGE PUMP OUTPUT DD range of 4.5 V to 5.5 V. A 204.8 kHz square wave output with 50% duty cycle is avail- able at the CPO output pin of the AD2S1200. This square wave The RESET pin must be held low for a minimum of 10 µs after output can be used for negative rail voltage generation, or to V is within the specified range (t in Figure 10). Applying a DD RST create a V rail. RESET signal to the AD2S1200 initializes the output position to CC a value of 0x000 (degrees output through the parallel, serial, and encoder interfaces) and causes LOS to be indicated (LOT and DOS pins pulled low) as shown in Figure 10. Failure to apply the above (correct) power-up/reset sequence can result in an incorrect position indication. Rev. 0 | Page 17 of 24

AD2S1200 CIRCUIT DYNAMICS AD2S1200 LOOP RESPONSE MODEL The closed-loop magnitude and phase responses are that of a ERROR second-order low-pass filter (see Figure 12 and Figure 13). (ACCELERATION) VELOCITY To convert G(z) into the s-plane, we perform an inverse bilinear θIN k1×k2 1–zc–1 11––bazz––11 1–zc–1 θOUT transformation by substituting for z, where T = the sampling – period (1/4.096 MHz ≈ 244 ns). Sin/Cos LOOKUP 04406-0-011 2 +s Figure 11. RDC System Response Block Diagram z= T 2 −s The RDC is a mixed-signal device, which uses two A/D T converters to digitize signals from the resolver and a Type II Substitution yields the open-loop transfer function G(s). tracking loop to convert these to digital position and velocity words. s2T2 T(1+a) 1+sT+ 1+s× The first gain stage consists of the ADC gain on the Sin/Cos G(s)= k1×k2(1−a)× 4 × 2(1−a) inputs, and the gain of the error signal into the first integrator. a−b s2 1+s×T(1+b) The first integrator generates a signal proportional to velocity. 2(1−b) The compensation filter contains a pole and a zero, used to This transformation produces the best matching at low provide phase margin and reduce high frequency noise gain. frequencies (f << f ). At lower frequencies (within the SAMPLE The second integrator is the same as the first integrator and closed-loop bandwidth of the AD2S1200), the transfer function generates the output position from the velocity signal. The can be simplified to Sin/Cos lookup has unity gain. Values are given below for each section: K 1+st G(s) ≅ a × 1 s2 1+st V (V ) 2 • ADC gain parameter k1= IN p (k1nom = 1.8/2.5) V (V) where: REF T(1+a) • Error gain parameter k2=18x106×2π t1 = 2(1−a) T(1+b) 4095 t = • Compensator zero coefficient a= 2 2(1−b) 4096 k1×k2(1−a) K = a 4085 a−b • Compensator pole coefficient b= 4096 Solving for each value gives t = 1 µs, t = 90 µs, and K ≈ 7.4 × 1 2 a 106 s-2. Note that the closed-loop response is described as 1 • Integrator gain parameter c= 4096000 G(s) H(s)= 1+G(s) c • INT1 and INT2 transfer function I(z)= 1−z−1 By converting to the s-domain, we are able to quantify the open-loop dc gain (K). This value is useful during calculation a • Compensation filter transfer 1−az−1 of acceleration error of the loop as discussed in the Sources of C(z)= function 1−bz−1 Error section. The step response to a 10° input step is shown in Figure 14. • R2D open-loop transfer function G(z)=k1×k2×I(z)2×C(z) Because the error calculation (Equation 3) is nonlinear for large values of θ − ϕ, the response time for larger step changes in G(z) • R2D closed-loop transfer function H(z)= position (90°–180°) will typically take three times as long as the 1+G(z) response to a small step change in position (<20°). In response to a step change in velocity, the AD2S1200 will exhibit the same response characteristics as for a step change in position. Rev. 0 | Page 18 of 24

AD2S1200 5 SOURCES OF ERROR –0 Acceleration –5 A tracking converter employing a Type II servo loop does not –10 suffer any velocity lag. There is, however, an error associated B) with acceleration. This error can be quantified using the DE (d–15 acceleration constant (Ka) of the converter. U–20 T GNI–25 InputAcceleration MA–30 Ka = TrackingError –35 Conversely, ––44501 10 100 1k 10k 100k04406-0-012 TrackingError= InputAcceleration FREQUENCY(Hz) Ka Figure 12. RDC System Magnitude Response Figure 15 shows tracking error versus acceleration for the AD2S1200. 0 The numerator and denominator’s units must be consistent. The –20 maximum acceleration of the AD2S1200 has been defined as –40 the acceleration that creates an output position error of 5° –60 (when LOT is indicated). The maximum acceleration can be s) ee –80 calculated as gr e ASE (D––112000 MaximumAcceleration= Ka(sec−2)×5° ≅103,000rps2 H 360(°/rev) P –140 The AD2S1200 will be able to withstand the maximum –160 ––128000 04406-0-013 raecaccehleirnagt iiotsn mofa 1x0im3,u0m00 trrpacs2k fionrg arpapter ooxf i1m,0a0te0l yr p1s0. ms before 1 10 100 1k 10k 100k 1,000(rps) FREQUENCY (Hz) ≅10ms Figure 13. RDC System Phase Response 103,000(rps2) 20 10 18 9 16 8 s) e egrees) 1124 OR (Degre 67 E (D 10 ERR 5 GL 8 G 4 N N A KI 6 C 3 A R 4 T 2 20 04406-0-014 10 04406-0-015 0 1 2 3 4 5 0 40k 80k 120k 160k 200k TIME (ms) ACCELERATION (rps2) Figure 14. RDC Small Step Response Figure 15. Tracking Error vs. Acceleration Rev. 0 | Page 19 of 24

AD2S1200 CLOCK REQUIREMENTS The SAMPLE signal on the AD2S1200 could be provided either by using a PIO or by inverting the PWMSYNC signal to To achieve the specified dynamic performance, an external synchronize the position and velocity reading with the PWM crystal of 8.192 MHz must be used at the CLKIN, XTALOUT pins. The position and velocity accuracy are guaranteed for switching frequency. CS and RDVEL may be obtained using two operation with a 8.192 MHz clock. However, the position PIO outputs of the ADMC401. The 12 bits of significant data accuracy will still be maintained for clock frequencies ±10% plus status bits are available on each consecutive negative edge around this value. The velocity outputs are scaled in proportion of the clock following the low going of the RD signal. Data is to the clock frequency so that if the clock is 10% higher than the clocked from the AD2S1200 into the data receive register of the nominal, the full-scale velocity will be 10% higher than ADMC401. This is internally set to 16 bits (12 bits data, 4 status nominal. The maximum tracking rate and the tracking loop bits) because 16 bits are received overall. The serial port bandwidth also vary with the clock frequency. automatically generates an internal processor interrupt. This allows the ADMC401 to read 16 bits at once and continue CONNECTING TO THE DSP processing. The AD2S1200 serial port is ideally suited for interfacing to All ADMC401 products can interface to the AD2S1200 with DSP configured microprocessors. Figure 16 shows the similar interface circuitry. AD2S1200 interfaced to ADMC401, one of the DSP based motor controllers. The on-chip serial port of the ADMC401 is used in the ADMC401 AD2S1200 following configuration: SCLK SCLK SOE • Alternate framing transmit mode with internal framing DR SO (internally inverted) TFS RD RFS • Normal framing receive mode with external framing (internally inverted) PWMSYNC SAMPLE •In thIisn tmerondael, stehrei aAl DclMocCk 4g0e1n eursaetsio tnh e internal TFS signal as PPIIOO CRSDVEL 04406-0-016 Figure 16. Connecting to the ADMC401 external RFS to fully control the timing of receiving data and it uses the same TFS as RD to the AD2S1200. The ADMC401 also provides an internal continuous serial clock to the AD2S1200. Rev. 0 | Page 20 of 24

AD2S1200 OUTLINE DIMENSIONS 0.75 1.60 MAX 0.60 12.00 BSC 0.45 44 34 1 33 SEATING PIN 1 PLANE 10.00 TOP VIEW BSC (PINS DOWN) 10°
1.45 6°
1.40 2°
0.20 0.09 1.35 VIEW A 7°
11 23 3.5°
12 22 0.15 0° 0.05 SEATING 0.10 MAX 0.80 0.45 PLANE COPLANARITY BSC 0.37 VIEW A 0.30 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026BCB Figure 17. 44-Lead Low Profile Quad Flat Package [LQFP] (ST-44) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Angular Accuracy Package Description Package Option AD2S1200YST −40°C to +125°C ±11 arc min 44-Lead Low Profile Quad Flat Package (LQFP) ST-44 AD2S1200WST −40°C to +125°C ±22 arc min 44-Lead Low Profile Quad Flat Package (LQFP) ST-44 Rev. 0 | Page 21 of 24

AD2S1200 NOTES Rev. 0 | Page 22 of 24

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AD2S1200 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04406-0-10/03(0) Rev. 0 | Page 24 of 24

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