8-Channel DAC with PLL and Single-Ended Outputs, 192 kHz, 24 Bits Data Sheet AD1934 FEATURES GENERAL DESCRIPTION PLL generated or direct master clock The AD1934 is a high performance, single chip that provides Low EMI design eight digital-to-analog converters (DACs) with single-ended 108 dB DAC dynamic range and SNR output using the Analog Devices, Inc., patented multibit sigma- −94 dB THD + N delta (Σ-Δ) architecture. An SPI port is included, allowing a Single 3.3 V supply microcontroller to adjust volume and many other parameters. Tolerance for 5 V logic inputs The AD1934 operates from 3.3 V digital and analog supplies. Supports 24 bits and 8 kHz to 192 kHz sample rates The AD1934 is available in a 48-lead (single-ended output) Single-ended DAC output LQFP. Other members of this family include a differential DAC Log volume control with autoramp function output version. SPI® controllable for flexibility Software-controllable clickless mute The AD1934 is designed for low EMI. This consideration is Software power-down apparent in both the system and circuit design architectures. Right-justified, left-justified, I2S, and TDM modes By using the on-board PLL to derive the master clock from the Master and slave modes up to 16-channel in/out LR clock or from an external crystal, the AD1934 eliminates the 48-lead LQFP need for a separate high frequency master clock and can also be Qualified for automotive applications used with a suppressed bit clock. The DACs are designed using the latest Analog Devices continuous time architectures to further APPLICATIONS minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. Automotive audio systems Home theater systems Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM AD1934 DAC DAC DAC DIGITAL FILTER DAC ANALOG AND AUDIO VOLUME DAC OUTPUTS CLOCKS CONTROL SERIAL TIMING MANAGEMENT DAC DIGITAL AUDIO DATA AND CONTROL INPUT/OUTPUT PORT SDATAIN (CLOCK AND PLL) DAC DAC PRECISION CONTROL PORT 6.144MHz VOLTAGE REFERENCE SPI CINOPNUTTR/OOLU TDPAUTTA 06106-001 Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

AD1934 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converters (DACs) .................................... 13 Applications ....................................................................................... 1 Clock Signals ............................................................................... 13 General Description ......................................................................... 1 Reset and Power-Down ............................................................. 13 Functional Block Diagram .............................................................. 1 Serial Control Port ..................................................................... 14 Revision History ............................................................................... 2 Power Supply and Voltage Reference ....................................... 15 Specifications ..................................................................................... 4 Serial Data Ports—Data Format ............................................... 15 Test Conditions ............................................................................. 4 Time-Division Multiplexed (TDM) Modes ............................ 15 Analog Performance Specifications ........................................... 4 Daisy-Chain Mode ..................................................................... 17 Crystal Oscillator Specifications................................................. 5 Control Registers ............................................................................ 21 Digital Input/Output Specifications........................................... 5 Definitions ................................................................................... 21 Power Supply Specifications........................................................ 6 PLL and Clock Control Registers ............................................. 21 Digital Filters ................................................................................. 7 DAC Control Registers .............................................................. 22 Timing Specifications .................................................................. 7 Auxiliary TDM Port Control Registers ................................... 24 Absolute Maximum Ratings ............................................................ 9 Additional Modes ....................................................................... 24 Thermal Resistance ...................................................................... 9 Application Circuits ....................................................................... 26 ESD Caution .................................................................................. 9 Outline Dimensions ....................................................................... 27 Pin Configuration and Function Descriptions ........................... 10 Ordering Guide .......................................................................... 27 Typical Performance Characteristics ........................................... 12 Automotive Products ................................................................. 27 Theory of Operation ...................................................................... 13 REVISION HISTORY 2/13—Rev. C to Rev. D 9/09—Rev. 0 to Rev. A Changes to t Comments, Table 7 ............................................... 6 Change to Title ................................................................................... 1 CLH Changes to Serial Control Port Section ....................................... 13 Change to Table 11 ......................................................................... 13 Change to Power Supply and Voltage Reference Section .......... 14 7/11—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 Deleted References to I2C ............................................. Throughout Changes to Figure 2 and Table 10, DSDATAx/AUXDATA1 Pin 8/07—Revision 0: Initial Version Descriptions ...................................................................................... 9 1/11—Rev. A to Rev. B Added Automotive Information .................................. Throughout Change to Table 2, Introductory Text ............................................ 4 Change to Table 4, Introductory Text ............................................ 4 Change to Table 7, Introductory Text ............................................ 6 Changes to Ordering Guide .......................................................... 26 Rev. D | Page 2 of 29

Data Sheet AD1934 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3.3 V Temperature Range1 As specified in Table 1 and Table 2 Master Clock 12.288 MHz (48 kHz f, 256 × f mode) S S Input Sample Rate 48 kHz Measurement Bandwidth 20 Hz to 20 kHz Word Width 24 bits Load Capacitance (Digital Output) 20 pF Load Current (Digital Output) ±1 mA or 1.5 kΩ to ½ DVDD supply Input Voltage HI 2.0 V Input Voltage LO 0.8 V 1 Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Eight channels running −86 −75 dB Full-Scale Output Voltage 0.88 (2.48) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 +16 mV Gain Drift −30 +30 ppm/°C Interchannel Isolation 100 dB Interchannel Phase Deviation 0 Degrees Volume Control Step 0.375 dB Volume Control Range 95 dB De-emphasis Gain Error ±0.6 dB Output Resistance at Each Pin 100 Ω REFERENCE Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V Rev. D | Page 3 of 28

AD1934 Data Sheet Specifications measured at 125°C (case). Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS Dynamic Range 20 Hz to 20 kHz, −60 dB input No Filter (RMS) 98 104 dB With A-Weighted Filter (RMS) 100 106 dB With A-Weighted Filter (Average) 108 dB Total Harmonic Distortion + Noise 0 dBFS Single-Ended Version Two channels running −92 dB Eight channels running −86 −70 dB Full-Scale Output Voltage 0.8775 (2.482) V rms (V p-p) Gain Error −10 +10 % Interchannel Gain Mismatch −0.2 +0.2 dB Offset Error −16 −4 +16 mV Gain Drift −30 +30 ppm/°C REFERENCE Internal Reference Voltage FILTR pin 1.50 V External Reference Voltage FILTR pin 1.32 1.50 1.68 V Common-Mode Reference Output CM pin 1.50 V CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Min Typ Max Unit Transconductance 3.5 mmhos DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < T < 125°C, DVDD = 3.3 V ± 10%. C Table 4. Parameter Test Conditions/Comments Min Typ Max Unit Input Voltage HI (V ) 2.0 V IH Input Voltage HI (V ) MCLKI pin 2.2 V IH Input Voltage LO (V ) 0.8 V IL Input Leakage I @ V = 2.4 V 10 μA IH IH I @ V = 0.8 V 10 μA IL IL High Level Output Voltage (V ) I = 1 mA DVDD − 0.60 V OH OH Low Level Output Voltage (V ) I = 1 mA 0.4 V OL OL Input Capacitance 5 pF Rev. D | Page 4 of 28

Data Sheet AD1934 POWER SUPPLY SPECIFICATIONS Table 5. Parameter Test Conditions/Comments Min Typ Max Unit SUPPLIES Voltage DVDD 3.0 3.3 3.6 V AVDD 3.0 3.3 3.6 V Digital Current MCLK = 256 f S Normal Operation f = 48 kHz 56 mA S f = 96 kHz 65 mA S f = 192 kHz 95 mA S Power-Down f = 48 kHz to 192 kHz 2.0 mA S Analog Current Normal Operation 74 mA Power-Down 23 mA DISSIPATION Operation MCLK = 256 f, 48 kHz S All Supplies 429 mW Digital Supply 185 mW Analog Supply 244 mW Power-Down, All Supplies 83 mW POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB 20 kHz, 200 mV p-p 50 dB Rev. D | Page 5 of 28

AD1934 Data Sheet DIGITAL FILTERS Table 6. Parameter Mode Factor Min Typ Max Unit DAC INTERPOLATION FILTER Pass Band 48 kHz mode, typ @ 48 kHz 0.4535 f 22 kHz S 96 kHz mode, typ @ 96 kHz 0.3646 f 35 kHz S 192 kHz mode, typ @ 192 kHz 0.3646 f 70 kHz S Pass-Band Ripple 48 kHz mode, typ @ 48 kHz ±0.01 dB 96 kHz mode, typ @ 96 kHz ±0.05 dB 192 kHz mode, typ @ 192 kHz ±0.1 dB Transition Band 48 kHz mode, typ @ 48 kHz 0.5 f 24 kHz S 96 kHz mode, typ @ 96 kHz 0.5 f 48 kHz S 192 kHz mode, typ @ 192 kHz 0.5 f 96 kHz S Stop Band 48 kHz mode, typ @ 48 kHz 0.5465 f 26 kHz S 96 kHz mode, typ @ 96 kHz 0.6354 f 61 kHz S 192 kHz mode, typ @ 192 kHz 0.6354 f 122 kHz S Stop-Band Attenuation 48 kHz mode, typ @ 48 kHz 70 dB 96 kHz mode, typ @ 96 kHz 70 dB 192 kHz mode, typ @ 192 kHz 70 dB Group Delay 48 kHz mode, typ @ 48 kHz 25/f 521 µs S 96 kHz mode, typ @ 96 kHz 11/f 115 µs S 192 kHz mode, typ @ 192 kHz 8/f 42 µs S TIMING SPECIFICATIONS −40°C < T < 125°C, DVDD = 3.3 V ± 10%. C Table 7. Parameter Condition Comments Min Max Unit INPUT MASTER CLOCK (MCLK) AND RESET t MCLK duty cycle DAC clock source = PLL clock @ 256 f, 40 60 % MH S 384 f, 512 f, 768 f S S S t DAC clock source = direct MCLK @ 512 f 40 60 % MH S (bypass on-chip PLL) f MCLK frequency PLL mode, 256 f reference 6.9 13.8 MHz MCLK S f Direct 512 f mode 27.6 MHz MCLK S tPDR RST low 15 ns tPDRR RST recovery Reset to active output 4096 tMCLK PLL Lock Time MCLK and LRCLK input 10 ms 256 f VCO Clock, Output Duty Cycle 40 60 % S MCLKO Pin SPI PORT See Figure 9 t CCLK high 35 ns CCH t CCLK low 35 ns CCL f CCLK frequency f = 1/t , only t shown in Figure 9 10 MHz CCLK CCLK CCP CCP t CDATA setup To CCLK rising 10 ns CDS t CDATA hold From CCLK rising 10 ns CDH tCLS CLATCH setup To CCLK rising 10 ns tCLH CLATCH hold From CCLK rising 10 ns tCLHIGH CLATCH high Not shown in Figure 9 10 ns t COUT enable From CCLK falling 30 ns COE t COUT delay From CCLK falling 30 ns COD t COUT hold From CCLK falling, not shown in Figure 9 30 ns COH t COUT tri-state From CCLK falling 30 ns COTS Rev. D | Page 6 of 28

Data Sheet AD1934 Parameter Condition Comments Min Max Unit DAC SERIAL PORT See Figure 16 t DBCLK high Slave mode 10 ns DBH t DBCLK low Slave mode 10 ns DBL t DLRCLK setup To DBCLK rising, slave mode 10 ns DLS t DLRCLK hold From DBCLK rising, slave mode 5 ns DLH t DLRCLK skew From DBCLK falling, master mode −8 +8 ns DLS t DSDATA setup To DBCLK rising 10 ns DDS t DSDATA hold From DBCLK rising 5 ns DDH AUXTDM SERIAL PORT See Figure 17 t AUXTDMBCLK high Slave mode 10 ns ABH t AUXTDMBCLK low Slave mode 10 ns ABL t AUXTDMLRCLK setup To AUXTDMBCLK rising, slave mode 10 ns ALS t AUXTDMLRCLK hold From AUXTDMBCLK rising, slave mode 5 ns ALH t AUXTDMLRCLK skew From AUXTDMBCLK falling, master mode −8 +8 ns ALS t DSDATA setup To AUXTDMBCLK, not shown in Figure 17 10 ns DDS t DSDATA hold From AUXTDMBCLK rising, not shown in 5 ns DDH Figure 17 AUXILIARY INTERFACE t AUXDATA delay From AUXBCLK falling 18 ns DXDD t AUXBCLK high 10 ns XBH t AUXBCLK low 10 ns XBL t AUXLRCLK setup To AUXBCLK rising 10 ns DLS t AUXLRCLK hold From AUXBCLK rising 5 ns DLH Rev. D | Page 7 of 28

AD1934 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. THERMAL RESISTANCE Parameter Rating θ represents thermal resistance, junction-to-ambient; Analog (AVDD) −0.3 V to +3.6 V JA θ represents the thermal resistance, junction-to-case. Digital (DVDD) −0.3 V to +3.6 V JC All characteristics are for a 4-layer board. Input Current (Except Supply Pins) ±20 mA Analog Input Voltage (Signal Pins) −0.3 V to AVDD + 0.3 V Table 9. Thermal Resistance Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V Package Type θJA θJC Unit Operating Temperature Range (Case) −40°C to +125°C 48-Lead LQFP 50.1 17 °C/W Storage Temperature Range −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings ESD CAUTION may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 8 of 28

Data Sheet AD1934 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D D D V F C C C C C C C C M V A L N N N N N N N N C A 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND MCLKI/XI 2 35 FILTR MCLKO/XO 3 34 AGND AGND 4 33 AVDD AVDD 5 AD1934 32 AGND OL3 6 TOP VIEW 31 OR2 (Not to Scale) OR3 7 30 OL2 SINGLE-ENDED OL4 8 OUTPUT 29 OR1 OR4 9 28 OL1 PD/RST 10 27 CLATCH DSDATA4 11 26 CCLK DGND 12 25 DGND 13 14 15 16 17 18 19 20 21 22 23 24 D 3 2 1 K K 1 C K K N T NC = NO CONNECT DVD DSDATA DSDATA DSDATA DBCL DLRCL AUXDATA N XTDMBCL TDMLRCL CI COU 06106-020 U X A AU Figure 2. Pin Configuration Table 10. Pin Function Description Pin No. Input/Output Mnemonic Description 1 I AGND Analog Ground. 2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input. 3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output. 4 I AGND Analog Ground. 5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 6 O OL3 DAC 3 Left Output. 7 O OR3 DAC 3 Right Output. 8 O OL4 DAC 4 Left Output. 9 O OR4 DAC 4 Right Output. 10 I PD/RST Power-Down Reset (Active Low). 11 I/O DSDATA4 DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line mode)/AUX DAC2 data out (to external DAC2). 12 I DGND Digital Ground. 13 I DVDD Digital Power Supply. Connect to digital 3.3 V supply. 14 I/O DSDATA3 DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line mode)/AUX not used. 15 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC2 data out/AUX not used. 16 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/AUX TDM data in. 17 I/O DBCLK Bit Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode). 18 I/O DLRCLK LR Clock for DACs (Regular Stereo, TDM, or Daisy-Chain TDM Mode). 19 O AUXDATA1 AUX DAC1 data out (to external DAC1). 20 NC No Connect. 21 I/O AUXTDMBCLK Auxiliary Mode Only DAC TDM Bit Clock. 22 I/O AUXTDMLRCLK Auxiliary Mode Only DAC LR TDM Clock. 23 I CIN/ADR0 Control Data Input (SPI). 24 I/O COUT/SDA Control Data Output (SPI). 25 I DGND Digital Ground. Rev. D | Page 9 of 28

AD1934 Data Sheet Pin No. Input/Output Mnemonic Description 26 I CCLK/SCL Control Clock Input (SPI). 27 I CLATCH/ADR1 Latch Input for Control Data (SPI). 28 O OL1 DAC 1 Left Output. 29 O OR1 DAC 1 Right Output. 30 O OL2 DAC 2 Left Output. 31 O OR2 DAC 2 Right Output. 32 I AGND Analog Ground. 33 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 34 I AGND Analog Ground. 35 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND. 36 I AGND Analog Ground. 37 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. 38 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with 47 µF||100 nF to AGND. 39 to 46 NC Must Be Tied to Common Mode, Pin 38. Alternately, ac-coupled to ground. 47 O LF PLL Loop Filter. Return to AVDD. 48 I AVDD Analog Power Supply. Connect to analog 3.3 V supply. Rev. D | Page 10 of 28

Data Sheet AD1934 TYPICAL PERFORMANCE CHARACTERISTICS 0.06 0 0.04 B) 0.02 dB) –50 E (d DE ( D U U 0 T NIT GNI G A A M M–0.02 –100 –0.04 –0.060 8FREQUENCY (kHz)16 24 06106-004 –1500 24 FREQUE4N8CY (kHz) 72 96 06106-007 Figure 3. DAC Pass-Band Filter Response, 48 kHz Figure 6. DAC Stop-Band Filter Response, 96 kHz 0.5 0 0.4 0.3 MAGNITUDE (dB) –1–0500 MAGNITUDE (dB) –000...1012 –0.2 –0.3 –0.4 –1500 12 FREQUE2N4CY (kHz) 36 48 06106-005 –0.50 8 FREQ16UENCY (kHz)32 64 06106-008 Figure 4. DAC Stop-Band Filter Response, 48 kHz Figure 7. DAC Pass-Band Filter Response, 192 kHz 0.10 0 0.05 –2 B) dB) E (d DE ( –4 D U U 0 T NIT GNI AG MA –6 M –0.05 –8 –0.100 24 FREQUE4N8CY (kHz) 72 96 06106-006 –1048 64FREQUENCY (kHz)80 96 06106-009 Figure 5. DAC Pass-Band Filter Response, 96 kHz Figure 8. DAC Stop-Band Filter Response, 192 kHz Rev. D | Page 11 of 28

AD1934 Data Sheet THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The PLL can be powered down in PLL and Clock Control 0 Register. To ensure reliable locking when changing PLL modes, The AD1934 DAC channels are arranged as single-ended, four or if the reference clock is unstable at power-on, power down stereo pairs giving eight analog outputs for minimum external the PLL and then power it back up when the reference clock components. The DACs include on-board digital reconstruction has stabilized. filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) The internal MCLK can be disabled in PLL and Clock Control 0 or 2 (192 kHz mode). Each channel has its own independently Register to reduce power dissipation when the AD1934 is idle. programmable attenuator, adjustable in 255 steps in increments The clock should be stable before it is enabled. Unless a stand- of 0.375 dB. Digital inputs are supplied through four serial data alone mode is selected (see the Serial Control Port section), the input pins (one for each stereo pair) and a common frame clock is disabled by reset and must be enabled by writing to the (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the SPI port for normal operation. TDM modes can be used to access up to 16 channels on a single TDM data line. To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited Each output pin has a nominal common-mode dc level of 1.5 V to less than 300 ps rms time interval error (TIE). Even at these and swings ±1.27 V for a 0 dBFS digital input signal. A single op levels, extra noise or tones can appear in the DAC outputs if the amp, third-order, external, low-pass filter is recommended to jitter spectrum contains large spectral peaks. If the internal PLL remove high frequency noise present on the output pins. The is not being used, it is highly recommended that an independent use of op amps with low slew rate or low bandwidth can cause crystal oscillator generate the master clock. In addition, it is high frequency noise and tones to fold down into the audio especially important that the clock signal not be passed through band; therefore, exercise care in selecting these components. an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1934. In most cases, this induces The voltage at CM, the common-mode reference pin, can be clock jitter due to the sharing of common power and ground used to bias the external op amps that buffer the output signals connections with other unrelated digital output signals. When (see the Power Supply and Voltage Reference section). the PLL is used, jitter in the reference clock is attenuated above CLOCK SIGNALS a certain frequency depending on the loop filter. The on-chip phase locked loop (PLL) can be selected to RESET AND POWER-DOWN reference the input sample rate from either of the LRCLK pins Reset sets all the control registers to their default settings. or 256, 384, 512, or 768 times the sample rate, referenced to the To avoid pops, reset does not power down the analog outputs. 48 kHz mode from the MCLKI pin. The default at power-up is After reset is deasserted, and the PLL acquires lock condition, 256 × f from MCLKI pin. In 96 kHz mode, the master clock S an initialization routine runs inside the AD1934. This frequency stays at the same absolute frequency; therefore, the initialization lasts for approximately 256 MCLKs. actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if a The power-down bits in the PLL and Clock Control 0 and DAC device in the AD1934 family is programmed in 256 × f mode, the S Control 1 registers power down the respective sections. All frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. other register settings are retained. To guarantee proper startup, If the AD1934 is then switched to 96 kHz operation (by writing the reset pin should be pulled low by an external resistor. to the SPI port), the frequency of the master clock should remain at 12.288 MHz, which is now 128 × f. In 192 kHz mode, S this becomes 64 × f. S The internal clock for the DACs varies by mode: 512 × f (48 kHz S mode), 256 × f (96 kHz mode), or 128 × f (192 kHz mode). By S S default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × f (referenced to 48 kHz S mode) master clock can be used for DACs if selected in PLL and Clock Control 1 Register. Rev. D | Page 12 of 28

Data Sheet AD1934 SERIAL CONTROL PORT The AD1934 has an SPI control port that permits programming The SPI control port of the AD1934 is a 4-wire serial control and reading back of the internal control registers for the ADCs, port. The format is similar to the Motorola SPI format except DACs, and clock system. A standalone mode is also available the input data-word is 24 bits wide. The serial bit clock and for operation without serial control; standalone is configured latch can be completely asynchronous to the sample rate of the at reset by connecting CIN, CCLK, and CLATCH to ground. DACs. Figure 9 shows the format of the SPI signal. The first In standalone mode, all registers are set to default, except the byte is a global address with a read/write bit. For the AD1934, internal MCLK enable, which is set to 1. The ADC ABCLK and the address is 0x04, shifted left 1 bit due to the R/W bit. The ALRCLK clock ports are set to master/slave by the connecting second byte is the AD1934 register address and the third byte the COUT pin to either DVDD or ground. Standalone mode is the data. only supports stereo mode with an I2S data format and 256 f S MCLK rate. Refer to Table 11 for details. If CIN, CCLK, and CLATCH are not grounded, the AD1934 SPI port is active. It is recommended to use a weak pull-up resistor on CLATCH in applications that have a microcontroller. This pull-up resistor ensures that the AD1934 recognizes the presence of a micro- controller. Table 11. SPI vs. Standalone Mode Configuration DAC Control COUT CIN CLATCH CCLK SPI OUT IN 1 (Pull-Up) IN Standalone 0 0 0 0 CLATCH tCLS tCCP tCCH tCCL tCLH tCOTS CCLK tCDStCDH CIN D23 D22 D9 D8 D0 COUT tCOE D9 D8 D0 tCOD 06106-010 Figure 9. Format of SPI Signal Rev. D | Page 13 of 28

AD1934 Data Sheet POWER SUPPLY AND VOLTAGE REFERENCE mode, the AUXTDMLRCLK and AUXTDMBCLK pins are The AD1934 is designed for 3.3 V supplies. Separate power configured as TDM port clocks. In regular TDM mode, the supply pins are provided for the analog and digital sections. DLRCLK and DBCLK pins are used as the TDM port clocks. These pins should be bypassed with 100 nF ceramic chip The auxiliary TDM serial port’s format and its serial clock capacitors, as close to the pins as possible, to minimize noise polarity is programmable according to the Auxiliary TDM Port pickup. A bulk aluminum electrolytic capacitor of at least 22 μF Control 0 Register and Control 1 Register. Both DAC and should also be provided on the same PC board as the DAC. For auxiliary TDM serial ports are programmable to become the critical applications, improved performance is obtained with bus masters according to DAC Control 1 Register and auxiliary separate supplies for the analog and digital sections. If this is TDM Control 1 Register. By default, both auxiliary TDM and not possible, it is recommended that the analog and digital DAC serial ports are in the slave mode. supplies be isolated by means of a ferrite bead in series with each supply. It is important that the analog supply be as TIME-DIVISION MULTIPLEXED (TDM) MODES clean as possible. The AD1934 serial ports also have several different TDM serial All digital inputs are compatible with TTL and CMOS levels. data modes. The most commonly used configuration is shown All outputs are driven from the 3.3 V DVDD supply and are in Figure 10. In Figure 10, the eight on-chip DAC data slots are compatible with TTL and 3.3 V CMOS levels. packed into one TDM stream. In this mode, DBCLK is 256 fS. The DAC internal voltage reference (VREF) is brought out on The I/O pins of the serial ports are defined according to the FILTR and should be bypassed as close as possible to the chip, serial mode selected. For a detailed description of the function with a parallel combination of 10 μF and 100 nF. Any external of each pin in TDM and AUX Modes, see Table 12. current drawn should be limited to less than 50 μA. The AD1934 allows systems with more than eight DAC channels The internal reference can be disabled in PLL and Clock to be easily configured by the use of an auxiliary serial data port. Control 1 Register and FILTR can be driven from an external The DAC TDM-AUX mode is shown in Figure 11. In this mode, source. This can be used to scale the DAC output to the clipping the AUX channels are the last four slots of the 16-channel TDM level of a power amplifier based on its power supply voltage. data stream. These slots are extracted and output to the AUX serial port. One major difference between the TDM mode and The CM pin is the internal common-mode reference. It should an auxiliary TDM mode is the assignment of the TDM port be bypassed as close as possible to the chip, with a parallel pins, as shown in Table 12. In auxiliary TDM mode, DBCLK combination of 47 μF and 100 nF. This voltage can be used to and DLRCLK are assigned as the auxiliary port clocks, and bias external op amps to the common-mode voltage of the input AUXTDMBCLK and AUXTDMLRCLK are assigned as the and output signal pins. The output current should be limited to TDM port clocks. In regular TDM or 16-channel, daisy-chain less than 0.5 mA source and 2 mA sink. TDM mode, the DLRCLK and DBCLK pins are set as the TDM SERIAL DATA PORTS—DATA FORMAT port clocks. It should be noted that due to the high AUXTDMBCLK frequency, 16-channel auxiliary TDM mode is The eight DAC channels use a common serial bit clock (DBCLK) available only in the 48 kHz/44.1 kHz/32 kHz sample rate. and a common left-right framing clock (DLRCLK) in the serial data port. The clock signals are all synchronous with the sample LRCLK rate. The normal stereo serial modes are shown in Figure 15. 256 BCLKs BCLK 32 BCLK The DAC serial data modes default to I2S. The ports can also be programmed for left-justified, right-justified, and TDM modes. DATA SLLEOFTT 11 RSILGOHTT 21 SLLEOFTT 23 RSILGOHTT 42 SLLEOFTT 35 RSILGOHTT 63 SLLEOFTT 47 RSILGOHTT 84 The word width is 24 bits by default and can be programmed for 16 or 20 bits. The DAC serial formats are programmable LRCLK according to DAC Control 0 Register. The polarity of the BCLK DBCLK and DLRCLK is programmable according to DAC MSB MSB–1 MSB–2 DATA 06106-017 Control 1 Register. The auxiliary TDM port is also provided for Figure 10. DAC TDM (8-Channel I2S Mode) applications requiring more than eight DAC channels. In this Rev. D | Page 14 of 28

Data Sheet AD1934 Table 12. Pin Function Changes in TDM and AUX Modes Pin Name Stereo Modes TDM Modes AUX Modes AUXDATA1 Not Used (Float) Not Used (Float) AUX Data Out 1 (to External DAC 1) DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In DSDATA2 DAC2 Data In DAC TDM Data Out Not Used (Ground) DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) Not Used (Ground) DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to External DAC 2) AUXTDMLRCLK Not Used (Ground) Not Used (Ground) TDM Frame Sync In/Out AUXTDMBCLK Not Used (Ground) Not Used (Ground) TDM BCLK In/Out DLRCLK DAC LRCLK In/Out DAC TDM Frame Sync In/Out AUX LRCLK In/Out DBCLK DAC BCLK In/Out DAC TDM BCLK In/Out AUX BCLK In/Out AUXTDMLRCLK AUXTDMBCLK AUXILIARY DAC CHANNELS WILL APPEAR AT UNUSED SLOTS 8-ON-CHIP DAC CHANNELS AUX DAC PORTS DSDATA1 (TDM_IN) EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 32 BITS MSB DLRCLK LEFT RIGHT (AUX PORT) DBCLK (AUX PORT) AUXDATA1 (AUX1_OUT) MSB MSB (AUDXS2D_AOTUAT4) MSB MSB 06106-051 Figure 11. 16-Channel DAC TDM-AUX Mode Rev. D | Page 15 of 28

AD1934 Data Sheet DAISY-CHAIN MODE The AD1934 also allows a daisy-chain configuration to expand The dual-line, DAC TDM mode can also be used to send data at the system 16 DACs (see Figure 12). In this mode, the DBCLK a 192 kHz sample rate into the AD1934, as shown in Figure 14. frequency is 512 f. The first eight slots of the DAC TDM data The I/O pins of the serial ports are defined according to the S stream belong to the first AD1934 in the chain and the last eight serial mode selected. See Table 13 for a detailed description of slots belong to the second AD1934. The second AD1934 is the the function of each pin. See Figure 18 for a typical AD1934 device attached to the DSP TDM port. configuration with two external stereo DACs. Figure 15 and Figure 16 show the serial mode formats. For maximum To accommodate 16 channels at a 96 kHz sample rate, the flexibility, the polarity of LRCLK and BCLK are programmable. AD1934 can be configured into a dual-line, DAC TDM mode, In these figures, all of the clocks are shown with their normal as shown in Figure 13. This mode allows a slower DBCLK than polarity. The default mode is I2S. normally required by the one-line TDM mode. Again, the first four channels of each TDM input belong to the first AD1934 in the chain and the last four channels belong to the second AD1934. DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DSDATA1 (TDM_IN) OF THE SECOND AD1934 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DSDATA2 (TDM_OUT) OF THE SECOND AD1934 THIS IS THE TDM DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 TO THE FIRST AD1934 8 UNUSED SLOTS 32 BITS AFDIR19S3T4 SAEDC1O93N4D DSP MSB 06106-054 Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain) DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DSDATA1 (IN) DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 (OUT) DAC L1 DAC R1 DAC L2 DAC R2 DSDATA3 (IN) DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4 DSDATA4 (OUT) DAC L3 DAC R3 DAC L4 DAC R4 32 BITS MSB AFDIR19S3T4 SAEDC1O93N4D DSP 06106-055 Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain; DSDATA3 and DSDATA4 Are the Daisy Chain) Rev. D | Page 16 of 28

Data Sheet AD1934 DLRCLK DBCLK DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4 32 BITS MSB 06106-058 Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode) LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA MSB LSB MSB LSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA MSB LSB MSB LSB I2S MODE—16 BITS TO 24 BITS PER CHANNEL LRCLK LEFT CHANNEL RIGHT CHANNEL BCLK SDATA MSB LSB MSB LSB RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 123... DLBRSCCPLL KMK FO NRDOEEQR DUMOEAENLSCL YYN OIOSTP N EIDORERANMTTEAISFLY LA YCT H6f4SA N×E NXLCERLEC.PLTK FBOURT DMSAPY MBOED OEP, EWRHAITCEHD I SIN 2 B×UfSR.ST MODE. 06106-013 Figure 15. Stereo Serial Modes Rev. D | Page 17 of 28

AD1934 Data Sheet tDBH DBCLK tDBL tDLS tDLH DLRCLK tDDS DSDATA LEFT-JUSTIFIED MSB MSB–1 MODE tDDH tDDS DSDATA I2S-JUSTIFIED MSB MODE tDDH tDDS tDDS DSDATA RIGHT-JUSTMIFOIDEDE MSBtDDH LSBtDDH 06106-014 Figure 16. DAC Serial Timing tABH AUXTDMBCLK tABL tALS tALH AUXTDMLRCLK DSDATA1 LEFT-JUSTIFIED MODE MSB MSB–1 DSDATA1 I2S-JUSTIFIED MSB MODE DSDATA1 RIGHT-JUSTMIFOIDEDE MSB LSB 06106-015 Figure 17. AUXTDM Serial Timing Rev. D | Page 18 of 28

Data Sheet AD1934 Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Pin Name Stereo Modes TDM Modes AUX Modes AUXDATA1 Not Used (Float) Not Used (Float) AUX Data Out 1 (to External DAC 1) DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In DSDATA2 DAC2 Data In DAC TDM Data Out Not Used (Ground) DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) Not Used (Ground) DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to External DAC 2) AUXTDMLRCLK Not Used (Ground) Not Used (Ground) TDM Frame Sync In/Out AUXTDMBCLK Not Used (Ground) Not Used (Ground) TDM BCLK In/Out DLRCLK DAC LRCLK In/Out DAC TDM Frame Sync In/Out AUX LRCLK In/Out DBCLK DAC BCLK In/Out DAC TDM BCLK In/Out AUX BCLK In/Out 30MHz SHARC IS RUNNING IN SLAVE MODE FS) SHARC (INTERRUPT-DRIVEN) R M ( D 12.288MHz C-T K NC) K TA YN CL S ( CL DA FS Rx TF Tx Tx LRCLK BCLK AUX DATA DAC 1 AUXTDMLRCLK AUXTDMBCLK DSDATA1 MCLK DBCLK DLRCLK AD1934 LRCLK DSDATA2 TDM MASTER AUXDATA1 BCLK AUX DSDATA3 AUX MASTER DSDATA4 DATA DAC 2 MCLK MCLK 06106-019 Figure 18. Example of AUX Mode Connection to SHARC® (AD1934 as TDM Master/AUX Master Shown) Rev. D | Page 19 of 28

AD1934 Data Sheet CONTROL REGISTERS DEFINITIONS The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/W bit. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Global Address R/W Register Address Data Bit 23:17 16 15:8 7:0 Table 15. Register Addresses and Functions Address Function 0 PLL and Clock Control 0 1 PLL and Clock Control 1 2 DAC Control 0 3 DAC Control 1 4 DAC Control 2 5 DAC individual channel mutes 6 DAC 1L volume control 7 DAC 1R volume control 8 DAC 2L volume control 9 DAC 2R volume control 10 DAC 3L volume control 11 DAC 3R volume control 12 DAC 4L volume control 13 DAC 4R volume control 14 Reserved 15 Auxiliary TDM Port Control 0 16 Auxiliary TDM Port Control 1 PLL AND CLOCK CONTROL REGISTERS Table 16. PLL and Clock Control 0 Bit Value Function Description 0 0 Normal operation PLL power-down 1 Power-down 2:1 00 INPUT 256 (×44.1 kHz or 48 kHz) MCLK pin functionality (PLL active) 01 INPUT 384 (×44.1 kHz or 48 kHz) 10 INPUT 512 (×44.1 kHz or 48 kHz) 11 INPUT 768 (×44.1 kHz or 48 kHz) 4:3 00 XTAL oscillator enabled MCLKO pin 01 256 × f VCO output S 10 512 × f VCO output S 11 Off 6:5 00 MCLK PLL input 01 DLRCLK 10 AUXTDMLRCLK 11 Reserved 7 0 Disable: DAC idle Internal MCLK enable 1 Enable: DAC active Rev. D | Page 20 of 28

Data Sheet AD1934 Table 17. PLL and Clock Control 1 Bit Value Function Description 0 0 PLL clock DAC clock source select 1 MCLK 1 0 PLL clock Clock source select 1 MCLK 2 0 Enabled On-chip voltage reference 1 Disabled 3 0 Not locked PLL lock indicator (read-only) 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS Table 18. DAC Control 0 Bit Value Function Description 0 0 Normal Power-down 1 Power-down 2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate 01 64 kHz/88.2 kHz/96 kHz 10 128 kHz/176.4 kHz/192 kHz 11 Reserved 5:3 000 1 SDATA delay (BCLK periods) 001 0 010 8 011 12 100 16 101 Reserved 110 Reserved 111 Reserved 7:6 00 Stereo (normal) Serial format 01 TDM (daisy chain) 10 DAC aux mode (DAC-, TDM-coupled) 11 Dual-line TDM Table 19. DAC Control 1 Bit Value Function Description 0 0 Latch in midcycle (normal) BCLK active edge (TDM in) 1 Latch in at end of cycle (pipeline) 2:1 00 64 (2 channels) BCLKs per frame 01 128 (4 channels) 10 256 (8 channels) 11 512 (16 channels) 3 0 Left low LRCLK polarity 1 Left high 4 0 Slave LRCLK master/slave 1 Master 5 0 Slave BCLK master/slave 1 Master 6 0 DBCLK pin BCLK source 1 Internally generated 7 0 Normal BCLK polarity 1 Inverted Rev. D | Page 21 of 28

AD1934 Data Sheet Table 20. DAC Control 2 Bit Value Function Description 0 0 Unmute Master mute 1 Mute 2:1 00 Flat De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4:3 00 24 Word width 01 20 10 Reserved 11 16 5 0 Noninverted DAC output polarity 1 Inverted 7:6 00 Reserved Table 21. DAC Individual Channel Mutes Bit Value Function Description 0 0 Unmute DAC 1 left mute 1 Mute 1 0 Unmute DAC 1 right mute 1 Mute 2 0 Unmute DAC 2 left mute 1 Mute 3 0 Unmute DAC 2 right mute 1 Mute 4 0 Unmute DAC 3 left mute 1 Mute 5 0 Unmute DAC 3 right mute 1 Mute 6 0 Unmute DAC 4 left mute 1 Mute 7 0 Unmute DAC 4 right mute 1 Mute Table 22. DAC Volume Controls Bit Value Function Description 7:0 0 No attenuation DAC volume control 1 to 254 −3/8 dB per step 255 Full attenuation Rev. D | Page 22 of 28

Data Sheet AD1934 AUXILIARY TDM PORT CONTROL REGISTERS Table 23. Auxiliary TDM Control 0 Bit Value Function Description 1:0 00 24 Word width 01 20 10 Reserved 11 16 4:2 000 1 SDATA delay (BCLK periods) 001 0 010 8 011 12 100 16 101 Reserved 110 Reserved 111 Reserved 6:5 00 Reserved Serial format 01 Reserved 10 DAC aux mode 11 Reserved 7 0 Latch in midcycle (normal) BCLK active edge (TDM in) 1 Latch in at end of cycle (pipeline) Table 24. Auxiliary TDM Control 1 Bit Value Function Description 0 0 50/50 (allows 32/24/20/16 BCLK/channel) LRCLK format 1 Pulse (32 BCLK/channel) 1 0 Drive out on falling edge (DEF) BCLK polarity 1 Drive out on rising edge 2 0 Left low LRCLK polarity 1 Left high 3 0 Slave LRCLK master/slave 1 Master 5:4 00 64 BCLKs per frame 01 128 10 256 11 512 6 0 Slave BCLK master/slave 1 Master 7 0 AUXTDMBCLK pin BCLK source 1 Internally generated ADDITIONAL MODES To relax the requirement for the setup time of the AD1934 in cases of high speed TDM data transmission, the AD1934 can The AD1934 offers several additional modes for board level latch in the data using the falling edge of DBCLK. This design enhancements. To reduce the EMI in board level design, effectively dedicates the entire BCLK period to the setup time. serial data can be transmitted without an explicit BCLK. See This mode is useful in cases where the source has a large delay Figure 19 for an example of a DAC TDM data transmission time in the serial data driver. Figure 20 shows this pipeline mode that does not require high speed DBCLK. This configuration mode of data transmission. is applicable when the AD1934 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency. Both the BLCK-less and pipeline modes are available. Rev. D | Page 23 of 28

AD1934 Data Sheet DLRCLK 32 BITS INTERNAL DBCLK DSDATA DLRCLK INTERNAL DBCLK TDM-DSDATA 06106-059 Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) DLRCLK DBCLK DATA MUST BE VALID AT THIS BCLK EDGE DSDATA MSB 06106-060 Figure 20. I2S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission) Rev. D | Page 24 of 28

Data Sheet AD1934 APPLICATION CIRCUITS Typical applications circuits are shown in Figure 21, Figure 22, 240pF NPO and Figure 23. Recommended loop filters for LR clock and mOuastpteurt cflioltcekr sa fso trh teh Pe LDLA rCef eoruetnpcuet sa raer es hshoowwnn i nin F Figiugurer e2 12.2 and DAC OUT 4.75kΩ 4.75kΩ 32 O+P275 1 604Ω 4+.7µF AOUUDTIPOUT Figure 23 for the noninverting and inverting cases, respectively. – 4.99kΩ 3N.3PnOF 49.9kΩ LF L3R9CnFLK LF M5C.6LnKF 27N0PpOF 4.99kΩ 06106-024 + 2.2nF 390pF Figure 22. Typical DAC Output Filter Circuit (Single-Ended, Noninverting) AVDD2 3.32kΩ AVDD2 562Ω 06106-027 11kΩ 6N8PpOF Figure 21. Recommended Loop Filters for LRCLK or MCLK PLL Reference DOAUCT 11kΩ 3.01kΩ 2 O–P275 1 604Ω 4.7µF AUDIO 3 + OUTPUT CM + 2.2nF 49.9kΩ 27N0PpOF 0.1µF NPO 06106-025 Figure 23. Typical DAC Output Filter Circuit (Single-Ended, Inverting) Rev. D | Page 25 of 28

AD1934 Data Sheet OUTLINE DIMENSIONS 9.20 0.75 9.00 SQ 1.60 0.60 MAX 8.80 0.45 48 37 1 36 PIN 1 7.20 1.45 TOP VIEW 7.00 SQ 1.40 0.20 (PINS DOWN) 6.80 0.09 1.35 7° 3.5° 12 25 0.15 0° 13 24 0.05 SPELAANTEING 0C.O08PLANARITY VIEW A 0.50 0.27 BSC 0.22 LEAD PITCH 0.17 VIEW A ROTATED 90° CCW COMPLIANTTO JEDEC STANDARDS MS-026-BBC 051706-A Figure 24. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model1, 2 Temperature Range Package Description Package Option AD1934YSTZ −40°C to +105°C 48-Lead LQFP ST-48 AD1934YSTZ-RL −40°C to +105°C 48-Lead LQFP, 13” Tape and Reel ST-48 AD1934WBSTZ −40°C to +105°C 48-Lead LQFP ST-48 AD1934WBSTZ-RL −40°C to +105°C 48-Lead LQFP, 13” Tape and Reel ST-48 EVAL-AD1938AZ Evaluation Board 1 Z = RoHS Compliant Part. 2 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD1934WBSTZ and AD1934WBSTZ-RL models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. D | Page 26 of 28

Data Sheet AD1934 NOTES Rev. D | Page 27 of 28

AD1934 Data Sheet NOTES ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06106-0-2/13(D) Rev. D | Page 28 of 28