a 12-Bit 100 kSPS A/D Converter AD1674* FUNCTIONAL BLOCK DIAGRAM FEATURES Complete Monolithic 12-Bit 10 (cid:109)s Sampling ADC 12/8 On-Board Sample-and-Hold Amplifier CS A STS I8n-d aunsdt r1y6 S-Btaitn Mdaicrdro Ppirnoocuetssor Interface RCA/CE0 AACAAONTROLAASREF AC and DC Specified and Tested FU B U(cid:54)n5 iVpo, l(cid:54)ar1 0a nVd, B0 iVpo–1la0r VIn, p0u Vts–20 V Input Ranges REF OUT AR10EVF ACLOAACK SAAR 12AT UTP U CoRmanmgeer cGiarla,d Iensdustrial and Military Temperature AGND 20k COMP AOE AT 12 DDBB101 ( L(MSBS)B) REF IN 12 ST MIL-STD-883 and SMD Compliant Versions Available 5k 10k 3- BIP OFF A/ S 20VIN 5k 10k DAC ERTS 10VIN 2.5k 5k IDAC AGIER 2.5k SHA AD1674 PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD1674 is a complete, multipurpose, 12-bit analog-to- 1. Industry Standard Pinout: The AD1674 utilizes the pinout digital converter, consisting of a user-transparent onboard established by the industry standard AD574A and AD674A. sample-and-hold amplifier (SHA), 10 volt reference, clock and 2. Integrated SHA: The AD1674 has an integrated SHA which three-state output buffers for microprocessor interface. supports the full Nyquist bandwidth of the converter. The The AD1674 is pin compatible with the industry standard SHA function is transparent to the user; no wait-states are AD574A and AD674A, but includes a sampling function while needed for SHA acquisition. delivering a faster conversion rate. The on-chip SHA has a wide 3. DC and AC Specified: In addition to traditional dc specifica- input bandwidth supporting 12-bit accuracy over the full tions, the AD1674 is also fully specified for frequency do- Nyquist bandwidth of the converter. main ac parameters such as total harmonic distortion, The AD1674 is fully specified for ac parameters (such as S/(N+D) signal-to-noise ratio and input bandwidth. These parameters ratio, THD, and IMD) and dc parameters (offset, full-scale can be tested and guaranteed as a result of the onboard error, etc.). With both ac and dc specifications, the AD1674 is SHA. ideal for use in signal processing and traditional dc measure- 4. Analog Operation: The precision, laser-trimmed scaling and ment applications. bipolar offset resistors provide four calibrated ranges: The AD1674 design is implemented using Analog Devices’ 0 V to +10 V and 0 V to +20 V unipolar, –5 V to +5 V and BiMOS II process allowing high performance bipolar analog cir- –10 V to +10 V bipolar. The AD1674 operates on +5 V and cuitry to be combined on the same die with digital CMOS logic. – 12 V or – 15 V power supplies. Five different temperature grades are available. The AD1674J 5. Flexible Digital Interface: On-chip multiple-mode and K grades are specified for operation over the 0(cid:176) C to +70(cid:176) C three-state output buffers and interface logic allow direct temperature range. The A and B grades are specified from connection to most microprocessors. –40(cid:176) C to +85(cid:176) C; the AD1674T grade is specified from –55(cid:176) C to +125(cid:176) C. The J and K grades are available in both 28-lead plastic DIP and SOIC. The A and B grade devices are available in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC. The T grade is available in 28-lead hermetically sealed ceramic DIP. *Protected by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586. REV.C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703

AD1674–SPECIFICATIONS (T to T , V = +15 V (cid:54) 10% or +12 V (cid:54) 5%, V = +5 V (cid:54) 10%, V = –15 V (cid:54) 10% or DC SPECIFICATIONS MIN MAX CC LOGIC EE –12 V (cid:54) 5% unless otherwise noted) AD1674J AD1674K Parameter Min Typ Max Min Typ Max Unit RESOLUTION 12 12 Bits INTEGRAL NONLINEARITY (INL) – 1 – 1/2 LSB DIFFERENTIAL NONLINEARITY (DNL) (No Missing Codes) 12 12 Bits UNIPOLAR OFFSET1 @ +25(cid:176) C – 3 – 2 LSB BIPOLAR OFFSET1 @ +25(cid:176) C – 6 – 4 LSB FULL-SCALE ERROR1, 2 @ +25(cid:176) C (with Fixed 50 W Resistor from REF OUT to REF IN) 0.1 0.25 0.1 0.25 % of FSR TEMPERATURE RANGE 0 +70 0 +70 (cid:176) C TEMPERATURE DRIFT3 Unipolar Offset2 – 2 – 1 LSB Bipolar Offset2 – 2 – 1 LSB Full-Scale Error2 – 6 – 3 LSB POWER SUPPLY REJECTION V = 15 V – 1.5 V or 12 V – 0.6 V – 2 – 1 LSB CC V = 5 V – 0.5 V – 1/2 – 1/2 LSB LOGIC V = –15 V – 1.5 V or –12 V – 0.6 V – 2 – 1 LSB EE ANALOG INPUT Input Ranges Bipolar –5 +5 –5 +5 Volts –10 +10 –10 +10 Volts Unipolar 0 +10 0 +10 Volts 0 +20 0 +20 Volts Input Impedance 10 Volt Span 3 5 7 3 5 7 kW 20 Volt Span 6 10 14 6 10 14 kW POWER SUPPLIES Operating Voltages V +4.5 +5.5 +4.5 +5.5 Volts LOGIC V +11.4 +16.5 +11.4 +16.5 Volts CC V –16.5 –11.4 –16.5 –11.4 Volts EE Operating Current I 5 8 5 8 mA LOGIC I 10 14 10 14 mA CC I 14 18 14 18 mA EE POWER DISSIPATION 385 575 385 575 mW INTERNAL REFERENCE VOLTAGE 9.9 10.0 10.1 9.9 10.0 10.1 Volts Output Current (Available for External Loads)4 2.0 2.0 mA (External Load Should Not Change During Conversion NOTES 1Adjustable to zero. 2Includes internal voltage reference error. 3Maximum change from 25(cid:176)C value to the value at T or T . MIN MAX 4Reference should be buffered for – 12 V operation. All min and max specifications are guaranteed. Specifications subject to change without notice. –2– REV. C

AD1674 AD1674A AD1674B AD1674T Parameter Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 12 12 12 Bits INTEGRAL NONLINEARITY (INL) – 1 – 1/2 – 1/2 LSB – 1 – 1/2 – 1 LSB DIFFERENTIAL NONLINEARITY (DNL) (No Missing Codes) 12 12 12 Bits UNIPOLAR OFFSET1 @ +25(cid:176) C – 2 – 2 – 2 LSB BIPOLAR OFFSET1 @ +25(cid:176) C – 6 – 3 – 3 LSB FULL-SCALE ERROR1, 2 @ +25(cid:176) C (with Fixed 50 W Resistor from REF OUT to REF IN) 0.1 0.25 0.1 0.125 0.1 0.125 % of FSR TEMPERATURE RANGE –40 +85 –40 +85 –55 +125 (cid:176) C TEMPERATURE DRIFT3 Unipolar Offset2 – 2 – 1 – 1 LSB Bipolar Offset2 – 2 – 1 – 2 LSB Full-Scale Error2 – 8 – 5 – 7 LSB POWER SUPPLY REJECTION V = 15 V – 1.5 V or 12 V – 0.6 V – 2 – 1 – 1 LSB CC V = 5 V – 0.5 V – 1/2 – 1/2 – 1/2 LSB LOGIC V = –15 V – 1.5 V or –12 V – 0.6 V – 2 – 1 – 1 LSB EE ANALOG INPUT Input Ranges Bipolar –5 +5 –5 +5 –5 +5 Volts –10 +10 –10 +10 –10 +10 Volts Unipolar 0 +10 0 +10 0 +10 Volts 0 +20 0 +20 0 +20 Volts Input Impedance 10 Volt Span 3 5 7 3 5 7 3 5 7 kW 20 Volt Span 6 10 14 6 10 14 6 10 14 kW POWER SUPPLIES Operating Voltages V +4.5 +5.5 +4.5 +5.5 +4.5 +5.5 Volts LOGIC V +11.4 +16.5 +11.4 +16.5 +11.4 +16.5 Volts CC V –16.5 –11.4 –16.5 –11.4 –16.5 –11.4 Volts EE Operating Current I 5 8 5 8 5 8 mA LOGIC I 10 14 10 14 10 14 mA CC I 14 18 14 18 14 18 mA EE POWER DISSIPATION 385 575 385 575 385 575 mW INTERNAL REFERENCE VOLTAGE 9.9 10.0 10.1 9.9 10.0 10.1 9.9 10.0 10.1 Volts Output Current (Available for External Loads)4 2.0 2.0 2.0 mA (External Load Should Not Change During Conversion REV. C –3–

AD1674–SPECIFICATIONS (T to T , with V = +15 V (cid:54) 10% or +12 V (cid:54) 5%, V = +5 V (cid:54) 10%, V = –15 V (cid:54)10% or AC SPECIFICATIONS MIN MAX CC LOGIC EE –12 V (cid:54) 5%, f = 100 kSPS, f = 10 kHz, stand-alone mode unless otherwise noted)1 SAMPLE IN AD1674J/A AD1674K/B/T Parameter Min Typ Max Min Typ Max Units Signal to Noise and Distortion (S/N+D) Ratio2, 3 69 70 70 71 dB Total Harmonic Distortion (THD)4 –90 –82 –90 –82 dB 0.008 0.008 % Peak Spurious or Peak Harmonic Component –92 –82 –92 –82 dB Full Power Bandwidth 1 1 MHz Full Linear Bandwidth 500 500 kHz Intermodulation Distortion (IMD)5 Second Order Products –90 –80 –90 –80 dB Third Order Products –90 –80 –90 –80 dB SHA (Specifications are Included in Overall Timing Specifications) Aperture Delay 50 50 ns Aperture Jitter 250 250 ps Acquisition Time 1 1 m s (for all grades T to T , with V = +15 V (cid:54) 10% or +12 V (cid:54) 5%, V = +5 V (cid:54) 10%, DIGITAL SPECIFICATIONS MIN MAX CC LOGIC V = –15 V (cid:54) 10% or –12 V (cid:54) 5%) EE Parameter Test Conditions Min Max Units LOGIC INPUTS V High Level Input Voltage +2.0 V +0.5 V V IH LOGIC V Low Level Input Voltage –0.5 +0.8 V IL I High Level Input Current (V = 5 V) V = V –10 +10 m A IH IN IN LOGIC I Low Level Input Current (V = 0 V) V = 0 V –10 +10 m A IL IN IN C Input Capacitance 10 pF IN LOGIC OUTPUTS V High Level Output Voltage I = 0.5 mA +2.4 V OH OH V Low Level Output Voltage I = 1.6 mA +0.4 V OL OL I High-Z Leakage Current V = 0 to V –10 +10 m A OZ IN LOGIC C High-Z Output Capacitance 10 pF OZ NOTES 1f amplitude = –0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to –0 dB (9.997 V p-p) input signal unless IN otherwise noted. 2Specified at worst case temperatures and supplies after one minute warm-up. 3See Figures 12 and 13 for other input frequencies and amplitudes. 4See Figure 11. 5fa = 9.08 kHz, fb = 9.58 kHz with f = 100 kHz. See Definition of Specifications section and Figure 15. SAMPLE All min and max specifications are guaranteed. Specifications subject to change without notice. –4– REV. C

AD1674 (for all grades T to T with V = +15 V (cid:54) 10% or +12 V (cid:54) 5%, MIN MAX CC V = +5 V (cid:54)10%, V = –15 V (cid:54) 10% or –12 V (cid:54) 5%; V = 0.4 V, SWITCHING SPECIFICATIONS LOGIC EE IL V = 2.4 V unless otherwise noted) IH CONVERTER START TIMING (Figure 1) J, K, A, B, Grades T Grade Parameter Symbol Min Typ Max Min Typ Max Units t CE HEC Co8n-vBerits iCony cTleime t 7 8 7 8 m s C_S_ tHSC C t 12-Bit Cycle t 9 10 9 10 m s SSC C STS Delay from CE tDSC 200 225 ns _ t t CE Pulse Width t 50 50 ns R/C SRC HRC HEC CS to CE Setup t 50 50 ns SSC CS Low During CE High t 50 50 ns HSC R/C to CE Setup t 50 50 ns R/C Low During CE High tSRC 50 50 ns A0 tSAC tHAC HRC A to CE Setup t 0 0 ns t 0 SAC C A Valid During CE High t 50 50 ns 0 HAC STS t DSC DB11 – DB0 HIGH IMPEDANCE READ TIMING—FULL CONTROL MODE (Figure 2) J, K, A, B, Grades T Grade Figure 1.Converter Start Timing Parameter Symbol Min Typ Max Min Typ Max Units Access Time t 1 75 150 75 150 ns DD Data Valid After CE Low tHD 225023 215524 nnss _C_E CS Output Float Delay tHL5 150 150 ns tSSR tHSR CS to CE Setup t 50 50 ns SSR R/C to CE Setup t 0 0 ns SRR _ A0 to CE Setup tSAR 50 50 ns R/C t t SSR HRR CS Valid After CE Low t 0 0 ns HSR R/C High After CE Low t 0 0 ns HRR A Valid After CE Low t 50 50 ns 0 HAR A0 tSAR tHAR NOTES 1t is measured with the load circuit of Figure 3 and is defined as the time DD required for an output to cross 0.4 V or 2.4 V. tHS 20(cid:176)C to T . STS MAX 3At –40(cid:176)C. t 4At –55(cid:176)C. HD 5tHL is defined as the time required for the data lines to change 0.5 V when DB11 – DB0 HIGH DATA HIGH loaded with the circuit of Figure 3. IMPEDANCE VALID IMP. All min and max specifications are guaranteed. tDD tHL Specifications subject to change without notice. Figure 2.Read Timing Test V C CP OUT Access Time High Z to Logic Low 5 V 100 pF I OL Float Time Logic High to High Z 0 V 10 pF Access Time High Z to Logic High 0 V 100 pF Float Time Logic Low to High Z 5 V 10 pF DOUT VCP C OUT I OH Figure 3.Load Circuit for Bus Timing Specifications REV. C –5–

AD1674 TIMING—STAND-ALONE MODE (Figures 4a and 4b) J, K, A, B Grades T Grade Parameter Symbol Min Typ Max Min Typ Max Units Data Access Time t 150 150 ns DDR Low R/C Pulse Width t 50 50 ns HRL STS Delay from R/C t 200 225 ns DS Data Valid After R/C Low t 25 25 ns HDR STS Delay After Data Valid t 0.6 0.8 1.2 0.6 0.8 1.2 m s HS High R/C Pulse Width t 150 150 ns HRH NOTE All min and max specifications are guaranteed. Specifications subject to change without notice. t HRL _ _ R/C R/C t t HRH DS t DS STS STS t C t t t DDR HDR C t t HDR HS DB11 – DB0 HIGH-Z DATA HIGH-Z DATA HIGH-Z VALID DB11 – DB0 DATA VALID VALID t HL Figure 4a.Stand-Alone Mode Timing Low Pulse for R/C Figure 4b. Stand-Alone Mode Timing High Pulse for R/C ABSOLUTE MAXIMUM RATINGS* . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC V to Digital Common . . . . . . . . . . . . . . . . . . . 0 to + 16.5 V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175(cid:176) C CC V to Digital Common . . . . . . . . . . . . . . . . . . . . .0 to –16.5 V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . .825 mW EE V to Digital Common . . . . . . . . . . . . . . . . . . 0 V to +7 V Lead Temperature, Soldering (10 sec) . . . . . . . +300(cid:176) C, 10 sec LOGIC Analog Common to Digital Common . . . . . . . . . . . . . . . – 1 V Storage Temperature . . . . . . . . . . . . . . . . . . .–65(cid:176) C to +150(cid:176) C Digital Inputs to Digital Common . . . –0.5 V to VLOGIC +0.5 V *Stresses above those listed under “Absolute Maximum Ratings” may cause Analog Inputs to Analog Common . . . . . . . . . . . . V to V permanent damage to the device. This is a stress rating only and functional EE CC 20 V to Analog Common . . . . . . . . . . . . . . . . . V to +24 V operation of the device at these or any other conditions above those indicated in the IN EE operational section of this specification is not implied. Exposure to absolute REF OUT . . . . . . . . . . . . . . . . . Indefinite Short to Common maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD1674 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE ORDERING GUIDE INL S/(N+D) Package Package Model1 Temperature Range (T to T ) (T to T ) Description Option2 MIN MAX MIN MAX AD1674JN 0(cid:176) C to +70(cid:176) C – 1 LSB 69 dB Plastic DIP N-28 AD1674KN 0(cid:176) C to +70(cid:176) C – 1/2 LSB 70 dB Plastic DIP N-28 AD1674JR 0(cid:176) C to +70(cid:176) C – 1 LSB 69 dB Plastic SOIC R-28 AD1674KR 0(cid:176) C to +70(cid:176) C – 1/2 LSB 70 dB Plastic SOIC R-28 AD1674AR –40(cid:176) C to +85(cid:176) C – 1 LSB 69 dB Plastic SOIC R-28 AD1674BR –40(cid:176) C to +85(cid:176) C – 1/2 LSB 70 dB Plastic SOIC R-28 AD1674AD –40(cid:176) C to +85(cid:176) C – 1 LSB 69 dB Ceramic DIP D-28 AD1674BD –40(cid:176) C to +85(cid:176) C – 1/2 LSB 70 dB Ceramic DIP D-28 AD1674TD –55(cid:176) C to +125(cid:176) C – 1 LSB 70 dB Ceramic DIP D-28 NOTES 1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military Products Databook or current AD1674/883B data sheet. SMD is also available. 2N = Plastic DIP; D = Hermetic Ceramic DIP; R = Plastic SOIC. –6– REV. C

AD1674 PIN DESCRIPTION Symbol Pin No. Type Name and Function AGND 9 P Analog Ground (Common). A 4 DI Byte Address/Short Cycle. If a conversion is started with A Active LOW, a full 12-bit conversion 0 0 cycle is initiated. If A is Active HIGH during a convert start, a shorter 8-bit conversion cycle 0 results. During Read (R/C = 1) with 12/8 LOW, A = LOW enables the 8 most significant bits 0 (DB4–DB11), and A = HIGH enables DB3–DB0 and sets DB7–DB4 = 0. 0 BIP OFF 12 AI Bipolar Offset. Connect through a 50 W resistor to REF OUT for bipolar operation or to Analog Common for unipolar operation. CE 6 DI Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation. CS 3 DI Chip Select. Chip Select is Active LOW. DB11–DB8 27–24 DO Data Bits 11 through 8. In the 12-bit format (see 12/8 and A pins), these pins provide the up- 0 per 4 bits of data. In the 8-bit format, they provide the upper 4 bits when A is LOW and are 0 disabled when A is HIGH. 0 DB7–DB4 23–20 DO Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the 8-bit format they provide the middle 4 bits when Ao is LOW and all zeroes when A is HIGH. 0 DB3–DB0 19–16 DO Data Bits 3 through 0. In the 12-bit format these pins provide the lower 4 bits of data. In the 8-bit format these pins provide the lower 4 bits of data when A is HIGH, they are disabled 0 when A is LOW. 0 DGND 15 P Digital Ground (Common). REF OUT 8 AO +10 V Reference Output. R/C 5 DI Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW for a convert operation. In the stand-alone mode, the falling edge of R/C initiates a conversion. REF IN 10 AI Reference Input is connected through a 50 W resistor to +10 V Reference for normal operation. STS 28 DO Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is completed. V 7 P +12 V/+15 V Analog Supply. CC V 11 P –12 V/–15 V Analog Supply. EE V 1 P +5 V Logic Supply. LOGIC 10 V 13 AI 10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the IN AD1674 in the 20 V Span 10 V should not be connected. IN 20 V 14 AI 20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using IN the AD1674 in the 10 V Span 20 V should not be connected. IN 12/8 2 DI The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words (12/8 LOW) or a single 12-bit word (12/8 HIGH). TYPE: AI = Analog Input AO = Analog Output FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION DI = Digital Input DO = Digital Output P = Power 12/8 VLOGIC 1 28 STS CAS CONTROL A STS 12/8 2 27 DB11(MSB) CE0 SR CS 3 26 DB10 R/C AAAAAAAFEF A0 4 25 DB9 U R/C 5 24 DB8 B REF OUT AR10EVFAACALOCK ASARA12 AT PUTOU REF OVCUCETC 786 (NAToODt Pt1o V 6SIE7caW4le) 222321 DDDBBB765 AGND 20k COMP A TEAT 12 DDBB101 ( L(MSBS)B) RAEGFN IDN 190 1290 DDBB43 REF IN 12 S BIP OFF 5k 10k A3- / S BIP OVFEFE 1121 1187 DDBB21 20VIN 5k 10k DAC RET 10VIN 13 16 DB0(LSB) S 10VIN 2.5k 5k IDAC AGIER 20VIN 14 15 DGND 2.5k SHA AD1674 REV. C –7–

AD1674 DEFINITION OF SPECIFICATIONS are present in a sample sequence. The result, called Prime Coherent Sampling, is a highly accurate and repeatable measure INTEGRAL NONLINEARITY (INL) of the actual frequency-domain response of the converter. The ideal transfer function for an ADC is a straight line drawn between “zero” and “full scale.” The point used as “zero” NYQUIST FREQUENCY occurs 1/2 LSB before the first code transition. “Full scale” is An implication of the Nyquist sampling theorem, the “Nyquist defined as a level 1 1/2 LSB beyond the last code transition. Frequency” of a converter is that input frequency which is one- Integral nonlinearity is the worst-case deviation of a code from half the sampling frequency of the converter. the straight line. The deviation of each code is measured from the middle of that code. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/(N+D) is the ratio of the rms value of the measured input sig- DIFFERENTIAL NONLINEARITY (DNL) nal to the rms sum of all other spectral components below the A specification which guarantees no missing codes requires that Nyquist frequency, including harmonics but excluding dc. The every code combination appear in a monotonic increasing value for S/(N+D) is expressed in decibels. sequence as the analog input level is increased. Thus every code must have a finite width. The AD1674 guarantees no missing TOTAL HARMONIC DISTORTION (THD) codes to 12-bit resolution; all 4096 codes are present over the THD is the ratio of the rms sum of the first six harmonic com- entire operating range. ponents to the rms value of a full-scale input signal and is ex- pressed as a percentage or in decibels. For input signals or UNIPOLAR OFFSET harmonics that are above the Nyquist frequency, the aliased The first transition should occur at a level 1/2 LSB above ana- component is used. log common. Unipolar offset is defined as the deviation of the actual transition from that point at 25(cid:176) C. This offset can be INTERMODULATION DISTORTION (IMD) adjusted as shown in Figure 11. With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, BIPOLAR OFFSET of order (m+n), at sum and difference frequencies of mfa – nfb, In the bipolar mode the major carry transition (0111 1111 1111 where m, n = 0, 1, 2, 3....Intermodulation terms are those for to 1000 0000 0000) should occur for an analog value 1/2 LSB which m or n is not equal to zero. For example, the second below analog common. The bipolar offset error specifies the order terms are (fa + fb) and (fa – fb) and the third order terms deviation of the actual transition from that point at 25(cid:176) C. This are (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The IMD offset can be adjusted as shown in Figure 12. products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. FULL-SCALE ERROR The two signals are of equal amplitude and the peak value of The last transition (from 1111 1111 1110 to 1111 1111 1111) their sums is –0.5 dB from full scale. The IMD products are should occur for an analog value 1 1/2 LSB below the nominal normalized to a 0 dB input signal. full scale (9.9963 volts for 10 volts full scale). The full-scale error is the deviation of the actual level of the last transition FULL-POWER BANDWIDTH from the ideal level at 25(cid:176) C. The full-scale error can be adjusted The full-power bandwidth is that input frequency at which the to zero as shown in Figures 11 and 12. amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input. TEMPERATURE DRIFT The temperature drifts for full-scale error, unipolar offset and FULL-LINEAR BANDWIDTH bipolar offset specify the maximum change from the initial The full-linear bandwidth is the input frequency at which the (25(cid:176) C) value to the value at T or T . slew rate limit of the sample-hold-amplifier (SHA) is reached. MIN MAX At this point, the amplitude of the reconstructed fundamental POWER SUPPLY REJECTION has degraded by less than –0.1 dB. Beyond this frequency, dis- The effect of power supply error on the performance of the tortion of the sampled input signal increases significantly. device will be a small change in full scale. The specifications show the maximum full-scale change from the initial value with APERTURE DELAY the supplies at various limits. Aperture delay is a measure of the SHA’s performance and is measured from the falling edge of Read/Convert (R/C) to when FREQUENCY-DOMAIN TESTING the input signal is held for conversion. The AD1674 is tested dynamically using a sine wave input and a 2048 point Fast Fourier Transform (FFT) to analyze the APERTURE JITTER resulting output. Coherent sampling is used, wherein the ADC Aperture jitter is the variation in aperture delay for successive sampling frequency and the analog input frequency are related samples and is manifested as noise on the input to the A/D. to each other by a ratio of integers. This ensures that an integral multiple of input cycles is captured, allowing direct FFT pro- cessing without windowing or digital filtering which could mask some of the dynamic characteristics of the device. In addition, the frequencies are chosen to he “relatively prime” (no common factors) to maximize the number of different ADC codes that –8– REV. C

Typical Dynamic Performance–AD1674 AAAA 80 fSAMPLE = 100kSPS 0dB INPUT FULL-SCALE = +10V 70 AAAA 0 60 –20dB INPUT dB –20 THD dB– 50 – E D –40 D) +N 40 UT –60 (S/ 30 LI MP –80 AAA A 20 3RD –60dB INPUT –100 AAAAHARMOAANIC 10 2NDHARMONIC –120 0 1 10 100 1000 10000 1 10 100 1000 10000 INPUT FREQUENCY – kHz INPUT FREQUENCY – kHz Figure 5.Harmonic Distortion vs. Figure 6.S/(N+D) vs. Input Frequency Figure 7. S/(N+D) vs. Input Amplitude Input Frequency and Amplitude 0 0 –10 –20 –20 B –30 d –E –40 B –40 DU –60 d– –50 ITPLMA –80 DEUITL –––786000 P –100 MA –90 –100 –120 –110 –120 –140 –130 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY – kHz FREQUENCY – kHz Figure 8.Nonaveraged 2048 Point FFT Figure 9. IMD Plot for f = 9.08 kHz (fa), 9.58 kHz (fb) at 100 kSPS, f = 25.049 kHz IN IN DAC current sum to be greater than or less than the input cur- GENERAL CIRCUIT OPERATION The AD1674 is a complete 12-bit, 10 m s sampling analog-to- rent. If the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit digital converter. A block diagram of the AD1674 is shown on binary code which accurately represents the input signal to page 7. within – 1/2 LSB. When the control section is commanded to initiate a conversion (as described later), it places the sample-and-hold amplifier CONTROL LOGIC (SHA) in the hold mode, enables the clock, and resets the suc- The AD1674 may be operated in one of two modes, the full- cessive approximation register (SAR). Once a conversion cycle control mode and the stand-alone mode. The full-control mode has begun, it cannot be stopped or restarted and data is not utilizes all the AD1674 control signals and is useful in systems available from the output buffers. The SAR, timed by the inter- that address decode multiple devices on a single data bus. The nal clock, will sequence through the conversion cycle and return stand-alone mode is useful in systems with dedicated input ports an end-of-convert flag to the control section when the conver- available and thus not requiring full bus interface capability. sion has been completed. The control section will then disable Table I is a truth table for the AD1674, and Figure 10 illus- the clock, switch the SHA to sample mode, and delay the STS trates the internal logic circuitry. LOW going edge to allow for acquisition to 12-bit accuracy. The control section will allow data read functions by external Table I. AD1674A Truth Table command anytime during the SHA acquisition interval. CE CS R/C 12/8 A Operation During the conversion cycle, the internal 12-bit, 1 mA full-scale 0 current output DAC is sequenced by the SAR from the most 0 X X X X None significant bit (MSB) to the least significant bit (LSB) to pro- X 1 X X X None vide an output that accurately balances the current through the 5 kW resistor from the input signal voltage held by the SHA. 1 0 0 X 0 Initiate 12-Bit Conversion 1 0 0 X 1 Initiate 8-Bit Conversion The SHA’s input scaling resistors divide the input voltage by 2 for the 10 V input span and by 4 V for the 20 V input span, 1 0 1 1 X Enable 12-Bit Parallel Output maintaining a 1 mA full-scale output current through the 5 kW 1 0 1 0 0 Enable 8 Most Significant Bits resistor for both ranges. The comparator determines whether 1 0 1 0 1 Enable 4 LSBs +4 Trailing Zeroes the addition of each successively weighted bit current causes the REV. C –9–

AD1674 VALUE OF A0 AT LAST CONVERT COMMAND Q D Q D QB EN EN EOC 12 EOC 8 R Q S S Q SAR RESET R QB 1µs DELAY-HOLD SETTLING CE CLK ENABLE CS STATUS R/C 1m s DELAY-ACQUISITION HOLD/SAMPLE A0 NYBBLE A READ NYBBLE B 12/8 TO OUTPUT NYBBLE C BUFFERS NYBBLE B = 0 Figure 10. Equivalent Internal Logic Circuitry FULL-CONTROL MODE The register control inputs, A and 12/8, control conversion 0 Chip Enable (CE), Chip Select (CS) and Read/ Convert (R/C) length and data format. If a conversion is started with A LOW, 0 are used to control Convert or Read modes of operation. Either a full 12-bit conversion cycle is initiated. If A is HIGH during a 0 CE or CS may be used to initiate a conversion. The state of R/C convert start, a shorter 8-bit conversion cycle results. when CE and CS are both asserted determines whether a data During data read operations, A determines whether the three- Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C 0 state buffers containing the 8 MSBs of the conversion result (A should be LOW before both CE and CS are asserted; if R/C is 0 = 0) or the 4 LSBs (A = 1) are enabled. The 12/8 pin deter- HIGH, a Read operation will momentarily occur, possibly 0 mines whether the output data is to be organized as two 8-bit resulting in system bus contention. words (12/8 tied LOW) or a single 12-bit word (12/8 tied HIGH). In the 8-bit mode, the byte addressed when A is high STAND-ALONE MODE 0 contains the 4 LSBs from the conversion followed by four trail- The AD1674 can be used in a “stand-alone” mode, which is ing zeroes. This organization allows the data lines to be over- useful in systems with dedicated input ports available and thus lapped for direct interface to 8-bit buses without the need for not requiring full bus interface capability. Stand-alone mode external three-state buffers. applications are generally able to issue conversion start com- mands more precisely than full-control mode. This improves ac INPUT CONNECTIONS AND CALIBRATION performance by reducing the amount of control-induced aper- The 10 V p-p and 20 V p-p full-scale input ranges of the ture jitter. AD1674 accept the majority of signal voltages without the need In stand-alone mode, the control interface for the AD1674 and for external voltage divider networks which could deteriorate the AD674A are identical. CE and 12/8 are wired HIGH, CS and accuracy of the ADC. A are wired LOW, and conversion is controlled by R/C. The 0 The AD1674 is factory trimmed to minimize offset, linearity, three-state buffers are enabled when R/C is HIGH and a con- and full-scale errors. In many applications, no calibration trim- version starts when R/C goes LOW. This gives rise to two pos- ming will be required and the AD1674 will exhibit the accuracy sible control signals—a high pulse or a low pulse. Operation limits listed in the specification tables. with a low pulse is shown in Figure 4a. In this case, the outputs In some applications, offset and full-scale errors need to be are forced into the high impedance state in response to the fall- trimmed out completely. The following sections describe the ing edge of R/C and return to valid logic levels after the conver- correct procedure for these various situations. sion cycle is completed. The STS line goes HIGH 200 ns after R/C goes LOW and returns low 1 m s after data is valid. UNIPOLAR RANGE INPUTS If conversion is initiated by a high pulse as shown in Figure 4b, Figure 11 illustrates the external connections for the AD1674 in the data lines are enabled during the time when R/C is HIGH. unipolar-input mode. The first output-code transition (from The falling edge of R/C starts the next conversion and the data 0000 0000 0000 to 0000 0000 0001) should nominally occur lines return to three-state (and remain three-state) until the next for an input level of +1/2 LSB (1.22 mV above ground for a 10 V high pulse of R/C. range; 2.44 mV for a 20 V range). To trim unipolar offset to this nominal value, apply a +1/2 LSB signal between Pin 13 and CONVERSION TIMING ground (10 V range) or Pin 14 and ground (20 V range) and ad- Once a conversion is started, the STS line goes HIGH. Convert just R1 until the first transition is located. If the offset trim is start commands will be ignored until the conversion cycle is not required, Pin 12 can be connected directly to Pin 9; the two complete. The output data buffers will be enabled a minimum of 0.6 m s prior to STS going LOW. The STS line will return resistors and trimmer for Pin 12 are then not needed. LOW at the end of the conversion cycle. –10– REV. C

AD1674 R1 REFERENCE DECOUPLING 100k 2 12/8 STS 28 It is recommended that a 10 m F tantalum capacitor be con- –15V +15V 3 CS HIGH BITS nected between REF IN (Pin 10) and ground. This has the 4 A 24-27 0 effect of improving the S/(N+D) ratio through filtering possible R2 5 R/C MIDDLE BITS 100k 100W 6 CE 20-23 broad-band noise contributions from the voltage reference. 10 REF IN LOW BITS 100W 8 REF OUT 16-19 BOARD LAYOUT 12 BIP OFF Designing with high resolution data converters requires careful 0 TO +10V AD1674 +5V 1 AINNAPLUOTGS 1134 1200VVIN +–1155VV 1 71 aAttt etnhtei o1n2 -tboi tb loeavredl, laa y5o umt.A T cruarcree nimt tpherdoaungche ais 0 a.5 s iWgn tirfaiccaen wt iilslsue. IN 0 TO +20V 9 ANA COM DIG COM 15 develop a voltage drop of 2.5 mV, which is 1 LSB for a 10 V full-scale range. In addition to ground drops, inductive and ca- pacitive coupling need to be considered, especially when high Figure 11.Unipolar Input Connections with Gain and accuracy analog signals share the same board with digital sig- Offset Trims nals. Finally, power supplies should be decoupled in order to filter out ac noise. The full-scale trim is done by applying a signal 1 1/2 LSB below the nominal full scale (9.9963 V for a 10 V range) and adjusting The AD1674 has a wide bandwidth sampling front end. This R2 until the last transition is located (1111 1111 1110 to 1111 means that the AD1674 will “see” high frequency noise at the 1111 1111). If full-scale adjustment is not required, R2 should input, which nonsampling (or limited-bandwidth sampling) be replaced with a fixed 50 W – 1% metal film resistor. If REF ADCs would ignore. Therefore, it’s important to make an effort OUT is connected directly to REF IN, the additional full-scale to eliminate such high frequency noise through decoupling or by error will be approximately 1%. using an anti-aliasing filter at the analog input of the AD1674. Analog and digital signals should not share a common path. BIPOLAR RANGE INPUTS Each signal should have an appropriate analog or digital return The connections for the bipolar-input mode are shown in Figure routed close to it. Using this approach, signal loops enclose a 12. Either or both of the trimming potentiometers can be small area, minimizing the inductive coupling of noise. Wide PC replaced with 50 W – 1% fixed resistors if the specified AD1674 tracks, large gauge wire, and ground planes are highly recom- accuracy limits are sufficient for the application. If the pins are mended to provide low impedance signal paths. Separate analog shorted together, the additional offset and gain errors will be and digital ground planes are also desirable, with a single inter- approximately 1%. connection point to minimize ground loops. Analog signals To trim bipolar offset to its nominal value, apply a signal 1/2 should be routed as far as possible from digital signals and LSB below midrange (–1.22 mV for a – 5 V range) and adjust should cross them (if necessary) only at right angles. R1 until the major carry transition is located (0111 1111 1111 The AD1674 incorporates several features to help the user’s lay- to 1000 0000 0000). To trim the full-scale error, apply a signal out. Analog pins are adjacent to help isolate analog from digital 1 1/2 LSB below full scale (+4.9963 V for a – 5 V range) and signals. Ground currents have been minimized by careful circuit adjust R2 to give the last positive transition (1111 1111 1110 to architecture. Current through AGND is 2.2 mA, with little 1111 1111 1111). These trims are interactive so several itera- code-dependent variation. The current through DGND is domi- tions may be necessary for convergence. nated by the return current for DB11–DB0. A single-pass calibration can be done by substituting a negative full-scale trim for the bipolar offset trim (error at midscale), SUPPLY DECOUPLING using the same circuit. First, apply a signal 1/2 LSB above minus The AD1674 power supplies should be well filtered, well regu- full scale (–4.9988 V for a – 5 V range) and adjust R1 until the lated, and free from high frequency noise. Switching power sup- minus full-scale transition is located (0000 0000 0001 to 0000 plies are not recommended due to their tendency to generate 0000 0000). Then perform the gain error trim as outlined above. spikes which can induce noise in the analog system. Decoupling capacitors should be used in very close layout prox- 2 12/8 STS 28 imity between all power supply pins and ground. A 10 m F tanta- 3 CS HIGH BITS lum capacitor in parallel with a 0.1 m F disc ceramic capacitor 4 A 24-27 0 provides adequate decoupling over a wide range of frequencies. R2 5 R/C MIDDLE BITS 100W 6 CE 20-23 An effort should be made to minimize the trace length between 10 REF IN LOW BITS the capacitor leads and the respective converter power supply 8 REF OUT 16-19 12 BIP OFF and common pins. The circuit layout should attempt to locate R1 the AD1674, associated analog input circuitry, and interconnec- ±5V 100W AD1674 +5V 1 ANALOG 13 10VIN +15V 7 tions as far as possible from logic circuitry. A solid analog INPUTS 14 20V –15V 11 ground plane around the AD1674 will isolate large switching IN ±10V 9 ANA COM DIG COM 15 ground currents. For these reasons, the use of wire-wrap circuit construction is not recommended; careful printed-circuit con- struction is preferred. Figure 12.Bipolar Input Connections with Gain and Offset Trims REV. C –11–

AD1674 GROUNDING PACKAGE INFORMATION If a single AD1674 is used with separate analog and digital Dimensions shown in inches and (mm). ground planes, connect the analog ground plane to AGND and the digital ground plane to DGND keeping lead lengths as short as possible. Then connect AGND and DGND together at the 28-Pin Ceramic DIP Package (D-28) AD1674. If multiple AD1674s are used or the AD1674 shares analog supplies with other components, connect the analog and digital returns together once at the power supplies rather than at 0.505 (12.83) 94 3/ each chip. This prevents large ground loops which inductively 28 15 0– 1 couple noise and allow digital currents to flow through the ana- – log system. PIN 1 (1 40..9589 ±±00..20514) 25b 4 1 1 14 C GENERAL MICROPROCESSOR INTERFACE 0.050 ±0.010 0.095 CONSIDERATIONS 1.42 (36.07) (1.27 ±0.254) (2.41) 1.40 (35.56) A typical A/D converter interface routine involves several opera- 0.145 ±0.02 tions. First, a write to the ADC address initiates a conversion. (3.68 ±0.51) The processor must then wait for the conversion cycle to com- 0.125 0.085 0.010 ±0.002 (3.17) (2.16) (0.254 ±0.05) plete, since most ADCs take longer than one instruction cycle to MIN SEATING 0.6 (15.24) complete a conversion. Valid data can, of course, only be read 0.017 ±0.003 0.1 (2.54) 0.047 ±0.007 PLANE (0.43 ±0.076) (1.19 ±0.178) after the conversion is complete. The AD1674 provides an out- put signal (STS) which indicates when a conversion is in progress. This signal can be polled by the processor by reading 28-Lead Plastic DIP Package (N-28) it through an external three-state buffer (or other input port). The STS signal can also be used to generate an interrupt upon completion of a conversion, if the system timing requirements 28 15 0.550 (13.97) are critical (bear in mind that the maximum conversion time of 0.530 (13.462) PIN 1 the AD1674 is only 10 microseconds) and the processor has 1 14 other tasks to perform during the ADC conversion cycle. An- 1.450 (38.83) 0.606 (15.39) other possible time-out method is to assume that the ADC will 1.440 (35.576) 0.160 (4.06) 0.594 (15.09) take 10 microseconds to convert, and insert a sufficient number 0.200 0.140 (3.56) (5.080) of “no-op” instructions to ensure that 10 microseconds of pro- MAX cessor time is consumed. 15° 0.012 (0.305) Once it is established that the conversion is finished, the data 00..117250 ((43..4055)) 00..002105 ((00..530881)) 00..100955 ((22..6471)) 00..006455 ((11..6154)) SEATING 0° 0.008 (0.203) can be read. In the case of an ADC of 8-bit resolution (or less), PLANE a single data read operation is sufficient. In the case of convert- ers with more data bits than are available on the bus, a choice of 28-Lead Wide-Body SO Package (R-28) data formats is required, and multiple read operations are needed. The AD1674 includes internal logic to permit direct in- terface to 8-bit or 16-bit data buses, selected by the 12/8 input. In 16-bit bus applications (12/8 HIGH) the data lines (DB11 28 15 through DB0) may be connected to either the 12 most signifi- 0.2992 (7.60) 0.2914 (7.40) cant or 12 least significant hits of the data bus. The remaining four bits should be masked in software. The interface to an 8-bit PIN 1 0.4193 (10.65) 1 14 0.3937 (10.00) data bus (12/8 LOW) contains the 8 MSBs (DB11 through DB4). The odd address (A HIGH) contains the 4 LSBs (DB3 0 through DB0) in the upper half of the byte, followed by four 0.1043 (2.65) trailing zeroes, thus eliminating bit masking instructions. 00..76192659 ((1187..1700)) 0.0926 (2.35) 00..00209918 ((00..7245))x 45° S.A. U. 00..00101480 ((00..3100)) 0.05B00S C(1.27) 00..00119328 ((00..4395)) 00..00102951 ((00..3223))80°° 00..00510507 ((10..2470)) TED IN N RI P AD1674 Data Format for 8-Bit Bus –12– REV. C

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